Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	845	1			T2	7		T14	15		T15	14
all_values[1]	845	1			T2	7		T14	15		T15	14
all_values[2]	845	1			T2	7		T14	15		T15	14
all_values[3]	845	1			T2	7		T14	15		T15	14
all_values[4]	845	1			T2	7		T14	15		T15	14
all_values[5]	845	1			T2	7		T14	15		T15	14
all_values[6]	845	1			T2	7		T14	15		T15	14
all_values[7]	845	1			T2	7		T14	15		T15	14
all_values[8]	845	1			T2	7		T14	15		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4071

1

T2

33

T14

78

T15

53

auto[1]

3534

1

T2

30

T14

57

T15

73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2518

1

T2

20

T14

37

T15

40

auto[1]

5087

1

T2

43

T14

98

T15

86

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4535

1

T2

36

T14

74

T15

69

auto[1]

3070

1

T2

27

T14

61

T15

57

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	282	1			T2	3		T14	6		T15	3
all_values[0]	auto[0]	auto[1]	auto[1]	221	1			T2	1		T14	1		T15	4
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T2	2		T14	6		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T2	1		T14	2		T15	6
all_values[1]	auto[0]	auto[0]	auto[0]	276	1			T2	4		T14	7		T15	3
all_values[1]	auto[0]	auto[1]	auto[0]	230	1			T2	2		T14	2		T15	3
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T2	1		T14	5		T15	4
all_values[1]	auto[1]	auto[1]	auto[1]	153	1			T14	1		T15	4		T42	1
all_values[2]	auto[0]	auto[0]	auto[0]	194	1			T2	1		T14	4		T15	4
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T28	1		T29	1		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	161	1			T14	3		T15	1		T42	4
all_values[2]	auto[0]	auto[1]	auto[1]	87	1			T2	1		T14	3		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T2	1		T14	2		T15	2
all_values[2]	auto[1]	auto[1]	auto[1]	152	1			T2	4		T14	3		T15	5
all_values[3]	auto[0]	auto[0]	auto[0]	179	1			T2	2		T14	1		T15	6
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T14	3		T15	1		T42	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T2	3		T14	1		T15	3
all_values[3]	auto[0]	auto[1]	auto[1]	93	1			T14	2		T30	1		T31	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T2	1		T14	3		T15	2
all_values[3]	auto[1]	auto[1]	auto[1]	157	1			T2	1		T14	5		T15	2
all_values[4]	auto[0]	auto[0]	auto[0]	181	1			T2	1		T14	3		T15	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T14	2		T42	2		T28	1
all_values[4]	auto[0]	auto[1]	auto[0]	157	1			T15	5		T42	3		T28	3
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T2	3		T14	3		T15	1
all_values[4]	auto[1]	auto[0]	auto[1]	159	1			T2	1		T14	1		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T2	2		T14	6		T15	4
all_values[5]	auto[0]	auto[0]	auto[0]	198	1			T2	1		T14	6		T15	2
all_values[5]	auto[0]	auto[0]	auto[1]	83	1			T2	1		T14	1		T42	2
all_values[5]	auto[0]	auto[1]	auto[0]	160	1			T2	2		T14	2		T15	1
all_values[5]	auto[0]	auto[1]	auto[1]	85	1			T14	1		T15	6		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T2	2		T14	5		T15	2
all_values[5]	auto[1]	auto[1]	auto[1]	145	1			T2	1		T15	3		T42	2
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T14	2		T15	5		T28	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T14	1		T15	1		T42	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T2	3		T14	1		T15	2
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T2	1		T14	3		T15	2
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T2	2		T14	3		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T2	1		T14	5		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T2	1		T15	2		T42	7
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T2	1		T14	2		T28	2
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T14	5		T15	2		T42	3
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T2	1		T14	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	187	1			T2	3		T14	4		T15	3
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T2	1		T14	3		T15	5
all_values[8]	auto[0]	auto[0]	auto[1]	272	1			T2	2		T14	5		T15	1
all_values[8]	auto[0]	auto[1]	auto[1]	218	1			T2	2		T14	3		T15	6
all_values[8]	auto[1]	auto[0]	auto[1]	199	1			T2	3		T14	6		T15	4
all_values[8]	auto[1]	auto[1]	auto[1]	156	1			T14	1		T15	3		T42	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal