Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.62


Total test records in report: 1308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1258 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2166976243 Jul 21 07:06:23 PM PDT 24 Jul 21 07:06:26 PM PDT 24 193535722 ps
T1259 /workspace/coverage/cover_reg_top/47.uart_intr_test.1030287847 Jul 21 07:06:44 PM PDT 24 Jul 21 07:06:45 PM PDT 24 26434035 ps
T1260 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1189676315 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:32 PM PDT 24 183379582 ps
T69 /workspace/coverage/cover_reg_top/7.uart_csr_rw.4084163485 Jul 21 07:06:35 PM PDT 24 Jul 21 07:06:36 PM PDT 24 46460571 ps
T1261 /workspace/coverage/cover_reg_top/24.uart_intr_test.2144556630 Jul 21 07:06:57 PM PDT 24 Jul 21 07:06:59 PM PDT 24 19904423 ps
T1262 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3169891539 Jul 21 07:06:29 PM PDT 24 Jul 21 07:06:32 PM PDT 24 131243972 ps
T70 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1632676083 Jul 21 07:06:24 PM PDT 24 Jul 21 07:06:29 PM PDT 24 865832609 ps
T1263 /workspace/coverage/cover_reg_top/16.uart_intr_test.826719531 Jul 21 07:06:35 PM PDT 24 Jul 21 07:06:37 PM PDT 24 171662935 ps
T1264 /workspace/coverage/cover_reg_top/12.uart_tl_errors.760392002 Jul 21 07:06:26 PM PDT 24 Jul 21 07:06:31 PM PDT 24 621097704 ps
T1265 /workspace/coverage/cover_reg_top/45.uart_intr_test.1686102744 Jul 21 07:06:39 PM PDT 24 Jul 21 07:06:40 PM PDT 24 22443000 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1421407687 Jul 21 07:06:25 PM PDT 24 Jul 21 07:06:28 PM PDT 24 143206447 ps
T1267 /workspace/coverage/cover_reg_top/49.uart_intr_test.1985907071 Jul 21 07:06:49 PM PDT 24 Jul 21 07:06:50 PM PDT 24 21266451 ps
T1268 /workspace/coverage/cover_reg_top/14.uart_intr_test.168039207 Jul 21 07:06:30 PM PDT 24 Jul 21 07:06:33 PM PDT 24 35182666 ps
T1269 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1624732816 Jul 21 07:06:37 PM PDT 24 Jul 21 07:06:38 PM PDT 24 73784142 ps
T1270 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2157658635 Jul 21 07:06:20 PM PDT 24 Jul 21 07:06:21 PM PDT 24 32045320 ps
T71 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2741878990 Jul 21 07:06:26 PM PDT 24 Jul 21 07:06:29 PM PDT 24 34096534 ps
T1271 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.73799599 Jul 21 07:06:56 PM PDT 24 Jul 21 07:06:57 PM PDT 24 27461623 ps
T1272 /workspace/coverage/cover_reg_top/42.uart_intr_test.2268751304 Jul 21 07:06:58 PM PDT 24 Jul 21 07:06:59 PM PDT 24 26653998 ps
T1273 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2226232095 Jul 21 07:06:21 PM PDT 24 Jul 21 07:06:22 PM PDT 24 75761555 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1403516430 Jul 21 07:06:23 PM PDT 24 Jul 21 07:06:26 PM PDT 24 52999728 ps
T1275 /workspace/coverage/cover_reg_top/36.uart_intr_test.125672587 Jul 21 07:06:56 PM PDT 24 Jul 21 07:06:57 PM PDT 24 28833397 ps
T97 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1911233977 Jul 21 07:06:31 PM PDT 24 Jul 21 07:06:34 PM PDT 24 94297587 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2715953828 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:33 PM PDT 24 137227741 ps
T1277 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.36747360 Jul 21 07:06:22 PM PDT 24 Jul 21 07:06:25 PM PDT 24 169039776 ps
T1278 /workspace/coverage/cover_reg_top/16.uart_tl_errors.647529396 Jul 21 07:06:30 PM PDT 24 Jul 21 07:06:34 PM PDT 24 40991972 ps
T1279 /workspace/coverage/cover_reg_top/29.uart_intr_test.890905177 Jul 21 07:06:55 PM PDT 24 Jul 21 07:06:56 PM PDT 24 15605878 ps
T1280 /workspace/coverage/cover_reg_top/44.uart_intr_test.3093888953 Jul 21 07:06:39 PM PDT 24 Jul 21 07:06:40 PM PDT 24 30722681 ps
T1281 /workspace/coverage/cover_reg_top/32.uart_intr_test.261126111 Jul 21 07:06:48 PM PDT 24 Jul 21 07:06:48 PM PDT 24 11311688 ps
T1282 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4278124839 Jul 21 07:06:23 PM PDT 24 Jul 21 07:06:25 PM PDT 24 112451878 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1873829686 Jul 21 07:06:20 PM PDT 24 Jul 21 07:06:21 PM PDT 24 89200409 ps
T1284 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.696741263 Jul 21 07:06:59 PM PDT 24 Jul 21 07:07:00 PM PDT 24 86921359 ps
T1285 /workspace/coverage/cover_reg_top/5.uart_intr_test.1844682372 Jul 21 07:06:35 PM PDT 24 Jul 21 07:06:36 PM PDT 24 15338348 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1266451398 Jul 21 07:06:29 PM PDT 24 Jul 21 07:06:33 PM PDT 24 117605788 ps
T1287 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.243876867 Jul 21 07:06:30 PM PDT 24 Jul 21 07:06:33 PM PDT 24 45908651 ps
T98 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.923463951 Jul 21 07:06:34 PM PDT 24 Jul 21 07:06:35 PM PDT 24 52643675 ps
T1288 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.219187600 Jul 21 07:06:27 PM PDT 24 Jul 21 07:06:31 PM PDT 24 97174371 ps
T72 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3599292004 Jul 21 07:06:35 PM PDT 24 Jul 21 07:06:36 PM PDT 24 41047345 ps
T1289 /workspace/coverage/cover_reg_top/40.uart_intr_test.1592793506 Jul 21 07:06:42 PM PDT 24 Jul 21 07:06:43 PM PDT 24 23143696 ps
T1290 /workspace/coverage/cover_reg_top/1.uart_intr_test.3374755979 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:32 PM PDT 24 12903653 ps
T1291 /workspace/coverage/cover_reg_top/11.uart_tl_errors.223432641 Jul 21 07:06:35 PM PDT 24 Jul 21 07:06:37 PM PDT 24 27000716 ps
T1292 /workspace/coverage/cover_reg_top/46.uart_intr_test.4123428580 Jul 21 07:06:39 PM PDT 24 Jul 21 07:06:41 PM PDT 24 40379681 ps
T1293 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3622695500 Jul 21 07:06:23 PM PDT 24 Jul 21 07:06:26 PM PDT 24 133941114 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3953192565 Jul 21 07:06:21 PM PDT 24 Jul 21 07:06:22 PM PDT 24 37959986 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3747752436 Jul 21 07:06:37 PM PDT 24 Jul 21 07:06:38 PM PDT 24 219570828 ps
T1296 /workspace/coverage/cover_reg_top/7.uart_intr_test.3552569847 Jul 21 07:06:36 PM PDT 24 Jul 21 07:06:37 PM PDT 24 13077867 ps
T99 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3252174121 Jul 21 07:06:22 PM PDT 24 Jul 21 07:06:25 PM PDT 24 89722829 ps
T1297 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3943358692 Jul 21 07:06:29 PM PDT 24 Jul 21 07:06:32 PM PDT 24 26181084 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1932309499 Jul 21 07:06:21 PM PDT 24 Jul 21 07:06:23 PM PDT 24 26332263 ps
T1299 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1367183343 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:32 PM PDT 24 58738162 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.545383130 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:31 PM PDT 24 26421045 ps
T1301 /workspace/coverage/cover_reg_top/43.uart_intr_test.307042357 Jul 21 07:06:44 PM PDT 24 Jul 21 07:06:45 PM PDT 24 56792884 ps
T1302 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.408610702 Jul 21 07:06:28 PM PDT 24 Jul 21 07:06:33 PM PDT 24 115897869 ps
T1303 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1380880571 Jul 21 07:06:27 PM PDT 24 Jul 21 07:06:30 PM PDT 24 15180784 ps
T1304 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1613239027 Jul 21 07:06:52 PM PDT 24 Jul 21 07:06:54 PM PDT 24 118410853 ps
T1305 /workspace/coverage/cover_reg_top/28.uart_intr_test.2712359197 Jul 21 07:06:43 PM PDT 24 Jul 21 07:06:44 PM PDT 24 15563331 ps
T1306 /workspace/coverage/cover_reg_top/20.uart_intr_test.2537535315 Jul 21 07:06:42 PM PDT 24 Jul 21 07:06:44 PM PDT 24 12027284 ps
T1307 /workspace/coverage/cover_reg_top/5.uart_csr_rw.4167531781 Jul 21 07:06:20 PM PDT 24 Jul 21 07:06:21 PM PDT 24 14925204 ps
T1308 /workspace/coverage/cover_reg_top/12.uart_intr_test.2344489506 Jul 21 07:06:32 PM PDT 24 Jul 21 07:06:34 PM PDT 24 13685652 ps

Test location /workspace/coverage/default/39.uart_rx_oversample.594383972
Short name T3
Test name
Test status
Simulation time 2712701657 ps
CPU time 18.14 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:17:53 PM PDT 24
Peak memory 199284 kb
Host smart-9ca7e0af-7d71-4bae-80ab-34e3c5f2969b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594383972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.594383972
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1887539057
Short name T14
Test name
Test status
Simulation time 93135534897 ps
CPU time 699.65 seconds
Started Jul 21 07:18:15 PM PDT 24
Finished Jul 21 07:31:23 PM PDT 24
Peak memory 216812 kb
Host smart-fec3d757-834a-4883-ad1b-bb77b147d1e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887539057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1887539057
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1241086281
Short name T9
Test name
Test status
Simulation time 133631410025 ps
CPU time 185.26 seconds
Started Jul 21 07:14:47 PM PDT 24
Finished Jul 21 07:17:53 PM PDT 24
Peak memory 200140 kb
Host smart-c53607d0-02c6-4b80-b5aa-a4ccd8b7302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241086281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1241086281
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2227231887
Short name T19
Test name
Test status
Simulation time 87755053732 ps
CPU time 2058.23 seconds
Started Jul 21 07:18:32 PM PDT 24
Finished Jul 21 07:54:03 PM PDT 24
Peak memory 216108 kb
Host smart-c538cd3f-6435-4685-8266-fabf7daeffc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227231887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2227231887
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.2238903782
Short name T42
Test name
Test status
Simulation time 435237218392 ps
CPU time 662.38 seconds
Started Jul 21 07:17:35 PM PDT 24
Finished Jul 21 07:30:39 PM PDT 24
Peak memory 208532 kb
Host smart-3ca2d945-ccac-4d00-951e-9bb381db0601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238903782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2238903782
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.980570548
Short name T33
Test name
Test status
Simulation time 89895585113 ps
CPU time 730.23 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:25:12 PM PDT 24
Peak memory 216724 kb
Host smart-5ce09318-974f-48df-bd5c-3a865541295c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980570548 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.980570548
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all.1601517453
Short name T115
Test name
Test status
Simulation time 644488662891 ps
CPU time 402.92 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:24:18 PM PDT 24
Peak memory 200192 kb
Host smart-1bcca834-eaa4-42bb-b6fd-8bbee3c9077d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601517453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1601517453
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1844746050
Short name T32
Test name
Test status
Simulation time 343796663124 ps
CPU time 615.24 seconds
Started Jul 21 07:18:54 PM PDT 24
Finished Jul 21 07:29:59 PM PDT 24
Peak memory 220400 kb
Host smart-984c88d3-1187-4cbf-b857-ea576c8a9d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844746050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1844746050
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.910811425
Short name T15
Test name
Test status
Simulation time 38770231044 ps
CPU time 374.75 seconds
Started Jul 21 07:17:48 PM PDT 24
Finished Jul 21 07:25:48 PM PDT 24
Peak memory 216704 kb
Host smart-1e80f83e-de3a-48fb-a5ac-b957c791dd3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910811425 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.910811425
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2895980025
Short name T25
Test name
Test status
Simulation time 446862494 ps
CPU time 0.89 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:12:42 PM PDT 24
Peak memory 218436 kb
Host smart-5042b6f8-9da6-4c97-8c9b-d47811bc62ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895980025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2895980025
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4140372344
Short name T34
Test name
Test status
Simulation time 136188630893 ps
CPU time 1402.42 seconds
Started Jul 21 07:17:47 PM PDT 24
Finished Jul 21 07:42:54 PM PDT 24
Peak memory 200192 kb
Host smart-1af8a39b-b6b3-4584-a001-9fc8151ecdab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140372344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4140372344
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_stress_all.4081591177
Short name T20
Test name
Test status
Simulation time 822661140945 ps
CPU time 171.43 seconds
Started Jul 21 07:13:39 PM PDT 24
Finished Jul 21 07:16:31 PM PDT 24
Peak memory 200164 kb
Host smart-03a4f3c0-76ee-45fb-b456-ea64056e4bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081591177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4081591177
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2165190492
Short name T116
Test name
Test status
Simulation time 252984471642 ps
CPU time 169.63 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:22:57 PM PDT 24
Peak memory 200164 kb
Host smart-265814a2-1ea0-4efb-9be4-11343ec535c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165190492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2165190492
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1592633902
Short name T30
Test name
Test status
Simulation time 267177551435 ps
CPU time 745.98 seconds
Started Jul 21 07:19:06 PM PDT 24
Finished Jul 21 07:32:13 PM PDT 24
Peak memory 224956 kb
Host smart-82268385-e09f-485f-9f18-e15cd84fbabc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592633902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1592633902
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.4251006241
Short name T76
Test name
Test status
Simulation time 193231235653 ps
CPU time 1832.56 seconds
Started Jul 21 07:14:43 PM PDT 24
Finished Jul 21 07:45:16 PM PDT 24
Peak memory 200120 kb
Host smart-d047283b-08d2-4918-a8e8-e029f1bff738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251006241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4251006241
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2254334353
Short name T55
Test name
Test status
Simulation time 129292166302 ps
CPU time 978.08 seconds
Started Jul 21 07:13:05 PM PDT 24
Finished Jul 21 07:29:24 PM PDT 24
Peak memory 226764 kb
Host smart-327f76b3-61b7-4bd1-a201-49fb204c9a34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254334353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2254334353
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2351339107
Short name T158
Test name
Test status
Simulation time 338963321101 ps
CPU time 803.83 seconds
Started Jul 21 07:17:53 PM PDT 24
Finished Jul 21 07:33:05 PM PDT 24
Peak memory 229852 kb
Host smart-ccbabe46-9dc2-4040-84df-a8705bb9dd10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351339107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2351339107
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2895094313
Short name T94
Test name
Test status
Simulation time 422780490 ps
CPU time 1.35 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 200224 kb
Host smart-f90e9279-7c6f-43a1-8dd2-ffc15eafa156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895094313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2895094313
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.473091105
Short name T132
Test name
Test status
Simulation time 121537803427 ps
CPU time 39.37 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:15:15 PM PDT 24
Peak memory 200104 kb
Host smart-0364787d-1803-4a44-8527-22e4622cc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473091105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.473091105
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4123243413
Short name T131
Test name
Test status
Simulation time 132902828900 ps
CPU time 496.36 seconds
Started Jul 21 07:20:14 PM PDT 24
Finished Jul 21 07:28:31 PM PDT 24
Peak memory 200152 kb
Host smart-4031f470-a949-4dde-af33-d1b458876e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123243413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4123243413
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2946987114
Short name T322
Test name
Test status
Simulation time 12594045 ps
CPU time 0.53 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:13:23 PM PDT 24
Peak memory 195068 kb
Host smart-cbfd858e-25b7-4d06-97ee-cfb5296dcffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946987114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2946987114
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3392064806
Short name T63
Test name
Test status
Simulation time 13944273 ps
CPU time 0.57 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 196336 kb
Host smart-674514bd-8692-47a2-8750-96e0bd7b1028
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392064806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3392064806
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1218718353
Short name T128
Test name
Test status
Simulation time 176679696286 ps
CPU time 110.57 seconds
Started Jul 21 07:19:43 PM PDT 24
Finished Jul 21 07:21:42 PM PDT 24
Peak memory 200160 kb
Host smart-c0993a6e-ceba-4c24-8139-cb28c707c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218718353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1218718353
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_full.412550661
Short name T124
Test name
Test status
Simulation time 40211802625 ps
CPU time 67.7 seconds
Started Jul 21 07:14:40 PM PDT 24
Finished Jul 21 07:15:49 PM PDT 24
Peak memory 200152 kb
Host smart-82de84b6-31a6-4fb1-9a8e-989982a6242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412550661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.412550661
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1939209747
Short name T106
Test name
Test status
Simulation time 389375459777 ps
CPU time 1315.11 seconds
Started Jul 21 07:18:37 PM PDT 24
Finished Jul 21 07:41:39 PM PDT 24
Peak memory 218736 kb
Host smart-e5c712ba-6f6e-4cab-b65f-bfd63fdf9bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939209747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1939209747
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_noise_filter.457191905
Short name T249
Test name
Test status
Simulation time 145578943488 ps
CPU time 116.47 seconds
Started Jul 21 07:15:16 PM PDT 24
Finished Jul 21 07:17:13 PM PDT 24
Peak memory 200240 kb
Host smart-3e7cdc70-b8cf-4d3b-b133-61b4da2658e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457191905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.457191905
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3162624659
Short name T129
Test name
Test status
Simulation time 114822910268 ps
CPU time 232.9 seconds
Started Jul 21 07:20:12 PM PDT 24
Finished Jul 21 07:24:06 PM PDT 24
Peak memory 200236 kb
Host smart-4f61466f-0359-4177-85e1-414469a55a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162624659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3162624659
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4068465027
Short name T121
Test name
Test status
Simulation time 241827341614 ps
CPU time 197.83 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:16:19 PM PDT 24
Peak memory 200172 kb
Host smart-db59a042-06dc-4644-abf1-11fb710ddf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068465027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4068465027
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3252174121
Short name T99
Test name
Test status
Simulation time 89722829 ps
CPU time 1.33 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 200280 kb
Host smart-263e78e9-6677-4d47-be2a-219bb833cf91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252174121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3252174121
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/35.uart_stress_all.3172563871
Short name T114
Test name
Test status
Simulation time 176897325596 ps
CPU time 289.02 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:20:44 PM PDT 24
Peak memory 200136 kb
Host smart-1df89854-9924-4414-a645-50747b352046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172563871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3172563871
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3616974047
Short name T293
Test name
Test status
Simulation time 48639669852 ps
CPU time 17.31 seconds
Started Jul 21 07:14:53 PM PDT 24
Finished Jul 21 07:15:11 PM PDT 24
Peak memory 200208 kb
Host smart-f3a3efc4-3464-4046-915a-53a463398041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616974047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3616974047
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.444532187
Short name T162
Test name
Test status
Simulation time 142547068007 ps
CPU time 642.36 seconds
Started Jul 21 07:19:17 PM PDT 24
Finished Jul 21 07:30:32 PM PDT 24
Peak memory 211220 kb
Host smart-51c7ec07-aae1-4230-b60d-7f7940e99440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444532187 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.444532187
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2376977722
Short name T126
Test name
Test status
Simulation time 42718766640 ps
CPU time 39.27 seconds
Started Jul 21 07:19:27 PM PDT 24
Finished Jul 21 07:20:29 PM PDT 24
Peak memory 200196 kb
Host smart-d6bda57d-21e4-49f1-b6e7-2bde11216d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376977722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2376977722
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.385127306
Short name T160
Test name
Test status
Simulation time 137516845406 ps
CPU time 59.47 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:50 PM PDT 24
Peak memory 200084 kb
Host smart-2abd451e-9398-430f-b4ef-daa771695dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385127306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.385127306
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.215255106
Short name T142
Test name
Test status
Simulation time 29670842704 ps
CPU time 13.85 seconds
Started Jul 21 07:19:37 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 199764 kb
Host smart-fac1c67c-d904-4ec8-8615-89ddc8ce6a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215255106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.215255106
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1109941887
Short name T51
Test name
Test status
Simulation time 50957750099 ps
CPU time 146.75 seconds
Started Jul 21 07:20:18 PM PDT 24
Finished Jul 21 07:22:47 PM PDT 24
Peak memory 200160 kb
Host smart-3b67fbef-32e2-42c1-b83b-15b4bdcb3792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109941887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1109941887
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.38059828
Short name T172
Test name
Test status
Simulation time 159214506535 ps
CPU time 220.06 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:17:39 PM PDT 24
Peak memory 200216 kb
Host smart-73f4d323-d17e-4597-83f3-90653077ba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38059828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.38059828
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.939076631
Short name T155
Test name
Test status
Simulation time 36547509473 ps
CPU time 14.63 seconds
Started Jul 21 07:20:50 PM PDT 24
Finished Jul 21 07:21:41 PM PDT 24
Peak memory 200124 kb
Host smart-66e2d851-6fe7-4614-836e-4bd687f45da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939076631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.939076631
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3738277230
Short name T187
Test name
Test status
Simulation time 78086093385 ps
CPU time 35.23 seconds
Started Jul 21 07:19:32 PM PDT 24
Finished Jul 21 07:20:25 PM PDT 24
Peak memory 200024 kb
Host smart-0e3dc9be-4043-4186-8b0b-b29e7c2766d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738277230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3738277230
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.3861063377
Short name T164
Test name
Test status
Simulation time 180240939731 ps
CPU time 59.42 seconds
Started Jul 21 07:13:52 PM PDT 24
Finished Jul 21 07:14:51 PM PDT 24
Peak memory 200248 kb
Host smart-b7cb3f6f-bbc4-4381-8f97-62af768a09eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861063377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3861063377
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.619464818
Short name T206
Test name
Test status
Simulation time 124069550319 ps
CPU time 103.15 seconds
Started Jul 21 07:20:10 PM PDT 24
Finished Jul 21 07:21:54 PM PDT 24
Peak memory 200208 kb
Host smart-2b4160ef-9d2a-4e07-8ea4-12ababc2cfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619464818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.619464818
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1134983639
Short name T173
Test name
Test status
Simulation time 23670494859 ps
CPU time 45.12 seconds
Started Jul 21 07:20:36 PM PDT 24
Finished Jul 21 07:21:29 PM PDT 24
Peak memory 200176 kb
Host smart-3738b2d7-49e6-4542-902c-6b5d265a12d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134983639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1134983639
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3538371514
Short name T169
Test name
Test status
Simulation time 109918385018 ps
CPU time 30.06 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:21:13 PM PDT 24
Peak memory 200204 kb
Host smart-73e0805b-c993-4e3e-a69e-dbf33eac2fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538371514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3538371514
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1416105789
Short name T194
Test name
Test status
Simulation time 51146666635 ps
CPU time 40.45 seconds
Started Jul 21 07:20:40 PM PDT 24
Finished Jul 21 07:21:35 PM PDT 24
Peak memory 200060 kb
Host smart-92d6b4c1-090b-42a0-96ff-a35d51917e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416105789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1416105789
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4030100269
Short name T197
Test name
Test status
Simulation time 127452354893 ps
CPU time 96.32 seconds
Started Jul 21 07:18:12 PM PDT 24
Finished Jul 21 07:21:22 PM PDT 24
Peak memory 200220 kb
Host smart-2b94be28-c182-4bf5-8d14-4459b3c8cdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030100269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4030100269
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.27887764
Short name T221
Test name
Test status
Simulation time 2031186637655 ps
CPU time 1415.46 seconds
Started Jul 21 07:18:37 PM PDT 24
Finished Jul 21 07:43:19 PM PDT 24
Peak memory 224888 kb
Host smart-50bf5c64-7a11-4092-847e-a071162357c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27887764 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.27887764
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4263358499
Short name T93
Test name
Test status
Simulation time 321382653 ps
CPU time 1.3 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 200184 kb
Host smart-116df557-91e2-4a1e-b80b-27f815274953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263358499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4263358499
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1937731323
Short name T134
Test name
Test status
Simulation time 124263167887 ps
CPU time 41.78 seconds
Started Jul 21 07:19:27 PM PDT 24
Finished Jul 21 07:20:31 PM PDT 24
Peak memory 200220 kb
Host smart-3bd147fb-e9de-4eeb-9a15-2f654ad329fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937731323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1937731323
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3774928206
Short name T183
Test name
Test status
Simulation time 59622091301 ps
CPU time 25.91 seconds
Started Jul 21 07:19:39 PM PDT 24
Finished Jul 21 07:20:17 PM PDT 24
Peak memory 200160 kb
Host smart-7f1574b1-68c1-4496-aedc-a107b567b201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774928206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3774928206
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2179548506
Short name T1010
Test name
Test status
Simulation time 15209115301 ps
CPU time 21.63 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:14:02 PM PDT 24
Peak memory 200148 kb
Host smart-869f1562-6b6e-4c93-aafa-d7b28306da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179548506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2179548506
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1930110009
Short name T265
Test name
Test status
Simulation time 46252953424 ps
CPU time 12.61 seconds
Started Jul 21 07:13:52 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 200168 kb
Host smart-b8ab1f3d-7ba1-427b-9608-56b31add9462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930110009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1930110009
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.621982666
Short name T212
Test name
Test status
Simulation time 57699926556 ps
CPU time 93.1 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:21:41 PM PDT 24
Peak memory 200148 kb
Host smart-64763ffc-ba1d-419c-9b28-cba541aeed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621982666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.621982666
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_perf.3667437997
Short name T391
Test name
Test status
Simulation time 11456030415 ps
CPU time 179.77 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:17:08 PM PDT 24
Peak memory 200132 kb
Host smart-45602416-4a73-41a6-8d9a-5e99cdc6d974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667437997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3667437997
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2156815924
Short name T235
Test name
Test status
Simulation time 156377453332 ps
CPU time 112.74 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:22:34 PM PDT 24
Peak memory 200176 kb
Host smart-b257d5a0-70fb-43cb-846e-2ff6d476bd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156815924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2156815924
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1309523941
Short name T110
Test name
Test status
Simulation time 186271147754 ps
CPU time 111.14 seconds
Started Jul 21 07:20:53 PM PDT 24
Finished Jul 21 07:23:22 PM PDT 24
Peak memory 200216 kb
Host smart-8117fa5c-5d47-49fa-9c97-454a8cf55f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309523941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1309523941
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.748499169
Short name T238
Test name
Test status
Simulation time 187168117199 ps
CPU time 62.08 seconds
Started Jul 21 07:18:07 PM PDT 24
Finished Jul 21 07:20:46 PM PDT 24
Peak memory 200204 kb
Host smart-49b75b2a-a079-4176-98cb-532280cba823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748499169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.748499169
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_perf.2410926642
Short name T11
Test name
Test status
Simulation time 12440734100 ps
CPU time 176.85 seconds
Started Jul 21 07:12:35 PM PDT 24
Finished Jul 21 07:15:32 PM PDT 24
Peak memory 200172 kb
Host smart-c02f8fad-a1b0-4b31-a535-614f50a15408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410926642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2410926642
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/12.uart_stress_all.4149635299
Short name T201
Test name
Test status
Simulation time 120364433234 ps
CPU time 88.86 seconds
Started Jul 21 07:13:31 PM PDT 24
Finished Jul 21 07:15:00 PM PDT 24
Peak memory 200156 kb
Host smart-f82096a0-539a-48f8-847b-e665b08c2ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149635299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4149635299
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.543394186
Short name T219
Test name
Test status
Simulation time 44603599579 ps
CPU time 14.09 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 200044 kb
Host smart-6d33afe1-5dd6-47ae-be64-e38c629775b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543394186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.543394186
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1186117450
Short name T301
Test name
Test status
Simulation time 21207543326 ps
CPU time 46.86 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:14:22 PM PDT 24
Peak memory 200140 kb
Host smart-df8b3309-e6f7-42bf-a6a5-66d94461c5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186117450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1186117450
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2484908785
Short name T223
Test name
Test status
Simulation time 165432234169 ps
CPU time 31.1 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:21 PM PDT 24
Peak memory 200208 kb
Host smart-2f8bd888-740f-486c-b3b1-7a64eb857a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484908785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2484908785
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3542508743
Short name T217
Test name
Test status
Simulation time 80246536127 ps
CPU time 32.51 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:20:23 PM PDT 24
Peak memory 200132 kb
Host smart-179def38-9516-4d0a-87be-b4c40f8f9435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542508743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3542508743
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.531256780
Short name T163
Test name
Test status
Simulation time 80232665288 ps
CPU time 27.13 seconds
Started Jul 21 07:20:14 PM PDT 24
Finished Jul 21 07:20:41 PM PDT 24
Peak memory 200068 kb
Host smart-efc536fd-55ff-41f5-8dc4-1aa0e220e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531256780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.531256780
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1648038947
Short name T241
Test name
Test status
Simulation time 210550348532 ps
CPU time 146.86 seconds
Started Jul 21 07:20:23 PM PDT 24
Finished Jul 21 07:22:51 PM PDT 24
Peak memory 200200 kb
Host smart-448fcd2e-9fa9-4ba8-9bd6-81387d5ed238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648038947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1648038947
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.623948622
Short name T233
Test name
Test status
Simulation time 71491995676 ps
CPU time 51.72 seconds
Started Jul 21 07:20:30 PM PDT 24
Finished Jul 21 07:21:27 PM PDT 24
Peak memory 200152 kb
Host smart-86708f71-35aa-4ae1-964d-2d93340fbf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623948622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.623948622
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4136927517
Short name T214
Test name
Test status
Simulation time 46096923713 ps
CPU time 16.38 seconds
Started Jul 21 07:20:28 PM PDT 24
Finished Jul 21 07:20:48 PM PDT 24
Peak memory 200136 kb
Host smart-26e782bd-4ef7-4d6f-99dc-742f726c955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136927517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4136927517
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3315330213
Short name T199
Test name
Test status
Simulation time 30626162797 ps
CPU time 24.52 seconds
Started Jul 21 07:20:52 PM PDT 24
Finished Jul 21 07:21:55 PM PDT 24
Peak memory 200220 kb
Host smart-5001bc15-627b-47ca-a553-bfeea85a67d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315330213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3315330213
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1810157809
Short name T138
Test name
Test status
Simulation time 160650519428 ps
CPU time 230.64 seconds
Started Jul 21 07:15:48 PM PDT 24
Finished Jul 21 07:19:48 PM PDT 24
Peak memory 200176 kb
Host smart-febc57eb-f662-4325-ab75-198265d386ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810157809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1810157809
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2963046232
Short name T231
Test name
Test status
Simulation time 82007930350 ps
CPU time 30.02 seconds
Started Jul 21 07:18:08 PM PDT 24
Finished Jul 21 07:20:11 PM PDT 24
Peak memory 200220 kb
Host smart-e40ff930-fc7c-4f46-8879-af4eaa0c286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963046232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2963046232
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1793616916
Short name T237
Test name
Test status
Simulation time 44697298322 ps
CPU time 65.72 seconds
Started Jul 21 07:18:16 PM PDT 24
Finished Jul 21 07:20:48 PM PDT 24
Peak memory 200176 kb
Host smart-1aa965e2-795c-49ac-816b-1bc9624b99c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793616916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1793616916
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4061686165
Short name T236
Test name
Test status
Simulation time 71284555042 ps
CPU time 28.8 seconds
Started Jul 21 07:18:19 PM PDT 24
Finished Jul 21 07:20:15 PM PDT 24
Peak memory 200124 kb
Host smart-6f6f9026-59df-4d13-9e5e-4a158b222faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061686165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4061686165
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4226270044
Short name T200
Test name
Test status
Simulation time 49521092431 ps
CPU time 18.62 seconds
Started Jul 21 07:18:37 PM PDT 24
Finished Jul 21 07:20:03 PM PDT 24
Peak memory 200148 kb
Host smart-98926f28-6725-4206-9818-2470ba1fb34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226270044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4226270044
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2741878990
Short name T71
Test name
Test status
Simulation time 34096534 ps
CPU time 0.79 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 197156 kb
Host smart-9847bcad-7e17-42d9-bf4f-d2fc9fff69df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741878990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2741878990
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.408610702
Short name T1302
Test name
Test status
Simulation time 115897869 ps
CPU time 2.21 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 198644 kb
Host smart-4c091de2-ebab-4889-86c9-a7930ce71dd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408610702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.408610702
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3176073844
Short name T65
Test name
Test status
Simulation time 15068654 ps
CPU time 0.6 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 196280 kb
Host smart-7434b468-649c-4ca4-9c46-b97cc6d81e1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176073844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3176073844
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1266451398
Short name T1286
Test name
Test status
Simulation time 117605788 ps
CPU time 1.12 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 200996 kb
Host smart-ce6352cb-93b5-4e77-9ef0-2193759d7af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266451398 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1266451398
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3665773442
Short name T88
Test name
Test status
Simulation time 14622247 ps
CPU time 0.56 seconds
Started Jul 21 07:06:16 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 196380 kb
Host smart-f56e2fbd-01ab-4490-a0e4-e8f4e0993838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665773442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3665773442
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.899983386
Short name T1186
Test name
Test status
Simulation time 13718507 ps
CPU time 0.55 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 195212 kb
Host smart-8f096521-784d-48c9-a3b1-f9eb91d430b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899983386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.899983386
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2226232095
Short name T1273
Test name
Test status
Simulation time 75761555 ps
CPU time 0.66 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 197720 kb
Host smart-7bcaa0e8-262d-405e-8192-2b2b6f1007e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226232095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2226232095
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1331216669
Short name T1174
Test name
Test status
Simulation time 90811944 ps
CPU time 1.41 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 200952 kb
Host smart-d737b951-5086-456c-b397-86beda19fcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331216669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1331216669
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1189676315
Short name T1260
Test name
Test status
Simulation time 183379582 ps
CPU time 0.76 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 197236 kb
Host smart-61ba1a56-62ba-4cb4-9bf0-54845035ee69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189676315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1189676315
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1141926960
Short name T1197
Test name
Test status
Simulation time 222071818 ps
CPU time 2.23 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 198708 kb
Host smart-fad6bdd3-2e1f-4638-89f4-14576416ef5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141926960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1141926960
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1358480187
Short name T1237
Test name
Test status
Simulation time 19338904 ps
CPU time 0.59 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 196268 kb
Host smart-9439a5ba-429e-45d2-bf52-9b3c098f7d74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358480187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1358480187
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3957014646
Short name T1181
Test name
Test status
Simulation time 47841013 ps
CPU time 0.76 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 200632 kb
Host smart-313c62af-acb8-43dd-b128-f73260d8598c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957014646 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3957014646
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3374755979
Short name T1290
Test name
Test status
Simulation time 12903653 ps
CPU time 0.56 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 195312 kb
Host smart-cf122fef-caed-41b0-9ec0-bd7cd5644511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374755979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3374755979
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1367183343
Short name T1299
Test name
Test status
Simulation time 58738162 ps
CPU time 0.75 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 197956 kb
Host smart-12370253-be8e-43f1-99ff-ddc79332df36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367183343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1367183343
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3796831562
Short name T1229
Test name
Test status
Simulation time 120276665 ps
CPU time 2.05 seconds
Started Jul 21 07:06:15 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 200932 kb
Host smart-527613e0-9b99-48b6-9308-113baa9ee387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796831562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3796831562
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3692613545
Short name T1232
Test name
Test status
Simulation time 45462181 ps
CPU time 0.98 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 199928 kb
Host smart-aef2a6f4-b02f-4d14-906c-95c33e9a6b69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692613545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3692613545
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1508251344
Short name T1256
Test name
Test status
Simulation time 38280737 ps
CPU time 0.92 seconds
Started Jul 21 07:06:19 PM PDT 24
Finished Jul 21 07:06:20 PM PDT 24
Peak memory 200672 kb
Host smart-4567f793-ec51-4cd9-977e-7f024b89c583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508251344 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1508251344
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1932309499
Short name T1298
Test name
Test status
Simulation time 26332263 ps
CPU time 0.56 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 196320 kb
Host smart-7aa75370-9243-4dec-931f-88a84347e8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932309499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1932309499
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.232213078
Short name T1209
Test name
Test status
Simulation time 14130590 ps
CPU time 0.56 seconds
Started Jul 21 07:06:38 PM PDT 24
Finished Jul 21 07:06:39 PM PDT 24
Peak memory 195280 kb
Host smart-324c52cd-de95-4449-971b-44dd3eca1eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232213078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.232213078
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2102686849
Short name T1204
Test name
Test status
Simulation time 36416690 ps
CPU time 0.61 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 196480 kb
Host smart-a657f41d-9f78-43f5-a121-3cfde6b49138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102686849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2102686849
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1613239027
Short name T1304
Test name
Test status
Simulation time 118410853 ps
CPU time 1.09 seconds
Started Jul 21 07:06:52 PM PDT 24
Finished Jul 21 07:06:54 PM PDT 24
Peak memory 200904 kb
Host smart-c139b26c-6f6e-4ffe-a2ee-99f469956a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613239027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1613239027
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3747752436
Short name T1295
Test name
Test status
Simulation time 219570828 ps
CPU time 1.21 seconds
Started Jul 21 07:06:37 PM PDT 24
Finished Jul 21 07:06:38 PM PDT 24
Peak memory 200312 kb
Host smart-3d884ca9-07fd-4dd7-8d0a-885a4176a146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747752436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3747752436
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3103388277
Short name T1240
Test name
Test status
Simulation time 27452278 ps
CPU time 1.22 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:28 PM PDT 24
Peak memory 200964 kb
Host smart-c932b148-b801-4ea0-9f15-aeb286b1e893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103388277 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3103388277
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3817597340
Short name T67
Test name
Test status
Simulation time 12550435 ps
CPU time 0.57 seconds
Started Jul 21 07:06:33 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 196288 kb
Host smart-1fd8f74a-af43-4d6f-8d5f-3f8304b4b325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817597340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3817597340
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2494095195
Short name T1201
Test name
Test status
Simulation time 12622650 ps
CPU time 0.54 seconds
Started Jul 21 07:06:25 PM PDT 24
Finished Jul 21 07:06:27 PM PDT 24
Peak memory 195164 kb
Host smart-a68af868-6104-4414-b8d4-54809cbaad31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494095195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2494095195
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1046976871
Short name T1248
Test name
Test status
Simulation time 102565636 ps
CPU time 0.65 seconds
Started Jul 21 07:06:31 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 195460 kb
Host smart-1f19920e-0eee-46df-9b9f-7e6eb14888ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046976871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1046976871
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.223432641
Short name T1291
Test name
Test status
Simulation time 27000716 ps
CPU time 1.33 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 200888 kb
Host smart-16338779-7bbf-4fb5-83d4-5deb20fbb86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223432641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.223432641
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2321530992
Short name T91
Test name
Test status
Simulation time 63274064 ps
CPU time 0.94 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 199676 kb
Host smart-f05a5a48-082a-470a-b581-cc1aef057617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321530992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2321530992
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.356473665
Short name T1211
Test name
Test status
Simulation time 29111337 ps
CPU time 0.77 seconds
Started Jul 21 07:06:33 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 200708 kb
Host smart-317c35ea-5c8c-4ea3-9a80-f9d6f409b035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356473665 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.356473665
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3191940090
Short name T1252
Test name
Test status
Simulation time 23877773 ps
CPU time 0.61 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 196352 kb
Host smart-229589dc-b7aa-4e51-8bad-48ee50c25ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191940090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3191940090
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2344489506
Short name T1308
Test name
Test status
Simulation time 13685652 ps
CPU time 0.61 seconds
Started Jul 21 07:06:32 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 195320 kb
Host smart-706cc424-6008-4eb1-a6d2-45dea609ab64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344489506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2344489506
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2795146084
Short name T1234
Test name
Test status
Simulation time 112037968 ps
CPU time 0.74 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 197460 kb
Host smart-c806a9b0-e0b4-406c-9fdd-84077e09ad4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795146084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2795146084
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.760392002
Short name T1264
Test name
Test status
Simulation time 621097704 ps
CPU time 2.63 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 200880 kb
Host smart-0b80cb54-b821-4f2c-8d16-f211f27eb500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760392002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.760392002
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3943358692
Short name T1297
Test name
Test status
Simulation time 26181084 ps
CPU time 0.76 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 199452 kb
Host smart-e3f86e12-4fc0-4cf5-a211-bbc3f5ea588f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943358692 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3943358692
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.739388504
Short name T84
Test name
Test status
Simulation time 28820907 ps
CPU time 0.67 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 196580 kb
Host smart-e44257f9-3a6d-48b4-a7b2-fcb85ace7c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739388504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.739388504
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4256416137
Short name T1225
Test name
Test status
Simulation time 21432557 ps
CPU time 0.59 seconds
Started Jul 21 07:06:36 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 195352 kb
Host smart-7bfabd72-533c-4f43-849a-3917e3c9c5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256416137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4256416137
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.44505905
Short name T1247
Test name
Test status
Simulation time 118498223 ps
CPU time 0.72 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 198028 kb
Host smart-73da7e16-bf1f-4449-937b-4e1b6710b795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44505905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_
outstanding.44505905
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1684768497
Short name T1199
Test name
Test status
Simulation time 27052326 ps
CPU time 1.32 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 200968 kb
Host smart-ea22d1de-b775-4e7c-8609-96d3ce3b6262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684768497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1684768497
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3943832463
Short name T1205
Test name
Test status
Simulation time 56035285 ps
CPU time 0.76 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 200732 kb
Host smart-d2d90548-2390-45b4-8c74-2cdf3f4115a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943832463 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3943832463
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.479081151
Short name T66
Test name
Test status
Simulation time 34664864 ps
CPU time 0.61 seconds
Started Jul 21 07:06:34 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 196320 kb
Host smart-7ea94977-2961-4942-9f91-f7b00ad4f8cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479081151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.479081151
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.168039207
Short name T1268
Test name
Test status
Simulation time 35182666 ps
CPU time 0.56 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 195292 kb
Host smart-514314ff-9dc7-4073-a201-30111a91432e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168039207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.168039207
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4943927
Short name T1203
Test name
Test status
Simulation time 20830980 ps
CPU time 0.66 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 197380 kb
Host smart-6e7f495b-6880-4e82-9afc-70b9a3a86294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4943927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_o
utstanding.4943927
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1477936802
Short name T1230
Test name
Test status
Simulation time 1723460939 ps
CPU time 2.5 seconds
Started Jul 21 07:06:46 PM PDT 24
Finished Jul 21 07:06:49 PM PDT 24
Peak memory 200972 kb
Host smart-aa4f0c90-5bd7-4fcc-bd2a-4d7a81c3c2b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477936802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1477936802
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4152521286
Short name T1233
Test name
Test status
Simulation time 176148796 ps
CPU time 0.99 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 199900 kb
Host smart-65946b06-b57b-4c95-bdbf-f326c75f653a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152521286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4152521286
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.243876867
Short name T1287
Test name
Test status
Simulation time 45908651 ps
CPU time 0.72 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 199176 kb
Host smart-3531ead5-1625-4a62-a476-5a16f81e4701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243876867 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.243876867
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1380880571
Short name T1303
Test name
Test status
Simulation time 15180784 ps
CPU time 0.62 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 196568 kb
Host smart-7dfa2f50-7ea2-4d42-9a6c-774bf050aef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380880571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1380880571
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.352830355
Short name T1193
Test name
Test status
Simulation time 14339373 ps
CPU time 0.57 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 194724 kb
Host smart-90e99873-abef-4945-8349-8b6744bde70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352830355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.352830355
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3785600538
Short name T1241
Test name
Test status
Simulation time 76758603 ps
CPU time 0.74 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 197492 kb
Host smart-f3d0c5cd-45d0-4d81-93bc-644aa1a57370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785600538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3785600538
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3776878844
Short name T1213
Test name
Test status
Simulation time 34457712 ps
CPU time 1.44 seconds
Started Jul 21 07:06:31 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 200944 kb
Host smart-0d9a9843-50c5-46c9-940c-35e0c033d918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776878844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3776878844
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.923463951
Short name T98
Test name
Test status
Simulation time 52643675 ps
CPU time 0.99 seconds
Started Jul 21 07:06:34 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 200040 kb
Host smart-7bf9ff56-1b13-4b1e-bbdd-b8c60e30436e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923463951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.923463951
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3169891539
Short name T1262
Test name
Test status
Simulation time 131243972 ps
CPU time 0.65 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 198100 kb
Host smart-50c2623b-25d7-4510-b20d-020da14db372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169891539 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3169891539
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4027642718
Short name T81
Test name
Test status
Simulation time 29505606 ps
CPU time 0.62 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 196308 kb
Host smart-62a8c641-3415-47d6-ab99-bbbe3374d56d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027642718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4027642718
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.826719531
Short name T1263
Test name
Test status
Simulation time 171662935 ps
CPU time 0.57 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 195460 kb
Host smart-2ba9c1ec-143e-4a31-bf55-003fa2d56672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826719531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.826719531
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3890407199
Short name T86
Test name
Test status
Simulation time 14509532 ps
CPU time 0.69 seconds
Started Jul 21 07:06:34 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 195672 kb
Host smart-7efbcbe4-b2cc-421e-bada-756247456f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890407199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3890407199
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.647529396
Short name T1278
Test name
Test status
Simulation time 40991972 ps
CPU time 2.05 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 201032 kb
Host smart-e48987bd-8e4a-495f-90f0-806edfae8c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647529396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.647529396
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.219187600
Short name T1288
Test name
Test status
Simulation time 97174371 ps
CPU time 0.99 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 199884 kb
Host smart-524365f0-24dd-48e0-9600-517efb56fef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219187600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.219187600
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1421407687
Short name T1266
Test name
Test status
Simulation time 143206447 ps
CPU time 0.78 seconds
Started Jul 21 07:06:25 PM PDT 24
Finished Jul 21 07:06:28 PM PDT 24
Peak memory 200688 kb
Host smart-7e040724-1b3e-43f6-a2f2-620d67f1eb8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421407687 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1421407687
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3785925012
Short name T1224
Test name
Test status
Simulation time 17892522 ps
CPU time 0.56 seconds
Started Jul 21 07:06:37 PM PDT 24
Finished Jul 21 07:06:38 PM PDT 24
Peak memory 196384 kb
Host smart-ca7a1176-ebd6-46d8-9614-dde674a9e0f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785925012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3785925012
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2917810288
Short name T1238
Test name
Test status
Simulation time 22638357 ps
CPU time 0.56 seconds
Started Jul 21 07:06:40 PM PDT 24
Finished Jul 21 07:06:42 PM PDT 24
Peak memory 195356 kb
Host smart-3cc4137a-9b72-4a98-ab2c-646306faed93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917810288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2917810288
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1161304991
Short name T1221
Test name
Test status
Simulation time 48093596 ps
CPU time 0.68 seconds
Started Jul 21 07:06:45 PM PDT 24
Finished Jul 21 07:06:46 PM PDT 24
Peak memory 197608 kb
Host smart-5aa7b6d2-8ec7-4348-84cb-9d464ddaa051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161304991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1161304991
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1734972737
Short name T1246
Test name
Test status
Simulation time 136015519 ps
CPU time 1.82 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 200992 kb
Host smart-f2fd582a-2f7a-492e-bfb9-d5a5b07c939b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734972737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1734972737
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2715953828
Short name T1276
Test name
Test status
Simulation time 137227741 ps
CPU time 1.43 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 200208 kb
Host smart-fd2757a2-a0b5-490a-87c4-7183e83146fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715953828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2715953828
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.73799599
Short name T1271
Test name
Test status
Simulation time 27461623 ps
CPU time 0.68 seconds
Started Jul 21 07:06:56 PM PDT 24
Finished Jul 21 07:06:57 PM PDT 24
Peak memory 199060 kb
Host smart-5fe02083-b31a-4ecb-9986-6e4a17418d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73799599 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.73799599
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.990142036
Short name T1220
Test name
Test status
Simulation time 40342244 ps
CPU time 0.61 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 195956 kb
Host smart-4b01c750-cd73-4a25-a4db-af73a5f700bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990142036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.990142036
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2686295174
Short name T1245
Test name
Test status
Simulation time 40909658 ps
CPU time 0.57 seconds
Started Jul 21 07:06:36 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 195340 kb
Host smart-f9acd57b-9512-4a0d-b936-5849821820fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686295174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2686295174
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3862251121
Short name T1255
Test name
Test status
Simulation time 16412798 ps
CPU time 0.66 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 196476 kb
Host smart-35084c4c-b699-4d7b-b45b-c435f98d1323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862251121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3862251121
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.484019510
Short name T1251
Test name
Test status
Simulation time 276523685 ps
CPU time 1.6 seconds
Started Jul 21 07:06:32 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 200948 kb
Host smart-6b1f43e0-ea3d-4cce-96ec-6e7e4ed16658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484019510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.484019510
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1911233977
Short name T97
Test name
Test status
Simulation time 94297587 ps
CPU time 1.29 seconds
Started Jul 21 07:06:31 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 200108 kb
Host smart-15b28b5f-9ff8-415d-8e54-e7ca8a933047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911233977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1911233977
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1677898843
Short name T1184
Test name
Test status
Simulation time 140953140 ps
CPU time 0.82 seconds
Started Jul 21 07:06:42 PM PDT 24
Finished Jul 21 07:06:43 PM PDT 24
Peak memory 200724 kb
Host smart-26e52302-7339-448d-910c-2616fbd493d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677898843 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1677898843
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1507467514
Short name T79
Test name
Test status
Simulation time 37243251 ps
CPU time 0.63 seconds
Started Jul 21 07:06:45 PM PDT 24
Finished Jul 21 07:06:46 PM PDT 24
Peak memory 196304 kb
Host smart-c9a38228-a7e9-4d53-860d-83668892936d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507467514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1507467514
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1030178198
Short name T1183
Test name
Test status
Simulation time 41613338 ps
CPU time 0.56 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:41 PM PDT 24
Peak memory 195312 kb
Host smart-db8b0f43-39c2-4cf9-918a-caed246dda09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030178198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1030178198
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.696741263
Short name T1284
Test name
Test status
Simulation time 86921359 ps
CPU time 0.77 seconds
Started Jul 21 07:06:59 PM PDT 24
Finished Jul 21 07:07:00 PM PDT 24
Peak memory 198140 kb
Host smart-dbac2001-794d-47bc-90ae-2730057cf354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696741263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.696741263
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1443557762
Short name T1223
Test name
Test status
Simulation time 328579596 ps
CPU time 1.98 seconds
Started Jul 21 07:06:41 PM PDT 24
Finished Jul 21 07:06:43 PM PDT 24
Peak memory 200992 kb
Host smart-7d05ede7-a1b2-476b-8225-ea3f02e2abb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443557762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1443557762
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4149574608
Short name T1216
Test name
Test status
Simulation time 307512783 ps
CPU time 1.26 seconds
Started Jul 21 07:06:40 PM PDT 24
Finished Jul 21 07:06:42 PM PDT 24
Peak memory 200052 kb
Host smart-79c43f79-3003-4802-8bc3-d7c20c2873e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149574608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4149574608
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.545383130
Short name T1300
Test name
Test status
Simulation time 26421045 ps
CPU time 0.78 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 197340 kb
Host smart-3ea4ae55-a691-4988-80b6-bbdf2b2b9a88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545383130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.545383130
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1632676083
Short name T70
Test name
Test status
Simulation time 865832609 ps
CPU time 2.63 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 198636 kb
Host smart-c865f657-74a5-4f80-99f9-5afb9002bf5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632676083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1632676083
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3953192565
Short name T1294
Test name
Test status
Simulation time 37959986 ps
CPU time 0.61 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 196320 kb
Host smart-00649009-9daf-418a-b59d-b23bd579cd54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953192565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3953192565
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2456436460
Short name T1178
Test name
Test status
Simulation time 63124366 ps
CPU time 0.74 seconds
Started Jul 21 07:06:32 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 199260 kb
Host smart-e5ff4e0e-7163-457c-9745-bd6f539daf0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456436460 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2456436460
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.280149632
Short name T1208
Test name
Test status
Simulation time 14944739 ps
CPU time 0.61 seconds
Started Jul 21 07:06:20 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 196360 kb
Host smart-1b6b37f8-43c1-409f-b49c-82ecccbdebd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280149632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.280149632
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3111551474
Short name T1244
Test name
Test status
Simulation time 40180853 ps
CPU time 0.58 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 195204 kb
Host smart-7038c97f-0826-488d-9b3b-d597828a2ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111551474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3111551474
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1077750224
Short name T85
Test name
Test status
Simulation time 73335382 ps
CPU time 0.74 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:27 PM PDT 24
Peak memory 198484 kb
Host smart-17589fd5-80aa-45d6-b5d0-0fda79395d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077750224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1077750224
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.264412420
Short name T1222
Test name
Test status
Simulation time 88464645 ps
CPU time 1.58 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:24 PM PDT 24
Peak memory 200888 kb
Host smart-e0919023-92d3-400c-8ae2-58c448802212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264412420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.264412420
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.36747360
Short name T1277
Test name
Test status
Simulation time 169039776 ps
CPU time 0.87 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 199672 kb
Host smart-80dc5577-594e-4ca1-afe5-6eb3dd760a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.36747360
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2537535315
Short name T1306
Test name
Test status
Simulation time 12027284 ps
CPU time 0.59 seconds
Started Jul 21 07:06:42 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 195308 kb
Host smart-fb8f7760-8689-4003-a10f-af922b3f1afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537535315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2537535315
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1879457607
Short name T1188
Test name
Test status
Simulation time 12737861 ps
CPU time 0.62 seconds
Started Jul 21 07:06:43 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 195308 kb
Host smart-60cdf2b8-36f7-4aaa-b592-3cb20b226e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879457607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1879457607
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.818032618
Short name T1200
Test name
Test status
Simulation time 14857458 ps
CPU time 0.57 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:40 PM PDT 24
Peak memory 195316 kb
Host smart-143141b8-eaa1-47be-84b2-8a8a42e4bf6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818032618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.818032618
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2560748549
Short name T1231
Test name
Test status
Simulation time 16500842 ps
CPU time 0.57 seconds
Started Jul 21 07:07:01 PM PDT 24
Finished Jul 21 07:07:02 PM PDT 24
Peak memory 195340 kb
Host smart-185ef5c6-bb3d-4708-b1ce-12b337be83cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560748549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2560748549
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2144556630
Short name T1261
Test name
Test status
Simulation time 19904423 ps
CPU time 0.56 seconds
Started Jul 21 07:06:57 PM PDT 24
Finished Jul 21 07:06:59 PM PDT 24
Peak memory 195220 kb
Host smart-c981944b-f2ca-4d86-903c-e35bbbcb8fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144556630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2144556630
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.391984713
Short name T1239
Test name
Test status
Simulation time 14337610 ps
CPU time 0.55 seconds
Started Jul 21 07:06:41 PM PDT 24
Finished Jul 21 07:06:42 PM PDT 24
Peak memory 195304 kb
Host smart-4dcb2035-8e78-4712-9fb5-924c869b6075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391984713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.391984713
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1604150787
Short name T1207
Test name
Test status
Simulation time 21788961 ps
CPU time 0.55 seconds
Started Jul 21 07:06:45 PM PDT 24
Finished Jul 21 07:06:46 PM PDT 24
Peak memory 195312 kb
Host smart-fa5989d3-7cfe-40f4-b2e2-dc92cb47deb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604150787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1604150787
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1727465312
Short name T1187
Test name
Test status
Simulation time 45104235 ps
CPU time 0.59 seconds
Started Jul 21 07:06:51 PM PDT 24
Finished Jul 21 07:06:52 PM PDT 24
Peak memory 195348 kb
Host smart-0655837b-a400-43f0-8eb7-fd77f46512df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727465312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1727465312
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2712359197
Short name T1305
Test name
Test status
Simulation time 15563331 ps
CPU time 0.55 seconds
Started Jul 21 07:06:43 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 195316 kb
Host smart-971625b8-2fc2-4a1a-8243-4ad2f1952277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712359197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2712359197
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.890905177
Short name T1279
Test name
Test status
Simulation time 15605878 ps
CPU time 0.57 seconds
Started Jul 21 07:06:55 PM PDT 24
Finished Jul 21 07:06:56 PM PDT 24
Peak memory 195320 kb
Host smart-365d04b0-e275-4acb-91c6-a942614698d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890905177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.890905177
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1227357253
Short name T1182
Test name
Test status
Simulation time 17860939 ps
CPU time 0.76 seconds
Started Jul 21 07:06:19 PM PDT 24
Finished Jul 21 07:06:20 PM PDT 24
Peak memory 197160 kb
Host smart-fb225024-61e3-473d-af4e-1b665a0f1c51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227357253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1227357253
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2865901828
Short name T64
Test name
Test status
Simulation time 968250162 ps
CPU time 2.61 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 198532 kb
Host smart-2ed6b097-ac6b-4c43-98e5-5b0212f2863a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865901828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2865901828
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2585515472
Short name T1249
Test name
Test status
Simulation time 71888220 ps
CPU time 0.59 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 196368 kb
Host smart-e9b77b28-1eb1-4eff-92b7-deb5c7a88ec7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585515472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2585515472
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2172096353
Short name T1215
Test name
Test status
Simulation time 128417969 ps
CPU time 0.85 seconds
Started Jul 21 07:06:33 PM PDT 24
Finished Jul 21 07:06:34 PM PDT 24
Peak memory 200536 kb
Host smart-74132eab-7923-4fff-956f-c893a4b2e3ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172096353 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2172096353
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4227922772
Short name T80
Test name
Test status
Simulation time 115267774 ps
CPU time 0.63 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 196392 kb
Host smart-1a02aa45-4d0a-4cf0-85a8-b129e0aa1e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227922772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4227922772
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2574117497
Short name T1179
Test name
Test status
Simulation time 16607870 ps
CPU time 0.54 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:24 PM PDT 24
Peak memory 195160 kb
Host smart-ce57e15f-d046-46bd-9188-d9441a00613e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574117497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2574117497
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1403516430
Short name T1274
Test name
Test status
Simulation time 52999728 ps
CPU time 0.68 seconds
Started Jul 21 07:06:23 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 196608 kb
Host smart-09b20348-726b-4255-9d9e-584f4979e4a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403516430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1403516430
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2166976243
Short name T1258
Test name
Test status
Simulation time 193535722 ps
CPU time 1.03 seconds
Started Jul 21 07:06:23 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 200752 kb
Host smart-08670c31-3a86-4107-ae25-72e0081f8a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166976243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2166976243
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3611157082
Short name T95
Test name
Test status
Simulation time 246688757 ps
CPU time 1.3 seconds
Started Jul 21 07:06:25 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 200224 kb
Host smart-e7325b2c-7eec-4263-9ab5-f307889017e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611157082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3611157082
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3775086949
Short name T1214
Test name
Test status
Simulation time 17323572 ps
CPU time 0.62 seconds
Started Jul 21 07:06:42 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 195320 kb
Host smart-aed42b62-2f7c-460c-a086-8526fe9971f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775086949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3775086949
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4225355734
Short name T1180
Test name
Test status
Simulation time 48413422 ps
CPU time 0.56 seconds
Started Jul 21 07:06:46 PM PDT 24
Finished Jul 21 07:06:47 PM PDT 24
Peak memory 195352 kb
Host smart-9b80afcb-b3c0-4512-b247-eaf4371d3471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225355734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4225355734
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.261126111
Short name T1281
Test name
Test status
Simulation time 11311688 ps
CPU time 0.56 seconds
Started Jul 21 07:06:48 PM PDT 24
Finished Jul 21 07:06:48 PM PDT 24
Peak memory 195248 kb
Host smart-d857f6ea-3fa7-4732-af4f-421a9c6efeaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261126111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.261126111
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1239549142
Short name T1175
Test name
Test status
Simulation time 17262244 ps
CPU time 0.59 seconds
Started Jul 21 07:06:54 PM PDT 24
Finished Jul 21 07:06:55 PM PDT 24
Peak memory 195288 kb
Host smart-66264daf-625d-47c9-887c-0d1669afde19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239549142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1239549142
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2535669538
Short name T1242
Test name
Test status
Simulation time 16918786 ps
CPU time 0.56 seconds
Started Jul 21 07:06:41 PM PDT 24
Finished Jul 21 07:06:42 PM PDT 24
Peak memory 195484 kb
Host smart-5ba59e28-0ecc-4429-8d6e-d5647043efdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535669538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2535669538
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3426724237
Short name T1189
Test name
Test status
Simulation time 26754504 ps
CPU time 0.6 seconds
Started Jul 21 07:06:52 PM PDT 24
Finished Jul 21 07:06:53 PM PDT 24
Peak memory 195256 kb
Host smart-0a29b93c-7025-41dc-bc35-06eb7061d1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426724237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3426724237
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.125672587
Short name T1275
Test name
Test status
Simulation time 28833397 ps
CPU time 0.57 seconds
Started Jul 21 07:06:56 PM PDT 24
Finished Jul 21 07:06:57 PM PDT 24
Peak memory 195332 kb
Host smart-27ee5f86-ed9c-498e-845c-67b01f4ec843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125672587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.125672587
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2789715652
Short name T1243
Test name
Test status
Simulation time 37595379 ps
CPU time 0.55 seconds
Started Jul 21 07:06:56 PM PDT 24
Finished Jul 21 07:06:57 PM PDT 24
Peak memory 195356 kb
Host smart-4279a37e-11a0-4643-8cd9-5cdaa20d61bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789715652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2789715652
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2211093426
Short name T1218
Test name
Test status
Simulation time 32354514 ps
CPU time 0.58 seconds
Started Jul 21 07:06:53 PM PDT 24
Finished Jul 21 07:06:54 PM PDT 24
Peak memory 195308 kb
Host smart-97768ebe-39cb-4a53-b3e7-4aa3fe10d497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211093426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2211093426
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.438625566
Short name T1192
Test name
Test status
Simulation time 13838631 ps
CPU time 0.59 seconds
Started Jul 21 07:06:54 PM PDT 24
Finished Jul 21 07:06:55 PM PDT 24
Peak memory 195360 kb
Host smart-4d56306d-c17d-4636-a8e1-b9cd749428ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438625566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.438625566
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1084284151
Short name T1219
Test name
Test status
Simulation time 20669235 ps
CPU time 0.65 seconds
Started Jul 21 07:06:42 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 195752 kb
Host smart-75066387-3762-4cc7-9f75-28cdcc6ff5df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084284151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1084284151
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.366351215
Short name T1191
Test name
Test status
Simulation time 37956807 ps
CPU time 1.34 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 198156 kb
Host smart-d57dbc65-c75c-4588-8d56-472f339a0bc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366351215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.366351215
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1875287199
Short name T1254
Test name
Test status
Simulation time 15515980 ps
CPU time 0.6 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 196348 kb
Host smart-a353571b-d963-4157-9de4-c868f6165e92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875287199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1875287199
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3622695500
Short name T1293
Test name
Test status
Simulation time 133941114 ps
CPU time 0.99 seconds
Started Jul 21 07:06:23 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 200724 kb
Host smart-9507ee15-3ebe-4595-9fd9-1805c68b4d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622695500 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3622695500
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2157658635
Short name T1270
Test name
Test status
Simulation time 32045320 ps
CPU time 0.56 seconds
Started Jul 21 07:06:20 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 196344 kb
Host smart-9f868640-7292-4eaa-ae67-70046464de26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157658635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2157658635
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2128201775
Short name T1212
Test name
Test status
Simulation time 28992467 ps
CPU time 0.57 seconds
Started Jul 21 07:06:29 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 195336 kb
Host smart-92781f92-a89b-4b1b-8ee0-339931101711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128201775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2128201775
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1873829686
Short name T1283
Test name
Test status
Simulation time 89200409 ps
CPU time 0.63 seconds
Started Jul 21 07:06:20 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 196344 kb
Host smart-fdd5922e-d9cd-4450-9200-97c0a736bbd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873829686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1873829686
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.948319289
Short name T1206
Test name
Test status
Simulation time 108701773 ps
CPU time 1.2 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:27 PM PDT 24
Peak memory 200980 kb
Host smart-548071d3-ac8f-47bc-ada9-4ee0ba446e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948319289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.948319289
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.451857404
Short name T96
Test name
Test status
Simulation time 154865222 ps
CPU time 0.92 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 199880 kb
Host smart-9d5524e7-2a49-46da-92d5-bea9d6ce41f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451857404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.451857404
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1592793506
Short name T1289
Test name
Test status
Simulation time 23143696 ps
CPU time 0.57 seconds
Started Jul 21 07:06:42 PM PDT 24
Finished Jul 21 07:06:43 PM PDT 24
Peak memory 195244 kb
Host smart-33c4dee4-9cbf-4315-976d-65176fd0ee1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592793506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1592793506
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4127541220
Short name T1185
Test name
Test status
Simulation time 52547152 ps
CPU time 0.58 seconds
Started Jul 21 07:06:52 PM PDT 24
Finished Jul 21 07:06:53 PM PDT 24
Peak memory 195328 kb
Host smart-233637ad-9ff6-42c4-b47d-0241617fd2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127541220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4127541220
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2268751304
Short name T1272
Test name
Test status
Simulation time 26653998 ps
CPU time 0.54 seconds
Started Jul 21 07:06:58 PM PDT 24
Finished Jul 21 07:06:59 PM PDT 24
Peak memory 195296 kb
Host smart-aa85ce2e-4ae5-4ff8-8400-e54526dbf50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268751304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2268751304
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.307042357
Short name T1301
Test name
Test status
Simulation time 56792884 ps
CPU time 0.55 seconds
Started Jul 21 07:06:44 PM PDT 24
Finished Jul 21 07:06:45 PM PDT 24
Peak memory 195228 kb
Host smart-27ee9c9b-5e5a-462d-8bf3-0b5df0d5992a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307042357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.307042357
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3093888953
Short name T1280
Test name
Test status
Simulation time 30722681 ps
CPU time 0.55 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:40 PM PDT 24
Peak memory 195216 kb
Host smart-754ac92d-fc38-45b5-a074-77c066fa0608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093888953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3093888953
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1686102744
Short name T1265
Test name
Test status
Simulation time 22443000 ps
CPU time 0.56 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:40 PM PDT 24
Peak memory 195148 kb
Host smart-a85f1677-0abe-4183-9dcb-07285a199e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686102744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1686102744
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4123428580
Short name T1292
Test name
Test status
Simulation time 40379681 ps
CPU time 0.55 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:41 PM PDT 24
Peak memory 195208 kb
Host smart-0c03bd15-8c51-4daf-b719-578070942b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123428580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4123428580
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1030287847
Short name T1259
Test name
Test status
Simulation time 26434035 ps
CPU time 0.58 seconds
Started Jul 21 07:06:44 PM PDT 24
Finished Jul 21 07:06:45 PM PDT 24
Peak memory 195312 kb
Host smart-a5510ca4-4b60-4b14-9234-000a63e09477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030287847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1030287847
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2741241787
Short name T1194
Test name
Test status
Simulation time 35499620 ps
CPU time 0.53 seconds
Started Jul 21 07:06:39 PM PDT 24
Finished Jul 21 07:06:40 PM PDT 24
Peak memory 195284 kb
Host smart-ccbb204c-fe8b-49f7-9955-5d520980b029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741241787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2741241787
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1985907071
Short name T1267
Test name
Test status
Simulation time 21266451 ps
CPU time 0.59 seconds
Started Jul 21 07:06:49 PM PDT 24
Finished Jul 21 07:06:50 PM PDT 24
Peak memory 195352 kb
Host smart-ad8acbc5-9787-4846-9afb-5215b7954702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985907071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1985907071
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2380482890
Short name T1250
Test name
Test status
Simulation time 15201963 ps
CPU time 0.65 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 198160 kb
Host smart-177e55b7-0a91-43c4-872d-08b4638d23f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380482890 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2380482890
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4167531781
Short name T1307
Test name
Test status
Simulation time 14925204 ps
CPU time 0.63 seconds
Started Jul 21 07:06:20 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 196440 kb
Host smart-c99bf479-176d-4fe4-8914-3cebd54e1d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167531781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4167531781
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1844682372
Short name T1285
Test name
Test status
Simulation time 15338348 ps
CPU time 0.57 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:36 PM PDT 24
Peak memory 195156 kb
Host smart-011a98cb-8c21-45a6-a0ac-5b8a5fe5967e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844682372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1844682372
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3796426003
Short name T1198
Test name
Test status
Simulation time 16807647 ps
CPU time 0.66 seconds
Started Jul 21 07:06:21 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 196504 kb
Host smart-77b33200-d964-4867-9a91-db0e533fcf97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796426003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3796426003
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2189368280
Short name T1176
Test name
Test status
Simulation time 128734219 ps
CPU time 1.53 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 200988 kb
Host smart-c6d3bce5-6214-4d71-a00a-af8fe87b4eff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189368280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2189368280
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1871587582
Short name T90
Test name
Test status
Simulation time 143386228 ps
CPU time 0.87 seconds
Started Jul 21 07:06:23 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 199808 kb
Host smart-3cc886bd-18bc-48a4-878b-6df7ba3d1fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871587582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1871587582
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.100651456
Short name T1195
Test name
Test status
Simulation time 38321289 ps
CPU time 1.08 seconds
Started Jul 21 07:06:37 PM PDT 24
Finished Jul 21 07:06:39 PM PDT 24
Peak memory 200728 kb
Host smart-a732072c-c251-4ac9-a2c2-d69bde232b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100651456 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.100651456
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.191420811
Short name T68
Test name
Test status
Simulation time 12846310 ps
CPU time 0.58 seconds
Started Jul 21 07:06:38 PM PDT 24
Finished Jul 21 07:06:39 PM PDT 24
Peak memory 196328 kb
Host smart-2bc9ffd0-c52d-4876-b90c-33a6e6865f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191420811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.191420811
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1471170906
Short name T1235
Test name
Test status
Simulation time 10285900 ps
CPU time 0.58 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 195280 kb
Host smart-232979f5-4034-4346-81ac-40e4c235f495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471170906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1471170906
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3839048090
Short name T83
Test name
Test status
Simulation time 60411743 ps
CPU time 0.65 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:36 PM PDT 24
Peak memory 196552 kb
Host smart-40fe767c-982a-4c92-b36f-bbb9e7baebb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839048090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3839048090
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4215006030
Short name T1257
Test name
Test status
Simulation time 44946639 ps
CPU time 2.22 seconds
Started Jul 21 07:06:24 PM PDT 24
Finished Jul 21 07:06:28 PM PDT 24
Peak memory 200944 kb
Host smart-50de9def-917d-4a6e-a720-8cdf0c80f8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215006030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4215006030
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1926598686
Short name T1226
Test name
Test status
Simulation time 286505739 ps
CPU time 0.9 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 199744 kb
Host smart-954d8678-c4b9-4613-8585-ae98d737a27e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926598686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1926598686
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3125128376
Short name T1236
Test name
Test status
Simulation time 96929546 ps
CPU time 0.82 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 199184 kb
Host smart-16c098aa-7245-4d36-9bb8-4df7368f96ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125128376 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3125128376
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4084163485
Short name T69
Test name
Test status
Simulation time 46460571 ps
CPU time 0.6 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:36 PM PDT 24
Peak memory 196324 kb
Host smart-09a46efe-8dff-4c9e-8b98-7eddaf673144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084163485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4084163485
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3552569847
Short name T1296
Test name
Test status
Simulation time 13077867 ps
CPU time 0.55 seconds
Started Jul 21 07:06:36 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 195272 kb
Host smart-0bbeb49e-e325-4485-9cda-eac8a0a586cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552569847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3552569847
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2999283375
Short name T1228
Test name
Test status
Simulation time 28896922 ps
CPU time 0.79 seconds
Started Jul 21 07:07:23 PM PDT 24
Finished Jul 21 07:07:27 PM PDT 24
Peak memory 197464 kb
Host smart-dc6ccc9a-9ee3-494c-ac7e-7d1e4da9870c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999283375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2999283375
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3911546410
Short name T1253
Test name
Test status
Simulation time 407031552 ps
CPU time 1.76 seconds
Started Jul 21 07:06:40 PM PDT 24
Finished Jul 21 07:06:43 PM PDT 24
Peak memory 200976 kb
Host smart-56c36135-2ccd-4f65-a148-93f740cf9ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911546410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3911546410
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3348116281
Short name T92
Test name
Test status
Simulation time 178856945 ps
CPU time 1.38 seconds
Started Jul 21 07:06:27 PM PDT 24
Finished Jul 21 07:06:30 PM PDT 24
Peak memory 200068 kb
Host smart-53446f88-6707-40eb-bf38-33fbfd824b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348116281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3348116281
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4290333810
Short name T1210
Test name
Test status
Simulation time 26116443 ps
CPU time 1.09 seconds
Started Jul 21 07:06:33 PM PDT 24
Finished Jul 21 07:06:35 PM PDT 24
Peak memory 200944 kb
Host smart-4c286724-b770-4d88-8bef-a43cb7ed3e6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290333810 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4290333810
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1131246327
Short name T1227
Test name
Test status
Simulation time 49768604 ps
CPU time 0.55 seconds
Started Jul 21 07:06:28 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 196332 kb
Host smart-bed46552-e085-47a9-a10e-cea1b53e70bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131246327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1131246327
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2193404410
Short name T1177
Test name
Test status
Simulation time 58580863 ps
CPU time 0.56 seconds
Started Jul 21 07:06:45 PM PDT 24
Finished Jul 21 07:06:46 PM PDT 24
Peak memory 195304 kb
Host smart-f588d281-da3e-4dda-a189-533338a9ff3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193404410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2193404410
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1392637209
Short name T87
Test name
Test status
Simulation time 37393149 ps
CPU time 0.64 seconds
Started Jul 21 07:06:26 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 196456 kb
Host smart-5d9d0a52-d103-412a-a8f9-f5b90c1f11ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392637209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1392637209
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2243932649
Short name T1196
Test name
Test status
Simulation time 29104356 ps
CPU time 1.47 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 200868 kb
Host smart-b516b7a5-1d8e-46ee-93c7-ece01f7fde3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243932649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2243932649
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1650718127
Short name T119
Test name
Test status
Simulation time 150420945 ps
CPU time 0.98 seconds
Started Jul 21 07:06:30 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 199996 kb
Host smart-41c1f2de-1c7b-4503-8741-afac879dbc89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650718127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1650718127
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4278124839
Short name T1282
Test name
Test status
Simulation time 112451878 ps
CPU time 0.84 seconds
Started Jul 21 07:06:23 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 200744 kb
Host smart-c5626058-d370-4a65-9c5f-b73852c96fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278124839 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4278124839
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3599292004
Short name T72
Test name
Test status
Simulation time 41047345 ps
CPU time 0.56 seconds
Started Jul 21 07:06:35 PM PDT 24
Finished Jul 21 07:06:36 PM PDT 24
Peak memory 196248 kb
Host smart-040d175f-1a01-4e32-ba19-bbcaf4428a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599292004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3599292004
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.480558428
Short name T1202
Test name
Test status
Simulation time 48498311 ps
CPU time 0.55 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 195248 kb
Host smart-93b23a86-df2c-4e1e-b66d-bb1e228f0509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480558428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.480558428
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1624732816
Short name T1269
Test name
Test status
Simulation time 73784142 ps
CPU time 0.73 seconds
Started Jul 21 07:06:37 PM PDT 24
Finished Jul 21 07:06:38 PM PDT 24
Peak memory 197868 kb
Host smart-848b3edc-a9d4-499f-86a8-2d2fbaef51b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624732816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1624732816
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3837051363
Short name T1217
Test name
Test status
Simulation time 55044483 ps
CPU time 1.36 seconds
Started Jul 21 07:06:22 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 200992 kb
Host smart-880c892a-53ae-49ff-9f9a-b4afa6422022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837051363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3837051363
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1783228727
Short name T1190
Test name
Test status
Simulation time 153688624 ps
CPU time 0.92 seconds
Started Jul 21 07:06:40 PM PDT 24
Finished Jul 21 07:06:42 PM PDT 24
Peak memory 199612 kb
Host smart-63b33761-6ba4-4132-8e91-fe71eec6c201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783228727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1783228727
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2864964696
Short name T1139
Test name
Test status
Simulation time 28739660 ps
CPU time 0.6 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:12:38 PM PDT 24
Peak memory 195124 kb
Host smart-d2745928-da87-4a5f-9e29-970d9a1d9f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864964696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2864964696
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3959485204
Short name T858
Test name
Test status
Simulation time 35987489695 ps
CPU time 4.65 seconds
Started Jul 21 07:12:22 PM PDT 24
Finished Jul 21 07:12:29 PM PDT 24
Peak memory 200196 kb
Host smart-3483399f-ea53-45b2-8b27-67ad60e64586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959485204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3959485204
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2679922446
Short name T486
Test name
Test status
Simulation time 46311860453 ps
CPU time 81.44 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:13:54 PM PDT 24
Peak memory 200096 kb
Host smart-1c28a7bf-f583-4f17-b8e7-cfdf370ad932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679922446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2679922446
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1878683834
Short name T994
Test name
Test status
Simulation time 38175578740 ps
CPU time 15.83 seconds
Started Jul 21 07:12:30 PM PDT 24
Finished Jul 21 07:12:47 PM PDT 24
Peak memory 199908 kb
Host smart-1d498e09-a563-49ab-8dd9-63e7d98ca415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878683834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1878683834
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1095021286
Short name T896
Test name
Test status
Simulation time 231473719804 ps
CPU time 358.59 seconds
Started Jul 21 07:12:23 PM PDT 24
Finished Jul 21 07:18:23 PM PDT 24
Peak memory 197644 kb
Host smart-bd4fc05e-97f2-4f2b-8419-7537c324cefa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095021286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1095021286
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2462268589
Short name T969
Test name
Test status
Simulation time 105805714422 ps
CPU time 254.21 seconds
Started Jul 21 07:12:25 PM PDT 24
Finished Jul 21 07:16:40 PM PDT 24
Peak memory 200132 kb
Host smart-2131095c-2636-410e-bceb-eee52f30d0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462268589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2462268589
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2513452946
Short name T357
Test name
Test status
Simulation time 248956173 ps
CPU time 0.92 seconds
Started Jul 21 07:12:27 PM PDT 24
Finished Jul 21 07:12:28 PM PDT 24
Peak memory 196140 kb
Host smart-0a16e715-8ed7-4d86-884c-eba70eca1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513452946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2513452946
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2673752085
Short name T475
Test name
Test status
Simulation time 80641818480 ps
CPU time 112.49 seconds
Started Jul 21 07:12:22 PM PDT 24
Finished Jul 21 07:14:17 PM PDT 24
Peak memory 208464 kb
Host smart-54530d31-4218-4eb6-aba0-5be6abd64191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673752085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2673752085
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2322070701
Short name T246
Test name
Test status
Simulation time 8802018965 ps
CPU time 225.95 seconds
Started Jul 21 07:12:27 PM PDT 24
Finished Jul 21 07:16:14 PM PDT 24
Peak memory 200184 kb
Host smart-5038886d-92a5-486c-b619-ab27228936f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322070701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2322070701
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2523705399
Short name T507
Test name
Test status
Simulation time 5757226790 ps
CPU time 25.32 seconds
Started Jul 21 07:12:29 PM PDT 24
Finished Jul 21 07:12:56 PM PDT 24
Peak memory 198720 kb
Host smart-04fe49f0-712b-4ca6-8a67-8875585ba635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523705399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2523705399
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1525470315
Short name T921
Test name
Test status
Simulation time 64920636907 ps
CPU time 41.83 seconds
Started Jul 21 07:12:26 PM PDT 24
Finished Jul 21 07:13:08 PM PDT 24
Peak memory 200112 kb
Host smart-6c937f6d-2281-4e57-94db-1b497725eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525470315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1525470315
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1550237602
Short name T563
Test name
Test status
Simulation time 633546897 ps
CPU time 1.15 seconds
Started Jul 21 07:12:22 PM PDT 24
Finished Jul 21 07:12:25 PM PDT 24
Peak memory 195448 kb
Host smart-2f4c5cc8-5dc9-4f83-886a-e5ddaaaf29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550237602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1550237602
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.4265972155
Short name T26
Test name
Test status
Simulation time 85806731 ps
CPU time 0.89 seconds
Started Jul 21 07:12:25 PM PDT 24
Finished Jul 21 07:12:26 PM PDT 24
Peak memory 218464 kb
Host smart-494976ce-e8f9-4b55-a9f1-7570c71e176f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265972155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4265972155
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2470022783
Short name T630
Test name
Test status
Simulation time 889622062 ps
CPU time 3.03 seconds
Started Jul 21 07:12:30 PM PDT 24
Finished Jul 21 07:12:34 PM PDT 24
Peak memory 198500 kb
Host smart-cda92052-1480-468b-a92a-500994394040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470022783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2470022783
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1519830047
Short name T1032
Test name
Test status
Simulation time 202696876104 ps
CPU time 435.09 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:19:52 PM PDT 24
Peak memory 215872 kb
Host smart-c4a42a4f-64a7-416a-b57e-826f1c274f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519830047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1519830047
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2262753086
Short name T831
Test name
Test status
Simulation time 117662861417 ps
CPU time 298.14 seconds
Started Jul 21 07:12:27 PM PDT 24
Finished Jul 21 07:17:26 PM PDT 24
Peak memory 226800 kb
Host smart-767a23b8-3017-4863-9e12-d36ad10470c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262753086 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2262753086
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1644142709
Short name T445
Test name
Test status
Simulation time 9122512232 ps
CPU time 8.61 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:12:46 PM PDT 24
Peak memory 200176 kb
Host smart-cc730e62-a900-4c8d-98df-79eb08a3577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644142709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1644142709
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1438418800
Short name T761
Test name
Test status
Simulation time 28252898429 ps
CPU time 85.82 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:14:03 PM PDT 24
Peak memory 200188 kb
Host smart-3f37ddb6-29ef-4825-8bff-9ec287f85bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438418800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1438418800
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3906846074
Short name T877
Test name
Test status
Simulation time 24663298 ps
CPU time 0.58 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:12:34 PM PDT 24
Peak memory 195632 kb
Host smart-f6cf3150-f5ca-4ae9-88a7-e3baed062323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906846074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3906846074
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3919783339
Short name T1053
Test name
Test status
Simulation time 204264368868 ps
CPU time 429.64 seconds
Started Jul 21 07:12:28 PM PDT 24
Finished Jul 21 07:19:38 PM PDT 24
Peak memory 200172 kb
Host smart-17cc8b6e-2554-415b-80cc-86d289cdd757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919783339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3919783339
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4091768477
Short name T412
Test name
Test status
Simulation time 129499433772 ps
CPU time 102.68 seconds
Started Jul 21 07:12:28 PM PDT 24
Finished Jul 21 07:14:11 PM PDT 24
Peak memory 200236 kb
Host smart-0b230e71-d2fc-4fdb-9db9-aea441010ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091768477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4091768477
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1182373775
Short name T528
Test name
Test status
Simulation time 106385505199 ps
CPU time 84.99 seconds
Started Jul 21 07:12:25 PM PDT 24
Finished Jul 21 07:13:51 PM PDT 24
Peak memory 199960 kb
Host smart-10444550-9de2-42d1-9766-646895c70612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182373775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1182373775
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3127518047
Short name T983
Test name
Test status
Simulation time 7386182987 ps
CPU time 4.59 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:12:42 PM PDT 24
Peak memory 199320 kb
Host smart-9047c97c-a214-4ff4-9e47-8c4bbcef8ebb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127518047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3127518047
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.694328214
Short name T827
Test name
Test status
Simulation time 117645088788 ps
CPU time 82.52 seconds
Started Jul 21 07:12:35 PM PDT 24
Finished Jul 21 07:13:58 PM PDT 24
Peak memory 200156 kb
Host smart-dab90b3c-57a6-43e9-9a32-f55df013e5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694328214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.694328214
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2916108073
Short name T381
Test name
Test status
Simulation time 6847126535 ps
CPU time 23.63 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:12:57 PM PDT 24
Peak memory 199940 kb
Host smart-cae5065b-67bc-480c-8d40-b56982508a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916108073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2916108073
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1313738714
Short name T276
Test name
Test status
Simulation time 108790167295 ps
CPU time 54.82 seconds
Started Jul 21 07:12:26 PM PDT 24
Finished Jul 21 07:13:21 PM PDT 24
Peak memory 200320 kb
Host smart-39566830-1b6f-4919-bf14-36a1759b932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313738714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1313738714
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1183998532
Short name T341
Test name
Test status
Simulation time 4670712032 ps
CPU time 37.92 seconds
Started Jul 21 07:12:36 PM PDT 24
Finished Jul 21 07:13:15 PM PDT 24
Peak memory 198308 kb
Host smart-c1ce18b0-6c3a-42f7-937e-0afe2176a64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183998532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1183998532
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3728246633
Short name T728
Test name
Test status
Simulation time 30106903097 ps
CPU time 10.96 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:12:44 PM PDT 24
Peak memory 200148 kb
Host smart-6e515b5a-1ba6-439f-9749-7a11a952c348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728246633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3728246633
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4188264398
Short name T875
Test name
Test status
Simulation time 4771047593 ps
CPU time 7.05 seconds
Started Jul 21 07:12:28 PM PDT 24
Finished Jul 21 07:12:36 PM PDT 24
Peak memory 196732 kb
Host smart-036b0357-57fc-42e2-80a2-1e0c5249573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188264398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4188264398
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2964498287
Short name T101
Test name
Test status
Simulation time 106235394 ps
CPU time 0.91 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:12:34 PM PDT 24
Peak memory 218452 kb
Host smart-eba642e1-6655-4be1-a557-b6da3e2de4c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964498287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2964498287
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1202674664
Short name T1033
Test name
Test status
Simulation time 11108428370 ps
CPU time 33.27 seconds
Started Jul 21 07:12:26 PM PDT 24
Finished Jul 21 07:12:59 PM PDT 24
Peak memory 200132 kb
Host smart-336ee9ef-dda2-4c82-bc49-9859a1986ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202674664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1202674664
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.4261952968
Short name T882
Test name
Test status
Simulation time 355348280207 ps
CPU time 433.8 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:19:47 PM PDT 24
Peak memory 208452 kb
Host smart-ee7e3ad2-aa68-4a7f-92b9-fbbd7f8b7b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261952968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4261952968
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3699650673
Short name T960
Test name
Test status
Simulation time 60214452882 ps
CPU time 344.07 seconds
Started Jul 21 07:12:34 PM PDT 24
Finished Jul 21 07:18:19 PM PDT 24
Peak memory 216608 kb
Host smart-d5cbb4d4-022c-4246-9321-4ef5255ccc85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699650673 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3699650673
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.158511402
Short name T1096
Test name
Test status
Simulation time 535197411 ps
CPU time 1.7 seconds
Started Jul 21 07:12:35 PM PDT 24
Finished Jul 21 07:12:37 PM PDT 24
Peak memory 198688 kb
Host smart-06c4a25e-4132-48cc-876e-42f17dd1a23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158511402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.158511402
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2091249131
Short name T1050
Test name
Test status
Simulation time 40725055207 ps
CPU time 31 seconds
Started Jul 21 07:12:27 PM PDT 24
Finished Jul 21 07:12:59 PM PDT 24
Peak memory 200188 kb
Host smart-f6b228e4-60e5-43fc-9353-0b1fc1246d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091249131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2091249131
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3275153255
Short name T860
Test name
Test status
Simulation time 15015085 ps
CPU time 0.57 seconds
Started Jul 21 07:13:20 PM PDT 24
Finished Jul 21 07:13:20 PM PDT 24
Peak memory 195584 kb
Host smart-87199e88-ace4-41c5-9934-7a63730fd5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275153255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3275153255
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2940987386
Short name T634
Test name
Test status
Simulation time 44606105605 ps
CPU time 73.82 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:14:26 PM PDT 24
Peak memory 200116 kb
Host smart-1a13151a-05ac-44ce-84e0-dcb81880cc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940987386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2940987386
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2758420147
Short name T718
Test name
Test status
Simulation time 73893671285 ps
CPU time 118.52 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:15:11 PM PDT 24
Peak memory 200216 kb
Host smart-ba9a0bf2-d682-47a7-bad4-63ef9ef304a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758420147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2758420147
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2928666773
Short name T1068
Test name
Test status
Simulation time 84837789041 ps
CPU time 54.93 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:14:08 PM PDT 24
Peak memory 200148 kb
Host smart-5e379c85-dd98-4157-bf76-97ba117f1924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928666773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2928666773
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3950877334
Short name T530
Test name
Test status
Simulation time 11089106844 ps
CPU time 15.83 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:13:28 PM PDT 24
Peak memory 200136 kb
Host smart-8c1b6807-972f-4792-9f4a-212a829a1a26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950877334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3950877334
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1807853351
Short name T260
Test name
Test status
Simulation time 107899211289 ps
CPU time 856.31 seconds
Started Jul 21 07:13:18 PM PDT 24
Finished Jul 21 07:27:35 PM PDT 24
Peak memory 200256 kb
Host smart-1d65cba5-3d0f-4a2d-a285-a15aa2a00da1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807853351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1807853351
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2861308306
Short name T485
Test name
Test status
Simulation time 10222792799 ps
CPU time 21.8 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:13:45 PM PDT 24
Peak memory 200136 kb
Host smart-21cace8c-6874-4165-b382-3e3f7306f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861308306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2861308306
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1940512292
Short name T442
Test name
Test status
Simulation time 77500697901 ps
CPU time 128.31 seconds
Started Jul 21 07:13:15 PM PDT 24
Finished Jul 21 07:15:24 PM PDT 24
Peak memory 200324 kb
Host smart-1a424a71-3b3a-42b4-ab2f-7805151924ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940512292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1940512292
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2088591618
Short name T651
Test name
Test status
Simulation time 30918396784 ps
CPU time 427.18 seconds
Started Jul 21 07:13:17 PM PDT 24
Finished Jul 21 07:20:25 PM PDT 24
Peak memory 200128 kb
Host smart-fe41a287-3932-4f7f-abaf-cdc4ed2439e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088591618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2088591618
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3238648847
Short name T426
Test name
Test status
Simulation time 5794540188 ps
CPU time 24.67 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:13:37 PM PDT 24
Peak memory 198384 kb
Host smart-12aeb9a4-f618-4cdb-b910-0833114eca39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238648847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3238648847
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1197282959
Short name T888
Test name
Test status
Simulation time 44415127120 ps
CPU time 70.34 seconds
Started Jul 21 07:13:18 PM PDT 24
Finished Jul 21 07:14:29 PM PDT 24
Peak memory 200176 kb
Host smart-e4078fd1-762f-4c97-bb4c-39b31f032df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197282959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1197282959
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2359347142
Short name T393
Test name
Test status
Simulation time 581305909 ps
CPU time 1.56 seconds
Started Jul 21 07:13:17 PM PDT 24
Finished Jul 21 07:13:18 PM PDT 24
Peak memory 195680 kb
Host smart-0b245bba-0d10-4cc2-b120-5e2f9bad21b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359347142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2359347142
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.31747813
Short name T296
Test name
Test status
Simulation time 531589268 ps
CPU time 1.25 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:13:13 PM PDT 24
Peak memory 198932 kb
Host smart-e3d9ff08-3555-44ad-beb3-8a3992d383e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31747813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.31747813
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.662695998
Short name T45
Test name
Test status
Simulation time 95636480081 ps
CPU time 38.27 seconds
Started Jul 21 07:13:20 PM PDT 24
Finished Jul 21 07:13:58 PM PDT 24
Peak memory 200096 kb
Host smart-bd7b1f7e-63e5-4ea8-a850-68b2f4899f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662695998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.662695998
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2123606445
Short name T924
Test name
Test status
Simulation time 167871988012 ps
CPU time 451.97 seconds
Started Jul 21 07:13:23 PM PDT 24
Finished Jul 21 07:20:55 PM PDT 24
Peak memory 225088 kb
Host smart-8791640d-1a63-4bf9-b171-a776d318ef4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123606445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2123606445
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4147216847
Short name T1092
Test name
Test status
Simulation time 2282762313 ps
CPU time 1.64 seconds
Started Jul 21 07:13:21 PM PDT 24
Finished Jul 21 07:13:23 PM PDT 24
Peak memory 200052 kb
Host smart-eba6bddf-31ca-407c-9d96-ed8a5e1a1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147216847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4147216847
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4178784600
Short name T107
Test name
Test status
Simulation time 19775397512 ps
CPU time 16.58 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:13:29 PM PDT 24
Peak memory 200216 kb
Host smart-f785845e-135d-4a13-9800-0c5deae064e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178784600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4178784600
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1779498612
Short name T179
Test name
Test status
Simulation time 90214314204 ps
CPU time 37 seconds
Started Jul 21 07:19:22 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 200116 kb
Host smart-afbf38b1-cbc2-4647-b3a6-69171765e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779498612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1779498612
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2332306856
Short name T135
Test name
Test status
Simulation time 252024840452 ps
CPU time 31.8 seconds
Started Jul 21 07:19:21 PM PDT 24
Finished Jul 21 07:20:22 PM PDT 24
Peak memory 200116 kb
Host smart-10921367-577f-495f-99a1-4b757b7f85d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332306856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2332306856
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.404697153
Short name T137
Test name
Test status
Simulation time 83607943141 ps
CPU time 35.03 seconds
Started Jul 21 07:19:22 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 200196 kb
Host smart-dd840330-b559-43e6-9e32-f43d64d4b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404697153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.404697153
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.434323473
Short name T456
Test name
Test status
Simulation time 125480576775 ps
CPU time 184.26 seconds
Started Jul 21 07:19:21 PM PDT 24
Finished Jul 21 07:22:54 PM PDT 24
Peak memory 200212 kb
Host smart-539e0709-1e15-4ba0-824a-1ed5ef64fc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434323473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.434323473
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1440898669
Short name T180
Test name
Test status
Simulation time 115009425594 ps
CPU time 43.83 seconds
Started Jul 21 07:19:22 PM PDT 24
Finished Jul 21 07:20:33 PM PDT 24
Peak memory 200124 kb
Host smart-33945669-39a2-4d4a-b2e6-7df768e8c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440898669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1440898669
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.181560320
Short name T7
Test name
Test status
Simulation time 46673235434 ps
CPU time 38.33 seconds
Started Jul 21 07:19:21 PM PDT 24
Finished Jul 21 07:20:28 PM PDT 24
Peak memory 200164 kb
Host smart-18090f5e-0910-4f68-8681-a0b8196bb0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181560320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.181560320
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2166254862
Short name T6
Test name
Test status
Simulation time 106567485823 ps
CPU time 40.47 seconds
Started Jul 21 07:19:27 PM PDT 24
Finished Jul 21 07:20:30 PM PDT 24
Peak memory 200208 kb
Host smart-550d7afa-16dc-42a8-bf3a-81fd9c49d85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166254862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2166254862
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.210344161
Short name T650
Test name
Test status
Simulation time 8548512182 ps
CPU time 5.09 seconds
Started Jul 21 07:19:28 PM PDT 24
Finished Jul 21 07:19:54 PM PDT 24
Peak memory 200224 kb
Host smart-2370eb05-e584-4a11-8bca-5dac36505dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210344161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.210344161
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3693801874
Short name T820
Test name
Test status
Simulation time 21351268647 ps
CPU time 18.06 seconds
Started Jul 21 07:19:28 PM PDT 24
Finished Jul 21 07:20:07 PM PDT 24
Peak memory 200124 kb
Host smart-5271bc46-33a1-4c64-b432-05f3922ef05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693801874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3693801874
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2062297876
Short name T586
Test name
Test status
Simulation time 186751671556 ps
CPU time 46.97 seconds
Started Jul 21 07:13:21 PM PDT 24
Finished Jul 21 07:14:09 PM PDT 24
Peak memory 200044 kb
Host smart-4a06c20b-2a39-4e2b-9d7e-02a17aab9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062297876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2062297876
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1306401353
Short name T244
Test name
Test status
Simulation time 200518036718 ps
CPU time 163.19 seconds
Started Jul 21 07:13:16 PM PDT 24
Finished Jul 21 07:15:59 PM PDT 24
Peak memory 200216 kb
Host smart-c0e67e1c-df2e-419d-8846-55119d1665ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306401353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1306401353
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2726221858
Short name T574
Test name
Test status
Simulation time 46719424488 ps
CPU time 41.56 seconds
Started Jul 21 07:13:23 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 199980 kb
Host smart-0d9602b7-f901-4365-b353-674c584e9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726221858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2726221858
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3242910338
Short name T1145
Test name
Test status
Simulation time 305388545472 ps
CPU time 123.97 seconds
Started Jul 21 07:13:18 PM PDT 24
Finished Jul 21 07:15:22 PM PDT 24
Peak memory 200000 kb
Host smart-40b96318-d81c-40b0-bc09-b3a0fa7b21aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242910338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3242910338
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1178914373
Short name T909
Test name
Test status
Simulation time 91028705662 ps
CPU time 632.1 seconds
Started Jul 21 07:13:24 PM PDT 24
Finished Jul 21 07:23:57 PM PDT 24
Peak memory 200132 kb
Host smart-54dcda34-ab24-4ba1-b79f-30438fab2ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178914373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1178914373
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1932477418
Short name T948
Test name
Test status
Simulation time 11232109893 ps
CPU time 7.1 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:13:29 PM PDT 24
Peak memory 199304 kb
Host smart-c48954d5-713d-44ef-a4b6-8aff6f8a7ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932477418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1932477418
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.974403476
Short name T662
Test name
Test status
Simulation time 139021797336 ps
CPU time 57.01 seconds
Started Jul 21 07:13:17 PM PDT 24
Finished Jul 21 07:14:14 PM PDT 24
Peak memory 199180 kb
Host smart-066f7eab-d003-4f24-ba24-3d3437430e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974403476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.974403476
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3895296410
Short name T686
Test name
Test status
Simulation time 12117095361 ps
CPU time 757.46 seconds
Started Jul 21 07:13:24 PM PDT 24
Finished Jul 21 07:26:01 PM PDT 24
Peak memory 200124 kb
Host smart-f41c02b4-3d58-4319-b313-065c2e0f5bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895296410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3895296410
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1354501193
Short name T1037
Test name
Test status
Simulation time 2978278057 ps
CPU time 5.13 seconds
Started Jul 21 07:13:17 PM PDT 24
Finished Jul 21 07:13:22 PM PDT 24
Peak memory 198976 kb
Host smart-2d8ad8c6-4cd4-4cbf-9c18-73a2b77787ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354501193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1354501193
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2608300411
Short name T1031
Test name
Test status
Simulation time 39645305773 ps
CPU time 14.72 seconds
Started Jul 21 07:13:23 PM PDT 24
Finished Jul 21 07:13:38 PM PDT 24
Peak memory 198692 kb
Host smart-5ba0d77f-b88f-4fa0-8aec-3cfd30869ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608300411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2608300411
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2017267834
Short name T421
Test name
Test status
Simulation time 49461539722 ps
CPU time 67.29 seconds
Started Jul 21 07:13:17 PM PDT 24
Finished Jul 21 07:14:25 PM PDT 24
Peak memory 196672 kb
Host smart-57098a76-866e-4c22-87ff-9e364ebc01ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017267834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2017267834
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3141086755
Short name T377
Test name
Test status
Simulation time 505089618 ps
CPU time 2.24 seconds
Started Jul 21 07:13:19 PM PDT 24
Finished Jul 21 07:13:22 PM PDT 24
Peak memory 200024 kb
Host smart-83e7f845-bb7a-4f8b-8882-698f52baa98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141086755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3141086755
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2556566546
Short name T694
Test name
Test status
Simulation time 131212674881 ps
CPU time 196.78 seconds
Started Jul 21 07:13:23 PM PDT 24
Finished Jul 21 07:16:40 PM PDT 24
Peak memory 200216 kb
Host smart-54f707aa-20b3-4de6-96eb-439765644f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556566546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2556566546
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.211161946
Short name T578
Test name
Test status
Simulation time 37850243674 ps
CPU time 969.75 seconds
Started Jul 21 07:13:25 PM PDT 24
Finished Jul 21 07:29:35 PM PDT 24
Peak memory 215664 kb
Host smart-d9c8d996-1249-4f0d-a1d8-9fb81742a914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211161946 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.211161946
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.95167563
Short name T259
Test name
Test status
Simulation time 1193784033 ps
CPU time 3.3 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:13:25 PM PDT 24
Peak memory 200108 kb
Host smart-e08703a2-1e37-447c-9074-de7a3a9604b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95167563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.95167563
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.745962954
Short name T1154
Test name
Test status
Simulation time 19340847439 ps
CPU time 15.6 seconds
Started Jul 21 07:13:19 PM PDT 24
Finished Jul 21 07:13:35 PM PDT 24
Peak memory 198144 kb
Host smart-9a24c9c7-7808-4746-b4b9-7eed1fa9e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745962954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.745962954
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3960203672
Short name T894
Test name
Test status
Simulation time 105190799896 ps
CPU time 89.08 seconds
Started Jul 21 07:19:26 PM PDT 24
Finished Jul 21 07:21:18 PM PDT 24
Peak memory 199980 kb
Host smart-b58860af-6f5f-4475-8a4a-728361024126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960203672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3960203672
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.692485143
Short name T779
Test name
Test status
Simulation time 51870789764 ps
CPU time 76.07 seconds
Started Jul 21 07:19:28 PM PDT 24
Finished Jul 21 07:21:05 PM PDT 24
Peak memory 200212 kb
Host smart-24b9368f-f944-44d9-98e8-2283a207f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692485143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.692485143
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2030647965
Short name T451
Test name
Test status
Simulation time 20745122752 ps
CPU time 18.06 seconds
Started Jul 21 07:19:28 PM PDT 24
Finished Jul 21 07:20:07 PM PDT 24
Peak memory 200084 kb
Host smart-bb3cf92c-2fe6-4e93-8d75-8ebb044eba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030647965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2030647965
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1076591892
Short name T618
Test name
Test status
Simulation time 107349558296 ps
CPU time 80 seconds
Started Jul 21 07:19:27 PM PDT 24
Finished Jul 21 07:21:09 PM PDT 24
Peak memory 200096 kb
Host smart-a45a9fa0-6bf6-4a71-83d9-eca9984421a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076591892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1076591892
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3272947162
Short name T1171
Test name
Test status
Simulation time 112355635578 ps
CPU time 187.55 seconds
Started Jul 21 07:19:30 PM PDT 24
Finished Jul 21 07:22:57 PM PDT 24
Peak memory 200116 kb
Host smart-da973601-d401-49bc-b102-75578093439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272947162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3272947162
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.633566844
Short name T972
Test name
Test status
Simulation time 38156290794 ps
CPU time 14.67 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 200144 kb
Host smart-34709483-1ff2-44dc-b450-60cb53dabec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633566844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.633566844
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3040586705
Short name T1018
Test name
Test status
Simulation time 41676247656 ps
CPU time 32.8 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:20:23 PM PDT 24
Peak memory 200232 kb
Host smart-51efa3b6-ff78-4af3-adb2-bb96f9d9c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040586705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3040586705
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1670634729
Short name T712
Test name
Test status
Simulation time 40894375778 ps
CPU time 19.67 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:20:10 PM PDT 24
Peak memory 200092 kb
Host smart-e6457b8f-876e-4cd9-ab27-ece904cd24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670634729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1670634729
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.69899789
Short name T502
Test name
Test status
Simulation time 12288939 ps
CPU time 0.55 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:13:29 PM PDT 24
Peak memory 195580 kb
Host smart-ba863d1d-57fc-47e2-9fd8-b059422f15e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69899789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.69899789
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.507975530
Short name T161
Test name
Test status
Simulation time 47301902357 ps
CPU time 41.61 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 200080 kb
Host smart-6d359b2f-ee0f-4ebc-bd27-c080e57d9e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507975530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.507975530
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.23927171
Short name T726
Test name
Test status
Simulation time 29085318555 ps
CPU time 52.01 seconds
Started Jul 21 07:13:24 PM PDT 24
Finished Jul 21 07:14:16 PM PDT 24
Peak memory 200144 kb
Host smart-d85fe5dc-04c4-4280-b6ff-2434ef17c317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23927171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.23927171
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2954426191
Short name T935
Test name
Test status
Simulation time 126975373290 ps
CPU time 124.78 seconds
Started Jul 21 07:13:24 PM PDT 24
Finished Jul 21 07:15:29 PM PDT 24
Peak memory 200196 kb
Host smart-9e65bdc7-6003-49e6-81ab-eb4f60acb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954426191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2954426191
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4191235163
Short name T557
Test name
Test status
Simulation time 50610792729 ps
CPU time 20.77 seconds
Started Jul 21 07:13:29 PM PDT 24
Finished Jul 21 07:13:50 PM PDT 24
Peak memory 200144 kb
Host smart-f33095bf-d0b9-4861-a9cc-4f5b161b3066
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191235163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4191235163
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1342978984
Short name T816
Test name
Test status
Simulation time 318444198189 ps
CPU time 338.83 seconds
Started Jul 21 07:13:29 PM PDT 24
Finished Jul 21 07:19:08 PM PDT 24
Peak memory 200192 kb
Host smart-1aa4911c-3cb5-4d0f-85ae-6b17ed2e0336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342978984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1342978984
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1032876705
Short name T701
Test name
Test status
Simulation time 1175664271 ps
CPU time 0.72 seconds
Started Jul 21 07:13:30 PM PDT 24
Finished Jul 21 07:13:31 PM PDT 24
Peak memory 196284 kb
Host smart-809154e7-86d1-4df1-b9fe-2344036274df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032876705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1032876705
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1047420231
Short name T995
Test name
Test status
Simulation time 80448073942 ps
CPU time 136.71 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:15:46 PM PDT 24
Peak memory 200152 kb
Host smart-5106f936-9cd0-408e-b209-3316980ff36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047420231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1047420231
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.808435086
Short name T834
Test name
Test status
Simulation time 11649482752 ps
CPU time 215.5 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:17:04 PM PDT 24
Peak memory 200164 kb
Host smart-61342c07-8fe3-45eb-a445-fe399fceb1a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808435086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.808435086
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.285858941
Short name T642
Test name
Test status
Simulation time 7215491614 ps
CPU time 63.36 seconds
Started Jul 21 07:13:22 PM PDT 24
Finished Jul 21 07:14:26 PM PDT 24
Peak memory 199328 kb
Host smart-acff288b-a8f9-4b82-a477-1823da3d1457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285858941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.285858941
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2610318638
Short name T660
Test name
Test status
Simulation time 62857956582 ps
CPU time 25.74 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:13:54 PM PDT 24
Peak memory 200004 kb
Host smart-e798cacc-6b12-4a68-b701-a703129e3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610318638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2610318638
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4142351591
Short name T510
Test name
Test status
Simulation time 34290127772 ps
CPU time 24.11 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:13:53 PM PDT 24
Peak memory 196036 kb
Host smart-a8b01685-d082-4b67-a288-ac87e3a99dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142351591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4142351591
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4159711203
Short name T1093
Test name
Test status
Simulation time 732996533 ps
CPU time 1.58 seconds
Started Jul 21 07:13:21 PM PDT 24
Finished Jul 21 07:13:23 PM PDT 24
Peak memory 199972 kb
Host smart-76215ab9-9b8c-4bf4-a60e-f96d6114d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159711203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4159711203
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.614143916
Short name T825
Test name
Test status
Simulation time 21597252368 ps
CPU time 208.91 seconds
Started Jul 21 07:13:28 PM PDT 24
Finished Jul 21 07:16:58 PM PDT 24
Peak memory 216864 kb
Host smart-aa65d9cd-995d-4ebb-b2d8-27d0c4282af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614143916 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.614143916
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.482692589
Short name T1102
Test name
Test status
Simulation time 6833359804 ps
CPU time 7.95 seconds
Started Jul 21 07:13:30 PM PDT 24
Finished Jul 21 07:13:38 PM PDT 24
Peak memory 199488 kb
Host smart-1ba00637-84b2-4fd8-8934-ae9a495c9e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482692589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.482692589
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2178926080
Short name T770
Test name
Test status
Simulation time 75126185793 ps
CPU time 47.43 seconds
Started Jul 21 07:13:24 PM PDT 24
Finished Jul 21 07:14:12 PM PDT 24
Peak memory 200168 kb
Host smart-4d1f6f36-3374-4d8c-9951-f5a865d68bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178926080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2178926080
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.848926509
Short name T849
Test name
Test status
Simulation time 39978957133 ps
CPU time 55.87 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:20:47 PM PDT 24
Peak memory 200208 kb
Host smart-5973664f-01d1-4485-84e3-e1dd0c1ecfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848926509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.848926509
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.11345425
Short name T1044
Test name
Test status
Simulation time 30593363886 ps
CPU time 45.01 seconds
Started Jul 21 07:19:35 PM PDT 24
Finished Jul 21 07:20:36 PM PDT 24
Peak memory 200092 kb
Host smart-baf06835-d6fa-43f4-b3f7-214d1a143aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11345425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.11345425
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1839168092
Short name T191
Test name
Test status
Simulation time 66273604058 ps
CPU time 26.6 seconds
Started Jul 21 07:19:36 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 200116 kb
Host smart-a88f69d7-5212-4521-8dbc-bdd84a7fcd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839168092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1839168092
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2726972734
Short name T871
Test name
Test status
Simulation time 90067494955 ps
CPU time 127.79 seconds
Started Jul 21 07:19:39 PM PDT 24
Finished Jul 21 07:21:59 PM PDT 24
Peak memory 200128 kb
Host smart-cc7d8677-60e0-49b8-91f3-e5be9e8fb611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726972734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2726972734
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2384527511
Short name T253
Test name
Test status
Simulation time 42548812238 ps
CPU time 27.02 seconds
Started Jul 21 07:19:35 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 199948 kb
Host smart-c1cf00c5-bfc7-4d24-b4e5-36d727460657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384527511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2384527511
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3497770576
Short name T524
Test name
Test status
Simulation time 102682385382 ps
CPU time 33.82 seconds
Started Jul 21 07:19:32 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 200144 kb
Host smart-62f61d97-bad4-459a-95c4-032c58a19780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497770576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3497770576
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1568875531
Short name T855
Test name
Test status
Simulation time 173932541493 ps
CPU time 99.71 seconds
Started Jul 21 07:19:32 PM PDT 24
Finished Jul 21 07:21:30 PM PDT 24
Peak memory 200200 kb
Host smart-cf02acda-1639-4ef6-ae22-8aea11fd0e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568875531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1568875531
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3373369110
Short name T555
Test name
Test status
Simulation time 176280117035 ps
CPU time 27.39 seconds
Started Jul 21 07:19:32 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 200196 kb
Host smart-80948f82-e7b2-4c19-98f1-fb3cc077ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373369110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3373369110
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.876516246
Short name T748
Test name
Test status
Simulation time 58037969 ps
CPU time 0.55 seconds
Started Jul 21 07:13:36 PM PDT 24
Finished Jul 21 07:13:37 PM PDT 24
Peak memory 194584 kb
Host smart-805c8f16-43a2-43ce-91a2-a40be472f652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876516246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.876516246
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.971232055
Short name T658
Test name
Test status
Simulation time 118837144704 ps
CPU time 42.44 seconds
Started Jul 21 07:13:36 PM PDT 24
Finished Jul 21 07:14:19 PM PDT 24
Peak memory 200128 kb
Host smart-61c46889-527e-4c9d-8679-f709087f0ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971232055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.971232055
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2745931729
Short name T1063
Test name
Test status
Simulation time 176646827705 ps
CPU time 85.5 seconds
Started Jul 21 07:13:34 PM PDT 24
Finished Jul 21 07:15:01 PM PDT 24
Peak memory 200128 kb
Host smart-33a3c0b7-cebb-44f6-9a00-88a2ea8d3068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745931729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2745931729
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2015325458
Short name T192
Test name
Test status
Simulation time 36016416752 ps
CPU time 20.32 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:56 PM PDT 24
Peak memory 200192 kb
Host smart-020e155b-ed36-4c06-96b6-8f87cc6ee96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015325458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2015325458
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2902732767
Short name T693
Test name
Test status
Simulation time 38927455692 ps
CPU time 67.87 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:14:44 PM PDT 24
Peak memory 200120 kb
Host smart-8b7c9898-4ae7-4935-9db3-c70b5ff24c46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902732767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2902732767
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_loopback.4058716836
Short name T544
Test name
Test status
Simulation time 2504540703 ps
CPU time 5.3 seconds
Started Jul 21 07:13:38 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 198872 kb
Host smart-6ffa8842-8e66-4a88-8b4d-a9e0cc7a775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058716836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4058716836
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2417570317
Short name T987
Test name
Test status
Simulation time 75591334483 ps
CPU time 121.39 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:15:37 PM PDT 24
Peak memory 200144 kb
Host smart-031e0441-056f-4e83-bd60-83fe221a82e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417570317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2417570317
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4006112536
Short name T735
Test name
Test status
Simulation time 21147763017 ps
CPU time 304.71 seconds
Started Jul 21 07:13:36 PM PDT 24
Finished Jul 21 07:18:42 PM PDT 24
Peak memory 200180 kb
Host smart-6d3e4b08-9e21-43fd-a287-4f626b34f27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006112536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4006112536
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.195948027
Short name T777
Test name
Test status
Simulation time 7144179218 ps
CPU time 64.01 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:14:40 PM PDT 24
Peak memory 199016 kb
Host smart-4956b1ab-7201-4a9f-92b2-b60b4bb2386d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195948027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.195948027
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1926164966
Short name T89
Test name
Test status
Simulation time 66490448520 ps
CPU time 33.42 seconds
Started Jul 21 07:13:34 PM PDT 24
Finished Jul 21 07:14:08 PM PDT 24
Peak memory 200092 kb
Host smart-f51f3c1e-6d0e-4947-a92b-f7d1ca418cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926164966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1926164966
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.586157591
Short name T1159
Test name
Test status
Simulation time 6132037041 ps
CPU time 5.49 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:42 PM PDT 24
Peak memory 197012 kb
Host smart-9eb5f1bc-0952-4ec3-b5a2-b7786125f040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586157591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.586157591
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1808523031
Short name T786
Test name
Test status
Simulation time 702869863 ps
CPU time 1.68 seconds
Started Jul 21 07:13:29 PM PDT 24
Finished Jul 21 07:13:31 PM PDT 24
Peak memory 198908 kb
Host smart-029b4b25-539f-4500-b6b9-ca19681244c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808523031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1808523031
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2991929194
Short name T17
Test name
Test status
Simulation time 57550380583 ps
CPU time 44.41 seconds
Started Jul 21 07:13:34 PM PDT 24
Finished Jul 21 07:14:18 PM PDT 24
Peak memory 200072 kb
Host smart-8786437c-b467-4e0e-96ea-48e9b3333f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991929194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2991929194
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3698805808
Short name T588
Test name
Test status
Simulation time 13253161176 ps
CPU time 22.27 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:58 PM PDT 24
Peak memory 200184 kb
Host smart-0d86ebe7-0c3c-4c09-9029-afaba2b57761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698805808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3698805808
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3906838170
Short name T1052
Test name
Test status
Simulation time 40831794427 ps
CPU time 78.31 seconds
Started Jul 21 07:13:29 PM PDT 24
Finished Jul 21 07:14:48 PM PDT 24
Peak memory 200136 kb
Host smart-038d9fd5-9949-4593-b25d-3d6ec5ae1676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906838170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3906838170
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1334027451
Short name T966
Test name
Test status
Simulation time 45094388358 ps
CPU time 70.88 seconds
Started Jul 21 07:19:34 PM PDT 24
Finished Jul 21 07:21:02 PM PDT 24
Peak memory 200148 kb
Host smart-4b239194-b274-4a35-9783-38f07d63a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334027451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1334027451
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2801283760
Short name T487
Test name
Test status
Simulation time 90408365207 ps
CPU time 174.03 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:22:45 PM PDT 24
Peak memory 200184 kb
Host smart-807d7761-774a-472d-a584-3e102517d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801283760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2801283760
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2503748259
Short name T125
Test name
Test status
Simulation time 51509649084 ps
CPU time 84.8 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:21:15 PM PDT 24
Peak memory 200124 kb
Host smart-f1d1e14d-1ca9-4a97-9560-15850dc3d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503748259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2503748259
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1226727740
Short name T666
Test name
Test status
Simulation time 28288419636 ps
CPU time 12.37 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:03 PM PDT 24
Peak memory 200104 kb
Host smart-b7371757-73ba-4399-998d-bc13e127dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226727740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1226727740
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4152196207
Short name T275
Test name
Test status
Simulation time 74133122656 ps
CPU time 119.09 seconds
Started Jul 21 07:19:36 PM PDT 24
Finished Jul 21 07:21:50 PM PDT 24
Peak memory 199856 kb
Host smart-f8fd552d-0c55-4c8c-a366-faaaa5fe3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152196207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4152196207
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3088968515
Short name T581
Test name
Test status
Simulation time 93947961063 ps
CPU time 193.69 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:23:04 PM PDT 24
Peak memory 200212 kb
Host smart-efe5b224-c9c9-4d70-ac8e-da35ae0a0a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088968515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3088968515
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3456251922
Short name T130
Test name
Test status
Simulation time 97246542131 ps
CPU time 36.64 seconds
Started Jul 21 07:19:35 PM PDT 24
Finished Jul 21 07:20:27 PM PDT 24
Peak memory 200060 kb
Host smart-31e27bed-c49e-471e-9b7b-b642bddc57ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456251922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3456251922
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3460305310
Short name T584
Test name
Test status
Simulation time 16422318209 ps
CPU time 22.83 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:13 PM PDT 24
Peak memory 200196 kb
Host smart-2505615c-114a-470c-9f09-ec01ecbbeb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460305310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3460305310
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3667150917
Short name T409
Test name
Test status
Simulation time 73807626139 ps
CPU time 164.42 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:22:35 PM PDT 24
Peak memory 200224 kb
Host smart-44e1f59b-f89e-4dea-bf39-716339cbbf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667150917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3667150917
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4056530980
Short name T595
Test name
Test status
Simulation time 43539995 ps
CPU time 0.59 seconds
Started Jul 21 07:13:42 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 195868 kb
Host smart-40db7af5-0e12-4689-9070-1133bcf159a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056530980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4056530980
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1851514824
Short name T643
Test name
Test status
Simulation time 210644514235 ps
CPU time 224.28 seconds
Started Jul 21 07:13:34 PM PDT 24
Finished Jul 21 07:17:19 PM PDT 24
Peak memory 200184 kb
Host smart-e1e3a519-42f7-4f9c-b251-16d353df5869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851514824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1851514824
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2638817883
Short name T509
Test name
Test status
Simulation time 64020957518 ps
CPU time 28.76 seconds
Started Jul 21 07:13:36 PM PDT 24
Finished Jul 21 07:14:06 PM PDT 24
Peak memory 200168 kb
Host smart-3ec20f8c-c032-4cb2-8eba-5b93dda9a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638817883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2638817883
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.849832873
Short name T1163
Test name
Test status
Simulation time 29336655841 ps
CPU time 7.05 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 199876 kb
Host smart-ec45f108-0eb3-44e8-9f17-215ef5e8228d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849832873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.849832873
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3185206993
Short name T733
Test name
Test status
Simulation time 182712697317 ps
CPU time 1777.6 seconds
Started Jul 21 07:13:47 PM PDT 24
Finished Jul 21 07:43:26 PM PDT 24
Peak memory 200208 kb
Host smart-f3fd49bb-d822-4100-8a6c-ceab5b8085fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185206993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3185206993
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1051137939
Short name T1088
Test name
Test status
Simulation time 4602135253 ps
CPU time 4.43 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:13:46 PM PDT 24
Peak memory 200104 kb
Host smart-1a4dbeb8-fee3-4d8c-879d-1deb13c777fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051137939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1051137939
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.29608374
Short name T282
Test name
Test status
Simulation time 40416793956 ps
CPU time 17.39 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:54 PM PDT 24
Peak memory 197060 kb
Host smart-02a57bb9-8eb9-4aba-9356-312b634bc5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29608374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.29608374
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.379944962
Short name T1134
Test name
Test status
Simulation time 26054670393 ps
CPU time 338.22 seconds
Started Jul 21 07:13:48 PM PDT 24
Finished Jul 21 07:19:27 PM PDT 24
Peak memory 200148 kb
Host smart-24c53109-70d3-4bb7-ad3b-ee1d4cd26bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379944962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.379944962
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.547586577
Short name T390
Test name
Test status
Simulation time 5298542417 ps
CPU time 22.21 seconds
Started Jul 21 07:13:35 PM PDT 24
Finished Jul 21 07:13:58 PM PDT 24
Peak memory 198388 kb
Host smart-810b6021-e988-474e-bc57-4b109670b3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547586577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.547586577
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2866378365
Short name T547
Test name
Test status
Simulation time 40127643358 ps
CPU time 65.86 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:14:47 PM PDT 24
Peak memory 199928 kb
Host smart-00d48f00-8797-4813-b9e8-14a1a052c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866378365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2866378365
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3378215458
Short name T758
Test name
Test status
Simulation time 4478572561 ps
CPU time 3.98 seconds
Started Jul 21 07:13:49 PM PDT 24
Finished Jul 21 07:13:54 PM PDT 24
Peak memory 196728 kb
Host smart-5f233a1e-7e6c-4d0f-af19-763a47bbecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378215458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3378215458
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.25816478
Short name T627
Test name
Test status
Simulation time 5809900908 ps
CPU time 17.03 seconds
Started Jul 21 07:13:36 PM PDT 24
Finished Jul 21 07:13:53 PM PDT 24
Peak memory 199400 kb
Host smart-4b57a461-ae10-4537-bfec-cc09004586f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25816478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.25816478
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1009301233
Short name T845
Test name
Test status
Simulation time 38460635997 ps
CPU time 578.82 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:23:20 PM PDT 24
Peak memory 200208 kb
Host smart-d911267c-614e-4a15-ae78-a30422f458cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009301233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1009301233
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2862517265
Short name T504
Test name
Test status
Simulation time 13583038755 ps
CPU time 159.87 seconds
Started Jul 21 07:13:49 PM PDT 24
Finished Jul 21 07:16:29 PM PDT 24
Peak memory 208624 kb
Host smart-cbd77a52-9a5b-4ae1-b2f4-bbfdc9a7586e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862517265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2862517265
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1505172626
Short name T395
Test name
Test status
Simulation time 1837649303 ps
CPU time 2.76 seconds
Started Jul 21 07:13:42 PM PDT 24
Finished Jul 21 07:13:45 PM PDT 24
Peak memory 200020 kb
Host smart-060e1bf1-e598-4c9d-8a13-4e69924a6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505172626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1505172626
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1851078463
Short name T1136
Test name
Test status
Simulation time 17893861633 ps
CPU time 13.86 seconds
Started Jul 21 07:13:34 PM PDT 24
Finished Jul 21 07:13:48 PM PDT 24
Peak memory 200140 kb
Host smart-dc0e7772-dc71-4dcf-9aab-b87c48edf8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851078463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1851078463
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3867779249
Short name T272
Test name
Test status
Simulation time 18793084519 ps
CPU time 33.06 seconds
Started Jul 21 07:19:36 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 200176 kb
Host smart-ee6eaa72-0e4c-420c-b24e-74501c802bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867779249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3867779249
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3772267914
Short name T207
Test name
Test status
Simulation time 24877602070 ps
CPU time 48 seconds
Started Jul 21 07:19:31 PM PDT 24
Finished Jul 21 07:20:38 PM PDT 24
Peak memory 200056 kb
Host smart-0bae29d5-7eea-482e-a7d8-408e9073c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772267914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3772267914
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.954760368
Short name T175
Test name
Test status
Simulation time 130949536109 ps
CPU time 79.02 seconds
Started Jul 21 07:19:35 PM PDT 24
Finished Jul 21 07:21:10 PM PDT 24
Peak memory 200052 kb
Host smart-0789e70e-56a7-4266-892c-043792ee852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954760368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.954760368
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3376976399
Short name T41
Test name
Test status
Simulation time 22331567147 ps
CPU time 29.91 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:20:20 PM PDT 24
Peak memory 200196 kb
Host smart-4a1d3a3c-d745-4bb6-b8d0-818d30b282a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376976399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3376976399
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.435069382
Short name T220
Test name
Test status
Simulation time 122833027294 ps
CPU time 93.15 seconds
Started Jul 21 07:19:33 PM PDT 24
Finished Jul 21 07:21:23 PM PDT 24
Peak memory 200192 kb
Host smart-f7e943e9-ee83-4434-8139-82087dc39a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435069382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.435069382
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3859183562
Short name T920
Test name
Test status
Simulation time 24528709209 ps
CPU time 36.93 seconds
Started Jul 21 07:19:32 PM PDT 24
Finished Jul 21 07:20:27 PM PDT 24
Peak memory 200200 kb
Host smart-0b3b5d71-6a17-46f9-bfc2-3e3d419fc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859183562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3859183562
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.546049609
Short name T252
Test name
Test status
Simulation time 40135505745 ps
CPU time 13.83 seconds
Started Jul 21 07:19:40 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 200220 kb
Host smart-0dfdf554-6339-4cf6-b159-d5d9111ee518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546049609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.546049609
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.944492162
Short name T539
Test name
Test status
Simulation time 29811137 ps
CPU time 0.57 seconds
Started Jul 21 07:13:47 PM PDT 24
Finished Jul 21 07:13:48 PM PDT 24
Peak memory 195840 kb
Host smart-3f92dc55-60e9-4799-b005-b9d4ae970f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944492162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.944492162
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4267235307
Short name T755
Test name
Test status
Simulation time 194413023891 ps
CPU time 440.98 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:21:02 PM PDT 24
Peak memory 200156 kb
Host smart-af35fb98-6cd3-4304-b1e4-b8f6d5ef9023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267235307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4267235307
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.778284618
Short name T760
Test name
Test status
Simulation time 25693418740 ps
CPU time 23.17 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 200192 kb
Host smart-adc085ed-cbb2-4c38-833d-6d185010b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778284618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.778284618
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.1908118237
Short name T1057
Test name
Test status
Simulation time 3171995117 ps
CPU time 1.97 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:13:44 PM PDT 24
Peak memory 196992 kb
Host smart-80745506-8f1c-44c3-a76d-b9b1f988b13b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908118237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1908118237
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1428092253
Short name T927
Test name
Test status
Simulation time 81691399381 ps
CPU time 270.86 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:18:12 PM PDT 24
Peak memory 200168 kb
Host smart-fdf08a37-e1ca-44f6-a342-f0596d7148e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428092253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1428092253
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1433283552
Short name T551
Test name
Test status
Simulation time 1258108642 ps
CPU time 2.9 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:13:44 PM PDT 24
Peak memory 198968 kb
Host smart-bf9c03f7-701c-48de-91d5-b74ae79b8a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433283552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1433283552
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2059987090
Short name T1000
Test name
Test status
Simulation time 184966985641 ps
CPU time 77.44 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 208524 kb
Host smart-86b28744-c4e0-4648-9a3c-4ca90834eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059987090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2059987090
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3084998844
Short name T892
Test name
Test status
Simulation time 8605290210 ps
CPU time 434.66 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:20:56 PM PDT 24
Peak memory 200164 kb
Host smart-b50a968e-7ad5-42b5-92b5-a437c4684cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084998844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3084998844
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.491616685
Short name T1085
Test name
Test status
Simulation time 5458080913 ps
CPU time 23.77 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 198312 kb
Host smart-7746f6cb-e62b-47ec-a54e-88184b1aeec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491616685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.491616685
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1620443149
Short name T1146
Test name
Test status
Simulation time 90064412113 ps
CPU time 15.53 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:13:56 PM PDT 24
Peak memory 199792 kb
Host smart-5db4af47-fae4-497e-8d0f-759935b09d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620443149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1620443149
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3959496441
Short name T732
Test name
Test status
Simulation time 5686904538 ps
CPU time 1.12 seconds
Started Jul 21 07:13:39 PM PDT 24
Finished Jul 21 07:13:40 PM PDT 24
Peak memory 196468 kb
Host smart-5b96b356-f7ac-4061-ad58-1f7bbc9e570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959496441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3959496441
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.997389063
Short name T914
Test name
Test status
Simulation time 5969308292 ps
CPU time 14.63 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:13:55 PM PDT 24
Peak memory 199448 kb
Host smart-56938528-cb58-41a8-bad2-2e81d6071888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997389063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.997389063
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3841002007
Short name T1054
Test name
Test status
Simulation time 176057903321 ps
CPU time 511.68 seconds
Started Jul 21 07:13:40 PM PDT 24
Finished Jul 21 07:22:12 PM PDT 24
Peak memory 216660 kb
Host smart-eff58307-314a-4c53-ad47-c65ff3121f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841002007 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3841002007
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1888830694
Short name T798
Test name
Test status
Simulation time 8107310981 ps
CPU time 11.29 seconds
Started Jul 21 07:13:42 PM PDT 24
Finished Jul 21 07:13:54 PM PDT 24
Peak memory 200196 kb
Host smart-49eab4b3-1a64-451a-aa4d-ea6933e510a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888830694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1888830694
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1963693539
Short name T1042
Test name
Test status
Simulation time 31039567080 ps
CPU time 48.27 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:14:30 PM PDT 24
Peak memory 200136 kb
Host smart-ab599c6b-1aa9-444e-92a9-1afbfcf866b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963693539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1963693539
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3137763759
Short name T863
Test name
Test status
Simulation time 75736574356 ps
CPU time 121.64 seconds
Started Jul 21 07:19:44 PM PDT 24
Finished Jul 21 07:21:54 PM PDT 24
Peak memory 200056 kb
Host smart-7e78c3e3-bc24-4b76-bf9c-ff579628a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137763759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3137763759
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1966341978
Short name T680
Test name
Test status
Simulation time 10132128701 ps
CPU time 22.67 seconds
Started Jul 21 07:19:46 PM PDT 24
Finished Jul 21 07:20:15 PM PDT 24
Peak memory 200128 kb
Host smart-536ec7f1-0091-4395-841a-68062d447f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966341978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1966341978
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2219876265
Short name T663
Test name
Test status
Simulation time 84584162427 ps
CPU time 73.4 seconds
Started Jul 21 07:19:43 PM PDT 24
Finished Jul 21 07:21:05 PM PDT 24
Peak memory 200144 kb
Host smart-09d53808-e02d-4b5f-b4a7-3806ec939f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219876265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2219876265
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.373058558
Short name T228
Test name
Test status
Simulation time 96939657825 ps
CPU time 12.08 seconds
Started Jul 21 07:19:43 PM PDT 24
Finished Jul 21 07:20:04 PM PDT 24
Peak memory 200196 kb
Host smart-7f3b918e-7e83-4957-af24-afb6d79b7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373058558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.373058558
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2584871278
Short name T736
Test name
Test status
Simulation time 154947584084 ps
CPU time 579.55 seconds
Started Jul 21 07:19:47 PM PDT 24
Finished Jul 21 07:29:32 PM PDT 24
Peak memory 200128 kb
Host smart-9ac185b5-1d1d-45c9-bc2a-51b364e6c564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584871278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2584871278
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1829887024
Short name T182
Test name
Test status
Simulation time 14083693076 ps
CPU time 26.74 seconds
Started Jul 21 07:19:44 PM PDT 24
Finished Jul 21 07:20:19 PM PDT 24
Peak memory 200236 kb
Host smart-a0b8300d-681f-49e6-92f6-b1aafab5e09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829887024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1829887024
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1309684642
Short name T893
Test name
Test status
Simulation time 135666173901 ps
CPU time 97.08 seconds
Started Jul 21 07:19:43 PM PDT 24
Finished Jul 21 07:21:29 PM PDT 24
Peak memory 200108 kb
Host smart-5bcd5168-623b-4980-98fa-159e432d3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309684642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1309684642
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1257979620
Short name T229
Test name
Test status
Simulation time 68235012098 ps
CPU time 24.21 seconds
Started Jul 21 07:19:44 PM PDT 24
Finished Jul 21 07:20:16 PM PDT 24
Peak memory 200084 kb
Host smart-bd113c5b-8b2d-4224-bfa3-3fd1352fd29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257979620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1257979620
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.162991648
Short name T1089
Test name
Test status
Simulation time 257842156981 ps
CPU time 144.41 seconds
Started Jul 21 07:19:47 PM PDT 24
Finished Jul 21 07:22:17 PM PDT 24
Peak memory 200044 kb
Host smart-90b99b74-103b-482a-aa7f-036ee493af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162991648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.162991648
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1586154650
Short name T850
Test name
Test status
Simulation time 140357249 ps
CPU time 0.58 seconds
Started Jul 21 07:13:51 PM PDT 24
Finished Jul 21 07:13:52 PM PDT 24
Peak memory 195596 kb
Host smart-2c0e83e2-fa5a-4e99-9ec1-c25382bd0936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586154650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1586154650
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.266804303
Short name T1115
Test name
Test status
Simulation time 237216208583 ps
CPU time 394.45 seconds
Started Jul 21 07:13:44 PM PDT 24
Finished Jul 21 07:20:19 PM PDT 24
Peak memory 200160 kb
Host smart-a82deda4-39d4-4bfd-bef1-a26d49a9f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266804303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.266804303
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2085879816
Short name T1087
Test name
Test status
Simulation time 202891042084 ps
CPU time 21.5 seconds
Started Jul 21 07:13:45 PM PDT 24
Finished Jul 21 07:14:07 PM PDT 24
Peak memory 200180 kb
Host smart-515893de-d361-45f6-8135-39bec1d422cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085879816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2085879816
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2421617737
Short name T876
Test name
Test status
Simulation time 9003706426 ps
CPU time 16.76 seconds
Started Jul 21 07:13:46 PM PDT 24
Finished Jul 21 07:14:03 PM PDT 24
Peak memory 200120 kb
Host smart-fa07dceb-9182-4db1-a96a-47b1a8e92592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421617737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2421617737
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3725914706
Short name T457
Test name
Test status
Simulation time 33192477737 ps
CPU time 15.81 seconds
Started Jul 21 07:13:44 PM PDT 24
Finished Jul 21 07:14:00 PM PDT 24
Peak memory 199784 kb
Host smart-6aa1f3ea-b4ef-4a39-943e-49cd3eec09e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725914706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3725914706
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1109069026
Short name T963
Test name
Test status
Simulation time 284609186285 ps
CPU time 125.82 seconds
Started Jul 21 07:13:49 PM PDT 24
Finished Jul 21 07:15:56 PM PDT 24
Peak memory 200104 kb
Host smart-2e9866a4-b1e2-4fa3-8ff7-f353b561cecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109069026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1109069026
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3339421478
Short name T546
Test name
Test status
Simulation time 8112292429 ps
CPU time 13.58 seconds
Started Jul 21 07:13:47 PM PDT 24
Finished Jul 21 07:14:02 PM PDT 24
Peak memory 199896 kb
Host smart-99597405-ec42-4391-9de7-63d2477c6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339421478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3339421478
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4001104284
Short name T513
Test name
Test status
Simulation time 70604175911 ps
CPU time 17.58 seconds
Started Jul 21 07:13:46 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 198176 kb
Host smart-e2d5f9cf-36ef-485a-8a34-fa2948db73b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001104284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4001104284
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3572452721
Short name T708
Test name
Test status
Simulation time 11811864494 ps
CPU time 687.07 seconds
Started Jul 21 07:13:46 PM PDT 24
Finished Jul 21 07:25:13 PM PDT 24
Peak memory 200204 kb
Host smart-eccee189-967d-4483-8679-b835d8b2ee89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572452721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3572452721
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2746239906
Short name T592
Test name
Test status
Simulation time 4537612392 ps
CPU time 34.87 seconds
Started Jul 21 07:13:45 PM PDT 24
Finished Jul 21 07:14:20 PM PDT 24
Peak memory 198036 kb
Host smart-ca9f467a-2e1d-48b7-81b8-d6e93f45f328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746239906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2746239906
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.658810830
Short name T810
Test name
Test status
Simulation time 33419942066 ps
CPU time 31.28 seconds
Started Jul 21 07:13:48 PM PDT 24
Finished Jul 21 07:14:19 PM PDT 24
Peak memory 200120 kb
Host smart-89aa3731-2b0e-4f37-a81f-c258939b0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658810830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.658810830
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.961404465
Short name T757
Test name
Test status
Simulation time 34103711919 ps
CPU time 12.88 seconds
Started Jul 21 07:13:44 PM PDT 24
Finished Jul 21 07:13:57 PM PDT 24
Peak memory 196200 kb
Host smart-c32bc094-af12-4a82-b5ee-77c023b4f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961404465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.961404465
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.565207541
Short name T936
Test name
Test status
Simulation time 736962379 ps
CPU time 1.68 seconds
Started Jul 21 07:13:41 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 198520 kb
Host smart-0cafa433-a847-4da9-aa7b-83b7d0994eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565207541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.565207541
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3623626233
Short name T610
Test name
Test status
Simulation time 50316880367 ps
CPU time 460.36 seconds
Started Jul 21 07:13:51 PM PDT 24
Finished Jul 21 07:21:32 PM PDT 24
Peak memory 216668 kb
Host smart-a2b67cd8-8e31-4db5-b0c4-1f7c3fe289e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623626233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3623626233
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2252329509
Short name T497
Test name
Test status
Simulation time 1355100825 ps
CPU time 4.97 seconds
Started Jul 21 07:13:43 PM PDT 24
Finished Jul 21 07:13:49 PM PDT 24
Peak memory 199720 kb
Host smart-4d9b57e1-2683-4446-b032-0a82e5047688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252329509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2252329509
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3008731587
Short name T797
Test name
Test status
Simulation time 19443458831 ps
CPU time 17.1 seconds
Started Jul 21 07:13:44 PM PDT 24
Finished Jul 21 07:14:02 PM PDT 24
Peak memory 200108 kb
Host smart-8af485d4-1d62-4c32-bd57-de1dd5c4122a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008731587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3008731587
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1044139188
Short name T756
Test name
Test status
Simulation time 177662114878 ps
CPU time 68.3 seconds
Started Jul 21 07:19:44 PM PDT 24
Finished Jul 21 07:21:00 PM PDT 24
Peak memory 200196 kb
Host smart-77698d65-797d-44d1-99a0-e560a9ff99c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044139188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1044139188
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3056305522
Short name T785
Test name
Test status
Simulation time 70538033903 ps
CPU time 102.01 seconds
Started Jul 21 07:19:50 PM PDT 24
Finished Jul 21 07:21:35 PM PDT 24
Peak memory 200236 kb
Host smart-325e5439-f945-4546-9e08-9cc618267ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056305522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3056305522
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1623837939
Short name T648
Test name
Test status
Simulation time 24077824837 ps
CPU time 15.46 seconds
Started Jul 21 07:19:51 PM PDT 24
Finished Jul 21 07:20:09 PM PDT 24
Peak memory 200116 kb
Host smart-261305eb-59de-4c28-b4de-2a1334370364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623837939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1623837939
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4270136309
Short name T1156
Test name
Test status
Simulation time 27800347848 ps
CPU time 59.72 seconds
Started Jul 21 07:19:59 PM PDT 24
Finished Jul 21 07:20:59 PM PDT 24
Peak memory 200124 kb
Host smart-fa4cbe2e-e6b3-4184-9e53-abe2ca97187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270136309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4270136309
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3273699872
Short name T338
Test name
Test status
Simulation time 88292285048 ps
CPU time 126.74 seconds
Started Jul 21 07:19:56 PM PDT 24
Finished Jul 21 07:22:04 PM PDT 24
Peak memory 200144 kb
Host smart-9f524018-4bb9-45ca-912c-4db95656390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273699872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3273699872
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.368245841
Short name T587
Test name
Test status
Simulation time 84218688884 ps
CPU time 27.61 seconds
Started Jul 21 07:19:56 PM PDT 24
Finished Jul 21 07:20:25 PM PDT 24
Peak memory 200152 kb
Host smart-141919c7-810b-4d83-b224-feb0f05b2d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368245841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.368245841
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1177131063
Short name T171
Test name
Test status
Simulation time 85354116657 ps
CPU time 121.88 seconds
Started Jul 21 07:19:56 PM PDT 24
Finished Jul 21 07:21:59 PM PDT 24
Peak memory 200212 kb
Host smart-136b1d04-efb4-4a5e-8009-bc51449a2fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177131063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1177131063
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3779989881
Short name T647
Test name
Test status
Simulation time 15803611422 ps
CPU time 12.72 seconds
Started Jul 21 07:19:56 PM PDT 24
Finished Jul 21 07:20:10 PM PDT 24
Peak memory 200112 kb
Host smart-ef79966b-d11b-4079-aab0-2464ca565779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779989881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3779989881
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2013243585
Short name T430
Test name
Test status
Simulation time 70738134335 ps
CPU time 106.16 seconds
Started Jul 21 07:20:00 PM PDT 24
Finished Jul 21 07:21:46 PM PDT 24
Peak memory 200216 kb
Host smart-eaabf45a-98ba-4a69-878c-294e048b4518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013243585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2013243585
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.875588437
Short name T213
Test name
Test status
Simulation time 16274658196 ps
CPU time 12.7 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:20:20 PM PDT 24
Peak memory 200176 kb
Host smart-3686c8ba-353b-43b1-a2e2-6a2ae38db5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875588437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.875588437
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1985300758
Short name T857
Test name
Test status
Simulation time 38091775 ps
CPU time 0.53 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:13:59 PM PDT 24
Peak memory 195568 kb
Host smart-6b97be0a-d95b-452f-a22b-e5365cb13920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985300758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1985300758
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.417027745
Short name T1152
Test name
Test status
Simulation time 40400005668 ps
CPU time 18.03 seconds
Started Jul 21 07:13:50 PM PDT 24
Finished Jul 21 07:14:09 PM PDT 24
Peak memory 200036 kb
Host smart-4fa95b65-959c-4edd-9752-98b4217631d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417027745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.417027745
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1071577964
Short name T512
Test name
Test status
Simulation time 176102729025 ps
CPU time 367.89 seconds
Started Jul 21 07:13:50 PM PDT 24
Finished Jul 21 07:19:59 PM PDT 24
Peak memory 200192 kb
Host smart-795e0933-906b-487e-9eb6-1d66249ea83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071577964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1071577964
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.60399522
Short name T705
Test name
Test status
Simulation time 14998197915 ps
CPU time 23.33 seconds
Started Jul 21 07:13:52 PM PDT 24
Finished Jul 21 07:14:16 PM PDT 24
Peak memory 199924 kb
Host smart-214519d1-9ada-42f1-813a-4d04346523cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60399522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.60399522
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2477229436
Short name T1168
Test name
Test status
Simulation time 171882368614 ps
CPU time 169.95 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:16:49 PM PDT 24
Peak memory 199996 kb
Host smart-f782f666-93e3-4c53-88e9-1c60e00e699c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477229436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2477229436
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.861424286
Short name T582
Test name
Test status
Simulation time 4700561400 ps
CPU time 7.87 seconds
Started Jul 21 07:13:59 PM PDT 24
Finished Jul 21 07:14:07 PM PDT 24
Peak memory 198916 kb
Host smart-e09cc173-dd3d-4e16-af2d-0262e2afb4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861424286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.861424286
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3796902623
Short name T644
Test name
Test status
Simulation time 28914398575 ps
CPU time 51.89 seconds
Started Jul 21 07:13:57 PM PDT 24
Finished Jul 21 07:14:50 PM PDT 24
Peak memory 199496 kb
Host smart-a7ba803e-ef71-4b0e-9d75-f9a4cf67a539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796902623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3796902623
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3048977125
Short name T939
Test name
Test status
Simulation time 4258876735 ps
CPU time 51.64 seconds
Started Jul 21 07:14:00 PM PDT 24
Finished Jul 21 07:14:52 PM PDT 24
Peak memory 200160 kb
Host smart-b1491239-cea4-4362-8abd-ad26b4aacbe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048977125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3048977125
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.496906478
Short name T458
Test name
Test status
Simulation time 6945299523 ps
CPU time 60.25 seconds
Started Jul 21 07:13:50 PM PDT 24
Finished Jul 21 07:14:51 PM PDT 24
Peak memory 198388 kb
Host smart-311b17cc-3a3a-4c58-b5d9-04753ba69182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496906478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.496906478
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1433951819
Short name T640
Test name
Test status
Simulation time 28821691186 ps
CPU time 40.65 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:14:40 PM PDT 24
Peak memory 198452 kb
Host smart-6e2f0464-acae-43ed-bcc1-4defc75b6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433951819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1433951819
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2621280062
Short name T774
Test name
Test status
Simulation time 37051144693 ps
CPU time 56.22 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:14:55 PM PDT 24
Peak memory 196220 kb
Host smart-c61d8e2c-f03c-48dd-bf9a-ecd3bbb6b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621280062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2621280062
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3271148492
Short name T294
Test name
Test status
Simulation time 5974552512 ps
CPU time 21.82 seconds
Started Jul 21 07:13:49 PM PDT 24
Finished Jul 21 07:14:12 PM PDT 24
Peak memory 199732 kb
Host smart-166c40b7-ba7c-4635-88ce-aeb30492e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271148492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3271148492
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.287092167
Short name T1019
Test name
Test status
Simulation time 216505752935 ps
CPU time 451.76 seconds
Started Jul 21 07:14:01 PM PDT 24
Finished Jul 21 07:21:33 PM PDT 24
Peak memory 200180 kb
Host smart-0c43668f-bf66-4134-95d6-f70c82d99263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287092167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.287092167
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1499012663
Short name T917
Test name
Test status
Simulation time 172773948876 ps
CPU time 318.67 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:19:18 PM PDT 24
Peak memory 216720 kb
Host smart-4b04dceb-76ee-404f-8b16-57dc7b935bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499012663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1499012663
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.535488350
Short name T591
Test name
Test status
Simulation time 6193182170 ps
CPU time 22.67 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:14:21 PM PDT 24
Peak memory 200040 kb
Host smart-2a75e7e7-b47e-41e7-9655-3677001a49f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535488350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.535488350
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2242264130
Short name T495
Test name
Test status
Simulation time 88808934066 ps
CPU time 27.52 seconds
Started Jul 21 07:13:51 PM PDT 24
Finished Jul 21 07:14:19 PM PDT 24
Peak memory 200140 kb
Host smart-87c34213-0441-476f-84c3-9945c7eb9a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242264130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2242264130
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.4189524654
Short name T664
Test name
Test status
Simulation time 112558455286 ps
CPU time 200.93 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:23:30 PM PDT 24
Peak memory 200132 kb
Host smart-c1361cbf-ec58-4d03-9b83-e5a4380e8aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189524654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4189524654
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.900752125
Short name T422
Test name
Test status
Simulation time 101634133335 ps
CPU time 29.84 seconds
Started Jul 21 07:20:06 PM PDT 24
Finished Jul 21 07:20:36 PM PDT 24
Peak memory 200140 kb
Host smart-507169f0-2390-4b92-aef3-0b9ee8fcd68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900752125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.900752125
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1943221906
Short name T949
Test name
Test status
Simulation time 67049174346 ps
CPU time 92.85 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:21:42 PM PDT 24
Peak memory 200164 kb
Host smart-b177fdae-1a91-49c6-9205-ff1549cc328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943221906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1943221906
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1565316614
Short name T824
Test name
Test status
Simulation time 20709368181 ps
CPU time 49.54 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:20:58 PM PDT 24
Peak memory 200212 kb
Host smart-f81d8eb2-6e0b-4aae-9614-d22a9c72d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565316614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1565316614
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3044705505
Short name T763
Test name
Test status
Simulation time 17818274142 ps
CPU time 34.73 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:20:44 PM PDT 24
Peak memory 200064 kb
Host smart-cab57a12-2c54-4ae9-81e5-ef9741bab7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044705505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3044705505
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1339249314
Short name T122
Test name
Test status
Simulation time 115019177299 ps
CPU time 57.81 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:21:06 PM PDT 24
Peak memory 200132 kb
Host smart-18a15a3b-eaf2-43e3-9112-aafec1945de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339249314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1339249314
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3656361087
Short name T570
Test name
Test status
Simulation time 54859836381 ps
CPU time 175.12 seconds
Started Jul 21 07:20:09 PM PDT 24
Finished Jul 21 07:23:06 PM PDT 24
Peak memory 200100 kb
Host smart-a4490e2b-4a5e-4c44-bcda-8083433feec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656361087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3656361087
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1833816201
Short name T1160
Test name
Test status
Simulation time 21608000219 ps
CPU time 25.7 seconds
Started Jul 21 07:20:10 PM PDT 24
Finished Jul 21 07:20:36 PM PDT 24
Peak memory 200144 kb
Host smart-6ef0e733-b8cb-48f8-b34f-90b160f56651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833816201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1833816201
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2247797706
Short name T867
Test name
Test status
Simulation time 36433313 ps
CPU time 0.57 seconds
Started Jul 21 07:14:03 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 195556 kb
Host smart-82107eb4-d021-464f-9543-02707b3a4158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247797706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2247797706
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3760422123
Short name T261
Test name
Test status
Simulation time 43845647529 ps
CPU time 19.8 seconds
Started Jul 21 07:14:00 PM PDT 24
Finished Jul 21 07:14:20 PM PDT 24
Peak memory 200132 kb
Host smart-1371dfc8-efa7-4c18-a2f4-13429c857831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760422123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3760422123
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.558108062
Short name T964
Test name
Test status
Simulation time 82267226366 ps
CPU time 11.26 seconds
Started Jul 21 07:14:00 PM PDT 24
Finished Jul 21 07:14:12 PM PDT 24
Peak memory 200200 kb
Host smart-846c5d60-15a9-4e18-9604-36c879960753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558108062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.558108062
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2854598331
Short name T906
Test name
Test status
Simulation time 47921219409 ps
CPU time 74.64 seconds
Started Jul 21 07:13:57 PM PDT 24
Finished Jul 21 07:15:13 PM PDT 24
Peak memory 200124 kb
Host smart-a379d911-9656-421f-9ec4-72e7c2b4fa59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854598331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2854598331
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.734708020
Short name T805
Test name
Test status
Simulation time 196115222390 ps
CPU time 284.38 seconds
Started Jul 21 07:14:01 PM PDT 24
Finished Jul 21 07:18:46 PM PDT 24
Peak memory 200120 kb
Host smart-7fb5636f-25cc-4a11-96ec-7cfba54cb911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734708020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.734708020
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1025012983
Short name T416
Test name
Test status
Simulation time 5302267941 ps
CPU time 2.98 seconds
Started Jul 21 07:14:00 PM PDT 24
Finished Jul 21 07:14:03 PM PDT 24
Peak memory 196636 kb
Host smart-364beb8f-34ab-4d9d-b0fb-246eda6d54ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025012983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1025012983
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4111731605
Short name T729
Test name
Test status
Simulation time 41933639541 ps
CPU time 30.31 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:14:29 PM PDT 24
Peak memory 198824 kb
Host smart-fab736a8-c3d2-4430-9a5c-816c3ee878a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111731605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4111731605
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2337691434
Short name T1086
Test name
Test status
Simulation time 5598927387 ps
CPU time 41.25 seconds
Started Jul 21 07:13:58 PM PDT 24
Finished Jul 21 07:14:40 PM PDT 24
Peak memory 198516 kb
Host smart-949ad35a-95e0-44b3-8457-be430298bd92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337691434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2337691434
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2558234630
Short name T127
Test name
Test status
Simulation time 97140327907 ps
CPU time 152.25 seconds
Started Jul 21 07:14:00 PM PDT 24
Finished Jul 21 07:16:33 PM PDT 24
Peak memory 200196 kb
Host smart-9556fa93-1964-4375-9c13-7d5ca422709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558234630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2558234630
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2746360826
Short name T401
Test name
Test status
Simulation time 1369721720 ps
CPU time 2.68 seconds
Started Jul 21 07:14:01 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 195860 kb
Host smart-79e0d7d7-8230-488f-8f63-27cf5427347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746360826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2746360826
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3291221626
Short name T928
Test name
Test status
Simulation time 920929272 ps
CPU time 1.43 seconds
Started Jul 21 07:13:57 PM PDT 24
Finished Jul 21 07:14:00 PM PDT 24
Peak memory 199568 kb
Host smart-064fd7b4-dcf9-474d-ac64-ecd8f942b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291221626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3291221626
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.465650191
Short name T287
Test name
Test status
Simulation time 339932130834 ps
CPU time 151.86 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:16:40 PM PDT 24
Peak memory 208368 kb
Host smart-38e9a4a4-8e7e-42ca-b695-f7efca08d53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465650191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.465650191
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3661291531
Short name T717
Test name
Test status
Simulation time 230086199498 ps
CPU time 689.73 seconds
Started Jul 21 07:14:09 PM PDT 24
Finished Jul 21 07:25:39 PM PDT 24
Peak memory 216620 kb
Host smart-3d4d3edb-5b4b-4f55-acfe-43c2d111102c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661291531 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3661291531
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.261712307
Short name T1065
Test name
Test status
Simulation time 602264256 ps
CPU time 1.99 seconds
Started Jul 21 07:14:01 PM PDT 24
Finished Jul 21 07:14:03 PM PDT 24
Peak memory 198756 kb
Host smart-d6df743b-67bd-49d4-a823-427740a0f2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261712307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.261712307
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.477544515
Short name T968
Test name
Test status
Simulation time 7017722383 ps
CPU time 12.25 seconds
Started Jul 21 07:13:57 PM PDT 24
Finished Jul 21 07:14:10 PM PDT 24
Peak memory 200172 kb
Host smart-a95b36d6-f506-4a81-84c6-e020c7eb68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477544515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.477544515
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2233600556
Short name T942
Test name
Test status
Simulation time 13350985707 ps
CPU time 19.42 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:20:29 PM PDT 24
Peak memory 200164 kb
Host smart-a66f84b9-bf08-4c89-a442-f46ca1ccf5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233600556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2233600556
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.845368378
Short name T234
Test name
Test status
Simulation time 73697956050 ps
CPU time 28.76 seconds
Started Jul 21 07:20:06 PM PDT 24
Finished Jul 21 07:20:35 PM PDT 24
Peak memory 200204 kb
Host smart-f1b615e1-de0c-4a78-a959-ca29b78aa245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845368378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.845368378
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3604698416
Short name T184
Test name
Test status
Simulation time 22475853320 ps
CPU time 30.62 seconds
Started Jul 21 07:20:11 PM PDT 24
Finished Jul 21 07:20:42 PM PDT 24
Peak memory 200192 kb
Host smart-c93682ef-8a97-4de1-94d1-c6926115f8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604698416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3604698416
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2566206303
Short name T209
Test name
Test status
Simulation time 32494458177 ps
CPU time 30.95 seconds
Started Jul 21 07:20:09 PM PDT 24
Finished Jul 21 07:20:42 PM PDT 24
Peak memory 200200 kb
Host smart-0a11ae80-c480-4c21-acad-6eafa2e6b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566206303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2566206303
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3063993047
Short name T356
Test name
Test status
Simulation time 25128194978 ps
CPU time 50.56 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:20:59 PM PDT 24
Peak memory 200128 kb
Host smart-d71b51f4-c9c0-48fb-af4e-26f94df81a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063993047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3063993047
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1887491636
Short name T190
Test name
Test status
Simulation time 72591617743 ps
CPU time 55.36 seconds
Started Jul 21 07:20:09 PM PDT 24
Finished Jul 21 07:21:06 PM PDT 24
Peak memory 200140 kb
Host smart-5df4cb04-3742-49d5-929a-5ce91ede3074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887491636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1887491636
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4204284694
Short name T1059
Test name
Test status
Simulation time 20843007557 ps
CPU time 30.94 seconds
Started Jul 21 07:20:06 PM PDT 24
Finished Jul 21 07:20:37 PM PDT 24
Peak memory 200084 kb
Host smart-7be970bd-8cc4-42de-b28b-3cf197f03b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204284694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4204284694
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.837874538
Short name T1167
Test name
Test status
Simulation time 155779205041 ps
CPU time 27.27 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:20:36 PM PDT 24
Peak memory 200212 kb
Host smart-c95990c4-d5a9-4ee2-8146-f46d6ba86b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837874538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.837874538
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4151639095
Short name T529
Test name
Test status
Simulation time 39362123071 ps
CPU time 15.4 seconds
Started Jul 21 07:20:08 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 200152 kb
Host smart-da9dc5e0-dddf-4512-be80-048a7b2056d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151639095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4151639095
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1899411857
Short name T612
Test name
Test status
Simulation time 14987012920 ps
CPU time 21.18 seconds
Started Jul 21 07:20:11 PM PDT 24
Finished Jul 21 07:20:33 PM PDT 24
Peak memory 200192 kb
Host smart-a13fbb56-a27f-48db-a8f9-bf81c6aa32e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899411857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1899411857
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1301578567
Short name T22
Test name
Test status
Simulation time 12804299 ps
CPU time 0.57 seconds
Started Jul 21 07:14:08 PM PDT 24
Finished Jul 21 07:14:09 PM PDT 24
Peak memory 195860 kb
Host smart-1ae27349-ee73-44d0-b457-04e0cd592ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301578567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1301578567
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3643250582
Short name T1166
Test name
Test status
Simulation time 94342437956 ps
CPU time 46.98 seconds
Started Jul 21 07:14:02 PM PDT 24
Finished Jul 21 07:14:49 PM PDT 24
Peak memory 200172 kb
Host smart-5d488bd0-8f98-4653-934c-9805155920c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643250582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3643250582
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3877333786
Short name T542
Test name
Test status
Simulation time 38676768808 ps
CPU time 53.09 seconds
Started Jul 21 07:14:09 PM PDT 24
Finished Jul 21 07:15:02 PM PDT 24
Peak memory 200100 kb
Host smart-4028fb99-d32d-4cda-b0df-5eae44d51766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877333786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3877333786
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.825106383
Short name T176
Test name
Test status
Simulation time 53499648817 ps
CPU time 62.57 seconds
Started Jul 21 07:14:03 PM PDT 24
Finished Jul 21 07:15:06 PM PDT 24
Peak memory 200176 kb
Host smart-4d7113df-2648-4452-a478-3b6b6a94e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825106383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.825106383
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1804700014
Short name T373
Test name
Test status
Simulation time 26687225512 ps
CPU time 13.71 seconds
Started Jul 21 07:14:02 PM PDT 24
Finished Jul 21 07:14:16 PM PDT 24
Peak memory 200168 kb
Host smart-3aa0228a-4a21-4271-b0ed-8bddfb6bd8d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804700014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1804700014
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4240192609
Short name T304
Test name
Test status
Simulation time 51594104406 ps
CPU time 201.02 seconds
Started Jul 21 07:14:06 PM PDT 24
Finished Jul 21 07:17:28 PM PDT 24
Peak memory 200144 kb
Host smart-7b58c884-4077-4bd4-b033-b0798a67e451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240192609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4240192609
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2442150998
Short name T945
Test name
Test status
Simulation time 3271533839 ps
CPU time 5.94 seconds
Started Jul 21 07:14:06 PM PDT 24
Finished Jul 21 07:14:12 PM PDT 24
Peak memory 196052 kb
Host smart-41d6abb2-126f-4e58-ae33-acf0ccdfa76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442150998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2442150998
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.356671226
Short name T631
Test name
Test status
Simulation time 7061300898 ps
CPU time 11.06 seconds
Started Jul 21 07:14:02 PM PDT 24
Finished Jul 21 07:14:13 PM PDT 24
Peak memory 198592 kb
Host smart-5deeb7c7-8291-42a2-a502-aa4e6c0c3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356671226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.356671226
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3401332449
Short name T269
Test name
Test status
Simulation time 8571961269 ps
CPU time 389.5 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:20:37 PM PDT 24
Peak memory 200188 kb
Host smart-f8810b06-1d50-457c-b58b-8c6a397884c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401332449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3401332449
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2776544803
Short name T408
Test name
Test status
Simulation time 1585690407 ps
CPU time 6.22 seconds
Started Jul 21 07:14:03 PM PDT 24
Finished Jul 21 07:14:10 PM PDT 24
Peak memory 198140 kb
Host smart-ace3575c-10a1-4ac4-8ae8-50451d1a8f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776544803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2776544803
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2184270598
Short name T722
Test name
Test status
Simulation time 164474756609 ps
CPU time 144.6 seconds
Started Jul 21 07:14:06 PM PDT 24
Finished Jul 21 07:16:31 PM PDT 24
Peak memory 200160 kb
Host smart-4bdb9caa-000e-41eb-b837-22b11402188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184270598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2184270598
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1027101414
Short name T470
Test name
Test status
Simulation time 3125271694 ps
CPU time 2.55 seconds
Started Jul 21 07:14:01 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 196308 kb
Host smart-286840a3-9db0-4b36-b8a8-cc9c94a0fd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027101414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1027101414
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3872538550
Short name T342
Test name
Test status
Simulation time 517509158 ps
CPU time 1.53 seconds
Started Jul 21 07:14:02 PM PDT 24
Finished Jul 21 07:14:04 PM PDT 24
Peak memory 199216 kb
Host smart-ed8a993f-cb1f-4372-9582-c047f847dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872538550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3872538550
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3940342422
Short name T883
Test name
Test status
Simulation time 303893356435 ps
CPU time 150.25 seconds
Started Jul 21 07:14:06 PM PDT 24
Finished Jul 21 07:16:37 PM PDT 24
Peak memory 200036 kb
Host smart-046ff368-2b42-40f8-bbf0-ddc57df10340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940342422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3940342422
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3254273682
Short name T307
Test name
Test status
Simulation time 195732454937 ps
CPU time 1841.38 seconds
Started Jul 21 07:14:06 PM PDT 24
Finished Jul 21 07:44:49 PM PDT 24
Peak memory 232892 kb
Host smart-4622ba53-30fb-4e9b-931f-229a7f7a7cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254273682 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3254273682
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.554950301
Short name T571
Test name
Test status
Simulation time 1758764210 ps
CPU time 1.6 seconds
Started Jul 21 07:14:08 PM PDT 24
Finished Jul 21 07:14:10 PM PDT 24
Peak memory 198884 kb
Host smart-beb809de-435e-4c95-9a23-d14a34d302f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554950301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.554950301
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1910946946
Short name T494
Test name
Test status
Simulation time 78786844425 ps
CPU time 67.68 seconds
Started Jul 21 07:14:09 PM PDT 24
Finished Jul 21 07:15:17 PM PDT 24
Peak memory 200128 kb
Host smart-ac851631-8254-49f2-acf1-a2f3b6974768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910946946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1910946946
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1134353463
Short name T188
Test name
Test status
Simulation time 36952837471 ps
CPU time 18.79 seconds
Started Jul 21 07:20:06 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 200200 kb
Host smart-a6ebfdcb-72f0-4948-b37b-7dd500df3c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134353463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1134353463
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1295645868
Short name T477
Test name
Test status
Simulation time 27297132624 ps
CPU time 47.07 seconds
Started Jul 21 07:20:09 PM PDT 24
Finished Jul 21 07:20:58 PM PDT 24
Peak memory 200156 kb
Host smart-ffee6fed-bbc3-48c7-a432-49450e18a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295645868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1295645868
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1075538263
Short name T982
Test name
Test status
Simulation time 336300280891 ps
CPU time 80.22 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:21:28 PM PDT 24
Peak memory 200124 kb
Host smart-f8af6efd-3dd2-4f51-a2b1-fa500022ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075538263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1075538263
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1332545553
Short name T488
Test name
Test status
Simulation time 261145471885 ps
CPU time 104.47 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:21:52 PM PDT 24
Peak memory 200180 kb
Host smart-915da3d5-6d37-4e0d-90e1-373afdcc26ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332545553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1332545553
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1700787505
Short name T152
Test name
Test status
Simulation time 163524419056 ps
CPU time 49.15 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:20:56 PM PDT 24
Peak memory 200316 kb
Host smart-5cfb88de-c5e0-4062-96ad-6322575906dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700787505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1700787505
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.911558287
Short name T918
Test name
Test status
Simulation time 35537241745 ps
CPU time 10.88 seconds
Started Jul 21 07:20:07 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 200112 kb
Host smart-330c62a8-513f-40e0-bdaf-dbd90dd16854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911558287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.911558287
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.481201027
Short name T225
Test name
Test status
Simulation time 120670145578 ps
CPU time 50.22 seconds
Started Jul 21 07:20:12 PM PDT 24
Finished Jul 21 07:21:03 PM PDT 24
Peak memory 200256 kb
Host smart-5d589fab-0e61-4240-8dc3-34a2adc09c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481201027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.481201027
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.459752714
Short name T1040
Test name
Test status
Simulation time 177353324450 ps
CPU time 79.55 seconds
Started Jul 21 07:20:14 PM PDT 24
Finished Jul 21 07:21:34 PM PDT 24
Peak memory 200136 kb
Host smart-f9048c8a-532f-4efb-8b8e-15e653d9f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459752714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.459752714
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1371327229
Short name T1
Test name
Test status
Simulation time 41099321 ps
CPU time 0.56 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:12:44 PM PDT 24
Peak memory 195892 kb
Host smart-60b30cc4-35c8-499b-9a4a-3c40ef2c98dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371327229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1371327229
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1788362574
Short name T1108
Test name
Test status
Simulation time 37523142489 ps
CPU time 31.83 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:13:06 PM PDT 24
Peak memory 200204 kb
Host smart-59212d8f-9b48-4f36-89a7-f5a3c93d0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788362574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1788362574
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1831113108
Short name T632
Test name
Test status
Simulation time 106402932773 ps
CPU time 144.52 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 200220 kb
Host smart-5e3d5158-b3d7-4ff3-a45b-255d22e13f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831113108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1831113108
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2532262156
Short name T536
Test name
Test status
Simulation time 32780647910 ps
CPU time 11.1 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:12:45 PM PDT 24
Peak memory 200220 kb
Host smart-b70eefca-e117-43f9-bd1c-4f18e195d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532262156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2532262156
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.158450709
Short name T286
Test name
Test status
Simulation time 8238799198 ps
CPU time 6.11 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:12:40 PM PDT 24
Peak memory 200124 kb
Host smart-6da76489-17f3-4fd2-9ae8-dfff807ce7ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158450709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.158450709
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3585914498
Short name T247
Test name
Test status
Simulation time 99256739459 ps
CPU time 958.6 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:28:39 PM PDT 24
Peak memory 200192 kb
Host smart-6ab58a35-b154-407f-8697-9562028cc5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585914498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3585914498
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3728524310
Short name T671
Test name
Test status
Simulation time 2622685747 ps
CPU time 4.58 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:12:46 PM PDT 24
Peak memory 196352 kb
Host smart-b5424614-dc06-4546-b538-33f4f8884191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728524310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3728524310
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2633051946
Short name T1008
Test name
Test status
Simulation time 6499693465 ps
CPU time 5.35 seconds
Started Jul 21 07:12:35 PM PDT 24
Finished Jul 21 07:12:41 PM PDT 24
Peak memory 194720 kb
Host smart-fbf879f1-c84f-4c60-bbad-e5b255ec04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633051946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2633051946
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3867648641
Short name T1173
Test name
Test status
Simulation time 28695607824 ps
CPU time 1708.5 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:41:09 PM PDT 24
Peak memory 200180 kb
Host smart-28039810-95f1-4505-a3cf-e2f36d5e6c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867648641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3867648641
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1530943687
Short name T364
Test name
Test status
Simulation time 7212104685 ps
CPU time 32.47 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:13:05 PM PDT 24
Peak memory 198396 kb
Host smart-bde5d3ec-4144-41ec-9d6e-bcf0b0d2639b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530943687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1530943687
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3609632567
Short name T622
Test name
Test status
Simulation time 206126417135 ps
CPU time 23.49 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:13:06 PM PDT 24
Peak memory 198496 kb
Host smart-a960aa93-e683-4e87-9619-ef1a01cb9060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609632567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3609632567
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.840365855
Short name T1084
Test name
Test status
Simulation time 3846216918 ps
CPU time 6.1 seconds
Started Jul 21 07:12:33 PM PDT 24
Finished Jul 21 07:12:40 PM PDT 24
Peak memory 196752 kb
Host smart-5c624b83-4b48-4ed0-b832-058d2005dfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840365855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.840365855
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.1353698377
Short name T552
Test name
Test status
Simulation time 501337656 ps
CPU time 1.65 seconds
Started Jul 21 07:12:32 PM PDT 24
Finished Jul 21 07:12:35 PM PDT 24
Peak memory 198864 kb
Host smart-0dd4560e-3cde-4335-b58f-c1dc68dccd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353698377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1353698377
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2006736111
Short name T299
Test name
Test status
Simulation time 90764019415 ps
CPU time 70.78 seconds
Started Jul 21 07:12:42 PM PDT 24
Finished Jul 21 07:13:58 PM PDT 24
Peak memory 200092 kb
Host smart-c03c6054-a53d-4ce2-aa9f-029dfe012d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006736111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2006736111
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1531527530
Short name T958
Test name
Test status
Simulation time 45938481223 ps
CPU time 986.22 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:29:11 PM PDT 24
Peak memory 216772 kb
Host smart-fa45982d-d916-4d04-929b-2cfd99c312c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531527530 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1531527530
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.207964774
Short name T710
Test name
Test status
Simulation time 2167977429 ps
CPU time 2.36 seconds
Started Jul 21 07:12:42 PM PDT 24
Finished Jul 21 07:12:50 PM PDT 24
Peak memory 199120 kb
Host smart-2e3ec726-4067-419b-b64a-0abc2982b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207964774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.207964774
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1943634165
Short name T514
Test name
Test status
Simulation time 100221362501 ps
CPU time 143.15 seconds
Started Jul 21 07:12:34 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 200124 kb
Host smart-cf2da06c-7cd4-4f1f-86ec-a65755fbbdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943634165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1943634165
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3948295778
Short name T52
Test name
Test status
Simulation time 15079192 ps
CPU time 0.55 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:14:19 PM PDT 24
Peak memory 195516 kb
Host smart-3fc0de39-15c5-4247-8f85-b07715cdaef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948295778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3948295778
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3032505997
Short name T1165
Test name
Test status
Simulation time 213017577529 ps
CPU time 85.01 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:15:33 PM PDT 24
Peak memory 200136 kb
Host smart-dfcc771e-a80f-46eb-9a8a-d615ceff52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032505997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3032505997
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2449914586
Short name T350
Test name
Test status
Simulation time 14571925736 ps
CPU time 10.49 seconds
Started Jul 21 07:14:08 PM PDT 24
Finished Jul 21 07:14:19 PM PDT 24
Peak memory 200156 kb
Host smart-44afafe5-59a9-4d02-9745-7f67646279a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449914586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2449914586
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4054403782
Short name T985
Test name
Test status
Simulation time 134108130251 ps
CPU time 31.33 seconds
Started Jul 21 07:14:08 PM PDT 24
Finished Jul 21 07:14:40 PM PDT 24
Peak memory 200172 kb
Host smart-8a2eb9a3-c45f-4efb-9809-72e144aeda07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054403782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4054403782
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3196109776
Short name T616
Test name
Test status
Simulation time 244848977183 ps
CPU time 86.94 seconds
Started Jul 21 07:14:13 PM PDT 24
Finished Jul 21 07:15:40 PM PDT 24
Peak memory 198340 kb
Host smart-6636fae6-7fb2-467f-a7da-53be92b3d6a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196109776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3196109776
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3963138067
Short name T603
Test name
Test status
Simulation time 192217548861 ps
CPU time 1588.57 seconds
Started Jul 21 07:14:14 PM PDT 24
Finished Jul 21 07:40:44 PM PDT 24
Peak memory 200200 kb
Host smart-e5426d69-f392-47ed-9d0d-6ebde6cae023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963138067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3963138067
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2439596812
Short name T897
Test name
Test status
Simulation time 5388601689 ps
CPU time 9.85 seconds
Started Jul 21 07:14:16 PM PDT 24
Finished Jul 21 07:14:27 PM PDT 24
Peak memory 198536 kb
Host smart-156f7859-0341-4438-bd9c-1d8e26c4ceee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439596812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2439596812
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2426497570
Short name T40
Test name
Test status
Simulation time 126596934005 ps
CPU time 236.43 seconds
Started Jul 21 07:14:13 PM PDT 24
Finished Jul 21 07:18:11 PM PDT 24
Peak memory 208344 kb
Host smart-941aff90-457a-48df-9a83-35f934514acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426497570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2426497570
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1125497711
Short name T359
Test name
Test status
Simulation time 20677306218 ps
CPU time 284.82 seconds
Started Jul 21 07:14:13 PM PDT 24
Finished Jul 21 07:18:59 PM PDT 24
Peak memory 200216 kb
Host smart-76ba815b-c1ce-4667-8aef-73b31c91feda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125497711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1125497711
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1136314215
Short name T635
Test name
Test status
Simulation time 5611462067 ps
CPU time 53.03 seconds
Started Jul 21 07:14:15 PM PDT 24
Finished Jul 21 07:15:09 PM PDT 24
Peak memory 198096 kb
Host smart-75eabc24-14fb-47ec-bfc8-76004cd8923a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136314215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1136314215
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.682314901
Short name T330
Test name
Test status
Simulation time 40083725128 ps
CPU time 13.45 seconds
Started Jul 21 07:14:14 PM PDT 24
Finished Jul 21 07:14:29 PM PDT 24
Peak memory 198644 kb
Host smart-b8f4da82-4829-4e66-865e-6d86c254c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682314901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.682314901
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.593837852
Short name T851
Test name
Test status
Simulation time 3588302602 ps
CPU time 5.48 seconds
Started Jul 21 07:14:14 PM PDT 24
Finished Jul 21 07:14:21 PM PDT 24
Peak memory 196196 kb
Host smart-1d9beeaf-7847-4063-a287-2eacffd605d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593837852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.593837852
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3871915543
Short name T1076
Test name
Test status
Simulation time 689591384 ps
CPU time 4.55 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:14:12 PM PDT 24
Peak memory 198480 kb
Host smart-29044d2b-a29d-4d87-b7c2-159d29e793e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871915543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3871915543
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3976729658
Short name T1157
Test name
Test status
Simulation time 267934237267 ps
CPU time 375.74 seconds
Started Jul 21 07:14:15 PM PDT 24
Finished Jul 21 07:20:32 PM PDT 24
Peak memory 200180 kb
Host smart-933ea46b-a069-4ff7-87ad-658389a62de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976729658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3976729658
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3008197974
Short name T105
Test name
Test status
Simulation time 26010788714 ps
CPU time 234.5 seconds
Started Jul 21 07:14:14 PM PDT 24
Finished Jul 21 07:18:10 PM PDT 24
Peak memory 208544 kb
Host smart-d1275380-8642-453a-ae67-c0fdb6979a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008197974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3008197974
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4198137269
Short name T941
Test name
Test status
Simulation time 1143204078 ps
CPU time 1.87 seconds
Started Jul 21 07:14:15 PM PDT 24
Finished Jul 21 07:14:18 PM PDT 24
Peak memory 199016 kb
Host smart-4abc1bcd-9023-44de-8dc6-ddaef3005c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198137269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4198137269
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.358252933
Short name T959
Test name
Test status
Simulation time 26628071729 ps
CPU time 24.94 seconds
Started Jul 21 07:14:07 PM PDT 24
Finished Jul 21 07:14:33 PM PDT 24
Peak memory 200180 kb
Host smart-0a259f5b-e086-43f5-9790-d6f5d383595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358252933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.358252933
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3177189855
Short name T503
Test name
Test status
Simulation time 111419353003 ps
CPU time 91.21 seconds
Started Jul 21 07:20:13 PM PDT 24
Finished Jul 21 07:21:45 PM PDT 24
Peak memory 200180 kb
Host smart-4cce93df-cf0c-42eb-bb42-11368c8d8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177189855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3177189855
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1292518787
Short name T787
Test name
Test status
Simulation time 44214136974 ps
CPU time 28.91 seconds
Started Jul 21 07:20:11 PM PDT 24
Finished Jul 21 07:20:41 PM PDT 24
Peak memory 200116 kb
Host smart-7df051ab-7187-48f3-8f7a-19711379f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292518787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1292518787
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.525191053
Short name T316
Test name
Test status
Simulation time 35362050208 ps
CPU time 58.74 seconds
Started Jul 21 07:20:12 PM PDT 24
Finished Jul 21 07:21:11 PM PDT 24
Peak memory 200196 kb
Host smart-2fe7ff75-f89c-4fe2-83ea-940c563fdf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525191053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.525191053
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2113688663
Short name T240
Test name
Test status
Simulation time 99096774701 ps
CPU time 17.24 seconds
Started Jul 21 07:20:14 PM PDT 24
Finished Jul 21 07:20:31 PM PDT 24
Peak memory 199404 kb
Host smart-77c16d98-4f8e-4cb7-ab99-e60c95a5af86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113688663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2113688663
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2440978783
Short name T1106
Test name
Test status
Simulation time 17939699152 ps
CPU time 28.6 seconds
Started Jul 21 07:20:12 PM PDT 24
Finished Jul 21 07:20:42 PM PDT 24
Peak memory 200168 kb
Host smart-6f8f812a-fe92-4533-bd13-0576b8bd36d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440978783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2440978783
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.60063575
Short name T258
Test name
Test status
Simulation time 54352071903 ps
CPU time 29.23 seconds
Started Jul 21 07:20:13 PM PDT 24
Finished Jul 21 07:20:43 PM PDT 24
Peak memory 200228 kb
Host smart-d56cb429-aa06-4f87-a01b-3e874958e3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60063575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.60063575
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.688619406
Short name T1046
Test name
Test status
Simulation time 53982167794 ps
CPU time 87.65 seconds
Started Jul 21 07:20:12 PM PDT 24
Finished Jul 21 07:21:40 PM PDT 24
Peak memory 200228 kb
Host smart-bd3370f7-d89a-442f-88a8-f559e5b767f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688619406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.688619406
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.115008259
Short name T73
Test name
Test status
Simulation time 70047771800 ps
CPU time 91.37 seconds
Started Jul 21 07:20:14 PM PDT 24
Finished Jul 21 07:21:45 PM PDT 24
Peak memory 200116 kb
Host smart-c9d06ca7-d9a0-4ec2-8b8c-d3b9f5e48d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115008259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.115008259
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.348247442
Short name T398
Test name
Test status
Simulation time 126656807 ps
CPU time 0.61 seconds
Started Jul 21 07:14:21 PM PDT 24
Finished Jul 21 07:14:22 PM PDT 24
Peak memory 195868 kb
Host smart-48619312-b5fa-4f0c-a68a-243bad5c6191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348247442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.348247442
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2683001418
Short name T140
Test name
Test status
Simulation time 19525578410 ps
CPU time 16.33 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:14:36 PM PDT 24
Peak memory 200184 kb
Host smart-5f65a165-cb5a-472d-8429-eff3d8897bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683001418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2683001418
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2626314634
Short name T721
Test name
Test status
Simulation time 127339463561 ps
CPU time 107.07 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:16:06 PM PDT 24
Peak memory 200192 kb
Host smart-6752a9aa-0eac-4fe4-b55b-ccf7dce1f851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626314634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2626314634
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2503015981
Short name T8
Test name
Test status
Simulation time 15985585757 ps
CPU time 15.26 seconds
Started Jul 21 07:14:19 PM PDT 24
Finished Jul 21 07:14:35 PM PDT 24
Peak memory 200104 kb
Host smart-a87de02e-e321-4d68-9788-29444da10072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503015981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2503015981
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1998873931
Short name T1118
Test name
Test status
Simulation time 49811556110 ps
CPU time 81.19 seconds
Started Jul 21 07:14:20 PM PDT 24
Finished Jul 21 07:15:41 PM PDT 24
Peak memory 199796 kb
Host smart-53c55cc9-3706-475f-86ef-d20477d21223
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998873931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1998873931
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3289449627
Short name T382
Test name
Test status
Simulation time 103023182565 ps
CPU time 225.81 seconds
Started Jul 21 07:14:19 PM PDT 24
Finished Jul 21 07:18:05 PM PDT 24
Peak memory 200180 kb
Host smart-0d40e81f-0c29-4d29-b55e-a0933c3281f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289449627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3289449627
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4181975922
Short name T638
Test name
Test status
Simulation time 11328172503 ps
CPU time 12.65 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:14:32 PM PDT 24
Peak memory 200028 kb
Host smart-92d97b3a-2142-43b8-916b-b82e31320fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181975922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4181975922
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1018244610
Short name T589
Test name
Test status
Simulation time 9877984884 ps
CPU time 15.19 seconds
Started Jul 21 07:14:20 PM PDT 24
Finished Jul 21 07:14:35 PM PDT 24
Peak memory 195108 kb
Host smart-966b19c2-3302-43cb-85e1-4d042b4020c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018244610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1018244610
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2675208426
Short name T628
Test name
Test status
Simulation time 28915403724 ps
CPU time 353.32 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:20:13 PM PDT 24
Peak memory 200212 kb
Host smart-6318df67-9825-42f4-9bc9-d314226fe676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675208426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2675208426
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.4167063994
Short name T840
Test name
Test status
Simulation time 3575625231 ps
CPU time 34.47 seconds
Started Jul 21 07:14:21 PM PDT 24
Finished Jul 21 07:14:56 PM PDT 24
Peak memory 198984 kb
Host smart-d9c60615-c79d-449b-8678-ab8194a6147e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167063994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4167063994
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3077917187
Short name T515
Test name
Test status
Simulation time 39393852826 ps
CPU time 17.48 seconds
Started Jul 21 07:14:19 PM PDT 24
Finished Jul 21 07:14:37 PM PDT 24
Peak memory 200180 kb
Host smart-155ad155-e71c-4eb6-b177-e604eaff3488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077917187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3077917187
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3420159462
Short name T389
Test name
Test status
Simulation time 4176853006 ps
CPU time 2.29 seconds
Started Jul 21 07:14:21 PM PDT 24
Finished Jul 21 07:14:24 PM PDT 24
Peak memory 196708 kb
Host smart-b03da2b0-d448-4ede-8d9d-fea6ced058d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420159462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3420159462
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3151916161
Short name T439
Test name
Test status
Simulation time 5556811392 ps
CPU time 13.14 seconds
Started Jul 21 07:14:19 PM PDT 24
Finished Jul 21 07:14:33 PM PDT 24
Peak memory 200068 kb
Host smart-8e482d9a-e02c-45d9-aadc-e11e23431013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151916161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3151916161
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.446532734
Short name T141
Test name
Test status
Simulation time 454702933988 ps
CPU time 219.39 seconds
Started Jul 21 07:14:23 PM PDT 24
Finished Jul 21 07:18:03 PM PDT 24
Peak memory 208680 kb
Host smart-ac4e98f5-2a26-4310-981c-ba8fd4b99cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446532734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.446532734
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1241296991
Short name T934
Test name
Test status
Simulation time 155406593340 ps
CPU time 1036.39 seconds
Started Jul 21 07:14:19 PM PDT 24
Finished Jul 21 07:31:36 PM PDT 24
Peak memory 225200 kb
Host smart-1087401a-ae57-487f-8058-dd92b7e3006b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241296991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1241296991
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.490282398
Short name T839
Test name
Test status
Simulation time 598924166 ps
CPU time 1.1 seconds
Started Jul 21 07:14:21 PM PDT 24
Finished Jul 21 07:14:22 PM PDT 24
Peak memory 198416 kb
Host smart-1b345cf6-5712-4623-9698-e82b0f29e722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490282398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.490282398
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2364448451
Short name T1112
Test name
Test status
Simulation time 14451873920 ps
CPU time 20.39 seconds
Started Jul 21 07:14:18 PM PDT 24
Finished Jul 21 07:14:39 PM PDT 24
Peak memory 197924 kb
Host smart-5c7df9bf-83dc-4f49-89cc-1471e47d7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364448451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2364448451
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1096231537
Short name T170
Test name
Test status
Simulation time 94048535995 ps
CPU time 152.14 seconds
Started Jul 21 07:20:22 PM PDT 24
Finished Jul 21 07:22:56 PM PDT 24
Peak memory 200172 kb
Host smart-56e7e177-cafa-4e2a-a324-6f60a0da7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096231537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1096231537
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.827675298
Short name T923
Test name
Test status
Simulation time 132478553083 ps
CPU time 133.05 seconds
Started Jul 21 07:20:18 PM PDT 24
Finished Jul 21 07:22:34 PM PDT 24
Peak memory 200080 kb
Host smart-73b40a64-0594-4ba4-8caa-ecfbbfc72ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827675298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.827675298
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2370646072
Short name T226
Test name
Test status
Simulation time 161244492067 ps
CPU time 22.66 seconds
Started Jul 21 07:20:18 PM PDT 24
Finished Jul 21 07:20:43 PM PDT 24
Peak memory 200132 kb
Host smart-01800878-e4c5-4c7f-8dc9-9a63d2d9c2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370646072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2370646072
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.384439503
Short name T216
Test name
Test status
Simulation time 45706884930 ps
CPU time 16.54 seconds
Started Jul 21 07:20:19 PM PDT 24
Finished Jul 21 07:20:37 PM PDT 24
Peak memory 200136 kb
Host smart-0818dd75-7bb4-4fd0-94d7-8cc878d36fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384439503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.384439503
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.319717249
Short name T148
Test name
Test status
Simulation time 140314024151 ps
CPU time 41.18 seconds
Started Jul 21 07:20:17 PM PDT 24
Finished Jul 21 07:21:02 PM PDT 24
Peak memory 200220 kb
Host smart-6393fb6c-411c-41b8-8e73-4310965b80e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319717249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.319717249
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.114814478
Short name T195
Test name
Test status
Simulation time 27182954514 ps
CPU time 20.54 seconds
Started Jul 21 07:20:23 PM PDT 24
Finished Jul 21 07:20:44 PM PDT 24
Peak memory 200168 kb
Host smart-16d74d9e-8d17-432f-9a80-6a6745269391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114814478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.114814478
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1170321220
Short name T508
Test name
Test status
Simulation time 29272016377 ps
CPU time 21.25 seconds
Started Jul 21 07:20:20 PM PDT 24
Finished Jul 21 07:20:42 PM PDT 24
Peak memory 200164 kb
Host smart-4f5de27a-7367-4583-a413-c93598c729e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170321220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1170321220
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1504820870
Short name T196
Test name
Test status
Simulation time 95302200622 ps
CPU time 177.78 seconds
Started Jul 21 07:20:18 PM PDT 24
Finished Jul 21 07:23:19 PM PDT 24
Peak memory 200144 kb
Host smart-36210552-f32c-4909-9f4a-f94d1b60c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504820870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1504820870
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1383644004
Short name T841
Test name
Test status
Simulation time 129705245519 ps
CPU time 199.28 seconds
Started Jul 21 07:20:17 PM PDT 24
Finished Jul 21 07:23:39 PM PDT 24
Peak memory 200164 kb
Host smart-6bf6a86d-4409-4b00-957f-4cffabe287ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383644004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1383644004
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3443207466
Short name T961
Test name
Test status
Simulation time 23528392 ps
CPU time 0.55 seconds
Started Jul 21 07:14:32 PM PDT 24
Finished Jul 21 07:14:33 PM PDT 24
Peak memory 195588 kb
Host smart-331b3b61-71a3-486a-9fe2-a6852d023ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443207466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3443207466
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3006625750
Short name T499
Test name
Test status
Simulation time 38146795467 ps
CPU time 35.35 seconds
Started Jul 21 07:14:24 PM PDT 24
Finished Jul 21 07:15:00 PM PDT 24
Peak memory 200148 kb
Host smart-de2ce795-3811-426e-9818-83003c116598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006625750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3006625750
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.818377996
Short name T674
Test name
Test status
Simulation time 4434013025 ps
CPU time 9.19 seconds
Started Jul 21 07:14:25 PM PDT 24
Finished Jul 21 07:14:35 PM PDT 24
Peak memory 200156 kb
Host smart-95933184-0c84-4444-830f-eaf66a2be876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818377996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.818377996
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3559556330
Short name T1048
Test name
Test status
Simulation time 236970537363 ps
CPU time 140.09 seconds
Started Jul 21 07:14:26 PM PDT 24
Finished Jul 21 07:16:47 PM PDT 24
Peak memory 200168 kb
Host smart-5bd3231b-7171-40a4-938c-b37ba3167e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559556330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3559556330
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3569897370
Short name T1114
Test name
Test status
Simulation time 16713825040 ps
CPU time 18.01 seconds
Started Jul 21 07:14:25 PM PDT 24
Finished Jul 21 07:14:43 PM PDT 24
Peak memory 200200 kb
Host smart-1d6f1e36-cd29-495f-b153-fcdef6ee65fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569897370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3569897370
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1887877365
Short name T1013
Test name
Test status
Simulation time 106482503185 ps
CPU time 122.09 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:16:33 PM PDT 24
Peak memory 200000 kb
Host smart-3e95df83-8915-4f2e-8cc1-5009e506aa4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887877365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1887877365
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2505912205
Short name T804
Test name
Test status
Simulation time 6230322585 ps
CPU time 12.26 seconds
Started Jul 21 07:14:25 PM PDT 24
Finished Jul 21 07:14:38 PM PDT 24
Peak memory 198976 kb
Host smart-a3fdf507-7209-49c5-a668-0bd6e2056277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505912205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2505912205
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2878660123
Short name T362
Test name
Test status
Simulation time 12022309770 ps
CPU time 22.37 seconds
Started Jul 21 07:14:28 PM PDT 24
Finished Jul 21 07:14:50 PM PDT 24
Peak memory 198604 kb
Host smart-9760ea1a-6cd8-4ece-a6dc-5aa4ab0e8983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878660123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2878660123
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3818512343
Short name T802
Test name
Test status
Simulation time 8253082796 ps
CPU time 118.16 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:16:29 PM PDT 24
Peak memory 200180 kb
Host smart-bd1aacb1-924d-4656-8a70-108f8e53068a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818512343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3818512343
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1800895584
Short name T687
Test name
Test status
Simulation time 4529335188 ps
CPU time 36.74 seconds
Started Jul 21 07:14:25 PM PDT 24
Finished Jul 21 07:15:02 PM PDT 24
Peak memory 199400 kb
Host smart-10e44fb4-e9b4-401e-88a2-115f538faeac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800895584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1800895584
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.431223529
Short name T490
Test name
Test status
Simulation time 11300869526 ps
CPU time 33.19 seconds
Started Jul 21 07:14:26 PM PDT 24
Finished Jul 21 07:14:59 PM PDT 24
Peak memory 200200 kb
Host smart-2a74f935-a0c8-40ba-86da-0d2cd923ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431223529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.431223529
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4025492826
Short name T773
Test name
Test status
Simulation time 40416739766 ps
CPU time 30.1 seconds
Started Jul 21 07:14:28 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 196028 kb
Host smart-290af4de-5c31-44fd-b55f-53859f62c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025492826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4025492826
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3666720997
Short name T274
Test name
Test status
Simulation time 564917676 ps
CPU time 0.97 seconds
Started Jul 21 07:14:20 PM PDT 24
Finished Jul 21 07:14:21 PM PDT 24
Peak memory 198588 kb
Host smart-a9af5d6e-915c-44c5-8f68-b1c0c12e39ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666720997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3666720997
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3443928288
Short name T940
Test name
Test status
Simulation time 302615052869 ps
CPU time 532.7 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:23:25 PM PDT 24
Peak memory 216628 kb
Host smart-edefa4f5-6a28-4b02-a00f-d53ff80e75a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443928288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3443928288
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.802546822
Short name T566
Test name
Test status
Simulation time 17585713231 ps
CPU time 235.81 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:18:28 PM PDT 24
Peak memory 208484 kb
Host smart-a0704130-2e99-4041-a1d2-c61d649bc19c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802546822 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.802546822
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.554225444
Short name T5
Test name
Test status
Simulation time 7263449976 ps
CPU time 9.53 seconds
Started Jul 21 07:14:25 PM PDT 24
Finished Jul 21 07:14:35 PM PDT 24
Peak memory 200124 kb
Host smart-9ea739ff-ba02-48fa-8cb4-8ecd38889bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554225444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.554225444
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3718783471
Short name T295
Test name
Test status
Simulation time 118131663331 ps
CPU time 203.26 seconds
Started Jul 21 07:14:23 PM PDT 24
Finished Jul 21 07:17:47 PM PDT 24
Peak memory 200128 kb
Host smart-710472f4-30aa-4287-ae65-e12efcc31f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718783471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3718783471
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3379854759
Short name T826
Test name
Test status
Simulation time 37311405136 ps
CPU time 50.15 seconds
Started Jul 21 07:20:22 PM PDT 24
Finished Jul 21 07:21:14 PM PDT 24
Peak memory 200108 kb
Host smart-bc30e8c4-e779-427c-9d6f-0cb430f22f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379854759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3379854759
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3804456331
Short name T336
Test name
Test status
Simulation time 41323573004 ps
CPU time 34.91 seconds
Started Jul 21 07:20:18 PM PDT 24
Finished Jul 21 07:20:56 PM PDT 24
Peak memory 200112 kb
Host smart-9e78ba51-ad2c-42c6-9dc5-2781796a2495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804456331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3804456331
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3273219455
Short name T501
Test name
Test status
Simulation time 20200115839 ps
CPU time 13.55 seconds
Started Jul 21 07:20:20 PM PDT 24
Finished Jul 21 07:20:34 PM PDT 24
Peak memory 200208 kb
Host smart-6c60f53c-1c1a-497b-9ffb-58917df20189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273219455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3273219455
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1420075185
Short name T771
Test name
Test status
Simulation time 148409973680 ps
CPU time 56.25 seconds
Started Jul 21 07:20:24 PM PDT 24
Finished Jul 21 07:21:22 PM PDT 24
Peak memory 200180 kb
Host smart-634141a6-5d26-4d90-8ac5-e19e10ddbc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420075185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1420075185
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2416756808
Short name T1025
Test name
Test status
Simulation time 179283658767 ps
CPU time 53.19 seconds
Started Jul 21 07:20:24 PM PDT 24
Finished Jul 21 07:21:19 PM PDT 24
Peak memory 200152 kb
Host smart-5c573499-4213-4f97-a9e4-99a9df3ac1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416756808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2416756808
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3122025683
Short name T204
Test name
Test status
Simulation time 114078103940 ps
CPU time 92.37 seconds
Started Jul 21 07:20:25 PM PDT 24
Finished Jul 21 07:21:58 PM PDT 24
Peak memory 200072 kb
Host smart-f85aff4e-09a8-4f85-8fe3-afd16b608bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122025683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3122025683
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2226918743
Short name T438
Test name
Test status
Simulation time 5831896142 ps
CPU time 9.43 seconds
Started Jul 21 07:20:22 PM PDT 24
Finished Jul 21 07:20:32 PM PDT 24
Peak memory 200004 kb
Host smart-1090c353-88db-47aa-a2c3-3ac1af5a51d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226918743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2226918743
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3207826821
Short name T1041
Test name
Test status
Simulation time 89115303053 ps
CPU time 143.29 seconds
Started Jul 21 07:20:24 PM PDT 24
Finished Jul 21 07:22:48 PM PDT 24
Peak memory 200144 kb
Host smart-a4ab0c9f-dbaf-4631-8179-97ea6181c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207826821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3207826821
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2018488662
Short name T813
Test name
Test status
Simulation time 145773028303 ps
CPU time 41.51 seconds
Started Jul 21 07:20:25 PM PDT 24
Finished Jul 21 07:21:08 PM PDT 24
Peak memory 200220 kb
Host smart-38088abf-df27-4250-8443-028726982897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018488662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2018488662
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.971736489
Short name T1109
Test name
Test status
Simulation time 37613159 ps
CPU time 0.52 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:14:36 PM PDT 24
Peak memory 194368 kb
Host smart-54bd6f7d-5969-48b1-a0c3-2d7923ed32b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971736489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.971736489
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.291407397
Short name T967
Test name
Test status
Simulation time 45411246200 ps
CPU time 72.42 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:15:43 PM PDT 24
Peak memory 200140 kb
Host smart-a1a1eb9d-7400-43e0-9081-1c0c614e53b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291407397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.291407397
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1389891888
Short name T1148
Test name
Test status
Simulation time 93128739563 ps
CPU time 26.66 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 199724 kb
Host smart-040297be-3494-4602-8cf8-f7b79a6d2279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389891888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1389891888
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4247469179
Short name T376
Test name
Test status
Simulation time 29415706824 ps
CPU time 44.49 seconds
Started Jul 21 07:14:32 PM PDT 24
Finished Jul 21 07:15:17 PM PDT 24
Peak memory 200220 kb
Host smart-e0ed151d-d9d3-4d1b-bf8d-e5abc1add75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247469179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4247469179
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.641153301
Short name T703
Test name
Test status
Simulation time 198398919720 ps
CPU time 156.02 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:17:08 PM PDT 24
Peak memory 199876 kb
Host smart-c19c0e4e-ff02-44e9-985c-00015e97820a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641153301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.641153301
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.482356145
Short name T854
Test name
Test status
Simulation time 96443206186 ps
CPU time 585.37 seconds
Started Jul 21 07:14:36 PM PDT 24
Finished Jul 21 07:24:22 PM PDT 24
Peak memory 200164 kb
Host smart-1ad2853e-a828-480a-bd26-2db0d2c3b561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482356145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.482356145
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.782631074
Short name T394
Test name
Test status
Simulation time 6302084809 ps
CPU time 10.94 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:14:43 PM PDT 24
Peak memory 198664 kb
Host smart-59ed242f-5651-4d55-a3f7-c76590af285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782631074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.782631074
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2105983586
Short name T489
Test name
Test status
Simulation time 41297690809 ps
CPU time 42.25 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:15:12 PM PDT 24
Peak memory 200324 kb
Host smart-2ec59f4a-dd6f-4f2b-a841-e3b4059c6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105983586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2105983586
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4147347696
Short name T573
Test name
Test status
Simulation time 24477413319 ps
CPU time 1244.6 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:35:17 PM PDT 24
Peak memory 200160 kb
Host smart-755264b1-c4ab-4b21-9487-8bbce63e54e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147347696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4147347696
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3520226086
Short name T623
Test name
Test status
Simulation time 1376751929 ps
CPU time 5.19 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:14:37 PM PDT 24
Peak memory 198220 kb
Host smart-493d300a-92a1-4b8f-a992-5b1826cae86a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520226086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3520226086
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2973067155
Short name T153
Test name
Test status
Simulation time 45057381113 ps
CPU time 79.85 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:15:50 PM PDT 24
Peak memory 200128 kb
Host smart-fc3ec70f-5224-4e1b-bc27-aa569061b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973067155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2973067155
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2237775280
Short name T113
Test name
Test status
Simulation time 3630141818 ps
CPU time 1.03 seconds
Started Jul 21 07:14:34 PM PDT 24
Finished Jul 21 07:14:35 PM PDT 24
Peak memory 196496 kb
Host smart-d94cd231-20f8-44c6-b579-9ebc93f4759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237775280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2237775280
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2707810352
Short name T744
Test name
Test status
Simulation time 288754306 ps
CPU time 1.77 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:14:32 PM PDT 24
Peak memory 199196 kb
Host smart-0cf96b65-3014-4262-ac77-f4d30dc755ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707810352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2707810352
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2613000651
Short name T976
Test name
Test status
Simulation time 310304325262 ps
CPU time 232.45 seconds
Started Jul 21 07:14:39 PM PDT 24
Finished Jul 21 07:18:33 PM PDT 24
Peak memory 200120 kb
Host smart-a5ed2b79-ff2b-40be-bdb2-2885e0bdacab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613000651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2613000651
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.153387321
Short name T103
Test name
Test status
Simulation time 52851115273 ps
CPU time 550.78 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:23:46 PM PDT 24
Peak memory 225048 kb
Host smart-0691cc35-5ad5-4e50-83c8-484739189d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153387321 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.153387321
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.904788308
Short name T35
Test name
Test status
Simulation time 982007447 ps
CPU time 1.69 seconds
Started Jul 21 07:14:31 PM PDT 24
Finished Jul 21 07:14:33 PM PDT 24
Peak memory 199048 kb
Host smart-619484c2-82e0-4f34-87b5-62f7f35c74ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904788308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.904788308
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3981498294
Short name T990
Test name
Test status
Simulation time 145139342633 ps
CPU time 91.97 seconds
Started Jul 21 07:14:30 PM PDT 24
Finished Jul 21 07:16:02 PM PDT 24
Peak memory 200216 kb
Host smart-2b28edd2-52ee-443a-9b2d-c2ac4fd830d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981498294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3981498294
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2118150100
Short name T856
Test name
Test status
Simulation time 46434133823 ps
CPU time 17.75 seconds
Started Jul 21 07:20:24 PM PDT 24
Finished Jul 21 07:20:42 PM PDT 24
Peak memory 199888 kb
Host smart-cc800d0d-8530-44e8-8a44-66cebd2bf0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118150100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2118150100
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3963124463
Short name T1058
Test name
Test status
Simulation time 91480910963 ps
CPU time 111.92 seconds
Started Jul 21 07:20:31 PM PDT 24
Finished Jul 21 07:22:29 PM PDT 24
Peak memory 199916 kb
Host smart-1a081dd7-9e7f-4193-ad78-16c916fc2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963124463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3963124463
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.110737462
Short name T429
Test name
Test status
Simulation time 19534057897 ps
CPU time 31.06 seconds
Started Jul 21 07:20:29 PM PDT 24
Finished Jul 21 07:21:03 PM PDT 24
Peak memory 200004 kb
Host smart-33ef81a5-7d66-49c1-9703-3a79bc94441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110737462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.110737462
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1835286939
Short name T482
Test name
Test status
Simulation time 68159125067 ps
CPU time 26.28 seconds
Started Jul 21 07:20:32 PM PDT 24
Finished Jul 21 07:21:04 PM PDT 24
Peak memory 200052 kb
Host smart-2e11b364-cad9-4a5c-86a1-3a7247546a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835286939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1835286939
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.570595486
Short name T157
Test name
Test status
Simulation time 46015991621 ps
CPU time 82.69 seconds
Started Jul 21 07:20:28 PM PDT 24
Finished Jul 21 07:21:54 PM PDT 24
Peak memory 200208 kb
Host smart-7e36ee25-31d7-4775-b0f3-5c4fe20e975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570595486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.570595486
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.226683154
Short name T719
Test name
Test status
Simulation time 37890252717 ps
CPU time 62.24 seconds
Started Jul 21 07:20:29 PM PDT 24
Finished Jul 21 07:21:35 PM PDT 24
Peak memory 200096 kb
Host smart-c97c26c5-4515-42c0-9b06-d3466ca6c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226683154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.226683154
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1690522192
Short name T251
Test name
Test status
Simulation time 14328296471 ps
CPU time 11.43 seconds
Started Jul 21 07:20:30 PM PDT 24
Finished Jul 21 07:20:46 PM PDT 24
Peak memory 200196 kb
Host smart-7bc9d6ed-621f-4b52-a88d-3c6dc678268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690522192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1690522192
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.42240522
Short name T975
Test name
Test status
Simulation time 136363024266 ps
CPU time 177.94 seconds
Started Jul 21 07:20:34 PM PDT 24
Finished Jul 21 07:23:40 PM PDT 24
Peak memory 200236 kb
Host smart-bfb5ff2a-9b96-4e14-a981-facf4581bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42240522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.42240522
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3204354109
Short name T23
Test name
Test status
Simulation time 37518399 ps
CPU time 0.56 seconds
Started Jul 21 07:14:44 PM PDT 24
Finished Jul 21 07:14:45 PM PDT 24
Peak memory 195544 kb
Host smart-187d7b04-d681-43e1-ae6d-fb9bb95865fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204354109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3204354109
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3973746000
Short name T615
Test name
Test status
Simulation time 344273013325 ps
CPU time 128.55 seconds
Started Jul 21 07:14:38 PM PDT 24
Finished Jul 21 07:16:47 PM PDT 24
Peak memory 200184 kb
Host smart-efbc5cdf-fd4a-46f3-b4de-32e4a0a8c2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973746000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3973746000
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3480494534
Short name T411
Test name
Test status
Simulation time 107509453872 ps
CPU time 241.07 seconds
Started Jul 21 07:14:37 PM PDT 24
Finished Jul 21 07:18:38 PM PDT 24
Peak memory 200204 kb
Host smart-e2d83636-f1f5-4a80-b1a6-cb92c8eb9169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480494534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3480494534
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.3558503196
Short name T654
Test name
Test status
Simulation time 16374794359 ps
CPU time 10.53 seconds
Started Jul 21 07:14:36 PM PDT 24
Finished Jul 21 07:14:47 PM PDT 24
Peak memory 197220 kb
Host smart-10e0c815-796d-45ee-a8b1-c33a52e9b7af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558503196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3558503196
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2088820617
Short name T641
Test name
Test status
Simulation time 144031099883 ps
CPU time 385.25 seconds
Started Jul 21 07:14:40 PM PDT 24
Finished Jul 21 07:21:06 PM PDT 24
Peak memory 200128 kb
Host smart-af4254c8-f598-455d-bae5-d0718ca439ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088820617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2088820617
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.893663746
Short name T669
Test name
Test status
Simulation time 5829860935 ps
CPU time 10.95 seconds
Started Jul 21 07:14:39 PM PDT 24
Finished Jul 21 07:14:51 PM PDT 24
Peak memory 199904 kb
Host smart-40096ade-7a74-4d2e-9fe5-c72ae444a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893663746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.893663746
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3442798725
Short name T404
Test name
Test status
Simulation time 10291964806 ps
CPU time 15.6 seconds
Started Jul 21 07:14:40 PM PDT 24
Finished Jul 21 07:14:56 PM PDT 24
Peak memory 197476 kb
Host smart-e2ec3a35-ff79-44df-9d5b-43fd9405684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442798725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3442798725
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2601509413
Short name T1060
Test name
Test status
Simulation time 10631460022 ps
CPU time 620.31 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:24:56 PM PDT 24
Peak memory 200108 kb
Host smart-5fe01987-6d61-478c-ad44-9863e6dae8f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601509413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2601509413
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2396091270
Short name T1143
Test name
Test status
Simulation time 3338062581 ps
CPU time 14.4 seconds
Started Jul 21 07:14:36 PM PDT 24
Finished Jul 21 07:14:51 PM PDT 24
Peak memory 198600 kb
Host smart-93896ff0-840f-47b9-af86-659d0e90310b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396091270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2396091270
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1653168734
Short name T12
Test name
Test status
Simulation time 120069374212 ps
CPU time 243.29 seconds
Started Jul 21 07:14:38 PM PDT 24
Finished Jul 21 07:18:41 PM PDT 24
Peak memory 200132 kb
Host smart-74b7315d-55aa-407e-8341-4bbdaa17b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653168734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1653168734
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1485159846
Short name T492
Test name
Test status
Simulation time 3412850139 ps
CPU time 1.95 seconds
Started Jul 21 07:14:39 PM PDT 24
Finished Jul 21 07:14:41 PM PDT 24
Peak memory 196316 kb
Host smart-52524a6e-fe38-444a-819c-fb6f06eb6eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485159846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1485159846
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.268967444
Short name T725
Test name
Test status
Simulation time 286368934 ps
CPU time 1.06 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:14:37 PM PDT 24
Peak memory 198828 kb
Host smart-1eaa04b3-97f1-41ce-86cc-51fb3a4fb6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268967444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.268967444
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3952917259
Short name T2
Test name
Test status
Simulation time 146212814693 ps
CPU time 138.75 seconds
Started Jul 21 07:14:43 PM PDT 24
Finished Jul 21 07:17:02 PM PDT 24
Peak memory 200116 kb
Host smart-5e5e18cb-4fed-4889-b9ee-e5998f7a90e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952917259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3952917259
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2116686108
Short name T308
Test name
Test status
Simulation time 34969774949 ps
CPU time 984.66 seconds
Started Jul 21 07:14:43 PM PDT 24
Finished Jul 21 07:31:09 PM PDT 24
Peak memory 216320 kb
Host smart-dfa043c5-77d7-4073-9890-f8538ba88181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116686108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2116686108
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1481898984
Short name T793
Test name
Test status
Simulation time 823482227 ps
CPU time 2.51 seconds
Started Jul 21 07:14:35 PM PDT 24
Finished Jul 21 07:14:38 PM PDT 24
Peak memory 198424 kb
Host smart-772d6cda-46ea-476c-b622-4c0942c410ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481898984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1481898984
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1026777381
Short name T818
Test name
Test status
Simulation time 38474038504 ps
CPU time 65.85 seconds
Started Jul 21 07:14:38 PM PDT 24
Finished Jul 21 07:15:45 PM PDT 24
Peak memory 200128 kb
Host smart-c983c530-ecf3-4bd2-8ccd-f2a85e92f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026777381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1026777381
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4013336122
Short name T145
Test name
Test status
Simulation time 38890148758 ps
CPU time 58.98 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:21:42 PM PDT 24
Peak memory 200148 kb
Host smart-8a777760-48df-49ab-a967-36ef3855e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013336122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4013336122
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2787245041
Short name T750
Test name
Test status
Simulation time 25385265556 ps
CPU time 14.25 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:20:56 PM PDT 24
Peak memory 200144 kb
Host smart-c39a037d-07de-48c4-b246-ee60a1261b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787245041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2787245041
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1103503629
Short name T415
Test name
Test status
Simulation time 57834240314 ps
CPU time 89.8 seconds
Started Jul 21 07:20:34 PM PDT 24
Finished Jul 21 07:22:10 PM PDT 24
Peak memory 200140 kb
Host smart-5a823bcf-a07d-4c70-b3c8-64260a8fb4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103503629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1103503629
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.702478518
Short name T796
Test name
Test status
Simulation time 46978933519 ps
CPU time 13.39 seconds
Started Jul 21 07:20:34 PM PDT 24
Finished Jul 21 07:20:54 PM PDT 24
Peak memory 200224 kb
Host smart-887a836f-3d95-4151-ae66-6e6d1c097ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702478518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.702478518
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.858480361
Short name T312
Test name
Test status
Simulation time 7785154826 ps
CPU time 12.06 seconds
Started Jul 21 07:20:36 PM PDT 24
Finished Jul 21 07:20:56 PM PDT 24
Peak memory 200172 kb
Host smart-370934ed-27a2-4dae-97e1-7dc22bee6848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858480361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.858480361
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1526293816
Short name T526
Test name
Test status
Simulation time 27342097618 ps
CPU time 14.61 seconds
Started Jul 21 07:20:36 PM PDT 24
Finished Jul 21 07:20:58 PM PDT 24
Peak memory 200200 kb
Host smart-698451c3-f6e9-4f2f-992d-7ae885fbfb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526293816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1526293816
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4281481353
Short name T371
Test name
Test status
Simulation time 21881597946 ps
CPU time 28.68 seconds
Started Jul 21 07:20:36 PM PDT 24
Finished Jul 21 07:21:13 PM PDT 24
Peak memory 200092 kb
Host smart-f25e01f7-bcff-44e8-b273-f83ea33b011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281481353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4281481353
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2267609044
Short name T186
Test name
Test status
Simulation time 51981881308 ps
CPU time 19.82 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:21:03 PM PDT 24
Peak memory 200196 kb
Host smart-fe0c13b7-934c-43bf-ba25-dee64faeae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267609044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2267609044
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2082823433
Short name T859
Test name
Test status
Simulation time 21335345 ps
CPU time 0.57 seconds
Started Jul 21 07:14:46 PM PDT 24
Finished Jul 21 07:14:48 PM PDT 24
Peak memory 195588 kb
Host smart-1c3b41ed-0413-4d22-8b8e-c7ff70e7a79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082823433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2082823433
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.4149432727
Short name T262
Test name
Test status
Simulation time 133803155595 ps
CPU time 425.64 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:21:49 PM PDT 24
Peak memory 200108 kb
Host smart-c8b9cf4f-88d4-4b46-af32-2138efa30f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149432727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4149432727
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3480128797
Short name T444
Test name
Test status
Simulation time 10605212748 ps
CPU time 28.72 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:15:11 PM PDT 24
Peak memory 200200 kb
Host smart-d771feda-ec0e-4196-8889-fcb611087d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480128797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3480128797
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3568169147
Short name T1009
Test name
Test status
Simulation time 15002895442 ps
CPU time 24.75 seconds
Started Jul 21 07:14:43 PM PDT 24
Finished Jul 21 07:15:08 PM PDT 24
Peak memory 198700 kb
Host smart-e11ca977-68b3-459d-a7e1-113d470cc537
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568169147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3568169147
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2627320817
Short name T709
Test name
Test status
Simulation time 147462625844 ps
CPU time 599.73 seconds
Started Jul 21 07:14:41 PM PDT 24
Finished Jul 21 07:24:41 PM PDT 24
Peak memory 200100 kb
Host smart-8447c447-d8d6-4993-a591-07c02281716e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627320817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2627320817
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.692803150
Short name T433
Test name
Test status
Simulation time 5849872247 ps
CPU time 3.3 seconds
Started Jul 21 07:14:40 PM PDT 24
Finished Jul 21 07:14:44 PM PDT 24
Peak memory 198192 kb
Host smart-ba02ed1f-b0b2-4532-82fd-a523eca5d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692803150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.692803150
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2626236471
Short name T673
Test name
Test status
Simulation time 46299974153 ps
CPU time 18.58 seconds
Started Jul 21 07:14:44 PM PDT 24
Finished Jul 21 07:15:03 PM PDT 24
Peak memory 208532 kb
Host smart-16004ee6-e5ec-416c-8493-2736bdd1ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626236471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2626236471
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3182043779
Short name T1029
Test name
Test status
Simulation time 8331064646 ps
CPU time 420.56 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:21:43 PM PDT 24
Peak memory 200140 kb
Host smart-8c01a871-d845-4a29-a930-18840ed9e6c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182043779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3182043779
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2493482621
Short name T323
Test name
Test status
Simulation time 5756802156 ps
CPU time 11.18 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:14:54 PM PDT 24
Peak memory 199872 kb
Host smart-aea5b995-bf99-43aa-9073-ba521a7339c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493482621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2493482621
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4284335257
Short name T1162
Test name
Test status
Simulation time 112092883905 ps
CPU time 44.36 seconds
Started Jul 21 07:14:41 PM PDT 24
Finished Jul 21 07:15:26 PM PDT 24
Peak memory 200040 kb
Host smart-a056f05d-1118-4bc4-aca6-211338fa1575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284335257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4284335257
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.43556876
Short name T916
Test name
Test status
Simulation time 3208267897 ps
CPU time 1.9 seconds
Started Jul 21 07:14:41 PM PDT 24
Finished Jul 21 07:14:43 PM PDT 24
Peak memory 196036 kb
Host smart-275fdba2-37b2-4a07-be8b-62a91804aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43556876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.43556876
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4011787040
Short name T505
Test name
Test status
Simulation time 715772537 ps
CPU time 2.2 seconds
Started Jul 21 07:14:41 PM PDT 24
Finished Jul 21 07:14:44 PM PDT 24
Peak memory 199008 kb
Host smart-820ea7a9-6307-4728-9d92-5e7343c1bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011787040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4011787040
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.497138265
Short name T516
Test name
Test status
Simulation time 163323284516 ps
CPU time 353.13 seconds
Started Jul 21 07:14:43 PM PDT 24
Finished Jul 21 07:20:37 PM PDT 24
Peak memory 225036 kb
Host smart-d103c3cc-a821-47d1-abac-e4b2a07db651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497138265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.497138265
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3342777385
Short name T388
Test name
Test status
Simulation time 1055997893 ps
CPU time 3.24 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:14:46 PM PDT 24
Peak memory 199784 kb
Host smart-a6713e3d-c5fc-4bfa-9493-6b92e06250fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342777385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3342777385
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3678122415
Short name T691
Test name
Test status
Simulation time 89203133554 ps
CPU time 150.75 seconds
Started Jul 21 07:14:42 PM PDT 24
Finished Jul 21 07:17:13 PM PDT 24
Peak memory 200140 kb
Host smart-bc49bec9-3169-4c42-be6b-f52ca3dc565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678122415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3678122415
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.230537095
Short name T313
Test name
Test status
Simulation time 94777524641 ps
CPU time 133.18 seconds
Started Jul 21 07:20:33 PM PDT 24
Finished Jul 21 07:22:52 PM PDT 24
Peak memory 200188 kb
Host smart-d4bd06c3-ff42-4251-bfff-6d0663d15a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230537095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.230537095
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2529957475
Short name T278
Test name
Test status
Simulation time 56852782114 ps
CPU time 149.75 seconds
Started Jul 21 07:20:35 PM PDT 24
Finished Jul 21 07:23:13 PM PDT 24
Peak memory 200200 kb
Host smart-e264951a-2d05-4a77-b2d4-5e31742ba009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529957475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2529957475
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.273168981
Short name T109
Test name
Test status
Simulation time 114246945730 ps
CPU time 47.55 seconds
Started Jul 21 07:20:36 PM PDT 24
Finished Jul 21 07:21:31 PM PDT 24
Peak memory 200112 kb
Host smart-ee4548d8-f774-40d4-9186-0f1c4b6da975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273168981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.273168981
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2577317594
Short name T189
Test name
Test status
Simulation time 64121970856 ps
CPU time 28.67 seconds
Started Jul 21 07:20:34 PM PDT 24
Finished Jul 21 07:21:10 PM PDT 24
Peak memory 200196 kb
Host smart-1df1281c-4ce5-4e01-b8b3-eed9e90c2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577317594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2577317594
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.805411887
Short name T965
Test name
Test status
Simulation time 121145144895 ps
CPU time 93.35 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:22:27 PM PDT 24
Peak memory 200036 kb
Host smart-66c50ea3-7325-4267-90d6-75296b97f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805411887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.805411887
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1677751301
Short name T167
Test name
Test status
Simulation time 46606779248 ps
CPU time 41.24 seconds
Started Jul 21 07:20:40 PM PDT 24
Finished Jul 21 07:21:38 PM PDT 24
Peak memory 200204 kb
Host smart-d689be04-7ccb-4f97-b20e-672a2944e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677751301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1677751301
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2214991487
Short name T481
Test name
Test status
Simulation time 98840244896 ps
CPU time 149.72 seconds
Started Jul 21 07:20:40 PM PDT 24
Finished Jul 21 07:23:27 PM PDT 24
Peak memory 200196 kb
Host smart-c31b7ad5-8142-46cb-96d0-53a931f73497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214991487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2214991487
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1178712371
Short name T230
Test name
Test status
Simulation time 13474404621 ps
CPU time 12.12 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:21:05 PM PDT 24
Peak memory 200208 kb
Host smart-fbabe245-512f-4f09-9278-790dbeb9ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178712371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1178712371
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3018438873
Short name T320
Test name
Test status
Simulation time 16820867 ps
CPU time 0.56 seconds
Started Jul 21 07:14:55 PM PDT 24
Finished Jul 21 07:14:56 PM PDT 24
Peak memory 195720 kb
Host smart-3a86e3e6-2fcd-43d5-94c5-d62e0da46137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018438873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3018438873
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1068394496
Short name T540
Test name
Test status
Simulation time 35821126555 ps
CPU time 19.64 seconds
Started Jul 21 07:14:48 PM PDT 24
Finished Jul 21 07:15:08 PM PDT 24
Peak memory 200364 kb
Host smart-8285e0fc-8e3a-401c-a9c5-9042be1a73b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068394496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1068394496
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3921853924
Short name T198
Test name
Test status
Simulation time 15575080025 ps
CPU time 37.21 seconds
Started Jul 21 07:14:46 PM PDT 24
Finished Jul 21 07:15:24 PM PDT 24
Peak memory 200116 kb
Host smart-1dcdfc2a-25c6-41b6-a92c-ae84442b4a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921853924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3921853924
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1153314552
Short name T443
Test name
Test status
Simulation time 417429748993 ps
CPU time 230.44 seconds
Started Jul 21 07:14:47 PM PDT 24
Finished Jul 21 07:18:38 PM PDT 24
Peak memory 200100 kb
Host smart-77f959fd-78d6-4c57-87c5-0caf33af18b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153314552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1153314552
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2758859925
Short name T930
Test name
Test status
Simulation time 62814987142 ps
CPU time 98.65 seconds
Started Jul 21 07:14:54 PM PDT 24
Finished Jul 21 07:16:32 PM PDT 24
Peak memory 200180 kb
Host smart-571560d4-79af-4a6c-98f8-5ec484fb6e05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758859925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2758859925
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.26005255
Short name T980
Test name
Test status
Simulation time 5059710678 ps
CPU time 3.47 seconds
Started Jul 21 07:14:45 PM PDT 24
Finished Jul 21 07:14:49 PM PDT 24
Peak memory 199824 kb
Host smart-867a391f-f7bc-480f-8b76-6634f84bb3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26005255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.26005255
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2934107727
Short name T517
Test name
Test status
Simulation time 163510023812 ps
CPU time 140.03 seconds
Started Jul 21 07:14:48 PM PDT 24
Finished Jul 21 07:17:08 PM PDT 24
Peak memory 200284 kb
Host smart-b3b7c72e-e96d-4061-bd4b-4f7a8108a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934107727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2934107727
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3793101039
Short name T998
Test name
Test status
Simulation time 5590650032 ps
CPU time 131.76 seconds
Started Jul 21 07:14:47 PM PDT 24
Finished Jul 21 07:16:59 PM PDT 24
Peak memory 200112 kb
Host smart-4e7f0c84-5f84-46a0-8da3-1a1ef5ab6704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793101039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3793101039
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.45283925
Short name T1101
Test name
Test status
Simulation time 4929985932 ps
CPU time 36.8 seconds
Started Jul 21 07:14:46 PM PDT 24
Finished Jul 21 07:15:23 PM PDT 24
Peak memory 199292 kb
Host smart-78003b37-86cf-4c51-b6f5-21ebb551b6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45283925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.45283925
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3341089644
Short name T462
Test name
Test status
Simulation time 30850735761 ps
CPU time 42.65 seconds
Started Jul 21 07:14:46 PM PDT 24
Finished Jul 21 07:15:29 PM PDT 24
Peak memory 200112 kb
Host smart-50a51f1c-d515-4246-a785-07ba37fe1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341089644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3341089644
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1220546231
Short name T665
Test name
Test status
Simulation time 3399769267 ps
CPU time 2.06 seconds
Started Jul 21 07:14:47 PM PDT 24
Finished Jul 21 07:14:50 PM PDT 24
Peak memory 196684 kb
Host smart-f19c33aa-c4d1-4b00-8f45-eedee4249743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220546231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1220546231
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2816945973
Short name T739
Test name
Test status
Simulation time 487843401 ps
CPU time 2.87 seconds
Started Jul 21 07:14:47 PM PDT 24
Finished Jul 21 07:14:50 PM PDT 24
Peak memory 199576 kb
Host smart-abead5cd-e8cb-4f48-95f5-7145acc29b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816945973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2816945973
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2543772829
Short name T579
Test name
Test status
Simulation time 322536181931 ps
CPU time 627.72 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:25:21 PM PDT 24
Peak memory 200100 kb
Host smart-4687da0e-b524-42fc-bad3-8b8a77d0e95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543772829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2543772829
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2595515042
Short name T600
Test name
Test status
Simulation time 38289809305 ps
CPU time 215.1 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:18:28 PM PDT 24
Peak memory 208476 kb
Host smart-d0e8d5f1-9451-440b-a635-48e40d5b5ca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595515042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2595515042
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2455679924
Short name T753
Test name
Test status
Simulation time 684438413 ps
CPU time 2.82 seconds
Started Jul 21 07:14:45 PM PDT 24
Finished Jul 21 07:14:49 PM PDT 24
Peak memory 198748 kb
Host smart-2cbfaa5a-91de-4a96-ba72-272ea22da5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455679924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2455679924
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3228601677
Short name T305
Test name
Test status
Simulation time 4847097813 ps
CPU time 7.9 seconds
Started Jul 21 07:14:46 PM PDT 24
Finished Jul 21 07:14:55 PM PDT 24
Peak memory 197832 kb
Host smart-49f14c53-dc4e-4fe4-92da-8580e804b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228601677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3228601677
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.204380335
Short name T123
Test name
Test status
Simulation time 24404164138 ps
CPU time 38.66 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:21:32 PM PDT 24
Peak memory 200116 kb
Host smart-946672a5-054d-43d0-9093-4c356f4822d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204380335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.204380335
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3030102819
Short name T1123
Test name
Test status
Simulation time 22232542138 ps
CPU time 19.92 seconds
Started Jul 21 07:20:41 PM PDT 24
Finished Jul 21 07:21:22 PM PDT 24
Peak memory 200212 kb
Host smart-9af9c5c7-2dec-4cc2-9229-5dc264a2a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030102819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3030102819
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1240970140
Short name T1111
Test name
Test status
Simulation time 82483824226 ps
CPU time 30.61 seconds
Started Jul 21 07:20:38 PM PDT 24
Finished Jul 21 07:21:21 PM PDT 24
Peak memory 200136 kb
Host smart-4d925fa8-5637-4347-8b30-4758231c39a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240970140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1240970140
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3896020476
Short name T222
Test name
Test status
Simulation time 249665333083 ps
CPU time 322.77 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:26:14 PM PDT 24
Peak memory 200176 kb
Host smart-7d63e621-da88-46ed-a756-3ee92b2b4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896020476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3896020476
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2282184884
Short name T146
Test name
Test status
Simulation time 63090508248 ps
CPU time 53.03 seconds
Started Jul 21 07:20:40 PM PDT 24
Finished Jul 21 07:21:48 PM PDT 24
Peak memory 200200 kb
Host smart-e4736f33-9254-4a85-8926-d82ac7299b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282184884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2282184884
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3330845827
Short name T205
Test name
Test status
Simulation time 55764163174 ps
CPU time 25.95 seconds
Started Jul 21 07:20:41 PM PDT 24
Finished Jul 21 07:21:27 PM PDT 24
Peak memory 200152 kb
Host smart-74893a9e-defe-45a8-833b-2a4e8af99880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330845827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3330845827
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4050519508
Short name T150
Test name
Test status
Simulation time 80325635609 ps
CPU time 70.21 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:22:04 PM PDT 24
Peak memory 200152 kb
Host smart-e9ff65e2-d85c-45ab-8995-57abdb574406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050519508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4050519508
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3907674981
Short name T889
Test name
Test status
Simulation time 46207502746 ps
CPU time 19.17 seconds
Started Jul 21 07:20:41 PM PDT 24
Finished Jul 21 07:21:20 PM PDT 24
Peak memory 200136 kb
Host smart-73ba5e84-577b-4b93-be9f-7992925891cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907674981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3907674981
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1882545308
Short name T895
Test name
Test status
Simulation time 15135520427 ps
CPU time 36.21 seconds
Started Jul 21 07:20:41 PM PDT 24
Finished Jul 21 07:21:35 PM PDT 24
Peak memory 200140 kb
Host smart-0b779d8d-8300-4c56-9805-559ac0b1ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882545308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1882545308
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.187139829
Short name T1047
Test name
Test status
Simulation time 66914388815 ps
CPU time 26.72 seconds
Started Jul 21 07:20:39 PM PDT 24
Finished Jul 21 07:21:20 PM PDT 24
Peak memory 200144 kb
Host smart-2a611197-0f6a-4035-a8a4-d5ef35fcbd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187139829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.187139829
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3791145237
Short name T380
Test name
Test status
Simulation time 98074634 ps
CPU time 0.55 seconds
Started Jul 21 07:14:59 PM PDT 24
Finished Jul 21 07:15:00 PM PDT 24
Peak memory 195580 kb
Host smart-75b12bb2-d3d4-4f60-98fd-edf3f4d011d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791145237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3791145237
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4145967124
Short name T677
Test name
Test status
Simulation time 20818327188 ps
CPU time 36.59 seconds
Started Jul 21 07:14:54 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 200200 kb
Host smart-8c7e839d-469c-4db1-b2fe-fde592473c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145967124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4145967124
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.94561474
Short name T605
Test name
Test status
Simulation time 114727705070 ps
CPU time 197.09 seconds
Started Jul 21 07:14:54 PM PDT 24
Finished Jul 21 07:18:12 PM PDT 24
Peak memory 200120 kb
Host smart-ef80a1f5-a87a-4cc1-85e5-8c032c78b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94561474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.94561474
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2741353489
Short name T519
Test name
Test status
Simulation time 70676543547 ps
CPU time 99.38 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:16:32 PM PDT 24
Peak memory 200196 kb
Host smart-f43d5e35-1ee2-480b-bb41-fd087456f8d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741353489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2741353489
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.612042967
Short name T602
Test name
Test status
Simulation time 78081553031 ps
CPU time 167.36 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:17:44 PM PDT 24
Peak memory 200136 kb
Host smart-588c1e54-bcf4-44e2-a3e6-aaf520c25224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612042967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.612042967
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3413649195
Short name T1140
Test name
Test status
Simulation time 4333510657 ps
CPU time 9.68 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:15:08 PM PDT 24
Peak memory 199020 kb
Host smart-033e1656-762d-4c11-96a8-40529c919369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413649195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3413649195
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3105614975
Short name T400
Test name
Test status
Simulation time 42370296632 ps
CPU time 22.69 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:15:15 PM PDT 24
Peak memory 198632 kb
Host smart-15ea0695-a39b-4056-8a50-84bf1bc5634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105614975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3105614975
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.85505238
Short name T938
Test name
Test status
Simulation time 18305936501 ps
CPU time 144.48 seconds
Started Jul 21 07:14:56 PM PDT 24
Finished Jul 21 07:17:21 PM PDT 24
Peak memory 200212 kb
Host smart-a732fb60-125a-4357-9567-87b54b31729c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85505238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.85505238
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.888170357
Short name T781
Test name
Test status
Simulation time 3721371219 ps
CPU time 7.22 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:14:59 PM PDT 24
Peak memory 199140 kb
Host smart-966e15bd-da57-468b-9257-945fecd398c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888170357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.888170357
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.937373908
Short name T243
Test name
Test status
Simulation time 111204526167 ps
CPU time 80.65 seconds
Started Jul 21 07:14:53 PM PDT 24
Finished Jul 21 07:16:14 PM PDT 24
Peak memory 200068 kb
Host smart-5695c7f8-30dd-46c2-8d20-ce23020348e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937373908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.937373908
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1592783319
Short name T842
Test name
Test status
Simulation time 6089540058 ps
CPU time 1.35 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:14:54 PM PDT 24
Peak memory 196444 kb
Host smart-2677b00a-4f6f-44d5-a344-f5ee136c5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592783319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1592783319
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3789449182
Short name T437
Test name
Test status
Simulation time 6064956176 ps
CPU time 10.03 seconds
Started Jul 21 07:14:51 PM PDT 24
Finished Jul 21 07:15:02 PM PDT 24
Peak memory 200016 kb
Host smart-b3b3a5b0-4922-4e81-a40c-3f9198b2b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789449182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3789449182
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3779296555
Short name T291
Test name
Test status
Simulation time 143120570545 ps
CPU time 318.99 seconds
Started Jul 21 07:14:59 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 200288 kb
Host smart-dbadd9aa-8ab8-4d26-a688-6135f5dbd53b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779296555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3779296555
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3903543196
Short name T807
Test name
Test status
Simulation time 187387313937 ps
CPU time 1019.51 seconds
Started Jul 21 07:15:02 PM PDT 24
Finished Jul 21 07:32:02 PM PDT 24
Peak memory 229148 kb
Host smart-71ae13b3-6c58-4496-ba11-6b87d241a8a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903543196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3903543196
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.304399028
Short name T493
Test name
Test status
Simulation time 1530692042 ps
CPU time 1.72 seconds
Started Jul 21 07:14:58 PM PDT 24
Finished Jul 21 07:15:00 PM PDT 24
Peak memory 198952 kb
Host smart-2ad54761-644c-498b-9d63-72b838160b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304399028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.304399028
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.611227063
Short name T496
Test name
Test status
Simulation time 34198748983 ps
CPU time 37.61 seconds
Started Jul 21 07:14:52 PM PDT 24
Finished Jul 21 07:15:30 PM PDT 24
Peak memory 200216 kb
Host smart-5c1ec0a8-3a39-47bf-80dd-d2ee71d67766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611227063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.611227063
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3497285591
Short name T1071
Test name
Test status
Simulation time 49259851172 ps
CPU time 46.72 seconds
Started Jul 21 07:20:45 PM PDT 24
Finished Jul 21 07:21:59 PM PDT 24
Peak memory 200060 kb
Host smart-81affb50-a0b8-43ec-b5db-7542a9f19033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497285591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3497285591
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3864027078
Short name T795
Test name
Test status
Simulation time 102168642236 ps
CPU time 171.12 seconds
Started Jul 21 07:20:45 PM PDT 24
Finished Jul 21 07:24:02 PM PDT 24
Peak memory 199980 kb
Host smart-68b1df03-cd68-4964-bbba-093655032185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864027078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3864027078
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3717071036
Short name T953
Test name
Test status
Simulation time 412100131925 ps
CPU time 47.58 seconds
Started Jul 21 07:20:47 PM PDT 24
Finished Jul 21 07:22:06 PM PDT 24
Peak memory 200176 kb
Host smart-d1c75dda-9c43-471d-b8ef-81620d69feeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717071036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3717071036
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1932459567
Short name T224
Test name
Test status
Simulation time 167473186576 ps
CPU time 134.58 seconds
Started Jul 21 07:20:49 PM PDT 24
Finished Jul 21 07:23:36 PM PDT 24
Peak memory 200148 kb
Host smart-cacd49cc-21bd-4ae9-87c7-868f3abfd9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932459567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1932459567
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.561660211
Short name T47
Test name
Test status
Simulation time 12675605366 ps
CPU time 9.7 seconds
Started Jul 21 07:20:47 PM PDT 24
Finished Jul 21 07:21:28 PM PDT 24
Peak memory 200084 kb
Host smart-a1566df7-4b48-4c00-ac08-40eb64717626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561660211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.561660211
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3729587390
Short name T1038
Test name
Test status
Simulation time 46438231431 ps
CPU time 216.88 seconds
Started Jul 21 07:20:48 PM PDT 24
Finished Jul 21 07:24:57 PM PDT 24
Peak memory 200092 kb
Host smart-266f7346-1bd8-40a2-9170-c4629bb1b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729587390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3729587390
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.777007838
Short name T254
Test name
Test status
Simulation time 189914603217 ps
CPU time 70.86 seconds
Started Jul 21 07:20:47 PM PDT 24
Finished Jul 21 07:22:29 PM PDT 24
Peak memory 200196 kb
Host smart-411cd189-d87f-4ad6-8b72-c34ee0889b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777007838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.777007838
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2637552534
Short name T117
Test name
Test status
Simulation time 41758429197 ps
CPU time 35.02 seconds
Started Jul 21 07:20:49 PM PDT 24
Finished Jul 21 07:21:58 PM PDT 24
Peak memory 200140 kb
Host smart-7b989b8c-d2a4-4585-939e-7f5af9df01d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637552534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2637552534
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1274659434
Short name T780
Test name
Test status
Simulation time 75638489096 ps
CPU time 30.07 seconds
Started Jul 21 07:20:45 PM PDT 24
Finished Jul 21 07:21:43 PM PDT 24
Peak memory 200136 kb
Host smart-e30a54c6-697f-4ef1-9a36-39460292b033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274659434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1274659434
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3072434911
Short name T884
Test name
Test status
Simulation time 118999596594 ps
CPU time 181.48 seconds
Started Jul 21 07:20:50 PM PDT 24
Finished Jul 21 07:24:27 PM PDT 24
Peak memory 199944 kb
Host smart-2b436b95-d3ca-4cf6-8d49-db1b20f32c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072434911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3072434911
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1125604000
Short name T869
Test name
Test status
Simulation time 48954544 ps
CPU time 0.58 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:04 PM PDT 24
Peak memory 195564 kb
Host smart-84e38f87-d358-4d5d-b28a-4732b5919567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125604000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1125604000
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3912674230
Short name T944
Test name
Test status
Simulation time 110605210505 ps
CPU time 54.91 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:15:53 PM PDT 24
Peak memory 200136 kb
Host smart-6ce8fee0-09b7-47e0-90f4-d4c31babe846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912674230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3912674230
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1203826827
Short name T567
Test name
Test status
Simulation time 38647861180 ps
CPU time 62.61 seconds
Started Jul 21 07:14:58 PM PDT 24
Finished Jul 21 07:16:01 PM PDT 24
Peak memory 200208 kb
Host smart-767847eb-0dc1-46db-9f9c-23b10387157d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203826827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1203826827
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1079714315
Short name T1012
Test name
Test status
Simulation time 33144309034 ps
CPU time 14.52 seconds
Started Jul 21 07:14:56 PM PDT 24
Finished Jul 21 07:15:11 PM PDT 24
Peak memory 200188 kb
Host smart-becdd17d-a380-41f1-bc1a-749125fb72e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079714315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1079714315
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.844976376
Short name T833
Test name
Test status
Simulation time 169552342533 ps
CPU time 86.37 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:16:30 PM PDT 24
Peak memory 200184 kb
Host smart-93fcb516-2788-4cfd-a9e2-cfc04dd61915
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844976376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.844976376
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4054437309
Short name T767
Test name
Test status
Simulation time 74436279056 ps
CPU time 684.68 seconds
Started Jul 21 07:15:04 PM PDT 24
Finished Jul 21 07:26:29 PM PDT 24
Peak memory 200120 kb
Host smart-caa3477a-10bf-48fb-81aa-16c21e24c871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054437309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4054437309
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2903870961
Short name T974
Test name
Test status
Simulation time 7565285902 ps
CPU time 7.83 seconds
Started Jul 21 07:15:02 PM PDT 24
Finished Jul 21 07:15:10 PM PDT 24
Peak memory 200068 kb
Host smart-11d9de8b-fd93-45d4-94fd-5f86535e10f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903870961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2903870961
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1999471336
Short name T900
Test name
Test status
Simulation time 19302256815 ps
CPU time 33.73 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 197548 kb
Host smart-d81784c8-0ad1-4930-85f5-0339c20450ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999471336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1999471336
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3539361627
Short name T984
Test name
Test status
Simulation time 20881134066 ps
CPU time 232.99 seconds
Started Jul 21 07:15:02 PM PDT 24
Finished Jul 21 07:18:55 PM PDT 24
Peak memory 200208 kb
Host smart-08ad59aa-c5a7-4b12-9c3b-d8f2aaa4136b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539361627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3539361627
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.96033084
Short name T759
Test name
Test status
Simulation time 6369422732 ps
CPU time 15.58 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:21 PM PDT 24
Peak memory 199416 kb
Host smart-e999b5cd-61dc-44f1-86ad-696ca04bbba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96033084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.96033084
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2134548802
Short name T575
Test name
Test status
Simulation time 38363852064 ps
CPU time 33.9 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:37 PM PDT 24
Peak memory 200004 kb
Host smart-8bf48c94-33a2-4f08-8c30-1edc4cd77b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134548802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2134548802
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4188307512
Short name T768
Test name
Test status
Simulation time 35665023227 ps
CPU time 21.27 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:25 PM PDT 24
Peak memory 195988 kb
Host smart-ffaf1f6c-7a5c-4782-8ecb-5fccf6fae906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188307512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4188307512
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2528219084
Short name T468
Test name
Test status
Simulation time 991305557 ps
CPU time 2.29 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:15:00 PM PDT 24
Peak memory 198636 kb
Host smart-fc632d6b-55a2-4f14-8bbb-90fb9ed9fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528219084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2528219084
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3285762263
Short name T447
Test name
Test status
Simulation time 123275620282 ps
CPU time 224.8 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:18:48 PM PDT 24
Peak memory 200124 kb
Host smart-b55de0a3-8d7e-4b70-b407-c12c0e5fd9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285762263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3285762263
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1016116794
Short name T685
Test name
Test status
Simulation time 34252305685 ps
CPU time 364.87 seconds
Started Jul 21 07:15:04 PM PDT 24
Finished Jul 21 07:21:09 PM PDT 24
Peak memory 210804 kb
Host smart-b3daba21-6410-4657-945e-213e0d23f651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016116794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1016116794
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2430502838
Short name T46
Test name
Test status
Simulation time 855110368 ps
CPU time 1.62 seconds
Started Jul 21 07:15:01 PM PDT 24
Finished Jul 21 07:15:03 PM PDT 24
Peak memory 198448 kb
Host smart-5ae718f7-b012-4502-a01a-a134d2f8871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430502838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2430502838
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.966119279
Short name T747
Test name
Test status
Simulation time 50194499434 ps
CPU time 79.98 seconds
Started Jul 21 07:14:57 PM PDT 24
Finished Jul 21 07:16:18 PM PDT 24
Peak memory 200116 kb
Host smart-18d99c23-e157-4ac4-877f-47b8da2b7e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966119279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.966119279
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.854108440
Short name T879
Test name
Test status
Simulation time 30606812426 ps
CPU time 14.62 seconds
Started Jul 21 07:20:45 PM PDT 24
Finished Jul 21 07:21:26 PM PDT 24
Peak memory 200220 kb
Host smart-1344eb90-e079-44f1-87ac-938c8a0ee38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854108440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.854108440
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3434195437
Short name T181
Test name
Test status
Simulation time 6111976187 ps
CPU time 9.35 seconds
Started Jul 21 07:20:48 PM PDT 24
Finished Jul 21 07:21:29 PM PDT 24
Peak memory 200132 kb
Host smart-4b2141eb-e3b2-4fcb-baf2-3101e5c6ef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434195437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3434195437
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.443585435
Short name T353
Test name
Test status
Simulation time 21872338616 ps
CPU time 40.48 seconds
Started Jul 21 07:20:45 PM PDT 24
Finished Jul 21 07:21:54 PM PDT 24
Peak memory 200152 kb
Host smart-f3844024-00f0-4a2f-9119-c5820bfe1d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443585435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.443585435
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3107123082
Short name T652
Test name
Test status
Simulation time 244971955084 ps
CPU time 182.42 seconds
Started Jul 21 07:20:46 PM PDT 24
Finished Jul 21 07:24:17 PM PDT 24
Peak memory 200196 kb
Host smart-4b0b9577-617f-4d79-886f-05b7b4da80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107123082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3107123082
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2748336968
Short name T1125
Test name
Test status
Simulation time 89730232217 ps
CPU time 35.29 seconds
Started Jul 21 07:20:46 PM PDT 24
Finished Jul 21 07:21:50 PM PDT 24
Peak memory 200124 kb
Host smart-d8af894f-3bf8-4cee-86e1-5fc396995876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748336968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2748336968
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1733766089
Short name T255
Test name
Test status
Simulation time 8495467827 ps
CPU time 13.83 seconds
Started Jul 21 07:20:42 PM PDT 24
Finished Jul 21 07:21:17 PM PDT 24
Peak memory 200184 kb
Host smart-d348dde0-a96a-4da7-99b3-614a47047ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733766089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1733766089
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1772111172
Short name T1016
Test name
Test status
Simulation time 108374030568 ps
CPU time 217.58 seconds
Started Jul 21 07:20:50 PM PDT 24
Finished Jul 21 07:25:05 PM PDT 24
Peak memory 200184 kb
Host smart-a13597f1-ff0d-4755-a61c-eb986146b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772111172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1772111172
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.640395532
Short name T782
Test name
Test status
Simulation time 72818687080 ps
CPU time 59.21 seconds
Started Jul 21 07:20:47 PM PDT 24
Finished Jul 21 07:22:17 PM PDT 24
Peak memory 200184 kb
Host smart-56b67544-bdb9-4272-8181-1ed5258f2f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640395532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.640395532
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.893607083
Short name T277
Test name
Test status
Simulation time 9286180632 ps
CPU time 26.34 seconds
Started Jul 21 07:20:46 PM PDT 24
Finished Jul 21 07:21:41 PM PDT 24
Peak memory 200176 kb
Host smart-14fcd8d2-53c0-4d46-8a96-c7d04e7e602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893607083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.893607083
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3837125698
Short name T177
Test name
Test status
Simulation time 20767289010 ps
CPU time 26.97 seconds
Started Jul 21 07:20:51 PM PDT 24
Finished Jul 21 07:21:56 PM PDT 24
Peak memory 200148 kb
Host smart-9306bfb4-1297-4be9-80d4-e0c1dda38703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837125698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3837125698
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.121698653
Short name T1005
Test name
Test status
Simulation time 15721755 ps
CPU time 0.62 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:15:09 PM PDT 24
Peak memory 195532 kb
Host smart-d9928edb-0633-4887-a1dc-4d33bc1c4995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121698653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.121698653
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1278420390
Short name T348
Test name
Test status
Simulation time 30952400550 ps
CPU time 23.25 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:27 PM PDT 24
Peak memory 200188 kb
Host smart-15468d0a-8475-417e-82c6-3cc6588be927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278420390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1278420390
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3169644835
Short name T288
Test name
Test status
Simulation time 16706483680 ps
CPU time 22.63 seconds
Started Jul 21 07:15:02 PM PDT 24
Finished Jul 21 07:15:25 PM PDT 24
Peak memory 200068 kb
Host smart-69dd67b0-2c3c-4fb2-9641-63f39088c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169644835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3169644835
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4139543998
Short name T431
Test name
Test status
Simulation time 82881503290 ps
CPU time 32.04 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:15:36 PM PDT 24
Peak memory 200160 kb
Host smart-7b360908-5a40-4273-aaaf-0d5d6993a49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139543998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4139543998
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2328561862
Short name T862
Test name
Test status
Simulation time 4537747846 ps
CPU time 17.02 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:15:25 PM PDT 24
Peak memory 199920 kb
Host smart-23ee4441-53f6-47e3-86fb-e590f3f47382
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328561862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2328561862
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2504130040
Short name T1158
Test name
Test status
Simulation time 117450008931 ps
CPU time 170.86 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:17:59 PM PDT 24
Peak memory 200208 kb
Host smart-2a5d6a62-6335-4198-97d4-db5cb8afb2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504130040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2504130040
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1806726044
Short name T370
Test name
Test status
Simulation time 4578316925 ps
CPU time 4.52 seconds
Started Jul 21 07:15:09 PM PDT 24
Finished Jul 21 07:15:14 PM PDT 24
Peak memory 198480 kb
Host smart-0782b1ac-3928-4248-9f67-bf78b0059576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806726044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1806726044
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.948668696
Short name T672
Test name
Test status
Simulation time 58655073282 ps
CPU time 77.97 seconds
Started Jul 21 07:15:09 PM PDT 24
Finished Jul 21 07:16:27 PM PDT 24
Peak memory 200192 kb
Host smart-5d09864e-795d-4d26-86ec-8055c5394af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948668696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.948668696
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.928620963
Short name T593
Test name
Test status
Simulation time 6724791299 ps
CPU time 196.22 seconds
Started Jul 21 07:15:09 PM PDT 24
Finished Jul 21 07:18:26 PM PDT 24
Peak memory 200120 kb
Host smart-1cdbe1db-d1c0-4fe9-8051-8b67f97b3605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928620963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.928620963
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1791159403
Short name T868
Test name
Test status
Simulation time 4987150637 ps
CPU time 39.95 seconds
Started Jul 21 07:15:07 PM PDT 24
Finished Jul 21 07:15:47 PM PDT 24
Peak memory 198136 kb
Host smart-9b27510e-96d6-4760-a98f-3d6d58bfddc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791159403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1791159403
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2297203331
Short name T853
Test name
Test status
Simulation time 53872601691 ps
CPU time 41.84 seconds
Started Jul 21 07:15:10 PM PDT 24
Finished Jul 21 07:15:52 PM PDT 24
Peak memory 200128 kb
Host smart-37557efc-cec8-47c4-be6d-44fe08b0efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297203331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2297203331
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1986298982
Short name T77
Test name
Test status
Simulation time 46965346470 ps
CPU time 19.06 seconds
Started Jul 21 07:15:10 PM PDT 24
Finished Jul 21 07:15:29 PM PDT 24
Peak memory 196448 kb
Host smart-563b37e2-2529-4253-8159-d2ac009f580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986298982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1986298982
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1694736849
Short name T432
Test name
Test status
Simulation time 102171766 ps
CPU time 0.94 seconds
Started Jul 21 07:15:04 PM PDT 24
Finished Jul 21 07:15:05 PM PDT 24
Peak memory 198276 kb
Host smart-6e76d5cb-770e-4148-882b-4c3fab5d5f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694736849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1694736849
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3241876826
Short name T700
Test name
Test status
Simulation time 558911055073 ps
CPU time 2477.83 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:56:26 PM PDT 24
Peak memory 200176 kb
Host smart-25ef6828-00d0-49c5-ac85-9bc8273205ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241876826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3241876826
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3607984708
Short name T1091
Test name
Test status
Simulation time 119652226161 ps
CPU time 951.98 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:31:01 PM PDT 24
Peak memory 216868 kb
Host smart-e71f6bcf-b4bb-4bca-9352-1657cfa51c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607984708 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3607984708
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.773436461
Short name T108
Test name
Test status
Simulation time 2294553561 ps
CPU time 2.31 seconds
Started Jul 21 07:15:08 PM PDT 24
Finished Jul 21 07:15:10 PM PDT 24
Peak memory 199596 kb
Host smart-79371267-d5c2-41f3-b507-63de8709d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773436461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.773436461
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2617131757
Short name T384
Test name
Test status
Simulation time 52523592484 ps
CPU time 71.58 seconds
Started Jul 21 07:15:03 PM PDT 24
Finished Jul 21 07:16:15 PM PDT 24
Peak memory 200156 kb
Host smart-be809d7e-2d39-4db4-a2b5-8b715ca0cfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617131757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2617131757
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1387559171
Short name T690
Test name
Test status
Simulation time 16577666347 ps
CPU time 12.08 seconds
Started Jul 21 07:20:50 PM PDT 24
Finished Jul 21 07:21:37 PM PDT 24
Peak memory 200164 kb
Host smart-938c2e5f-69ab-43b1-8c78-8719caafd564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387559171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1387559171
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3327286314
Short name T947
Test name
Test status
Simulation time 134808119454 ps
CPU time 74.93 seconds
Started Jul 21 07:20:51 PM PDT 24
Finished Jul 21 07:22:42 PM PDT 24
Peak memory 200212 kb
Host smart-1c619093-5e9d-4744-909c-1b8a0b1108b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327286314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3327286314
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1147241695
Short name T151
Test name
Test status
Simulation time 13954383594 ps
CPU time 6.86 seconds
Started Jul 21 07:20:52 PM PDT 24
Finished Jul 21 07:21:37 PM PDT 24
Peak memory 200028 kb
Host smart-109be161-0157-4ca2-b565-7a3d7f345369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147241695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1147241695
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3834292992
Short name T549
Test name
Test status
Simulation time 10313898886 ps
CPU time 16.26 seconds
Started Jul 21 07:20:52 PM PDT 24
Finished Jul 21 07:21:47 PM PDT 24
Peak memory 200188 kb
Host smart-e09dc502-554b-4d01-8c27-306e35c13350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834292992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3834292992
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3558764521
Short name T550
Test name
Test status
Simulation time 246143207470 ps
CPU time 91.86 seconds
Started Jul 21 07:20:52 PM PDT 24
Finished Jul 21 07:23:02 PM PDT 24
Peak memory 200200 kb
Host smart-268df59c-469d-454c-b1a5-28ef200f4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558764521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3558764521
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1175660139
Short name T211
Test name
Test status
Simulation time 60096659342 ps
CPU time 48.09 seconds
Started Jul 21 07:20:51 PM PDT 24
Finished Jul 21 07:22:17 PM PDT 24
Peak memory 200180 kb
Host smart-0f017022-9669-453b-86bc-c9d1025144a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175660139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1175660139
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1707952641
Short name T37
Test name
Test status
Simulation time 160264823236 ps
CPU time 127.81 seconds
Started Jul 21 07:20:51 PM PDT 24
Finished Jul 21 07:23:37 PM PDT 24
Peak memory 200068 kb
Host smart-9d648049-70eb-43fb-8f2c-c66578c31af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707952641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1707952641
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1235229879
Short name T707
Test name
Test status
Simulation time 61658399 ps
CPU time 0.55 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:12:49 PM PDT 24
Peak memory 195812 kb
Host smart-fb2fd1a8-ac8a-4318-9853-8f3e1cc297df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235229879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1235229879
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1578152073
Short name T120
Test name
Test status
Simulation time 139735521232 ps
CPU time 59.47 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 200160 kb
Host smart-3b1113bd-ca22-4d18-94df-0eaac6ce5a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578152073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1578152073
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1290804510
Short name T577
Test name
Test status
Simulation time 83841388952 ps
CPU time 156.79 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:15:21 PM PDT 24
Peak memory 200168 kb
Host smart-a700ac5d-f2a2-4b62-948e-8414d33ffe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290804510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1290804510
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2028083394
Short name T257
Test name
Test status
Simulation time 57324789204 ps
CPU time 24.94 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:13:07 PM PDT 24
Peak memory 200152 kb
Host smart-11c82386-85c9-4b86-a747-57a0d53a333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028083394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2028083394
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.698210063
Short name T891
Test name
Test status
Simulation time 36897053678 ps
CPU time 29.18 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:13:10 PM PDT 24
Peak memory 200220 kb
Host smart-ed56ea4a-9c58-4e86-8b99-88042ea51ad2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698210063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.698210063
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2158372096
Short name T886
Test name
Test status
Simulation time 136822676368 ps
CPU time 795.37 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:26:09 PM PDT 24
Peak memory 200120 kb
Host smart-c908b1b1-80aa-487f-b430-c5c61a71c1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158372096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2158372096
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1553010091
Short name T830
Test name
Test status
Simulation time 7801041959 ps
CPU time 6.88 seconds
Started Jul 21 07:12:38 PM PDT 24
Finished Jul 21 07:12:48 PM PDT 24
Peak memory 200032 kb
Host smart-7fa13fe5-cd0d-4d6d-852d-7bb4a9ab5705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553010091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1553010091
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2978279195
Short name T1172
Test name
Test status
Simulation time 60510904286 ps
CPU time 58.44 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:13:42 PM PDT 24
Peak memory 200456 kb
Host smart-c0ab2c49-e356-457b-9d0e-56b0def56b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978279195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2978279195
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2533421131
Short name T808
Test name
Test status
Simulation time 6753640566 ps
CPU time 302.94 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:17:46 PM PDT 24
Peak memory 200152 kb
Host smart-0db17ef1-a985-4766-8ea2-71efeec2fbfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533421131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2533421131
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3138442718
Short name T363
Test name
Test status
Simulation time 1924209086 ps
CPU time 2.5 seconds
Started Jul 21 07:12:40 PM PDT 24
Finished Jul 21 07:12:47 PM PDT 24
Peak memory 198052 kb
Host smart-258ddd1d-b69c-4817-9e67-c50ec8a6199a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138442718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3138442718
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4261703496
Short name T1074
Test name
Test status
Simulation time 55183700717 ps
CPU time 86.84 seconds
Started Jul 21 07:12:43 PM PDT 24
Finished Jul 21 07:14:15 PM PDT 24
Peak memory 200192 kb
Host smart-6766721a-453e-47ac-9170-b119d586c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261703496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4261703496
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.863296027
Short name T792
Test name
Test status
Simulation time 3786601138 ps
CPU time 2.44 seconds
Started Jul 21 07:12:37 PM PDT 24
Finished Jul 21 07:12:40 PM PDT 24
Peak memory 196500 kb
Host smart-cf986f4c-e1e9-4b1a-b5d6-c3d257c6005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863296027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.863296027
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.4210543461
Short name T100
Test name
Test status
Simulation time 272884299 ps
CPU time 0.88 seconds
Started Jul 21 07:12:47 PM PDT 24
Finished Jul 21 07:12:52 PM PDT 24
Peak memory 218400 kb
Host smart-e0e4c576-abb3-46fd-b6d3-97ffae3fc921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210543461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4210543461
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.63486647
Short name T446
Test name
Test status
Simulation time 483468362 ps
CPU time 1.36 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:12:45 PM PDT 24
Peak memory 200048 kb
Host smart-31d3f9bd-e839-4aea-8aeb-8ea963ff4863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63486647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.63486647
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3589476722
Short name T866
Test name
Test status
Simulation time 152231569256 ps
CPU time 426.9 seconds
Started Jul 21 07:12:52 PM PDT 24
Finished Jul 21 07:20:00 PM PDT 24
Peak memory 200120 kb
Host smart-6a4e3681-acac-4280-9255-51a679b6f7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589476722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3589476722
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1257277393
Short name T814
Test name
Test status
Simulation time 37308234493 ps
CPU time 330.16 seconds
Started Jul 21 07:12:46 PM PDT 24
Finished Jul 21 07:18:20 PM PDT 24
Peak memory 216620 kb
Host smart-5beabe71-572f-4b0c-b6c1-9ec2da716d76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257277393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1257277393
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2239524247
Short name T952
Test name
Test status
Simulation time 397974027 ps
CPU time 1.19 seconds
Started Jul 21 07:12:39 PM PDT 24
Finished Jul 21 07:12:45 PM PDT 24
Peak memory 198404 kb
Host smart-a0331fe3-a958-45e5-8800-1fac9685f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239524247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2239524247
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.715284008
Short name T281
Test name
Test status
Simulation time 28409571754 ps
CPU time 39.21 seconds
Started Jul 21 07:12:41 PM PDT 24
Finished Jul 21 07:13:26 PM PDT 24
Peak memory 200044 kb
Host smart-4e3b3b7e-b54a-4869-a5eb-390772005490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715284008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.715284008
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2415921024
Short name T321
Test name
Test status
Simulation time 45009832 ps
CPU time 0.57 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:15:14 PM PDT 24
Peak memory 195584 kb
Host smart-aa2c68f2-0e18-409d-8174-8cf5440256f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415921024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2415921024
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3956125630
Short name T1100
Test name
Test status
Simulation time 42842567456 ps
CPU time 10.03 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:15:24 PM PDT 24
Peak memory 198452 kb
Host smart-5b69dab2-e907-464b-877d-f9ffe4937f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956125630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3956125630
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3609674597
Short name T1090
Test name
Test status
Simulation time 104331607623 ps
CPU time 39.26 seconds
Started Jul 21 07:15:12 PM PDT 24
Finished Jul 21 07:15:52 PM PDT 24
Peak memory 200116 kb
Host smart-7694d15e-3682-4b02-8904-0d76be98d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609674597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3609674597
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3598679221
Short name T843
Test name
Test status
Simulation time 100655299231 ps
CPU time 130.44 seconds
Started Jul 21 07:15:15 PM PDT 24
Finished Jul 21 07:17:26 PM PDT 24
Peak memory 200128 kb
Host smart-9ab3a1f0-ad15-402d-b03f-dc8c57301cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598679221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3598679221
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1911278112
Short name T13
Test name
Test status
Simulation time 236921533653 ps
CPU time 100.74 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:16:56 PM PDT 24
Peak memory 199788 kb
Host smart-f4d1a997-9b33-4101-95f8-feaea5b326a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911278112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1911278112
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.699013395
Short name T410
Test name
Test status
Simulation time 48318219185 ps
CPU time 78.82 seconds
Started Jul 21 07:15:12 PM PDT 24
Finished Jul 21 07:16:32 PM PDT 24
Peak memory 200232 kb
Host smart-7bc639a6-eca2-4a19-bf02-e5ec6a5833a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699013395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.699013395
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3062018624
Short name T1164
Test name
Test status
Simulation time 913563860 ps
CPU time 0.94 seconds
Started Jul 21 07:15:15 PM PDT 24
Finished Jul 21 07:15:16 PM PDT 24
Peak memory 195872 kb
Host smart-c534875b-f771-4143-a423-335a3557352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062018624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3062018624
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1651753954
Short name T1035
Test name
Test status
Simulation time 20883493398 ps
CPU time 100.95 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:16:56 PM PDT 24
Peak memory 200180 kb
Host smart-298f562e-6667-4b30-8a52-99e6465a5627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651753954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1651753954
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3416848507
Short name T448
Test name
Test status
Simulation time 6646280152 ps
CPU time 60.76 seconds
Started Jul 21 07:15:16 PM PDT 24
Finished Jul 21 07:16:17 PM PDT 24
Peak memory 198624 kb
Host smart-05ca4153-2739-4428-ac50-2df05dcebe23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416848507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3416848507
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3702644832
Short name T491
Test name
Test status
Simulation time 18141486781 ps
CPU time 29.05 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:15:44 PM PDT 24
Peak memory 200208 kb
Host smart-c9e4e6f2-39ec-4a5a-bd36-2f11f858e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702644832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3702644832
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3112370258
Short name T885
Test name
Test status
Simulation time 52761351447 ps
CPU time 16.13 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 196300 kb
Host smart-5b614544-224c-4ee1-9c8e-074996b963db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112370258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3112370258
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2113572876
Short name T887
Test name
Test status
Simulation time 6072136914 ps
CPU time 22.85 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:15:38 PM PDT 24
Peak memory 200160 kb
Host smart-c61117b0-1f66-47c5-a624-f3e6c5bc0342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113572876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2113572876
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1141769405
Short name T402
Test name
Test status
Simulation time 540777951538 ps
CPU time 491.23 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:23:25 PM PDT 24
Peak memory 200164 kb
Host smart-077092f7-e8d6-4988-9c1e-21f0070bd3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141769405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1141769405
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1999320636
Short name T675
Test name
Test status
Simulation time 47463211177 ps
CPU time 1159.01 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:34:34 PM PDT 24
Peak memory 216628 kb
Host smart-29cb0057-135b-4a65-ad4a-1ffa846f29c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999320636 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1999320636
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1955591987
Short name T531
Test name
Test status
Simulation time 831032375 ps
CPU time 2.61 seconds
Started Jul 21 07:15:14 PM PDT 24
Finished Jul 21 07:15:18 PM PDT 24
Peak memory 198556 kb
Host smart-707ec8c9-54af-424b-9485-f6da19183ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955591987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1955591987
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2447324630
Short name T714
Test name
Test status
Simulation time 45796887889 ps
CPU time 79.48 seconds
Started Jul 21 07:15:12 PM PDT 24
Finished Jul 21 07:16:32 PM PDT 24
Peak memory 199976 kb
Host smart-81324584-a18a-44e9-8fb8-7ff6ca4bfea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447324630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2447324630
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.138342543
Short name T392
Test name
Test status
Simulation time 47224775 ps
CPU time 0.55 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:15:20 PM PDT 24
Peak memory 195052 kb
Host smart-a112ad9a-a342-4377-b9b0-d9244e039691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138342543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.138342543
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3565655694
Short name T165
Test name
Test status
Simulation time 28385716889 ps
CPU time 25.22 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:15:40 PM PDT 24
Peak memory 200172 kb
Host smart-ca8ad0c0-1841-4370-9e99-d840dced3ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565655694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3565655694
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.929729562
Short name T471
Test name
Test status
Simulation time 17000129366 ps
CPU time 33.83 seconds
Started Jul 21 07:15:15 PM PDT 24
Finished Jul 21 07:15:50 PM PDT 24
Peak memory 200180 kb
Host smart-101644fb-9ff6-4362-a046-73ccc74c0afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929729562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.929729562
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1798529151
Short name T1147
Test name
Test status
Simulation time 130660170217 ps
CPU time 76.05 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:16:34 PM PDT 24
Peak memory 200152 kb
Host smart-2be4fd7e-50de-4c56-8299-84f6a48d1043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798529151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1798529151
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3686213612
Short name T1142
Test name
Test status
Simulation time 29303339207 ps
CPU time 11.8 seconds
Started Jul 21 07:15:21 PM PDT 24
Finished Jul 21 07:15:34 PM PDT 24
Peak memory 197708 kb
Host smart-69bd3e30-0ca0-40a4-9058-657dec1f951d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686213612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3686213612
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3732044894
Short name T533
Test name
Test status
Simulation time 218511183452 ps
CPU time 507.41 seconds
Started Jul 21 07:15:19 PM PDT 24
Finished Jul 21 07:23:48 PM PDT 24
Peak memory 200192 kb
Host smart-f1f01548-dac3-47ea-a374-cb8eec323ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732044894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3732044894
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3212353097
Short name T1024
Test name
Test status
Simulation time 676239738 ps
CPU time 2.54 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:15:21 PM PDT 24
Peak memory 197692 kb
Host smart-d1fa7239-99b5-4b75-bbda-7b8f5466ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212353097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3212353097
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3279762834
Short name T264
Test name
Test status
Simulation time 416876268987 ps
CPU time 57.07 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:16:16 PM PDT 24
Peak memory 208520 kb
Host smart-18679287-9f06-4af5-91d1-44dc1f4080d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279762834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3279762834
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.385444775
Short name T870
Test name
Test status
Simulation time 18189174725 ps
CPU time 1035.45 seconds
Started Jul 21 07:15:19 PM PDT 24
Finished Jul 21 07:32:36 PM PDT 24
Peak memory 200192 kb
Host smart-d0693b7f-dbb6-4753-84f3-592401cecdb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=385444775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.385444775
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3452198889
Short name T358
Test name
Test status
Simulation time 5518704111 ps
CPU time 46.37 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:16:00 PM PDT 24
Peak memory 199084 kb
Host smart-2a1863d8-76c2-4b5b-9965-44d4580b3144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452198889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3452198889
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.666239477
Short name T734
Test name
Test status
Simulation time 145009972743 ps
CPU time 306.98 seconds
Started Jul 21 07:15:21 PM PDT 24
Finished Jul 21 07:20:29 PM PDT 24
Peak memory 200120 kb
Host smart-592a1d1d-e622-4d18-9430-4ef4479ffc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666239477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.666239477
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1346963443
Short name T1026
Test name
Test status
Simulation time 33491253449 ps
CPU time 13.05 seconds
Started Jul 21 07:15:20 PM PDT 24
Finished Jul 21 07:15:35 PM PDT 24
Peak memory 197060 kb
Host smart-e6671aed-c46a-4224-b3a8-dec3f13925dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346963443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1346963443
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.571170172
Short name T865
Test name
Test status
Simulation time 623728235 ps
CPU time 2.28 seconds
Started Jul 21 07:15:16 PM PDT 24
Finished Jul 21 07:15:19 PM PDT 24
Peak memory 199324 kb
Host smart-832b018c-0206-468a-97c9-9a449f4ca373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571170172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.571170172
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3071512827
Short name T1131
Test name
Test status
Simulation time 140472248253 ps
CPU time 134.61 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:17:34 PM PDT 24
Peak memory 200184 kb
Host smart-48cd6763-e51c-42f5-b363-8fc0c873bd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071512827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3071512827
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.898091057
Short name T572
Test name
Test status
Simulation time 117789894997 ps
CPU time 207.62 seconds
Started Jul 21 07:15:21 PM PDT 24
Finished Jul 21 07:18:50 PM PDT 24
Peak memory 216504 kb
Host smart-596ff62a-a952-4972-a4e2-f6a74a50684b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898091057 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.898091057
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3319745224
Short name T1121
Test name
Test status
Simulation time 1120133764 ps
CPU time 4.65 seconds
Started Jul 21 07:15:19 PM PDT 24
Finished Jul 21 07:15:25 PM PDT 24
Peak memory 200144 kb
Host smart-bae3d44c-4fad-454e-90a5-bd0460f0d22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319745224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3319745224
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3800788367
Short name T1099
Test name
Test status
Simulation time 84374595407 ps
CPU time 27.47 seconds
Started Jul 21 07:15:13 PM PDT 24
Finished Jul 21 07:15:41 PM PDT 24
Peak memory 199748 kb
Host smart-f96dd2e8-428e-415a-a4f6-6d088568f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800788367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3800788367
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4012623837
Short name T738
Test name
Test status
Simulation time 32541011 ps
CPU time 0.59 seconds
Started Jul 21 07:15:30 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 195536 kb
Host smart-16f8996a-a8e0-4b07-be25-24fca3c5d131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012623837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4012623837
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3748669939
Short name T1149
Test name
Test status
Simulation time 79292709018 ps
CPU time 17.19 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:15:36 PM PDT 24
Peak memory 200208 kb
Host smart-92d2294e-9c9d-48a7-a693-29e0643fdf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748669939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3748669939
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3762121662
Short name T801
Test name
Test status
Simulation time 50984387999 ps
CPU time 19.26 seconds
Started Jul 21 07:15:22 PM PDT 24
Finished Jul 21 07:15:42 PM PDT 24
Peak memory 199728 kb
Host smart-d43db787-c424-41f8-9a95-24fd628cdeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762121662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3762121662
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.89274475
Short name T737
Test name
Test status
Simulation time 63427305383 ps
CPU time 96.66 seconds
Started Jul 21 07:15:22 PM PDT 24
Finished Jul 21 07:16:59 PM PDT 24
Peak memory 199920 kb
Host smart-25fc7307-21f9-481a-8897-dda7a4b48195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89274475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.89274475
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2791783006
Short name T778
Test name
Test status
Simulation time 7877906151 ps
CPU time 3.83 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:15:23 PM PDT 24
Peak memory 196952 kb
Host smart-b64c23f2-d26d-4ad0-baa7-7b1455d38daf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791783006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2791783006
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1836069363
Short name T335
Test name
Test status
Simulation time 143845609571 ps
CPU time 352.43 seconds
Started Jul 21 07:15:25 PM PDT 24
Finished Jul 21 07:21:19 PM PDT 24
Peak memory 199996 kb
Host smart-a6ece02d-0f64-47db-b7aa-f7e7114218fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836069363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1836069363
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.812142542
Short name T769
Test name
Test status
Simulation time 7070062549 ps
CPU time 8.08 seconds
Started Jul 21 07:15:22 PM PDT 24
Finished Jul 21 07:15:32 PM PDT 24
Peak memory 199148 kb
Host smart-e621cd44-466d-4bcb-8ded-ee87e39e62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812142542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.812142542
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3283399975
Short name T461
Test name
Test status
Simulation time 66734805245 ps
CPU time 49.65 seconds
Started Jul 21 07:15:24 PM PDT 24
Finished Jul 21 07:16:16 PM PDT 24
Peak memory 200216 kb
Host smart-1a0a31c4-86c5-40d5-9251-d1c200219b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283399975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3283399975
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.412983587
Short name T268
Test name
Test status
Simulation time 25254389928 ps
CPU time 181.22 seconds
Started Jul 21 07:15:29 PM PDT 24
Finished Jul 21 07:18:31 PM PDT 24
Peak memory 200104 kb
Host smart-15bb4510-2d6f-47a0-a215-79ea41836de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412983587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.412983587
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3280522960
Short name T1116
Test name
Test status
Simulation time 1698562079 ps
CPU time 8.14 seconds
Started Jul 21 07:15:20 PM PDT 24
Finished Jul 21 07:15:29 PM PDT 24
Peak memory 198228 kb
Host smart-6111ab7b-8415-4db9-b7cc-b56a6c8f6a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280522960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3280522960
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1882698131
Short name T633
Test name
Test status
Simulation time 45281207235 ps
CPU time 21.08 seconds
Started Jul 21 07:15:25 PM PDT 24
Finished Jul 21 07:15:48 PM PDT 24
Peak memory 200104 kb
Host smart-e9570e20-4d34-4313-a31d-941e4526680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882698131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1882698131
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4093191455
Short name T464
Test name
Test status
Simulation time 6670248848 ps
CPU time 9.87 seconds
Started Jul 21 07:15:23 PM PDT 24
Finished Jul 21 07:15:34 PM PDT 24
Peak memory 196452 kb
Host smart-df734d9b-1317-4b17-9833-903cf68543c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093191455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4093191455
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3350491139
Short name T639
Test name
Test status
Simulation time 6331940992 ps
CPU time 23.61 seconds
Started Jul 21 07:15:21 PM PDT 24
Finished Jul 21 07:15:46 PM PDT 24
Peak memory 199948 kb
Host smart-a42f53e3-c80c-4977-baa3-84e1fd4d7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350491139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3350491139
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2340858176
Short name T472
Test name
Test status
Simulation time 177147031386 ps
CPU time 295.43 seconds
Started Jul 21 07:15:24 PM PDT 24
Finished Jul 21 07:20:22 PM PDT 24
Peak memory 208472 kb
Host smart-a316641b-22d7-40e2-8f38-7b56d0a69f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340858176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2340858176
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1356936692
Short name T611
Test name
Test status
Simulation time 216231199265 ps
CPU time 608.73 seconds
Started Jul 21 07:15:24 PM PDT 24
Finished Jul 21 07:25:34 PM PDT 24
Peak memory 216656 kb
Host smart-24effd79-dcc9-4d7d-91e8-3031f50036d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356936692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1356936692
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3230959984
Short name T803
Test name
Test status
Simulation time 1018588047 ps
CPU time 4.31 seconds
Started Jul 21 07:15:24 PM PDT 24
Finished Jul 21 07:15:29 PM PDT 24
Peak memory 199740 kb
Host smart-18809580-fcf0-4591-9d60-3cda599d6d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230959984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3230959984
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.139720385
Short name T1073
Test name
Test status
Simulation time 86769922322 ps
CPU time 194.92 seconds
Started Jul 21 07:15:18 PM PDT 24
Finished Jul 21 07:18:33 PM PDT 24
Peak memory 200160 kb
Host smart-ce4e8ea1-d3d1-439c-8f1c-c12d9cbaf56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139720385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.139720385
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1396887901
Short name T345
Test name
Test status
Simulation time 12872132 ps
CPU time 0.56 seconds
Started Jul 21 07:15:35 PM PDT 24
Finished Jul 21 07:15:38 PM PDT 24
Peak memory 195212 kb
Host smart-df6e8980-c7b0-491d-b83b-c8fd93afc7e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396887901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1396887901
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2440584090
Short name T1098
Test name
Test status
Simulation time 71125972502 ps
CPU time 73.28 seconds
Started Jul 21 07:15:23 PM PDT 24
Finished Jul 21 07:16:38 PM PDT 24
Peak memory 200168 kb
Host smart-cc6bb0ab-21fb-492e-b587-99aa0e97607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440584090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2440584090
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.468534853
Short name T1161
Test name
Test status
Simulation time 141374899985 ps
CPU time 28 seconds
Started Jul 21 07:15:23 PM PDT 24
Finished Jul 21 07:15:52 PM PDT 24
Peak memory 200204 kb
Host smart-fdc1cf4d-2846-42d9-b703-0bf59a6db749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468534853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.468534853
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3456847443
Short name T775
Test name
Test status
Simulation time 60400147869 ps
CPU time 30.49 seconds
Started Jul 21 07:15:23 PM PDT 24
Finished Jul 21 07:15:55 PM PDT 24
Peak memory 200232 kb
Host smart-ac1050b4-9050-4c29-809e-abb2dc3898c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456847443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3456847443
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1009949143
Short name T435
Test name
Test status
Simulation time 12452829032 ps
CPU time 3.49 seconds
Started Jul 21 07:15:30 PM PDT 24
Finished Jul 21 07:15:34 PM PDT 24
Peak memory 200092 kb
Host smart-71dc9d94-a867-4cd5-bb4a-ce93de6e07d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009949143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1009949143
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2533455675
Short name T791
Test name
Test status
Simulation time 183479629421 ps
CPU time 1546.16 seconds
Started Jul 21 07:15:29 PM PDT 24
Finished Jul 21 07:41:16 PM PDT 24
Peak memory 200132 kb
Host smart-bfc4939f-863d-4df6-bd4b-896a07f978ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533455675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2533455675
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1950887330
Short name T619
Test name
Test status
Simulation time 6022321933 ps
CPU time 9.71 seconds
Started Jul 21 07:15:29 PM PDT 24
Finished Jul 21 07:15:40 PM PDT 24
Peak memory 198376 kb
Host smart-b000f112-bbc5-4461-80b8-0475f4d2ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950887330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1950887330
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1144939696
Short name T1126
Test name
Test status
Simulation time 81687645510 ps
CPU time 33.23 seconds
Started Jul 21 07:15:34 PM PDT 24
Finished Jul 21 07:16:10 PM PDT 24
Peak memory 199076 kb
Host smart-6c3217e5-28bc-4eed-b25e-93e5eab67ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144939696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1144939696
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2899994446
Short name T1077
Test name
Test status
Simulation time 21598747099 ps
CPU time 296.23 seconds
Started Jul 21 07:15:29 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 200100 kb
Host smart-5d6dab62-5e61-4982-a4b1-24914b7b270b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899994446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2899994446
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.796700963
Short name T1056
Test name
Test status
Simulation time 2123559055 ps
CPU time 1.06 seconds
Started Jul 21 07:15:30 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 198052 kb
Host smart-df178db9-74ac-48cb-b31b-1cd523222520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796700963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.796700963
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1235909365
Short name T1023
Test name
Test status
Simulation time 74311603244 ps
CPU time 28.69 seconds
Started Jul 21 07:15:31 PM PDT 24
Finished Jul 21 07:16:00 PM PDT 24
Peak memory 200236 kb
Host smart-f8f56635-99c7-427f-bee3-1c45a7d0141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235909365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1235909365
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2584373836
Short name T1075
Test name
Test status
Simulation time 34197372899 ps
CPU time 47.62 seconds
Started Jul 21 07:15:35 PM PDT 24
Finished Jul 21 07:16:25 PM PDT 24
Peak memory 196208 kb
Host smart-1c0a8780-ef52-4a63-9428-9a2a1e39423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584373836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2584373836
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2935139762
Short name T302
Test name
Test status
Simulation time 699373281 ps
CPU time 1.88 seconds
Started Jul 21 07:15:25 PM PDT 24
Finished Jul 21 07:15:28 PM PDT 24
Peak memory 198460 kb
Host smart-1456c807-6555-41b1-984b-e5f41594f77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935139762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2935139762
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2409595846
Short name T267
Test name
Test status
Simulation time 45561770893 ps
CPU time 92.13 seconds
Started Jul 21 07:15:29 PM PDT 24
Finished Jul 21 07:17:02 PM PDT 24
Peak memory 200180 kb
Host smart-ff3b025c-b36e-4f14-95e0-27c291f70eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409595846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2409595846
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.67875595
Short name T58
Test name
Test status
Simulation time 59256647862 ps
CPU time 1082.41 seconds
Started Jul 21 07:15:30 PM PDT 24
Finished Jul 21 07:33:33 PM PDT 24
Peak memory 209992 kb
Host smart-b0b0800a-e3b7-44ae-aad0-db47c9f7cb89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67875595 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.67875595
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.574322448
Short name T374
Test name
Test status
Simulation time 1771142749 ps
CPU time 2.92 seconds
Started Jul 21 07:15:28 PM PDT 24
Finished Jul 21 07:15:31 PM PDT 24
Peak memory 199724 kb
Host smart-fedf37f0-bed5-4af7-bebe-cb4f312f30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574322448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.574322448
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2307036640
Short name T742
Test name
Test status
Simulation time 17507253276 ps
CPU time 25.85 seconds
Started Jul 21 07:15:30 PM PDT 24
Finished Jul 21 07:15:57 PM PDT 24
Peak memory 200168 kb
Host smart-dd1ad049-6bb0-4a9b-a802-162321244b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307036640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2307036640
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2923244959
Short name T506
Test name
Test status
Simulation time 26954830 ps
CPU time 0.56 seconds
Started Jul 21 07:15:38 PM PDT 24
Finished Jul 21 07:15:42 PM PDT 24
Peak memory 195580 kb
Host smart-a4304dd1-3b79-47fd-b470-b9ec099f9b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923244959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2923244959
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1212480336
Short name T569
Test name
Test status
Simulation time 82893537184 ps
CPU time 28.52 seconds
Started Jul 21 07:15:37 PM PDT 24
Finished Jul 21 07:16:09 PM PDT 24
Peak memory 200208 kb
Host smart-dc39d7fb-5d89-48ac-bb62-0f90783fe774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212480336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1212480336
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1076414888
Short name T697
Test name
Test status
Simulation time 29891630048 ps
CPU time 11.92 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:52 PM PDT 24
Peak memory 200276 kb
Host smart-1a255c19-9522-4cea-88cb-8a309311c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076414888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1076414888
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1849782515
Short name T971
Test name
Test status
Simulation time 157958649402 ps
CPU time 135.25 seconds
Started Jul 21 07:15:37 PM PDT 24
Finished Jul 21 07:17:56 PM PDT 24
Peak memory 200180 kb
Host smart-d43e6663-4c9c-432b-a03f-5a085310ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849782515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1849782515
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1458916194
Short name T310
Test name
Test status
Simulation time 22514209216 ps
CPU time 9.85 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:49 PM PDT 24
Peak memory 200132 kb
Host smart-125321c1-ea60-4d0a-8455-340894c21f81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458916194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1458916194
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1850690574
Short name T413
Test name
Test status
Simulation time 42826084435 ps
CPU time 224.21 seconds
Started Jul 21 07:15:35 PM PDT 24
Finished Jul 21 07:19:22 PM PDT 24
Peak memory 200184 kb
Host smart-c02bee0c-2873-4469-9db6-e352a70a952a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850690574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1850690574
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1897880552
Short name T532
Test name
Test status
Simulation time 9878931949 ps
CPU time 21.21 seconds
Started Jul 21 07:15:37 PM PDT 24
Finished Jul 21 07:16:02 PM PDT 24
Peak memory 199680 kb
Host smart-4533bc01-c4ea-4924-ad6f-2edf5fa3be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897880552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1897880552
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3496163705
Short name T625
Test name
Test status
Simulation time 16588432511 ps
CPU time 22.95 seconds
Started Jul 21 07:15:38 PM PDT 24
Finished Jul 21 07:16:05 PM PDT 24
Peak memory 197960 kb
Host smart-6cc32959-a142-447b-be55-789d2e3760f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496163705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3496163705
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2731625134
Short name T351
Test name
Test status
Simulation time 8261716133 ps
CPU time 498.76 seconds
Started Jul 21 07:15:35 PM PDT 24
Finished Jul 21 07:23:57 PM PDT 24
Peak memory 200156 kb
Host smart-b94312b6-9286-42bf-8db7-9a3b36035b0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731625134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2731625134
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2430767712
Short name T1081
Test name
Test status
Simulation time 6645836802 ps
CPU time 15.54 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:55 PM PDT 24
Peak memory 198036 kb
Host smart-7ba3ba00-0534-493d-a3b7-8eb0f08f7ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430767712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2430767712
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4220706438
Short name T1133
Test name
Test status
Simulation time 30932568628 ps
CPU time 12.4 seconds
Started Jul 21 07:15:38 PM PDT 24
Finished Jul 21 07:15:54 PM PDT 24
Peak memory 200120 kb
Host smart-8a670291-ca25-4409-9c92-2165843586f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220706438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4220706438
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2598889315
Short name T599
Test name
Test status
Simulation time 43219723833 ps
CPU time 17.98 seconds
Started Jul 21 07:15:49 PM PDT 24
Finished Jul 21 07:16:18 PM PDT 24
Peak memory 196328 kb
Host smart-7ec8a7cf-64f4-46a3-8f3a-97fe1c305caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598889315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2598889315
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.28233217
Short name T474
Test name
Test status
Simulation time 856810577 ps
CPU time 2.19 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:42 PM PDT 24
Peak memory 198412 kb
Host smart-9ad361e9-b52b-46d1-a40c-c6f24bf923ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28233217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.28233217
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1708991968
Short name T466
Test name
Test status
Simulation time 276865187015 ps
CPU time 57.56 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:16:37 PM PDT 24
Peak memory 200152 kb
Host smart-fed3055b-4509-41f9-9a54-fcba7bb0e1a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708991968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1708991968
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3436067670
Short name T62
Test name
Test status
Simulation time 375446909236 ps
CPU time 1176.96 seconds
Started Jul 21 07:15:37 PM PDT 24
Finished Jul 21 07:35:17 PM PDT 24
Peak memory 225188 kb
Host smart-b4b335e0-bf32-4817-b8ef-2b248f480ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436067670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3436067670
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.962670674
Short name T1080
Test name
Test status
Simulation time 1337208054 ps
CPU time 4.52 seconds
Started Jul 21 07:15:37 PM PDT 24
Finished Jul 21 07:15:45 PM PDT 24
Peak memory 198720 kb
Host smart-7764858e-d85d-4a90-bc69-89bfa386b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962670674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.962670674
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3423792686
Short name T1003
Test name
Test status
Simulation time 17291383411 ps
CPU time 12.45 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:52 PM PDT 24
Peak memory 198256 kb
Host smart-d3e52f38-b43b-460d-a49d-f81662e56512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423792686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3423792686
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4008507857
Short name T699
Test name
Test status
Simulation time 39273625 ps
CPU time 0.55 seconds
Started Jul 21 07:15:45 PM PDT 24
Finished Jul 21 07:15:50 PM PDT 24
Peak memory 194844 kb
Host smart-d3cac72e-891f-440b-9635-a2e5362ea9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008507857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4008507857
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1232970715
Short name T560
Test name
Test status
Simulation time 128258552008 ps
CPU time 193.55 seconds
Started Jul 21 07:15:39 PM PDT 24
Finished Jul 21 07:18:56 PM PDT 24
Peak memory 200056 kb
Host smart-241ca6d4-c75e-408b-bac7-9bc7c480ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232970715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1232970715
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.483311908
Short name T749
Test name
Test status
Simulation time 36032996967 ps
CPU time 57.94 seconds
Started Jul 21 07:15:45 PM PDT 24
Finished Jul 21 07:16:49 PM PDT 24
Peak memory 200184 kb
Host smart-936cc035-edf3-4e7a-b285-e848d9ab6756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483311908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.483311908
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1032265807
Short name T956
Test name
Test status
Simulation time 36593227742 ps
CPU time 17.88 seconds
Started Jul 21 07:15:41 PM PDT 24
Finished Jul 21 07:16:00 PM PDT 24
Peak memory 199860 kb
Host smart-936adf24-b2dd-4dcc-a8b7-5ba968b6f7aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032265807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1032265807
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1259017187
Short name T926
Test name
Test status
Simulation time 73837863951 ps
CPU time 486.42 seconds
Started Jul 21 07:15:42 PM PDT 24
Finished Jul 21 07:23:49 PM PDT 24
Peak memory 200080 kb
Host smart-82f20247-5ca7-4fc6-b4ff-e53234ac54c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1259017187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1259017187
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.4101725360
Short name T1127
Test name
Test status
Simulation time 21831991 ps
CPU time 0.65 seconds
Started Jul 21 07:15:40 PM PDT 24
Finished Jul 21 07:15:43 PM PDT 24
Peak memory 196288 kb
Host smart-48ac2469-8594-4b83-9cfc-9557dc55be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101725360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4101725360
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.872388915
Short name T711
Test name
Test status
Simulation time 203590756279 ps
CPU time 89.79 seconds
Started Jul 21 07:15:43 PM PDT 24
Finished Jul 21 07:17:14 PM PDT 24
Peak memory 208460 kb
Host smart-5df28f06-5553-4b56-b36e-31c81ebf38cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872388915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.872388915
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2666862259
Short name T248
Test name
Test status
Simulation time 17682733565 ps
CPU time 244.34 seconds
Started Jul 21 07:15:41 PM PDT 24
Finished Jul 21 07:19:47 PM PDT 24
Peak memory 200196 kb
Host smart-83bb1c6b-eb58-4558-9d69-69ef7b7b40a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666862259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2666862259
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.610297371
Short name T716
Test name
Test status
Simulation time 4664595410 ps
CPU time 29.96 seconds
Started Jul 21 07:15:43 PM PDT 24
Finished Jul 21 07:16:14 PM PDT 24
Peak memory 198960 kb
Host smart-e75906df-bd8c-4f1f-85da-ec3c5d6be8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610297371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.610297371
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.819357018
Short name T144
Test name
Test status
Simulation time 60738061046 ps
CPU time 19.89 seconds
Started Jul 21 07:15:40 PM PDT 24
Finished Jul 21 07:16:02 PM PDT 24
Peak memory 199156 kb
Host smart-46f9a815-59a6-44b4-8bb2-aa45dc307905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819357018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.819357018
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3003777759
Short name T910
Test name
Test status
Simulation time 3165765660 ps
CPU time 5.12 seconds
Started Jul 21 07:15:42 PM PDT 24
Finished Jul 21 07:15:49 PM PDT 24
Peak memory 196228 kb
Host smart-ebf93981-dc5b-438e-b745-c33c20c325a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003777759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3003777759
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1556797408
Short name T352
Test name
Test status
Simulation time 309023447 ps
CPU time 1.07 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:15:41 PM PDT 24
Peak memory 198684 kb
Host smart-fdf25948-367d-4658-aa5e-088803550cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556797408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1556797408
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3315078198
Short name T1022
Test name
Test status
Simulation time 90882911265 ps
CPU time 620.99 seconds
Started Jul 21 07:15:45 PM PDT 24
Finished Jul 21 07:26:12 PM PDT 24
Peak memory 216724 kb
Host smart-707e1d96-6bbd-4199-a4ff-c4f6b5a71c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315078198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3315078198
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3105771038
Short name T1094
Test name
Test status
Simulation time 2268447060 ps
CPU time 1.99 seconds
Started Jul 21 07:15:41 PM PDT 24
Finished Jul 21 07:15:45 PM PDT 24
Peak memory 198960 kb
Host smart-17efb211-0fd3-46f6-a412-076cce291acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105771038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3105771038
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2734065067
Short name T1017
Test name
Test status
Simulation time 91064492947 ps
CPU time 67.07 seconds
Started Jul 21 07:15:36 PM PDT 24
Finished Jul 21 07:16:47 PM PDT 24
Peak memory 200144 kb
Host smart-1e149869-f1e6-4d43-9aa4-70fc5b411929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734065067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2734065067
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3198069038
Short name T331
Test name
Test status
Simulation time 13476420 ps
CPU time 0.55 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:16:11 PM PDT 24
Peak memory 195856 kb
Host smart-94839425-c5ae-459c-a2fd-967eb69d8179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198069038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3198069038
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.4185954359
Short name T626
Test name
Test status
Simulation time 217131039118 ps
CPU time 158.99 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:18:34 PM PDT 24
Peak memory 200152 kb
Host smart-7a441485-0753-4b46-9c86-a147fd4fd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185954359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.4185954359
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.236871874
Short name T1144
Test name
Test status
Simulation time 121014347373 ps
CPU time 243.2 seconds
Started Jul 21 07:15:46 PM PDT 24
Finished Jul 21 07:19:56 PM PDT 24
Peak memory 200148 kb
Host smart-6ada7e02-a667-450e-9cdb-9c88419481e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236871874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.236871874
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.8272276
Short name T480
Test name
Test status
Simulation time 32020456967 ps
CPU time 49.19 seconds
Started Jul 21 07:15:48 PM PDT 24
Finished Jul 21 07:16:47 PM PDT 24
Peak memory 200032 kb
Host smart-78d96863-44b0-4985-9cdb-6755bcdf92f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8272276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.8272276
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3373570338
Short name T417
Test name
Test status
Simulation time 98244220497 ps
CPU time 187.67 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:19:20 PM PDT 24
Peak memory 200184 kb
Host smart-a5fea2bf-8e98-4191-ba91-85899104ad55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373570338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3373570338
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2196031872
Short name T48
Test name
Test status
Simulation time 11317893285 ps
CPU time 31.54 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:16:42 PM PDT 24
Peak memory 199260 kb
Host smart-902e207a-02d8-4c9d-83de-0c0cff3e8570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196031872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2196031872
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3754163820
Short name T745
Test name
Test status
Simulation time 46170699588 ps
CPU time 29.11 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:16:23 PM PDT 24
Peak memory 199680 kb
Host smart-6e1112de-af57-46b4-b600-545c85d19797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754163820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3754163820
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4097671649
Short name T1095
Test name
Test status
Simulation time 10578161955 ps
CPU time 92.71 seconds
Started Jul 21 07:15:53 PM PDT 24
Finished Jul 21 07:17:47 PM PDT 24
Peak memory 200240 kb
Host smart-da8634e6-4b50-4782-a0f1-86ab9cdc8515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097671649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4097671649
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1441644183
Short name T922
Test name
Test status
Simulation time 4458282074 ps
CPU time 20.06 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:16:14 PM PDT 24
Peak memory 198308 kb
Host smart-78570a48-d09f-487b-a6fd-f57b8d0a2e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441644183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1441644183
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3873309071
Short name T340
Test name
Test status
Simulation time 26875670716 ps
CPU time 10.91 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:16:05 PM PDT 24
Peak memory 199644 kb
Host smart-9c234fa7-9c1b-449a-84ca-1cc68f84fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873309071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3873309071
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.332342239
Short name T932
Test name
Test status
Simulation time 2727115814 ps
CPU time 2.47 seconds
Started Jul 21 07:15:48 PM PDT 24
Finished Jul 21 07:16:02 PM PDT 24
Peak memory 196696 kb
Host smart-127c40b2-e5c2-4b54-aa76-7a9fe7abd17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332342239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.332342239
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1755999451
Short name T653
Test name
Test status
Simulation time 289946150 ps
CPU time 1.49 seconds
Started Jul 21 07:15:47 PM PDT 24
Finished Jul 21 07:15:57 PM PDT 24
Peak memory 199236 kb
Host smart-7607518f-a165-486d-b551-c9ea5bdc98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755999451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1755999451
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1089269956
Short name T720
Test name
Test status
Simulation time 200273366436 ps
CPU time 544.66 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:25:16 PM PDT 24
Peak memory 200068 kb
Host smart-b5a1b63e-5257-4ac6-93cd-5bd8e2ba1188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089269956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1089269956
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3871916537
Short name T565
Test name
Test status
Simulation time 12915385242 ps
CPU time 122.11 seconds
Started Jul 21 07:15:51 PM PDT 24
Finished Jul 21 07:18:11 PM PDT 24
Peak memory 216692 kb
Host smart-462c1323-cba6-43d1-9982-0f18fa0996d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871916537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3871916537
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.403705213
Short name T379
Test name
Test status
Simulation time 1248784586 ps
CPU time 1.87 seconds
Started Jul 21 07:15:46 PM PDT 24
Finished Jul 21 07:15:54 PM PDT 24
Peak memory 199888 kb
Host smart-488268a4-13e6-4ad6-9005-0e498af7e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403705213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.403705213
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4170288787
Short name T613
Test name
Test status
Simulation time 19612654014 ps
CPU time 16.15 seconds
Started Jul 21 07:15:53 PM PDT 24
Finished Jul 21 07:16:29 PM PDT 24
Peak memory 200192 kb
Host smart-54a1898a-be07-4e2e-9113-0659da851272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170288787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4170288787
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.368702044
Short name T334
Test name
Test status
Simulation time 24760067 ps
CPU time 0.57 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:16:41 PM PDT 24
Peak memory 195932 kb
Host smart-176b994d-d25a-4254-90a7-24677077367c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368702044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.368702044
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2597753155
Short name T645
Test name
Test status
Simulation time 66942226208 ps
CPU time 96.43 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:17:49 PM PDT 24
Peak memory 199904 kb
Host smart-b4b15a30-7223-4aad-9a56-ee5885eef0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597753155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2597753155
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1452109046
Short name T347
Test name
Test status
Simulation time 170011207102 ps
CPU time 66.46 seconds
Started Jul 21 07:15:51 PM PDT 24
Finished Jul 21 07:17:14 PM PDT 24
Peak memory 200128 kb
Host smart-9371559f-0b16-4945-9f1a-a24db1a793e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452109046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1452109046
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1491809838
Short name T218
Test name
Test status
Simulation time 130474717717 ps
CPU time 48.23 seconds
Started Jul 21 07:15:52 PM PDT 24
Finished Jul 21 07:16:59 PM PDT 24
Peak memory 200176 kb
Host smart-0c7f3d68-f1df-4a11-a56b-2b4f606e0f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491809838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1491809838
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2312388572
Short name T596
Test name
Test status
Simulation time 30081058442 ps
CPU time 9.91 seconds
Started Jul 21 07:15:59 PM PDT 24
Finished Jul 21 07:16:56 PM PDT 24
Peak memory 199384 kb
Host smart-ecfb779b-f1d1-4724-848d-f01f27fd9cdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312388572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2312388572
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2064385345
Short name T874
Test name
Test status
Simulation time 164304019999 ps
CPU time 1793.64 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:46:34 PM PDT 24
Peak memory 200180 kb
Host smart-aad8f11c-29fd-4a14-89eb-bf8dee08f7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064385345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2064385345
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2619314485
Short name T344
Test name
Test status
Simulation time 9549735867 ps
CPU time 2.14 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:16:42 PM PDT 24
Peak memory 198588 kb
Host smart-b90f9322-57b8-442b-b275-7570407aaab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619314485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2619314485
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2693268726
Short name T1117
Test name
Test status
Simulation time 77520181333 ps
CPU time 98.12 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:18:18 PM PDT 24
Peak memory 199948 kb
Host smart-8d924055-c9c4-4761-b829-cd26eb258243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693268726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2693268726
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4148429441
Short name T1034
Test name
Test status
Simulation time 7886554288 ps
CPU time 228.15 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:20:23 PM PDT 24
Peak memory 200164 kb
Host smart-d7a441b6-ba84-403b-8429-0f3fbcc64c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148429441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4148429441
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2545673251
Short name T346
Test name
Test status
Simulation time 4282980521 ps
CPU time 18.04 seconds
Started Jul 21 07:15:58 PM PDT 24
Finished Jul 21 07:17:01 PM PDT 24
Peak memory 199376 kb
Host smart-64e73e23-9795-4e27-b58d-0f5a7cce1c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545673251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2545673251
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.693716756
Short name T270
Test name
Test status
Simulation time 35225255963 ps
CPU time 13.67 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:16:53 PM PDT 24
Peak memory 199836 kb
Host smart-3d92214a-2682-432d-88cf-856b010b8924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693716756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.693716756
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2763872206
Short name T585
Test name
Test status
Simulation time 1669520253 ps
CPU time 3.09 seconds
Started Jul 21 07:15:56 PM PDT 24
Finished Jul 21 07:16:38 PM PDT 24
Peak memory 195660 kb
Host smart-08492a68-2b47-41a1-9c6d-1e870d76226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763872206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2763872206
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1680411343
Short name T271
Test name
Test status
Simulation time 288441080 ps
CPU time 1.53 seconds
Started Jul 21 07:15:53 PM PDT 24
Finished Jul 21 07:16:15 PM PDT 24
Peak memory 198660 kb
Host smart-27dba545-8fe1-4a04-be6e-d7f2d4b186f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680411343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1680411343
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4193416879
Short name T637
Test name
Test status
Simulation time 240378743840 ps
CPU time 105.26 seconds
Started Jul 21 07:15:59 PM PDT 24
Finished Jul 21 07:18:32 PM PDT 24
Peak memory 208544 kb
Host smart-97058724-dfac-460f-bf9a-05808bc2a119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193416879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4193416879
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.14264573
Short name T1027
Test name
Test status
Simulation time 127888675910 ps
CPU time 933.88 seconds
Started Jul 21 07:16:00 PM PDT 24
Finished Jul 21 07:32:32 PM PDT 24
Peak memory 224976 kb
Host smart-cd4bce3d-c2dd-404d-ad70-f0e17bd950d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264573 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.14264573
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1304190794
Short name T339
Test name
Test status
Simulation time 9064953620 ps
CPU time 8.99 seconds
Started Jul 21 07:15:56 PM PDT 24
Finished Jul 21 07:16:40 PM PDT 24
Peak memory 200092 kb
Host smart-f2d7b1df-a87c-42c9-a57d-fb9091647a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304190794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1304190794
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1487299446
Short name T303
Test name
Test status
Simulation time 109411513294 ps
CPU time 166.41 seconds
Started Jul 21 07:15:55 PM PDT 24
Finished Jul 21 07:19:10 PM PDT 24
Peak memory 200208 kb
Host smart-d6dbdc7a-a6bf-4b52-beb6-4f66a9636d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487299446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1487299446
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3726049902
Short name T367
Test name
Test status
Simulation time 10538163 ps
CPU time 0.57 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:17:49 PM PDT 24
Peak memory 195212 kb
Host smart-36185c98-5503-44bb-a86a-1fcab3d52ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726049902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3726049902
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1704616796
Short name T766
Test name
Test status
Simulation time 235476928527 ps
CPU time 19.55 seconds
Started Jul 21 07:15:57 PM PDT 24
Finished Jul 21 07:17:00 PM PDT 24
Peak memory 200184 kb
Host smart-8917e511-c60c-4505-8a08-5e3586e38f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704616796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1704616796
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1454714221
Short name T459
Test name
Test status
Simulation time 6990821011 ps
CPU time 14.37 seconds
Started Jul 21 07:16:03 PM PDT 24
Finished Jul 21 07:17:23 PM PDT 24
Peak memory 200132 kb
Host smart-9413104f-4fa3-4601-84df-66b22489a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454714221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1454714221
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2104350400
Short name T806
Test name
Test status
Simulation time 30185864060 ps
CPU time 13.09 seconds
Started Jul 21 07:16:04 PM PDT 24
Finished Jul 21 07:17:27 PM PDT 24
Peak memory 200128 kb
Host smart-be121333-435d-4f11-ab3c-6553aa41b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104350400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2104350400
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2788633613
Short name T730
Test name
Test status
Simulation time 12043850386 ps
CPU time 4.74 seconds
Started Jul 21 07:16:06 PM PDT 24
Finished Jul 21 07:17:27 PM PDT 24
Peak memory 198532 kb
Host smart-38c39c75-2dbe-44c4-b6d8-8786da1d37a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788633613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2788633613
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4126259849
Short name T553
Test name
Test status
Simulation time 119919677675 ps
CPU time 165.07 seconds
Started Jul 21 07:16:05 PM PDT 24
Finished Jul 21 07:20:03 PM PDT 24
Peak memory 200180 kb
Host smart-1a72e289-bc24-4306-9b55-2713417df8a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126259849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4126259849
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.350677012
Short name T498
Test name
Test status
Simulation time 1522394001 ps
CPU time 2.62 seconds
Started Jul 21 07:16:06 PM PDT 24
Finished Jul 21 07:17:25 PM PDT 24
Peak memory 198692 kb
Host smart-f2436866-985f-4cfe-9a1e-4a43a8c8dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350677012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.350677012
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1179862707
Short name T1169
Test name
Test status
Simulation time 21241757023 ps
CPU time 25.02 seconds
Started Jul 21 07:16:06 PM PDT 24
Finished Jul 21 07:17:48 PM PDT 24
Peak memory 198944 kb
Host smart-cb0e415f-9680-4b58-8b34-3182c4a099a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179862707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1179862707
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.555650538
Short name T828
Test name
Test status
Simulation time 9768692869 ps
CPU time 503.82 seconds
Started Jul 21 07:16:03 PM PDT 24
Finished Jul 21 07:25:33 PM PDT 24
Peak memory 200152 kb
Host smart-25371e4b-c6f5-4e6f-9baf-0e3e5538f342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555650538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.555650538
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2379801774
Short name T878
Test name
Test status
Simulation time 2761231957 ps
CPU time 10.75 seconds
Started Jul 21 07:16:02 PM PDT 24
Finished Jul 21 07:17:20 PM PDT 24
Peak memory 198460 kb
Host smart-74be5a97-1f8e-42b9-a4d0-540622f80169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379801774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2379801774
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3457739838
Short name T723
Test name
Test status
Simulation time 35470611964 ps
CPU time 63.83 seconds
Started Jul 21 07:16:05 PM PDT 24
Finished Jul 21 07:18:22 PM PDT 24
Peak memory 200052 kb
Host smart-4ec1a35f-c3fb-453b-a66c-f64191fab502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457739838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3457739838
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1422739685
Short name T724
Test name
Test status
Simulation time 45243167356 ps
CPU time 16.93 seconds
Started Jul 21 07:16:03 PM PDT 24
Finished Jul 21 07:17:29 PM PDT 24
Peak memory 196040 kb
Host smart-bdc510ba-0f6c-4049-999e-84d2510702bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422739685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1422739685
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1375862194
Short name T298
Test name
Test status
Simulation time 85000792 ps
CPU time 0.81 seconds
Started Jul 21 07:16:00 PM PDT 24
Finished Jul 21 07:16:56 PM PDT 24
Peak memory 197264 kb
Host smart-ca581eea-3414-4cc2-ae5e-580333892b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375862194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1375862194
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2855877978
Short name T1069
Test name
Test status
Simulation time 497961807334 ps
CPU time 312.2 seconds
Started Jul 21 07:16:03 PM PDT 24
Finished Jul 21 07:22:21 PM PDT 24
Peak memory 200084 kb
Host smart-584f2334-6e3c-41d4-8fb5-eb0a9f873fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855877978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2855877978
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1697860521
Short name T159
Test name
Test status
Simulation time 47212079972 ps
CPU time 252.37 seconds
Started Jul 21 07:16:03 PM PDT 24
Finished Jul 21 07:21:26 PM PDT 24
Peak memory 216756 kb
Host smart-355674f6-08cf-4135-9f12-530a63eb0097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697860521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1697860521
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.659706127
Short name T764
Test name
Test status
Simulation time 6171858478 ps
CPU time 21.7 seconds
Started Jul 21 07:16:02 PM PDT 24
Finished Jul 21 07:17:29 PM PDT 24
Peak memory 200188 kb
Host smart-ae6f9961-9037-4464-98b4-d4a5e7854a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659706127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.659706127
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.4019701082
Short name T1028
Test name
Test status
Simulation time 65352742344 ps
CPU time 33.17 seconds
Started Jul 21 07:16:00 PM PDT 24
Finished Jul 21 07:17:29 PM PDT 24
Peak memory 200156 kb
Host smart-c98636fd-188c-4f21-bf76-9745e91b1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019701082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.4019701082
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2831314131
Short name T847
Test name
Test status
Simulation time 12042455 ps
CPU time 0.58 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:17:49 PM PDT 24
Peak memory 195556 kb
Host smart-ec307a4e-c54e-493b-ac1b-c95649f146cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831314131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2831314131
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2050519663
Short name T746
Test name
Test status
Simulation time 86794685132 ps
CPU time 89.37 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:19:08 PM PDT 24
Peak memory 200200 kb
Host smart-b3c5ff53-8de9-46b5-8786-ae86560dc81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050519663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2050519663
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3658476664
Short name T49
Test name
Test status
Simulation time 15231012370 ps
CPU time 24.75 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:18:00 PM PDT 24
Peak memory 200220 kb
Host smart-6468dbc7-057a-4222-9269-71a39dec5aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658476664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3658476664
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.4186878071
Short name T741
Test name
Test status
Simulation time 228716662522 ps
CPU time 336.3 seconds
Started Jul 21 07:16:11 PM PDT 24
Finished Jul 21 07:23:18 PM PDT 24
Peak memory 200220 kb
Host smart-3e1cf9a7-7f82-4876-b60e-8f1932bf2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186878071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.4186878071
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1363597981
Short name T931
Test name
Test status
Simulation time 63664494563 ps
CPU time 13.34 seconds
Started Jul 21 07:16:08 PM PDT 24
Finished Jul 21 07:17:52 PM PDT 24
Peak memory 199888 kb
Host smart-dc9758be-11e8-4a43-872d-c4aa9f4ade79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363597981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1363597981
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1828670158
Short name T453
Test name
Test status
Simulation time 29329773448 ps
CPU time 126.62 seconds
Started Jul 21 07:16:08 PM PDT 24
Finished Jul 21 07:19:46 PM PDT 24
Peak memory 200140 kb
Host smart-315aaa95-0170-446a-a613-fabd9bb312cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828670158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1828670158
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2839260537
Short name T1103
Test name
Test status
Simulation time 6018356249 ps
CPU time 2.42 seconds
Started Jul 21 07:16:11 PM PDT 24
Finished Jul 21 07:17:45 PM PDT 24
Peak memory 199772 kb
Host smart-a2dbc873-1739-4a48-91d2-606c6056b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839260537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2839260537
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3801088564
Short name T245
Test name
Test status
Simulation time 81763544825 ps
CPU time 141.4 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:20:00 PM PDT 24
Peak memory 200248 kb
Host smart-f7cf12a3-e013-41d6-a1eb-8844991944ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801088564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3801088564
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3023490153
Short name T598
Test name
Test status
Simulation time 11052360901 ps
CPU time 271.99 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:22:11 PM PDT 24
Peak memory 200200 kb
Host smart-ea699507-9a68-4d67-9fda-e461feb62771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023490153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3023490153
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3627229387
Short name T284
Test name
Test status
Simulation time 75366674934 ps
CPU time 65.75 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:18:41 PM PDT 24
Peak memory 200136 kb
Host smart-0bbf3b31-bba5-455b-9e91-43b9408978d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627229387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3627229387
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.738613514
Short name T977
Test name
Test status
Simulation time 5279603935 ps
CPU time 7.66 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:17:43 PM PDT 24
Peak memory 196508 kb
Host smart-4f761c5d-4088-4c9f-b445-4b56e95b9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738613514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.738613514
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1289207326
Short name T250
Test name
Test status
Simulation time 314361551 ps
CPU time 1.62 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:17:41 PM PDT 24
Peak memory 199236 kb
Host smart-510f0bf5-867a-4648-be4a-78e26e7e17a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289207326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1289207326
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3880019858
Short name T56
Test name
Test status
Simulation time 58950070585 ps
CPU time 442.12 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:25:01 PM PDT 24
Peak memory 216872 kb
Host smart-71a27151-f3a3-4d98-8388-707f0a122366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880019858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3880019858
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2000694499
Short name T823
Test name
Test status
Simulation time 734659371 ps
CPU time 1.37 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:17:36 PM PDT 24
Peak memory 198852 kb
Host smart-db0cf8b1-ded3-4d1b-9e0d-d21dba9220a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000694499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2000694499
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3619101947
Short name T1082
Test name
Test status
Simulation time 44089612792 ps
CPU time 18.19 seconds
Started Jul 21 07:16:10 PM PDT 24
Finished Jul 21 07:17:56 PM PDT 24
Peak memory 199248 kb
Host smart-079b198d-a606-4242-84c0-b5fbbeaf7827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619101947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3619101947
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1226732789
Short name T659
Test name
Test status
Simulation time 19436392 ps
CPU time 0.57 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:12:49 PM PDT 24
Peak memory 195880 kb
Host smart-e6bb855d-bcb7-4338-87f8-e9b5cda1e964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226732789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1226732789
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2895170668
Short name T698
Test name
Test status
Simulation time 121266687763 ps
CPU time 42.62 seconds
Started Jul 21 07:12:46 PM PDT 24
Finished Jul 21 07:13:33 PM PDT 24
Peak memory 200140 kb
Host smart-3a678e83-ce11-453f-a4f1-4cab863fe291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895170668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2895170668
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2338061808
Short name T554
Test name
Test status
Simulation time 19062962169 ps
CPU time 30.42 seconds
Started Jul 21 07:12:45 PM PDT 24
Finished Jul 21 07:13:20 PM PDT 24
Peak memory 200164 kb
Host smart-766a4d7c-8846-463e-b022-1af66c3b6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338061808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2338061808
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1652018289
Short name T168
Test name
Test status
Simulation time 134959009161 ps
CPU time 130.05 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:14:59 PM PDT 24
Peak memory 200180 kb
Host smart-c96d2825-5017-4b4f-ba53-5970d6c7f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652018289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1652018289
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3053177976
Short name T822
Test name
Test status
Simulation time 20769311161 ps
CPU time 42.01 seconds
Started Jul 21 07:12:43 PM PDT 24
Finished Jul 21 07:13:30 PM PDT 24
Peak memory 200180 kb
Host smart-ca68b7cd-127a-41e0-8471-939dc9c39339
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053177976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3053177976
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3825919074
Short name T419
Test name
Test status
Simulation time 104859907146 ps
CPU time 293.41 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:17:43 PM PDT 24
Peak memory 200176 kb
Host smart-3799a12f-5447-4c2e-a0e3-1d098cee1239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825919074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3825919074
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2600080977
Short name T957
Test name
Test status
Simulation time 10442020759 ps
CPU time 18.68 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:13:07 PM PDT 24
Peak memory 200152 kb
Host smart-b585b4db-03c0-4641-8f98-059425a73b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600080977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2600080977
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1516907563
Short name T1072
Test name
Test status
Simulation time 67177073391 ps
CPU time 30.54 seconds
Started Jul 21 07:12:45 PM PDT 24
Finished Jul 21 07:13:20 PM PDT 24
Peak memory 200016 kb
Host smart-7ef5aee6-1520-420b-8417-859f36af3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516907563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1516907563
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3608830567
Short name T684
Test name
Test status
Simulation time 14205044997 ps
CPU time 131.98 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:15:01 PM PDT 24
Peak memory 200184 kb
Host smart-ce35ace3-e2df-4539-90be-25cd8efbe77f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608830567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3608830567
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4261118435
Short name T427
Test name
Test status
Simulation time 3264852990 ps
CPU time 13.78 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:13:03 PM PDT 24
Peak memory 198264 kb
Host smart-02895e59-91cf-4667-ab4c-605e4f378f36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261118435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4261118435
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1741216064
Short name T10
Test name
Test status
Simulation time 62589758556 ps
CPU time 46.82 seconds
Started Jul 21 07:12:47 PM PDT 24
Finished Jul 21 07:13:38 PM PDT 24
Peak memory 200176 kb
Host smart-353ef90f-04ba-4845-8b10-e27149b9f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741216064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1741216064
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.4017633432
Short name T899
Test name
Test status
Simulation time 4377190553 ps
CPU time 6.56 seconds
Started Jul 21 07:12:44 PM PDT 24
Finished Jul 21 07:12:55 PM PDT 24
Peak memory 196496 kb
Host smart-0a3b6bcb-e77e-490c-bcdf-9e2caaa64baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017633432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4017633432
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1157614702
Short name T24
Test name
Test status
Simulation time 151232534 ps
CPU time 0.82 seconds
Started Jul 21 07:12:47 PM PDT 24
Finished Jul 21 07:12:52 PM PDT 24
Peak memory 218344 kb
Host smart-bfe7d327-0e68-47f6-8211-3dd73631214b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157614702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1157614702
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1779792991
Short name T898
Test name
Test status
Simulation time 5764732031 ps
CPU time 16.72 seconds
Started Jul 21 07:12:43 PM PDT 24
Finished Jul 21 07:13:05 PM PDT 24
Peak memory 200072 kb
Host smart-f60bf465-5570-40c4-ac04-90cff0004955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779792991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1779792991
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.442075623
Short name T75
Test name
Test status
Simulation time 447529337284 ps
CPU time 325.4 seconds
Started Jul 21 07:12:46 PM PDT 24
Finished Jul 21 07:18:16 PM PDT 24
Peak memory 200156 kb
Host smart-b227414f-29f6-480e-a0be-bd4e5a8cf039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442075623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.442075623
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.472456815
Short name T558
Test name
Test status
Simulation time 12447943853 ps
CPU time 83.9 seconds
Started Jul 21 07:12:47 PM PDT 24
Finished Jul 21 07:14:15 PM PDT 24
Peak memory 208520 kb
Host smart-2ad5b70a-df3d-4e6c-bf66-fcc6922e5d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472456815 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.472456815
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1506809433
Short name T39
Test name
Test status
Simulation time 1020108918 ps
CPU time 2.01 seconds
Started Jul 21 07:12:45 PM PDT 24
Finished Jul 21 07:12:52 PM PDT 24
Peak memory 198772 kb
Host smart-365ef055-b048-45c3-8a2a-51c8d0ddb4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506809433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1506809433
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.991893958
Short name T1045
Test name
Test status
Simulation time 69963126038 ps
CPU time 100.19 seconds
Started Jul 21 07:12:47 PM PDT 24
Finished Jul 21 07:14:31 PM PDT 24
Peak memory 200116 kb
Host smart-d3273565-5e02-4cd8-acf3-829f4429091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991893958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.991893958
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2774883654
Short name T683
Test name
Test status
Simulation time 13676610 ps
CPU time 0.55 seconds
Started Jul 21 07:16:21 PM PDT 24
Finished Jul 21 07:18:07 PM PDT 24
Peak memory 194844 kb
Host smart-6343f66e-6ed4-404f-9840-fc787b68e718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774883654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2774883654
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2840576282
Short name T656
Test name
Test status
Simulation time 119435720454 ps
CPU time 297.01 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:22:46 PM PDT 24
Peak memory 200128 kb
Host smart-afe4667b-a7ee-46ff-a9ea-8a20a6bbd31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840576282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2840576282
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3689490284
Short name T452
Test name
Test status
Simulation time 46260614621 ps
CPU time 15.96 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:18:09 PM PDT 24
Peak memory 200208 kb
Host smart-6aeafde6-e61d-4018-92ca-4f90141f4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689490284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3689490284
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2135360779
Short name T449
Test name
Test status
Simulation time 227206067113 ps
CPU time 286.47 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:22:35 PM PDT 24
Peak memory 200116 kb
Host smart-139cd0a1-0baa-4dc6-ae83-371ec3468e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135360779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2135360779
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2973726504
Short name T1132
Test name
Test status
Simulation time 21696958008 ps
CPU time 17.78 seconds
Started Jul 21 07:16:16 PM PDT 24
Finished Jul 21 07:18:11 PM PDT 24
Peak memory 200152 kb
Host smart-471d3f45-902b-4005-bbfd-c388985655f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973726504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2973726504
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2706271764
Short name T354
Test name
Test status
Simulation time 90633049825 ps
CPU time 880.53 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:32:30 PM PDT 24
Peak memory 200144 kb
Host smart-2a6e31a3-bac1-42ff-b018-d9cd25e03943
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706271764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2706271764
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1007699336
Short name T53
Test name
Test status
Simulation time 5863959798 ps
CPU time 3.76 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:17:53 PM PDT 24
Peak memory 199764 kb
Host smart-64e93a5a-307b-4e14-861e-c132df758d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007699336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1007699336
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.34030136
Short name T919
Test name
Test status
Simulation time 79747404674 ps
CPU time 131.87 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 208456 kb
Host smart-cc3ec7b5-7151-4627-8107-702337a6778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34030136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.34030136
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2812643538
Short name T403
Test name
Test status
Simulation time 19595338671 ps
CPU time 241.42 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:21:54 PM PDT 24
Peak memory 200072 kb
Host smart-c8f9fcf3-d7ce-49c7-b12b-44abc3f78e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812643538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2812643538
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2969365376
Short name T361
Test name
Test status
Simulation time 1479490444 ps
CPU time 5.66 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:17:55 PM PDT 24
Peak memory 198164 kb
Host smart-94e4649e-fef0-4fad-89fa-ac7c1d454dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969365376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2969365376
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2815614595
Short name T511
Test name
Test status
Simulation time 130603960165 ps
CPU time 52.24 seconds
Started Jul 21 07:16:16 PM PDT 24
Finished Jul 21 07:19:14 PM PDT 24
Peak memory 200116 kb
Host smart-0156c679-63ce-4f96-ad36-feee15c3fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815614595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2815614595
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2598700682
Short name T832
Test name
Test status
Simulation time 49246209918 ps
CPU time 63.15 seconds
Started Jul 21 07:16:14 PM PDT 24
Finished Jul 21 07:18:52 PM PDT 24
Peak memory 196044 kb
Host smart-a73db075-7c54-47cc-9569-24eb34a5970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598700682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2598700682
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3948889474
Short name T414
Test name
Test status
Simulation time 449633018 ps
CPU time 1.84 seconds
Started Jul 21 07:16:09 PM PDT 24
Finished Jul 21 07:17:37 PM PDT 24
Peak memory 199028 kb
Host smart-97cb7961-8c11-46fd-b236-acebb687c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948889474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3948889474
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.807068877
Short name T239
Test name
Test status
Simulation time 188754034686 ps
CPU time 304.94 seconds
Started Jul 21 07:16:18 PM PDT 24
Finished Jul 21 07:23:43 PM PDT 24
Peak memory 200108 kb
Host smart-9f5a7d07-cdae-4d83-a8b3-2356536644ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807068877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.807068877
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1819896905
Short name T713
Test name
Test status
Simulation time 41790423671 ps
CPU time 391.06 seconds
Started Jul 21 07:16:17 PM PDT 24
Finished Jul 21 07:24:53 PM PDT 24
Peak memory 216820 kb
Host smart-f677d11f-f8a6-4857-aa2d-9d33c4d86f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819896905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1819896905
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.944581791
Short name T355
Test name
Test status
Simulation time 888962309 ps
CPU time 1.57 seconds
Started Jul 21 07:16:16 PM PDT 24
Finished Jul 21 07:18:23 PM PDT 24
Peak memory 198756 kb
Host smart-25156722-3a66-457f-9d02-4487cf71d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944581791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.944581791
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1939039367
Short name T1039
Test name
Test status
Simulation time 88093258807 ps
CPU time 126.99 seconds
Started Jul 21 07:16:15 PM PDT 24
Finished Jul 21 07:19:56 PM PDT 24
Peak memory 200152 kb
Host smart-40f9b7aa-7ad4-4777-84d4-fec2a3c37adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939039367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1939039367
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1790419416
Short name T337
Test name
Test status
Simulation time 16982304 ps
CPU time 0.55 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:18:31 PM PDT 24
Peak memory 195832 kb
Host smart-d2a2be3a-fa76-4416-b4ce-32eb82fdd24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790419416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1790419416
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1024613435
Short name T463
Test name
Test status
Simulation time 60868586421 ps
CPU time 50.01 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:19:59 PM PDT 24
Peak memory 200196 kb
Host smart-02a9587c-c4c0-4d53-89e8-991aad857409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024613435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1024613435
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2888916249
Short name T999
Test name
Test status
Simulation time 34098409987 ps
CPU time 25.7 seconds
Started Jul 21 07:16:21 PM PDT 24
Finished Jul 21 07:18:40 PM PDT 24
Peak memory 200108 kb
Host smart-6ab4e5e7-9c48-46ba-8c7f-09d61fe705e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888916249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2888916249
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1873751708
Short name T208
Test name
Test status
Simulation time 25380467385 ps
CPU time 34.16 seconds
Started Jul 21 07:16:21 PM PDT 24
Finished Jul 21 07:19:11 PM PDT 24
Peak memory 200132 kb
Host smart-c75cfed4-c7c3-489c-8e87-1b7aa80bf558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873751708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1873751708
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.730307121
Short name T16
Test name
Test status
Simulation time 22780066460 ps
CPU time 11.04 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:18:55 PM PDT 24
Peak memory 197804 kb
Host smart-18acbfb2-42b6-417e-afe0-0a133a73bbfb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730307121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.730307121
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3638752927
Short name T1061
Test name
Test status
Simulation time 108123302539 ps
CPU time 342.35 seconds
Started Jul 21 07:16:21 PM PDT 24
Finished Jul 21 07:23:56 PM PDT 24
Peak memory 200200 kb
Host smart-5f9e61bf-7e0d-4de2-8474-965e357dd6d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638752927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3638752927
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1684093022
Short name T327
Test name
Test status
Simulation time 122672586 ps
CPU time 0.74 seconds
Started Jul 21 07:16:20 PM PDT 24
Finished Jul 21 07:18:14 PM PDT 24
Peak memory 197308 kb
Host smart-91ac382e-ea2d-4a9e-8261-50ce4e95d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684093022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1684093022
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4051677206
Short name T624
Test name
Test status
Simulation time 63253263744 ps
CPU time 51.17 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:19:35 PM PDT 24
Peak memory 200204 kb
Host smart-589b7f8e-6e73-45cb-a88d-f72c676451c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051677206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4051677206
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2472843679
Short name T343
Test name
Test status
Simulation time 16730677057 ps
CPU time 696.71 seconds
Started Jul 21 07:16:20 PM PDT 24
Finished Jul 21 07:29:50 PM PDT 24
Peak memory 200160 kb
Host smart-9970112b-ac20-4512-ae44-05011434cb5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472843679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2472843679
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1083427359
Short name T946
Test name
Test status
Simulation time 4351474767 ps
CPU time 9.7 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:18:54 PM PDT 24
Peak memory 199400 kb
Host smart-6f141181-865f-42ef-a3ce-10ea4329cd1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083427359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1083427359
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2919214923
Short name T992
Test name
Test status
Simulation time 11622109663 ps
CPU time 14.77 seconds
Started Jul 21 07:16:34 PM PDT 24
Finished Jul 21 07:18:49 PM PDT 24
Peak memory 199972 kb
Host smart-41b5d0b2-c5f8-4d5d-a072-f9e534b420fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919214923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2919214923
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.530713275
Short name T696
Test name
Test status
Simulation time 76109952115 ps
CPU time 118.09 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 197060 kb
Host smart-c99ea981-e1bc-4fbc-b713-301d16b5569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530713275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.530713275
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3037951865
Short name T50
Test name
Test status
Simulation time 461241111 ps
CPU time 1.77 seconds
Started Jul 21 07:16:21 PM PDT 24
Finished Jul 21 07:18:16 PM PDT 24
Peak memory 199644 kb
Host smart-075fceca-efb1-45ab-a0ff-0f6f96e8e55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037951865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3037951865
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2514670617
Short name T688
Test name
Test status
Simulation time 29227860305 ps
CPU time 183.88 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:21:35 PM PDT 24
Peak memory 200176 kb
Host smart-a212f1a8-3c22-42af-b26c-dc55289abf36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514670617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2514670617
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4031251504
Short name T752
Test name
Test status
Simulation time 71731494621 ps
CPU time 1348.27 seconds
Started Jul 21 07:16:34 PM PDT 24
Finished Jul 21 07:41:03 PM PDT 24
Peak memory 225048 kb
Host smart-42f367a2-a37a-48ce-bc43-89a0e27be853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031251504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4031251504
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1540461100
Short name T1007
Test name
Test status
Simulation time 1181830994 ps
CPU time 3.93 seconds
Started Jul 21 07:16:20 PM PDT 24
Finished Jul 21 07:18:32 PM PDT 24
Peak memory 199036 kb
Host smart-3a5bd826-ae79-4146-a43c-150f9ab5e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540461100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1540461100
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2252187822
Short name T273
Test name
Test status
Simulation time 21053583094 ps
CPU time 29.15 seconds
Started Jul 21 07:16:31 PM PDT 24
Finished Jul 21 07:19:38 PM PDT 24
Peak memory 200224 kb
Host smart-5b88cf64-90e8-4cc5-8a1f-59da63dd8786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252187822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2252187822
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.409511643
Short name T1002
Test name
Test status
Simulation time 36032777 ps
CPU time 0.57 seconds
Started Jul 21 07:16:44 PM PDT 24
Finished Jul 21 07:18:52 PM PDT 24
Peak memory 195868 kb
Host smart-117537e8-60e8-45a6-9f6f-9c2c90cf502d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409511643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.409511643
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1283058841
Short name T329
Test name
Test status
Simulation time 16942483608 ps
CPU time 7.96 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:18:39 PM PDT 24
Peak memory 199900 kb
Host smart-d5f59f72-8a87-47e8-bdf4-583cb8c63623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283058841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1283058841
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3974669996
Short name T590
Test name
Test status
Simulation time 110227761785 ps
CPU time 169.73 seconds
Started Jul 21 07:16:33 PM PDT 24
Finished Jul 21 07:21:23 PM PDT 24
Peak memory 200148 kb
Host smart-ed938d79-3861-4209-9abb-75b151f23490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974669996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3974669996
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3059971178
Short name T864
Test name
Test status
Simulation time 6460750473 ps
CPU time 13.65 seconds
Started Jul 21 07:16:31 PM PDT 24
Finished Jul 21 07:19:23 PM PDT 24
Peak memory 200172 kb
Host smart-e765f93d-54d7-4657-82b6-35db999aade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059971178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3059971178
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.4156108175
Short name T479
Test name
Test status
Simulation time 46889482378 ps
CPU time 85.98 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:19:57 PM PDT 24
Peak memory 200172 kb
Host smart-646b3d7e-f361-4c6b-9c78-cd8ad237199b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156108175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4156108175
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.869673326
Short name T44
Test name
Test status
Simulation time 37325866677 ps
CPU time 79.65 seconds
Started Jul 21 07:16:26 PM PDT 24
Finished Jul 21 07:20:11 PM PDT 24
Peak memory 200336 kb
Host smart-ccffb612-e589-4ea4-9c3b-f73a2f081526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869673326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.869673326
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.606700094
Short name T783
Test name
Test status
Simulation time 790522473 ps
CPU time 0.91 seconds
Started Jul 21 07:16:33 PM PDT 24
Finished Jul 21 07:18:35 PM PDT 24
Peak memory 196184 kb
Host smart-e326934e-9afa-46b3-b8a7-65c6bfee0a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606700094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.606700094
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3167590327
Short name T1064
Test name
Test status
Simulation time 78058336349 ps
CPU time 48.6 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:19:27 PM PDT 24
Peak memory 200428 kb
Host smart-404203e2-2530-4e68-b1db-57b62400c826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167590327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3167590327
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3885928701
Short name T375
Test name
Test status
Simulation time 5919426333 ps
CPU time 73.98 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:20:23 PM PDT 24
Peak memory 200132 kb
Host smart-774c5971-ce29-43e8-8630-28726356351a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885928701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3885928701
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3136825079
Short name T943
Test name
Test status
Simulation time 2638100886 ps
CPU time 11.76 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:18:43 PM PDT 24
Peak memory 198328 kb
Host smart-3d367ffb-20c1-42c1-9cfd-5ff415b10678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136825079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3136825079
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4258537782
Short name T378
Test name
Test status
Simulation time 151825305282 ps
CPU time 68.97 seconds
Started Jul 21 07:16:32 PM PDT 24
Finished Jul 21 07:19:42 PM PDT 24
Peak memory 200132 kb
Host smart-8b7b4a18-263b-4962-a93c-8f69d7645924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258537782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4258537782
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4229168434
Short name T970
Test name
Test status
Simulation time 4632426162 ps
CPU time 4.33 seconds
Started Jul 21 07:16:31 PM PDT 24
Finished Jul 21 07:19:13 PM PDT 24
Peak memory 197036 kb
Host smart-6210ed76-efdc-4763-90a2-f478f00b463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229168434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4229168434
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1049565583
Short name T657
Test name
Test status
Simulation time 736955501 ps
CPU time 1.82 seconds
Started Jul 21 07:16:25 PM PDT 24
Finished Jul 21 07:18:40 PM PDT 24
Peak memory 199992 kb
Host smart-5c9ac0a9-c45c-4d50-8e0a-7d3ecea7c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049565583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1049565583
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2160489906
Short name T743
Test name
Test status
Simulation time 536194602958 ps
CPU time 373.43 seconds
Started Jul 21 07:16:34 PM PDT 24
Finished Jul 21 07:24:48 PM PDT 24
Peak memory 200116 kb
Host smart-d321546a-5a11-4d18-8bf2-598930889938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160489906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2160489906
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2734269668
Short name T78
Test name
Test status
Simulation time 98689501520 ps
CPU time 1061.71 seconds
Started Jul 21 07:16:32 PM PDT 24
Finished Jul 21 07:36:15 PM PDT 24
Peak memory 216148 kb
Host smart-0f326801-0ad4-4cd3-b4db-d73d95d19c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734269668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2734269668
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4156326497
Short name T280
Test name
Test status
Simulation time 515626424 ps
CPU time 2.11 seconds
Started Jul 21 07:16:33 PM PDT 24
Finished Jul 21 07:18:36 PM PDT 24
Peak memory 198500 kb
Host smart-a8c71f5f-0ce4-4f6e-9726-0e02fc8a30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156326497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4156326497
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2403702133
Short name T800
Test name
Test status
Simulation time 18542041798 ps
CPU time 30.08 seconds
Started Jul 21 07:16:31 PM PDT 24
Finished Jul 21 07:19:39 PM PDT 24
Peak memory 200052 kb
Host smart-3f72be5c-c60e-41ca-b048-624aa5c70a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403702133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2403702133
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2367452848
Short name T950
Test name
Test status
Simulation time 14244043 ps
CPU time 0.56 seconds
Started Jul 21 07:16:47 PM PDT 24
Finished Jul 21 07:18:56 PM PDT 24
Peak memory 194560 kb
Host smart-746cd375-1290-49ec-8168-456c880f2e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367452848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2367452848
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1133994260
Short name T156
Test name
Test status
Simulation time 83496742711 ps
CPU time 116.85 seconds
Started Jul 21 07:16:30 PM PDT 24
Finished Jul 21 07:21:08 PM PDT 24
Peak memory 200124 kb
Host smart-88ac7ad6-0d50-4981-8a84-ec0529cfeaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133994260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1133994260
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3293764385
Short name T266
Test name
Test status
Simulation time 117283431813 ps
CPU time 265.47 seconds
Started Jul 21 07:16:37 PM PDT 24
Finished Jul 21 07:23:05 PM PDT 24
Peak memory 200152 kb
Host smart-998345b2-e2df-4b17-bc4c-eef827eac519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293764385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3293764385
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.835871337
Short name T242
Test name
Test status
Simulation time 16171472437 ps
CPU time 7.45 seconds
Started Jul 21 07:16:38 PM PDT 24
Finished Jul 21 07:19:13 PM PDT 24
Peak memory 200188 kb
Host smart-f3413b04-11da-4273-951e-5b084cb00e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835871337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.835871337
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.667857919
Short name T1119
Test name
Test status
Simulation time 24387671005 ps
CPU time 10.35 seconds
Started Jul 21 07:16:37 PM PDT 24
Finished Jul 21 07:18:55 PM PDT 24
Peak memory 197452 kb
Host smart-ac4c9b8f-492a-448f-a462-aceae704619e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667857919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.667857919
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1125804663
Short name T1107
Test name
Test status
Simulation time 93110524165 ps
CPU time 259.95 seconds
Started Jul 21 07:16:37 PM PDT 24
Finished Jul 21 07:22:59 PM PDT 24
Peak memory 200168 kb
Host smart-2e1b4cbc-7dad-4115-acf5-ba1a5a29feaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125804663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1125804663
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.863956254
Short name T1036
Test name
Test status
Simulation time 6696379171 ps
CPU time 5.74 seconds
Started Jul 21 07:16:36 PM PDT 24
Finished Jul 21 07:18:44 PM PDT 24
Peak memory 199244 kb
Host smart-2b8c1262-081a-4f03-937e-f704b8831a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863956254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.863956254
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2928891621
Short name T522
Test name
Test status
Simulation time 78482562949 ps
CPU time 109.14 seconds
Started Jul 21 07:16:36 PM PDT 24
Finished Jul 21 07:20:28 PM PDT 24
Peak memory 198440 kb
Host smart-e18f0131-5723-4f28-a229-4113c20288cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928891621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2928891621
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2518615173
Short name T776
Test name
Test status
Simulation time 17520935569 ps
CPU time 201.78 seconds
Started Jul 21 07:16:37 PM PDT 24
Finished Jul 21 07:22:06 PM PDT 24
Peak memory 200100 kb
Host smart-a390b018-94fe-48cf-a78c-2c197bc8116e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518615173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2518615173
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.985682434
Short name T399
Test name
Test status
Simulation time 3474287251 ps
CPU time 26.11 seconds
Started Jul 21 07:16:38 PM PDT 24
Finished Jul 21 07:19:31 PM PDT 24
Peak memory 198540 kb
Host smart-b90d6248-30be-4095-93f9-f67d684772f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985682434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.985682434
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2972541060
Short name T1135
Test name
Test status
Simulation time 118872168746 ps
CPU time 21.53 seconds
Started Jul 21 07:16:37 PM PDT 24
Finished Jul 21 07:19:01 PM PDT 24
Peak memory 200184 kb
Host smart-2a73e76f-5bed-4cf6-a0c4-e49f7e442ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972541060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2972541060
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.995988930
Short name T815
Test name
Test status
Simulation time 5050596708 ps
CPU time 2.64 seconds
Started Jul 21 07:16:38 PM PDT 24
Finished Jul 21 07:19:08 PM PDT 24
Peak memory 196996 kb
Host smart-4d9c93f5-788c-419d-b11c-5dadec8fe30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995988930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.995988930
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3795312096
Short name T991
Test name
Test status
Simulation time 268667201 ps
CPU time 1.25 seconds
Started Jul 21 07:16:33 PM PDT 24
Finished Jul 21 07:18:35 PM PDT 24
Peak memory 198792 kb
Host smart-6b43b086-869d-4c09-a084-fb7f0b0b3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795312096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3795312096
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2850469898
Short name T911
Test name
Test status
Simulation time 222022067812 ps
CPU time 677.63 seconds
Started Jul 21 07:16:48 PM PDT 24
Finished Jul 21 07:30:14 PM PDT 24
Peak memory 200148 kb
Host smart-4d49901a-3563-408d-be16-f0bbf1db8d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850469898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2850469898
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.4025684430
Short name T102
Test name
Test status
Simulation time 66771254294 ps
CPU time 778.72 seconds
Started Jul 21 07:16:46 PM PDT 24
Finished Jul 21 07:31:53 PM PDT 24
Peak memory 224968 kb
Host smart-771cd9f7-af58-4026-a2d7-25c67f245ed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025684430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.4025684430
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2543088766
Short name T368
Test name
Test status
Simulation time 2128348741 ps
CPU time 1.66 seconds
Started Jul 21 07:16:38 PM PDT 24
Finished Jul 21 07:19:07 PM PDT 24
Peak memory 198792 kb
Host smart-a13f07be-807d-41a3-8f08-19597076b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543088766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2543088766
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1705017100
Short name T829
Test name
Test status
Simulation time 41571689915 ps
CPU time 16.83 seconds
Started Jul 21 07:16:32 PM PDT 24
Finished Jul 21 07:18:50 PM PDT 24
Peak memory 200144 kb
Host smart-2961eea9-a299-4a6b-b1f7-2518cffdde7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705017100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1705017100
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2738852792
Short name T478
Test name
Test status
Simulation time 26470109 ps
CPU time 0.57 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:18:58 PM PDT 24
Peak memory 195896 kb
Host smart-a99e650c-b5e7-4845-9126-be7b3c29f4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738852792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2738852792
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3352593845
Short name T154
Test name
Test status
Simulation time 180966793606 ps
CPU time 68.19 seconds
Started Jul 21 07:16:47 PM PDT 24
Finished Jul 21 07:20:04 PM PDT 24
Peak memory 200236 kb
Host smart-13b573fc-a0a1-4ae3-ba3f-02f0f4933bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352593845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3352593845
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3136635721
Short name T441
Test name
Test status
Simulation time 23118718045 ps
CPU time 36.51 seconds
Started Jul 21 07:16:47 PM PDT 24
Finished Jul 21 07:20:03 PM PDT 24
Peak memory 200228 kb
Host smart-be9834a3-8aff-417c-8897-2532f257fb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136635721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3136635721
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2143564428
Short name T954
Test name
Test status
Simulation time 26971490439 ps
CPU time 8.8 seconds
Started Jul 21 07:16:48 PM PDT 24
Finished Jul 21 07:19:05 PM PDT 24
Peak memory 200208 kb
Host smart-92660f2c-03bf-4748-a001-9892c00f5c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143564428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2143564428
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.199392562
Short name T754
Test name
Test status
Simulation time 119583058288 ps
CPU time 186.84 seconds
Started Jul 21 07:16:50 PM PDT 24
Finished Jul 21 07:22:01 PM PDT 24
Peak memory 200132 kb
Host smart-fffe29f1-8e47-4f4f-a69a-b6934319f8d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199392562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.199392562
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3144078003
Short name T1020
Test name
Test status
Simulation time 173855264525 ps
CPU time 899.51 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:33:57 PM PDT 24
Peak memory 200192 kb
Host smart-3fcb5a9a-3b02-47d1-a600-d71436eba1c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144078003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3144078003
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3368730059
Short name T1170
Test name
Test status
Simulation time 4059506133 ps
CPU time 14.28 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:19:12 PM PDT 24
Peak memory 200100 kb
Host smart-cd8dd7e6-7101-41b8-bd8a-6bd44b124c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368730059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3368730059
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2060592570
Short name T929
Test name
Test status
Simulation time 210193473878 ps
CPU time 24.16 seconds
Started Jul 21 07:16:51 PM PDT 24
Finished Jul 21 07:19:21 PM PDT 24
Peak memory 200124 kb
Host smart-fd95ca60-4d7f-4387-be0c-ce4364c52c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060592570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2060592570
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.122205234
Short name T465
Test name
Test status
Simulation time 15227800632 ps
CPU time 764.19 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:31:42 PM PDT 24
Peak memory 200196 kb
Host smart-988b6b3f-d16f-45bc-bae1-cf9660341f09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122205234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.122205234
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2552784567
Short name T609
Test name
Test status
Simulation time 5910647744 ps
CPU time 23.23 seconds
Started Jul 21 07:16:47 PM PDT 24
Finished Jul 21 07:19:49 PM PDT 24
Peak memory 198040 kb
Host smart-828dfa94-c046-4dec-8b7d-35fdfeeb0eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552784567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2552784567
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.396072244
Short name T1104
Test name
Test status
Simulation time 21108051362 ps
CPU time 23.34 seconds
Started Jul 21 07:16:50 PM PDT 24
Finished Jul 21 07:19:20 PM PDT 24
Peak memory 200076 kb
Host smart-7812104f-888c-48a4-b2ff-4de8a3d224ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396072244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.396072244
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2925739222
Short name T872
Test name
Test status
Simulation time 3130227020 ps
CPU time 3.02 seconds
Started Jul 21 07:16:49 PM PDT 24
Finished Jul 21 07:18:59 PM PDT 24
Peak memory 196680 kb
Host smart-37804e04-3df8-4b38-b074-aae873ba200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925739222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2925739222
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1188659064
Short name T604
Test name
Test status
Simulation time 651269811 ps
CPU time 1.54 seconds
Started Jul 21 07:16:47 PM PDT 24
Finished Jul 21 07:18:57 PM PDT 24
Peak memory 199064 kb
Host smart-222f3a9a-5f6a-4670-bbd0-816ca30b4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188659064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1188659064
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1723732465
Short name T1030
Test name
Test status
Simulation time 147809005710 ps
CPU time 267.09 seconds
Started Jul 21 07:16:53 PM PDT 24
Finished Jul 21 07:23:24 PM PDT 24
Peak memory 208420 kb
Host smart-93d854a8-bc85-492c-8932-6589dee5ae7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723732465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1723732465
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3647145843
Short name T667
Test name
Test status
Simulation time 181856880490 ps
CPU time 263.94 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:23:22 PM PDT 24
Peak memory 216580 kb
Host smart-26dcbde7-822c-481d-845f-6ef886746b1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647145843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3647145843
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3718338620
Short name T881
Test name
Test status
Simulation time 7107974148 ps
CPU time 14.52 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:19:12 PM PDT 24
Peak memory 200348 kb
Host smart-d92af60d-710d-44c2-9c77-374b787b784a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718338620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3718338620
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2500430079
Short name T902
Test name
Test status
Simulation time 31546521282 ps
CPU time 56.19 seconds
Started Jul 21 07:16:48 PM PDT 24
Finished Jul 21 07:19:52 PM PDT 24
Peak memory 200212 kb
Host smart-3b8deabb-aa76-45d2-bb10-af21360af2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500430079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2500430079
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1149345753
Short name T324
Test name
Test status
Simulation time 18278036 ps
CPU time 0.54 seconds
Started Jul 21 07:17:11 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 195508 kb
Host smart-a3ab26ea-d68c-4a0e-becc-f4e637bb8bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149345753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1149345753
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2153622794
Short name T147
Test name
Test status
Simulation time 152419390053 ps
CPU time 20.36 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:19:18 PM PDT 24
Peak memory 200076 kb
Host smart-10e8627e-2f35-4128-bdc0-224d02760f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153622794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2153622794
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1025444042
Short name T981
Test name
Test status
Simulation time 17182489133 ps
CPU time 19.18 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:19:17 PM PDT 24
Peak memory 200136 kb
Host smart-19eb6218-534c-4b0d-a24a-97e8bbf262cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025444042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1025444042
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1100925495
Short name T314
Test name
Test status
Simulation time 19622503625 ps
CPU time 28.54 seconds
Started Jul 21 07:16:53 PM PDT 24
Finished Jul 21 07:19:26 PM PDT 24
Peak memory 200092 kb
Host smart-8fef0a97-6371-4e1a-a553-99716ab5a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100925495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1100925495
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1949853341
Short name T349
Test name
Test status
Simulation time 24874824259 ps
CPU time 19.96 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:19:17 PM PDT 24
Peak memory 200132 kb
Host smart-de2af90e-f48f-433a-bf75-1753db5c7b00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949853341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1949853341
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.2803701372
Short name T955
Test name
Test status
Simulation time 2106279052 ps
CPU time 3.96 seconds
Started Jul 21 07:17:05 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 195864 kb
Host smart-d0aa0dc8-2a28-41b3-94da-9d618f1f06da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803701372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2803701372
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.77458741
Short name T383
Test name
Test status
Simulation time 36146541365 ps
CPU time 25.4 seconds
Started Jul 21 07:16:58 PM PDT 24
Finished Jul 21 07:19:52 PM PDT 24
Peak memory 199244 kb
Host smart-f4459b13-4f76-4506-92cb-a6509a0daf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77458741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.77458741
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.980935875
Short name T1110
Test name
Test status
Simulation time 14747390405 ps
CPU time 834.02 seconds
Started Jul 21 07:17:05 PM PDT 24
Finished Jul 21 07:33:24 PM PDT 24
Peak memory 200196 kb
Host smart-d1d30590-bea9-4f98-8dab-1da0c060238d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980935875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.980935875
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3743270026
Short name T454
Test name
Test status
Simulation time 5600794075 ps
CPU time 33.13 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:19:31 PM PDT 24
Peak memory 198976 kb
Host smart-1c6c2da5-755e-46e3-bef4-d951f64880a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743270026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3743270026
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2460403092
Short name T562
Test name
Test status
Simulation time 146151229321 ps
CPU time 220.43 seconds
Started Jul 21 07:16:59 PM PDT 24
Finished Jul 21 07:23:07 PM PDT 24
Peak memory 200060 kb
Host smart-183a1ae2-ebb9-4c6a-a876-0fa0bce9aa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460403092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2460403092
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3950370459
Short name T325
Test name
Test status
Simulation time 2068070189 ps
CPU time 2.28 seconds
Started Jul 21 07:16:58 PM PDT 24
Finished Jul 21 07:19:29 PM PDT 24
Peak memory 195652 kb
Host smart-ccc47df1-566a-43bf-843d-11d54521d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950370459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3950370459
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2416263385
Short name T681
Test name
Test status
Simulation time 631179221 ps
CPU time 2.09 seconds
Started Jul 21 07:16:54 PM PDT 24
Finished Jul 21 07:18:59 PM PDT 24
Peak memory 198620 kb
Host smart-64664775-fd55-4584-9d56-3e9b6c478de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416263385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2416263385
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4063220529
Short name T292
Test name
Test status
Simulation time 105698366916 ps
CPU time 56.55 seconds
Started Jul 21 07:17:05 PM PDT 24
Finished Jul 21 07:20:27 PM PDT 24
Peak memory 200260 kb
Host smart-c90127de-b642-4928-8494-77783bdfb0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063220529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4063220529
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3867161521
Short name T979
Test name
Test status
Simulation time 31710644392 ps
CPU time 1069.79 seconds
Started Jul 21 07:17:03 PM PDT 24
Finished Jul 21 07:37:19 PM PDT 24
Peak memory 216800 kb
Host smart-db5003a6-0bb4-403d-9445-2a473fd2693c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867161521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3867161521
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.130189171
Short name T369
Test name
Test status
Simulation time 6879819921 ps
CPU time 18.09 seconds
Started Jul 21 07:16:58 PM PDT 24
Finished Jul 21 07:19:45 PM PDT 24
Peak memory 200156 kb
Host smart-a7445d1f-d8f7-4d5d-b530-8bde1fd5de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130189171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.130189171
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3841452980
Short name T1137
Test name
Test status
Simulation time 84000709400 ps
CPU time 126.13 seconds
Started Jul 21 07:16:55 PM PDT 24
Finished Jul 21 07:21:04 PM PDT 24
Peak memory 200132 kb
Host smart-653438d6-df9c-448d-ab6a-4eb384a0ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841452980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3841452980
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4222753447
Short name T905
Test name
Test status
Simulation time 17067910 ps
CPU time 0.65 seconds
Started Jul 21 07:17:19 PM PDT 24
Finished Jul 21 07:19:28 PM PDT 24
Peak memory 195916 kb
Host smart-3b29ccf9-51f9-4f27-a231-cfbe078d66ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222753447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4222753447
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1712374086
Short name T661
Test name
Test status
Simulation time 125416197344 ps
CPU time 80.1 seconds
Started Jul 21 07:17:09 PM PDT 24
Finished Jul 21 07:20:47 PM PDT 24
Peak memory 200132 kb
Host smart-030f0b2d-df89-42cd-9f6a-2ab4bda990f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712374086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1712374086
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4204401728
Short name T1043
Test name
Test status
Simulation time 37647757127 ps
CPU time 58.52 seconds
Started Jul 21 07:17:10 PM PDT 24
Finished Jul 21 07:20:24 PM PDT 24
Peak memory 200132 kb
Host smart-41255792-7667-43d1-b09c-ea061449d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204401728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4204401728
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4208148141
Short name T210
Test name
Test status
Simulation time 140401128172 ps
CPU time 19.39 seconds
Started Jul 21 07:17:10 PM PDT 24
Finished Jul 21 07:19:40 PM PDT 24
Peak memory 200188 kb
Host smart-04af5845-4a10-49f7-99e8-2863fd3b5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208148141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4208148141
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2529549948
Short name T844
Test name
Test status
Simulation time 65577660669 ps
CPU time 107.75 seconds
Started Jul 21 07:17:15 PM PDT 24
Finished Jul 21 07:21:14 PM PDT 24
Peak memory 200156 kb
Host smart-5fcb2df6-0bcd-4db4-b955-65d52bad7ef7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529549948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2529549948
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2525868239
Short name T682
Test name
Test status
Simulation time 80136356965 ps
CPU time 120.34 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:21:37 PM PDT 24
Peak memory 200104 kb
Host smart-a44897ed-08a4-48a7-b145-ce2dd8561885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525868239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2525868239
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.539775827
Short name T1153
Test name
Test status
Simulation time 7400779638 ps
CPU time 4.77 seconds
Started Jul 21 07:17:15 PM PDT 24
Finished Jul 21 07:19:31 PM PDT 24
Peak memory 199808 kb
Host smart-45359859-5e7c-4dcf-88f0-dbfc4ab42767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539775827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.539775827
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4202758320
Short name T852
Test name
Test status
Simulation time 33375105647 ps
CPU time 96.22 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:21:02 PM PDT 24
Peak memory 198456 kb
Host smart-d450a692-5d1d-46fb-8e6e-bd5c5a4fa25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202758320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4202758320
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.227088291
Short name T912
Test name
Test status
Simulation time 25611881934 ps
CPU time 1534.45 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:45:01 PM PDT 24
Peak memory 200148 kb
Host smart-aa27c003-51bb-4b8f-8808-b78889c2e4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227088291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.227088291
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1057585370
Short name T112
Test name
Test status
Simulation time 68665115426 ps
CPU time 28.42 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:19:56 PM PDT 24
Peak memory 200116 kb
Host smart-524fb134-6ec8-4048-9b45-82ac05dcee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057585370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1057585370
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2916773096
Short name T21
Test name
Test status
Simulation time 4166797330 ps
CPU time 7.05 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:19:33 PM PDT 24
Peak memory 196684 kb
Host smart-ab2a532e-5447-4c5d-9227-700bb6d49c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916773096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2916773096
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1465922090
Short name T387
Test name
Test status
Simulation time 494076313 ps
CPU time 1.17 seconds
Started Jul 21 07:17:10 PM PDT 24
Finished Jul 21 07:19:22 PM PDT 24
Peak memory 198748 kb
Host smart-e5f1e157-dc00-4471-b5de-70b766e298ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465922090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1465922090
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.837981271
Short name T1155
Test name
Test status
Simulation time 103456093192 ps
CPU time 428.23 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:26:34 PM PDT 24
Peak memory 208356 kb
Host smart-2503e306-ad3f-4cc4-9c5a-66acaba67615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837981271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.837981271
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2024216059
Short name T740
Test name
Test status
Simulation time 92837237063 ps
CPU time 802.13 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:32:23 PM PDT 24
Peak memory 225000 kb
Host smart-e2887848-fb3f-49a1-9e79-cf3a076bc66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024216059 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2024216059
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2612068797
Short name T436
Test name
Test status
Simulation time 1835220887 ps
CPU time 1.98 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:19:03 PM PDT 24
Peak memory 198904 kb
Host smart-0a77eec3-4a7d-491e-ade4-34d28809e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612068797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2612068797
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.36427017
Short name T318
Test name
Test status
Simulation time 128220568441 ps
CPU time 52.96 seconds
Started Jul 21 07:17:11 PM PDT 24
Finished Jul 21 07:20:15 PM PDT 24
Peak memory 200176 kb
Host smart-25b7eae1-7ec0-4af8-acac-269d7945857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36427017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.36427017
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3190810082
Short name T385
Test name
Test status
Simulation time 40525573 ps
CPU time 0.56 seconds
Started Jul 21 07:17:22 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 195836 kb
Host smart-6fe2e547-9584-4b96-974d-68d9dd46b95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190810082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3190810082
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1090434866
Short name T706
Test name
Test status
Simulation time 138267502445 ps
CPU time 187.73 seconds
Started Jul 21 07:17:15 PM PDT 24
Finished Jul 21 07:22:43 PM PDT 24
Peak memory 200180 kb
Host smart-25441e9c-cde4-4134-aa3c-2ea41fa48034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090434866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1090434866
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.136062740
Short name T1079
Test name
Test status
Simulation time 44492711461 ps
CPU time 68.67 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:20:35 PM PDT 24
Peak memory 200136 kb
Host smart-73515c7e-cc3e-4f1d-8f73-06af85ccae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136062740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.136062740
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2541526943
Short name T608
Test name
Test status
Simulation time 40039461405 ps
CPU time 17.48 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:19:54 PM PDT 24
Peak memory 200156 kb
Host smart-b62d990b-d781-464d-9b04-18ffccb35387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541526943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2541526943
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3943246075
Short name T520
Test name
Test status
Simulation time 59132677425 ps
CPU time 271.86 seconds
Started Jul 21 07:17:20 PM PDT 24
Finished Jul 21 07:23:57 PM PDT 24
Peak memory 200144 kb
Host smart-743a7523-923a-4dd9-a8de-3e8b79d44aa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943246075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3943246075
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.515465354
Short name T538
Test name
Test status
Simulation time 11123675542 ps
CPU time 6.31 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:19:32 PM PDT 24
Peak memory 199696 kb
Host smart-11aa1e2b-993d-4124-99e2-b9563201a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515465354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.515465354
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.998291801
Short name T43
Test name
Test status
Simulation time 7053299582 ps
CPU time 59.99 seconds
Started Jul 21 07:17:17 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 199332 kb
Host smart-398864cd-d2ea-4da7-b1f6-e58a90dc3e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998291801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.998291801
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4201977583
Short name T997
Test name
Test status
Simulation time 1732331287 ps
CPU time 3.05 seconds
Started Jul 21 07:17:18 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 195640 kb
Host smart-2050fb21-8840-470f-b3c8-75f53757904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201977583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4201977583
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4233523396
Short name T297
Test name
Test status
Simulation time 737010347 ps
CPU time 1.98 seconds
Started Jul 21 07:17:16 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 199952 kb
Host smart-104ffa05-4e08-44f8-8fc7-0de55b196999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233523396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4233523396
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2235421661
Short name T809
Test name
Test status
Simulation time 1010447045548 ps
CPU time 286.41 seconds
Started Jul 21 07:17:22 PM PDT 24
Finished Jul 21 07:24:16 PM PDT 24
Peak memory 200168 kb
Host smart-f1983639-1b1a-4641-ab19-aef33a7238f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235421661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2235421661
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1752324214
Short name T580
Test name
Test status
Simulation time 280221062159 ps
CPU time 470.49 seconds
Started Jul 21 07:17:20 PM PDT 24
Finished Jul 21 07:27:15 PM PDT 24
Peak memory 212244 kb
Host smart-8d1f3f73-4836-441d-87fb-00ae3f2d46ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752324214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1752324214
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.967653628
Short name T476
Test name
Test status
Simulation time 6420546009 ps
CPU time 17.74 seconds
Started Jul 21 07:17:15 PM PDT 24
Finished Jul 21 07:19:48 PM PDT 24
Peak memory 200052 kb
Host smart-61647091-c0fc-4483-8303-147cce83f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967653628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.967653628
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2750373697
Short name T521
Test name
Test status
Simulation time 323722847633 ps
CPU time 42.12 seconds
Started Jul 21 07:17:17 PM PDT 24
Finished Jul 21 07:20:08 PM PDT 24
Peak memory 200008 kb
Host smart-1838c039-980c-4001-b4f5-8406ebaf8b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750373697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2750373697
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.777358468
Short name T360
Test name
Test status
Simulation time 12306813 ps
CPU time 0.56 seconds
Started Jul 21 07:17:35 PM PDT 24
Finished Jul 21 07:19:37 PM PDT 24
Peak memory 195832 kb
Host smart-d9def26d-3288-4542-9695-5a7f037d49fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777358468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.777358468
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2465201536
Short name T819
Test name
Test status
Simulation time 102075681857 ps
CPU time 11.61 seconds
Started Jul 21 07:17:21 PM PDT 24
Finished Jul 21 07:19:42 PM PDT 24
Peak memory 200192 kb
Host smart-2a9a8558-8a3f-46d9-b54a-64a2faafd9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465201536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2465201536
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_intr.1249480060
Short name T309
Test name
Test status
Simulation time 45798185577 ps
CPU time 36.26 seconds
Started Jul 21 07:17:36 PM PDT 24
Finished Jul 21 07:20:13 PM PDT 24
Peak memory 200044 kb
Host smart-a4adc883-d522-46e1-8bc8-007584740ed8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249480060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1249480060
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1571152602
Short name T290
Test name
Test status
Simulation time 142805483010 ps
CPU time 1360.85 seconds
Started Jul 21 07:17:35 PM PDT 24
Finished Jul 21 07:42:10 PM PDT 24
Peak memory 200120 kb
Host smart-4940a78d-bf00-45a8-aae7-9b30608d347f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571152602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1571152602
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2189182791
Short name T366
Test name
Test status
Simulation time 10552117075 ps
CPU time 8.16 seconds
Started Jul 21 07:17:34 PM PDT 24
Finished Jul 21 07:19:37 PM PDT 24
Peak memory 199960 kb
Host smart-ba94c43c-02f2-4238-b5c3-26a00449cd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189182791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2189182791
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3825254687
Short name T668
Test name
Test status
Simulation time 168677048890 ps
CPU time 124.65 seconds
Started Jul 21 07:17:34 PM PDT 24
Finished Jul 21 07:21:25 PM PDT 24
Peak memory 200040 kb
Host smart-518173f7-d0bf-4698-acb2-59284e31b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825254687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3825254687
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2747014371
Short name T1015
Test name
Test status
Simulation time 31482201498 ps
CPU time 239.12 seconds
Started Jul 21 07:17:34 PM PDT 24
Finished Jul 21 07:23:19 PM PDT 24
Peak memory 200148 kb
Host smart-a7c26678-81da-4532-a340-d7e8573f19c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747014371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2747014371
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3503890498
Short name T821
Test name
Test status
Simulation time 3480564136 ps
CPU time 26.53 seconds
Started Jul 21 07:17:25 PM PDT 24
Finished Jul 21 07:19:57 PM PDT 24
Peak memory 198188 kb
Host smart-68d51661-5ca3-43a2-9677-bb41335648ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503890498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3503890498
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2026955926
Short name T702
Test name
Test status
Simulation time 260086026047 ps
CPU time 367.92 seconds
Started Jul 21 07:17:36 PM PDT 24
Finished Jul 21 07:25:45 PM PDT 24
Peak memory 200052 kb
Host smart-4b9048b0-cd31-4737-8192-b210a36ab402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026955926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2026955926
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3613181770
Short name T915
Test name
Test status
Simulation time 36448377208 ps
CPU time 52.82 seconds
Started Jul 21 07:17:33 PM PDT 24
Finished Jul 21 07:20:22 PM PDT 24
Peak memory 196140 kb
Host smart-2c041424-6b41-4ba1-bcd7-62fe9034380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613181770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3613181770
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1117764209
Short name T256
Test name
Test status
Simulation time 671931914 ps
CPU time 4.05 seconds
Started Jul 21 07:17:20 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 198588 kb
Host smart-ed2b579d-39c7-4860-afdc-7592885435c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117764209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1117764209
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1514594466
Short name T564
Test name
Test status
Simulation time 131802853261 ps
CPU time 233.67 seconds
Started Jul 21 07:17:39 PM PDT 24
Finished Jul 21 07:23:23 PM PDT 24
Peak memory 216696 kb
Host smart-53c11718-d7ab-41f7-8be1-0b0c39ad8293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514594466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1514594466
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4063509916
Short name T405
Test name
Test status
Simulation time 6693042335 ps
CPU time 18.42 seconds
Started Jul 21 07:17:35 PM PDT 24
Finished Jul 21 07:19:55 PM PDT 24
Peak memory 199364 kb
Host smart-deb07990-acaa-4f85-9d89-bfd4ef4b2289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063509916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4063509916
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_alert_test.1981602023
Short name T695
Test name
Test status
Simulation time 11732609 ps
CPU time 0.55 seconds
Started Jul 21 07:17:54 PM PDT 24
Finished Jul 21 07:19:45 PM PDT 24
Peak memory 195580 kb
Host smart-cf117342-494b-4241-94a8-a4dfd5c5c9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981602023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1981602023
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.548401848
Short name T139
Test name
Test status
Simulation time 132004949514 ps
CPU time 57.71 seconds
Started Jul 21 07:17:38 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 200128 kb
Host smart-c48dfdeb-6704-4023-b01f-98a3d89ebca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548401848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.548401848
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2788256936
Short name T989
Test name
Test status
Simulation time 19406111556 ps
CPU time 8.97 seconds
Started Jul 21 07:17:38 PM PDT 24
Finished Jul 21 07:19:38 PM PDT 24
Peak memory 200176 kb
Host smart-d59cfb2d-f4bc-47e4-b49d-b46bb8b66db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788256936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2788256936
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2080342253
Short name T1138
Test name
Test status
Simulation time 71197572722 ps
CPU time 32.24 seconds
Started Jul 21 07:17:37 PM PDT 24
Finished Jul 21 07:20:09 PM PDT 24
Peak memory 200128 kb
Host smart-7eeb822b-a60d-4a7d-a39e-1da7181f6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080342253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2080342253
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2622998114
Short name T118
Test name
Test status
Simulation time 258794329939 ps
CPU time 90.17 seconds
Started Jul 21 07:17:44 PM PDT 24
Finished Jul 21 07:21:07 PM PDT 24
Peak memory 198764 kb
Host smart-6d0026eb-8e17-4046-8fd5-e79202ff57da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622998114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2622998114
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_loopback.2405544394
Short name T799
Test name
Test status
Simulation time 12141460644 ps
CPU time 24.68 seconds
Started Jul 21 07:17:47 PM PDT 24
Finished Jul 21 07:19:56 PM PDT 24
Peak memory 200204 kb
Host smart-b331774f-4abc-48ec-be47-f31bd5ff3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405544394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2405544394
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3034862754
Short name T372
Test name
Test status
Simulation time 47362685307 ps
CPU time 20.62 seconds
Started Jul 21 07:17:44 PM PDT 24
Finished Jul 21 07:19:57 PM PDT 24
Peak memory 200204 kb
Host smart-91c05766-7012-41c9-b2bd-bc0587b4794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034862754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3034862754
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3359511806
Short name T561
Test name
Test status
Simulation time 24390239265 ps
CPU time 75.46 seconds
Started Jul 21 07:17:54 PM PDT 24
Finished Jul 21 07:20:58 PM PDT 24
Peak memory 200180 kb
Host smart-0dc6f179-896a-49a2-850a-310a573e0f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359511806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3359511806
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1085830301
Short name T636
Test name
Test status
Simulation time 1953677768 ps
CPU time 1.77 seconds
Started Jul 21 07:17:44 PM PDT 24
Finished Jul 21 07:19:39 PM PDT 24
Peak memory 199532 kb
Host smart-fc45c2b9-b823-4683-bbae-c4bb09126099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085830301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1085830301
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1516102336
Short name T537
Test name
Test status
Simulation time 101773762651 ps
CPU time 25.02 seconds
Started Jul 21 07:17:44 PM PDT 24
Finished Jul 21 07:20:02 PM PDT 24
Peak memory 200196 kb
Host smart-cb46115c-0408-438f-9b06-8c578d3d1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516102336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1516102336
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.251143587
Short name T751
Test name
Test status
Simulation time 3347554979 ps
CPU time 1.74 seconds
Started Jul 21 07:17:43 PM PDT 24
Finished Jul 21 07:19:39 PM PDT 24
Peak memory 197052 kb
Host smart-837b9106-5a02-4ce6-820b-b61519a6cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251143587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.251143587
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2991117926
Short name T365
Test name
Test status
Simulation time 603918895 ps
CPU time 2.29 seconds
Started Jul 21 07:17:32 PM PDT 24
Finished Jul 21 07:19:31 PM PDT 24
Peak memory 200188 kb
Host smart-b987c17b-8159-41ed-8619-ede0b0a5a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991117926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2991117926
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3258325290
Short name T386
Test name
Test status
Simulation time 288041214799 ps
CPU time 2074.27 seconds
Started Jul 21 07:17:53 PM PDT 24
Finished Jul 21 07:54:18 PM PDT 24
Peak memory 208460 kb
Host smart-4aedd664-67cc-45ef-a926-e4d49b2c7b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258325290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3258325290
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2267679469
Short name T215
Test name
Test status
Simulation time 700677033004 ps
CPU time 788.14 seconds
Started Jul 21 07:17:54 PM PDT 24
Finished Jul 21 07:32:51 PM PDT 24
Peak memory 216672 kb
Host smart-92796e20-c976-4483-b3fa-25c6802ddd60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267679469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2267679469
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2705603948
Short name T873
Test name
Test status
Simulation time 5955557449 ps
CPU time 1.82 seconds
Started Jul 21 07:17:54 PM PDT 24
Finished Jul 21 07:19:45 PM PDT 24
Peak memory 199228 kb
Host smart-8b0b6b08-9aaa-47d3-85a3-d316bfbe4532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705603948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2705603948
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.320854407
Short name T772
Test name
Test status
Simulation time 61943546647 ps
CPU time 23.42 seconds
Started Jul 21 07:17:38 PM PDT 24
Finished Jul 21 07:19:52 PM PDT 24
Peak memory 200192 kb
Host smart-9b460c64-ff7b-47b5-b418-df7ac62651de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320854407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.320854407
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3571046057
Short name T559
Test name
Test status
Simulation time 18099401 ps
CPU time 0.56 seconds
Started Jul 21 07:12:53 PM PDT 24
Finished Jul 21 07:12:54 PM PDT 24
Peak memory 194828 kb
Host smart-aa71524c-29bc-4b4f-ae5f-06793a189ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571046057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3571046057
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2770820467
Short name T133
Test name
Test status
Simulation time 31681603194 ps
CPU time 34.32 seconds
Started Jul 21 07:12:43 PM PDT 24
Finished Jul 21 07:13:23 PM PDT 24
Peak memory 200128 kb
Host smart-c4f8dfad-6cfe-4ece-845c-7bc9b888de6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770820467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2770820467
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.474425027
Short name T143
Test name
Test status
Simulation time 21266873484 ps
CPU time 29.78 seconds
Started Jul 21 07:12:45 PM PDT 24
Finished Jul 21 07:13:19 PM PDT 24
Peak memory 199800 kb
Host smart-911a659f-405d-438a-808a-75e96afb5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474425027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.474425027
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2572910084
Short name T880
Test name
Test status
Simulation time 22953952108 ps
CPU time 37.64 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:13:30 PM PDT 24
Peak memory 200148 kb
Host smart-ed95281b-8ceb-4780-b6b5-3d34fc9325f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572910084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2572910084
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1570486678
Short name T283
Test name
Test status
Simulation time 48390377729 ps
CPU time 75.75 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:14:08 PM PDT 24
Peak memory 200152 kb
Host smart-009cbb17-b93c-4b60-9546-760dfaa6e4f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570486678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1570486678
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2995445572
Short name T1130
Test name
Test status
Simulation time 121406514346 ps
CPU time 1277.8 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:34:11 PM PDT 24
Peak memory 200200 kb
Host smart-5ae35992-3405-4305-a6e7-a67e108b6cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995445572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2995445572
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3189466196
Short name T1062
Test name
Test status
Simulation time 29296122 ps
CPU time 0.59 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:12:54 PM PDT 24
Peak memory 195916 kb
Host smart-0bac129a-237f-4c9f-9bcb-921d44375dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189466196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3189466196
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2543639207
Short name T428
Test name
Test status
Simulation time 88409893038 ps
CPU time 130.22 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:15:03 PM PDT 24
Peak memory 200204 kb
Host smart-590021ca-1811-4a21-83b5-f131c6c871b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543639207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2543639207
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3644783912
Short name T670
Test name
Test status
Simulation time 8196889325 ps
CPU time 44.35 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:13:37 PM PDT 24
Peak memory 200196 kb
Host smart-7f36225c-6d97-4785-a614-ffd1ff2afbc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644783912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3644783912
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.561848940
Short name T450
Test name
Test status
Simulation time 4413625275 ps
CPU time 30.07 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:13:22 PM PDT 24
Peak memory 200092 kb
Host smart-e4fd7aa1-d815-4a52-86a4-2a398e0396de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561848940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.561848940
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3615292351
Short name T715
Test name
Test status
Simulation time 110258885337 ps
CPU time 60.01 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:13:53 PM PDT 24
Peak memory 200152 kb
Host smart-cc5540ae-f37c-4e0b-a366-7474fab09461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615292351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3615292351
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.556663846
Short name T289
Test name
Test status
Simulation time 5257539097 ps
CPU time 4.04 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:12:57 PM PDT 24
Peak memory 196632 kb
Host smart-253fd47b-9629-4276-8298-52e0eed04df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556663846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.556663846
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1573300857
Short name T1011
Test name
Test status
Simulation time 5290728163 ps
CPU time 8.04 seconds
Started Jul 21 07:12:45 PM PDT 24
Finished Jul 21 07:12:57 PM PDT 24
Peak memory 200132 kb
Host smart-38844c1a-49f5-4fde-bf55-856fa4b27a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573300857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1573300857
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3317391626
Short name T136
Test name
Test status
Simulation time 397940169178 ps
CPU time 704.62 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:24:38 PM PDT 24
Peak memory 208472 kb
Host smart-22b86cd6-7376-4492-95ec-361a309720a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317391626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3317391626
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4201366727
Short name T61
Test name
Test status
Simulation time 308641937210 ps
CPU time 797.6 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:26:10 PM PDT 24
Peak memory 225064 kb
Host smart-b11194d8-ab6b-40d0-b9ee-d79dd9e02dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201366727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4201366727
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1090038253
Short name T1120
Test name
Test status
Simulation time 1155750676 ps
CPU time 1.6 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:12:53 PM PDT 24
Peak memory 199584 kb
Host smart-844f628d-67ce-410f-ba29-b8fedea758a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090038253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1090038253
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1233441361
Short name T317
Test name
Test status
Simulation time 35746751331 ps
CPU time 49.75 seconds
Started Jul 21 07:12:52 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 200188 kb
Host smart-cc9eeeb2-a79b-4d6a-ac3a-f70038260727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233441361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1233441361
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2033027251
Short name T1078
Test name
Test status
Simulation time 102786922314 ps
CPU time 131.69 seconds
Started Jul 21 07:17:48 PM PDT 24
Finished Jul 21 07:21:43 PM PDT 24
Peak memory 200196 kb
Host smart-e13f5d64-dd13-49cc-b3bc-362a11172970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033027251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2033027251
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1329710356
Short name T1141
Test name
Test status
Simulation time 74505055899 ps
CPU time 175.39 seconds
Started Jul 21 07:17:55 PM PDT 24
Finished Jul 21 07:22:28 PM PDT 24
Peak memory 200196 kb
Host smart-d3805a5f-e548-4b6d-9675-667d276c18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329710356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1329710356
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.34101015
Short name T1066
Test name
Test status
Simulation time 51214376879 ps
CPU time 20.59 seconds
Started Jul 21 07:17:55 PM PDT 24
Finished Jul 21 07:20:05 PM PDT 24
Peak memory 200116 kb
Host smart-7c76272a-018b-4f01-a910-081554bb76b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34101015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.34101015
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3330920968
Short name T676
Test name
Test status
Simulation time 178544082271 ps
CPU time 503.98 seconds
Started Jul 21 07:18:07 PM PDT 24
Finished Jul 21 07:28:05 PM PDT 24
Peak memory 225060 kb
Host smart-d97f6d59-98bb-4bce-bf35-d15f8c25744b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330920968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3330920968
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.254698693
Short name T104
Test name
Test status
Simulation time 74578323439 ps
CPU time 463.05 seconds
Started Jul 21 07:18:08 PM PDT 24
Finished Jul 21 07:27:27 PM PDT 24
Peak memory 216856 kb
Host smart-e23a94ad-b240-4605-95d0-6f9c4861462c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254698693 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.254698693
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3955324360
Short name T1150
Test name
Test status
Simulation time 47841405209 ps
CPU time 23.89 seconds
Started Jul 21 07:18:07 PM PDT 24
Finished Jul 21 07:20:08 PM PDT 24
Peak memory 200216 kb
Host smart-80784db7-a8f5-4f01-bac3-99c98770b4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955324360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3955324360
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.588227062
Short name T279
Test name
Test status
Simulation time 113275342412 ps
CPU time 266.05 seconds
Started Jul 21 07:18:08 PM PDT 24
Finished Jul 21 07:24:10 PM PDT 24
Peak memory 215072 kb
Host smart-f3ecb5d1-1425-4e35-aacc-f1ee701a1449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588227062 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.588227062
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3842975208
Short name T545
Test name
Test status
Simulation time 55801836606 ps
CPU time 554.19 seconds
Started Jul 21 07:18:09 PM PDT 24
Finished Jul 21 07:29:00 PM PDT 24
Peak memory 216784 kb
Host smart-d901beca-0f4a-4907-9b49-6fa6590c5cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842975208 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3842975208
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3640646865
Short name T838
Test name
Test status
Simulation time 29332616567 ps
CPU time 56.76 seconds
Started Jul 21 07:18:08 PM PDT 24
Finished Jul 21 07:20:39 PM PDT 24
Peak memory 200208 kb
Host smart-65afb652-5a3d-4844-af9d-bcc717de1d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640646865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3640646865
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1651195875
Short name T18
Test name
Test status
Simulation time 74458510228 ps
CPU time 773.85 seconds
Started Jul 21 07:18:09 PM PDT 24
Finished Jul 21 07:32:40 PM PDT 24
Peak memory 216720 kb
Host smart-77865495-7c62-46b2-b900-7d05140b4804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651195875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1651195875
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.284795920
Short name T1051
Test name
Test status
Simulation time 105786729250 ps
CPU time 173.14 seconds
Started Jul 21 07:18:08 PM PDT 24
Finished Jul 21 07:22:37 PM PDT 24
Peak memory 200196 kb
Host smart-5b2af266-ac6a-47de-906b-5f9787ec682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284795920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.284795920
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3090681307
Short name T60
Test name
Test status
Simulation time 255184678189 ps
CPU time 1418.54 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:43:25 PM PDT 24
Peak memory 225052 kb
Host smart-79931864-ac63-4d95-9653-51abf51c8101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090681307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3090681307
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.649451074
Short name T31
Test name
Test status
Simulation time 14456280694 ps
CPU time 202.7 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:23:07 PM PDT 24
Peak memory 215824 kb
Host smart-5d73dfed-adc0-445a-bd87-63dba2e3f897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649451074 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.649451074
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3824337340
Short name T762
Test name
Test status
Simulation time 35789793827 ps
CPU time 63.5 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:20:48 PM PDT 24
Peak memory 200144 kb
Host smart-a58a1122-c61e-4692-bfb3-629e473bfb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824337340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3824337340
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.172130198
Short name T951
Test name
Test status
Simulation time 32689314907 ps
CPU time 167.52 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:22:32 PM PDT 24
Peak memory 216836 kb
Host smart-d6254f14-20d4-4e62-acac-362df8a2f0ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172130198 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.172130198
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3398599600
Short name T434
Test name
Test status
Simulation time 12859531 ps
CPU time 0.56 seconds
Started Jul 21 07:12:56 PM PDT 24
Finished Jul 21 07:12:57 PM PDT 24
Peak memory 195584 kb
Host smart-51a1b020-2565-4dca-9420-b8a74f8d7d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398599600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3398599600
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2947024206
Short name T617
Test name
Test status
Simulation time 39143988327 ps
CPU time 10.27 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:13:03 PM PDT 24
Peak memory 200132 kb
Host smart-61438713-80c5-4ba0-8c4f-ebd63e0d714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947024206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2947024206
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1404716835
Short name T988
Test name
Test status
Simulation time 23222285704 ps
CPU time 13.53 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:13:06 PM PDT 24
Peak memory 199096 kb
Host smart-d976dff2-175f-4ea1-8476-c6295962d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404716835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1404716835
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1727907015
Short name T836
Test name
Test status
Simulation time 200951945294 ps
CPU time 278.07 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:17:31 PM PDT 24
Peak memory 200080 kb
Host smart-e8b11969-3290-4bfb-ad81-208f0eabb8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727907015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1727907015
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1551369668
Short name T484
Test name
Test status
Simulation time 15261742006 ps
CPU time 13.87 seconds
Started Jul 21 07:12:49 PM PDT 24
Finished Jul 21 07:13:06 PM PDT 24
Peak memory 199248 kb
Host smart-9bed7d71-3caa-45b1-a1a7-01419dd54e03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551369668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1551369668
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2400136451
Short name T1021
Test name
Test status
Simulation time 131826329060 ps
CPU time 277.33 seconds
Started Jul 21 07:12:57 PM PDT 24
Finished Jul 21 07:17:35 PM PDT 24
Peak memory 200124 kb
Host smart-9f6cd2ca-9495-40a0-900d-af89e679fe0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400136451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2400136451
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.924246981
Short name T556
Test name
Test status
Simulation time 3679044958 ps
CPU time 4.24 seconds
Started Jul 21 07:12:53 PM PDT 24
Finished Jul 21 07:12:58 PM PDT 24
Peak memory 198872 kb
Host smart-759490b9-2455-4406-8339-5cdde2f14228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924246981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.924246981
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3791575847
Short name T424
Test name
Test status
Simulation time 231089306968 ps
CPU time 70.92 seconds
Started Jul 21 07:12:53 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 208600 kb
Host smart-9fafe83a-fb64-457c-bf2d-31181966d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791575847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3791575847
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3030560826
Short name T614
Test name
Test status
Simulation time 20102729127 ps
CPU time 466.01 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:20:47 PM PDT 24
Peak memory 199352 kb
Host smart-6fa5b019-82a5-4cd5-8cb5-c5c9274c1d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030560826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3030560826
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3131768496
Short name T333
Test name
Test status
Simulation time 2970228703 ps
CPU time 3.25 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:12:56 PM PDT 24
Peak memory 199316 kb
Host smart-c8a4c831-f8a6-42eb-a23f-76da9b082468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131768496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3131768496
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.895528433
Short name T111
Test name
Test status
Simulation time 78368733770 ps
CPU time 34.94 seconds
Started Jul 21 07:12:59 PM PDT 24
Finished Jul 21 07:13:34 PM PDT 24
Peak memory 199968 kb
Host smart-e9ea0fdb-b248-4c8c-a9ad-2d7e08738d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895528433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.895528433
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2889716906
Short name T811
Test name
Test status
Simulation time 36253321033 ps
CPU time 36.6 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:13:32 PM PDT 24
Peak memory 196256 kb
Host smart-44e48a60-fcc0-47de-a0a6-1445866c2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889716906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2889716906
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2925515845
Short name T848
Test name
Test status
Simulation time 5716998478 ps
CPU time 8.13 seconds
Started Jul 21 07:12:51 PM PDT 24
Finished Jul 21 07:13:01 PM PDT 24
Peak memory 200032 kb
Host smart-fa9f56f4-f5bb-490f-a8e7-7d058790832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925515845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2925515845
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.40768499
Short name T784
Test name
Test status
Simulation time 345096914331 ps
CPU time 209.65 seconds
Started Jul 21 07:12:58 PM PDT 24
Finished Jul 21 07:16:28 PM PDT 24
Peak memory 200176 kb
Host smart-582c7640-cc51-4fc9-82c2-459621d81cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40768499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.40768499
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2653220787
Short name T606
Test name
Test status
Simulation time 284474792111 ps
CPU time 667.99 seconds
Started Jul 21 07:12:56 PM PDT 24
Finished Jul 21 07:24:04 PM PDT 24
Peak memory 227584 kb
Host smart-b5e84495-cee3-45cb-9ebb-d4b14be89f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653220787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2653220787
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.174984904
Short name T993
Test name
Test status
Simulation time 2514855579 ps
CPU time 2.44 seconds
Started Jul 21 07:12:58 PM PDT 24
Finished Jul 21 07:13:00 PM PDT 24
Peak memory 198756 kb
Host smart-623385bc-26ce-4652-8b1e-523bdc0ee2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174984904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.174984904
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2315988857
Short name T1124
Test name
Test status
Simulation time 56216813031 ps
CPU time 34.26 seconds
Started Jul 21 07:12:50 PM PDT 24
Finished Jul 21 07:13:27 PM PDT 24
Peak memory 200124 kb
Host smart-d60c5cbc-78f6-4ea7-ae78-2de7a8bd7b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315988857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2315988857
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.482146163
Short name T583
Test name
Test status
Simulation time 24240609564 ps
CPU time 49.48 seconds
Started Jul 21 07:18:10 PM PDT 24
Finished Jul 21 07:20:34 PM PDT 24
Peak memory 200108 kb
Host smart-2d79284f-2f41-4270-8c86-e31e2a52af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482146163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.482146163
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.644595362
Short name T311
Test name
Test status
Simulation time 120469976633 ps
CPU time 385.26 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:26:09 PM PDT 24
Peak memory 216648 kb
Host smart-a3427cd1-bc9e-464d-80f3-f26916e7d4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644595362 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.644595362
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3967948176
Short name T74
Test name
Test status
Simulation time 71326364288 ps
CPU time 131.32 seconds
Started Jul 21 07:18:10 PM PDT 24
Finished Jul 21 07:21:55 PM PDT 24
Peak memory 200184 kb
Host smart-b06b7648-9b31-46d7-baab-2f0b44845b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967948176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3967948176
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1210513579
Short name T418
Test name
Test status
Simulation time 129483464200 ps
CPU time 489.87 seconds
Started Jul 21 07:18:10 PM PDT 24
Finished Jul 21 07:27:54 PM PDT 24
Peak memory 227020 kb
Host smart-bc578a3b-f37e-4c79-bb0d-b6db6135ac3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210513579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1210513579
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2270288160
Short name T407
Test name
Test status
Simulation time 38211790553 ps
CPU time 17.26 seconds
Started Jul 21 07:18:10 PM PDT 24
Finished Jul 21 07:20:01 PM PDT 24
Peak memory 200200 kb
Host smart-d13b7875-dfb3-438c-a3d7-409bb63016af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270288160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2270288160
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.48783521
Short name T568
Test name
Test status
Simulation time 126870388679 ps
CPU time 517.63 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:28:21 PM PDT 24
Peak memory 216632 kb
Host smart-784fd8de-4c4d-469f-8931-98bbdaa6bd69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48783521 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.48783521
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3969888561
Short name T202
Test name
Test status
Simulation time 94546857715 ps
CPU time 108.95 seconds
Started Jul 21 07:18:11 PM PDT 24
Finished Jul 21 07:21:33 PM PDT 24
Peak memory 200188 kb
Host smart-e581667e-921f-4a63-b742-2ae6f4671d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969888561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3969888561
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.631587961
Short name T835
Test name
Test status
Simulation time 672071242365 ps
CPU time 719.69 seconds
Started Jul 21 07:18:18 PM PDT 24
Finished Jul 21 07:31:44 PM PDT 24
Peak memory 224984 kb
Host smart-4a951e7d-fa4d-425d-99bf-c139429db312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631587961 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.631587961
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3383947641
Short name T523
Test name
Test status
Simulation time 146877741502 ps
CPU time 52.22 seconds
Started Jul 21 07:18:19 PM PDT 24
Finished Jul 21 07:20:38 PM PDT 24
Peak memory 200104 kb
Host smart-62315949-9a02-4add-9395-81b14e3b58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383947641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3383947641
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4272822955
Short name T621
Test name
Test status
Simulation time 51777363303 ps
CPU time 203.37 seconds
Started Jul 21 07:18:19 PM PDT 24
Finished Jul 21 07:23:09 PM PDT 24
Peak memory 215848 kb
Host smart-c4ccfeab-a5e3-4a6e-9037-33a840d4b32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272822955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4272822955
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2464148962
Short name T1014
Test name
Test status
Simulation time 32857566493 ps
CPU time 350.89 seconds
Started Jul 21 07:18:21 PM PDT 24
Finished Jul 21 07:25:35 PM PDT 24
Peak memory 216656 kb
Host smart-2a633012-dadb-4b9c-a738-35f4db7c16f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464148962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2464148962
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1195911850
Short name T1070
Test name
Test status
Simulation time 61812104307 ps
CPU time 69.74 seconds
Started Jul 21 07:18:22 PM PDT 24
Finished Jul 21 07:20:54 PM PDT 24
Peak memory 200180 kb
Host smart-2152a833-f07b-4d2c-8e86-25e04649314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195911850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1195911850
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1315260628
Short name T406
Test name
Test status
Simulation time 57341829813 ps
CPU time 746.05 seconds
Started Jul 21 07:18:22 PM PDT 24
Finished Jul 21 07:32:10 PM PDT 24
Peak memory 216640 kb
Host smart-fee062e3-ffde-41f9-ab09-028f4561620f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315260628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1315260628
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.57752316
Short name T817
Test name
Test status
Simulation time 77598962554 ps
CPU time 33.46 seconds
Started Jul 21 07:18:22 PM PDT 24
Finished Jul 21 07:20:18 PM PDT 24
Peak memory 200104 kb
Host smart-95bc5e2b-9dc6-4f4f-b183-8e9032e718e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57752316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.57752316
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1906087566
Short name T57
Test name
Test status
Simulation time 130876661774 ps
CPU time 958.1 seconds
Started Jul 21 07:18:20 PM PDT 24
Finished Jul 21 07:35:42 PM PDT 24
Peak memory 225144 kb
Host smart-ee71803a-ddea-474b-a67b-dc8a0b60055f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906087566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1906087566
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1265760577
Short name T655
Test name
Test status
Simulation time 31920157606 ps
CPU time 31.97 seconds
Started Jul 21 07:18:27 PM PDT 24
Finished Jul 21 07:20:16 PM PDT 24
Peak memory 200036 kb
Host smart-c66dea51-90b2-487d-8e7c-d99d92c54eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265760577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1265760577
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4155324959
Short name T1097
Test name
Test status
Simulation time 101831529227 ps
CPU time 1292.05 seconds
Started Jul 21 07:18:32 PM PDT 24
Finished Jul 21 07:41:18 PM PDT 24
Peak memory 226568 kb
Host smart-79cdb1eb-0653-4bad-aa2a-1726ccd80e17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155324959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4155324959
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2393872359
Short name T1105
Test name
Test status
Simulation time 48117017 ps
CPU time 0.53 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:12:56 PM PDT 24
Peak memory 195568 kb
Host smart-338d3ff8-285d-4351-ac9d-57ad518b4cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393872359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2393872359
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3653991745
Short name T1122
Test name
Test status
Simulation time 36655768765 ps
CPU time 32.6 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:13:28 PM PDT 24
Peak memory 200172 kb
Host smart-c84a2c3a-0c4e-4048-9a6f-0ac2bd08d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653991745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3653991745
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1345637629
Short name T541
Test name
Test status
Simulation time 170179933871 ps
CPU time 32.09 seconds
Started Jul 21 07:12:56 PM PDT 24
Finished Jul 21 07:13:28 PM PDT 24
Peak memory 200236 kb
Host smart-17147d74-8c93-461a-af6a-6c042e9ba8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345637629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1345637629
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3085860766
Short name T518
Test name
Test status
Simulation time 94504078626 ps
CPU time 24.07 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:13:25 PM PDT 24
Peak memory 200192 kb
Host smart-6ea283c5-d9e7-49a0-a495-79f70f690fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085860766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3085860766
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3062886791
Short name T38
Test name
Test status
Simulation time 13489795486 ps
CPU time 21.18 seconds
Started Jul 21 07:12:54 PM PDT 24
Finished Jul 21 07:13:16 PM PDT 24
Peak memory 197960 kb
Host smart-5f30f869-a372-450d-9b62-e552fd115b2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062886791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3062886791
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.951331988
Short name T396
Test name
Test status
Simulation time 66338345750 ps
CPU time 104.36 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:14:47 PM PDT 24
Peak memory 200104 kb
Host smart-e74a4318-ef70-4d60-a99d-28fa28f11b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951331988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.951331988
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.79226706
Short name T731
Test name
Test status
Simulation time 6941829498 ps
CPU time 5.11 seconds
Started Jul 21 07:12:57 PM PDT 24
Finished Jul 21 07:13:02 PM PDT 24
Peak memory 199916 kb
Host smart-f717be9b-75d5-4ce2-95a6-6bd8b0d74857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79226706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.79226706
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.477724207
Short name T1128
Test name
Test status
Simulation time 10316319076 ps
CPU time 16.04 seconds
Started Jul 21 07:12:56 PM PDT 24
Finished Jul 21 07:13:13 PM PDT 24
Peak memory 195324 kb
Host smart-a043fa54-956b-4038-9959-986b1e3ac481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477724207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.477724207
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2967538279
Short name T788
Test name
Test status
Simulation time 4865225886 ps
CPU time 60.55 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:13:57 PM PDT 24
Peak memory 199904 kb
Host smart-6495d010-3471-4282-aa2d-0208e8f9a016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967538279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2967538279
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3490903755
Short name T326
Test name
Test status
Simulation time 6739184274 ps
CPU time 59.83 seconds
Started Jul 21 07:12:56 PM PDT 24
Finished Jul 21 07:13:56 PM PDT 24
Peak memory 198116 kb
Host smart-cd8711e4-a3ea-4014-a15b-b58330500b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490903755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3490903755
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1142692057
Short name T1055
Test name
Test status
Simulation time 9265854879 ps
CPU time 4.82 seconds
Started Jul 21 07:12:54 PM PDT 24
Finished Jul 21 07:12:59 PM PDT 24
Peak memory 198772 kb
Host smart-8fe8f7cb-71ee-4059-bb37-a30ec5495eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142692057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1142692057
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2617322943
Short name T704
Test name
Test status
Simulation time 1603442484 ps
CPU time 2.79 seconds
Started Jul 21 07:12:57 PM PDT 24
Finished Jul 21 07:13:01 PM PDT 24
Peak memory 195688 kb
Host smart-5cfe3129-1f51-486f-a83b-3725d59bb3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617322943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2617322943
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2239809034
Short name T1001
Test name
Test status
Simulation time 5789001363 ps
CPU time 7.15 seconds
Started Jul 21 07:12:54 PM PDT 24
Finished Jul 21 07:13:02 PM PDT 24
Peak memory 200052 kb
Host smart-38e4ea29-d478-4458-ac4d-c6b16b293ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239809034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2239809034
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3097028255
Short name T890
Test name
Test status
Simulation time 308316767980 ps
CPU time 923.76 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:28:19 PM PDT 24
Peak memory 200184 kb
Host smart-fef6b9cb-f769-45f4-835c-625670b0767d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097028255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3097028255
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2641170010
Short name T597
Test name
Test status
Simulation time 136946096424 ps
CPU time 422.42 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:20:03 PM PDT 24
Peak memory 216052 kb
Host smart-2bfc3855-b93a-4b7e-bd6b-fc59ae80ac8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641170010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2641170010
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.988726826
Short name T620
Test name
Test status
Simulation time 1709864890 ps
CPU time 1.6 seconds
Started Jul 21 07:12:59 PM PDT 24
Finished Jul 21 07:13:02 PM PDT 24
Peak memory 198632 kb
Host smart-f7fe2b9d-27d6-4a56-82e4-40134e3a6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988726826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.988726826
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.267539985
Short name T649
Test name
Test status
Simulation time 52628684693 ps
CPU time 48.81 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:13:49 PM PDT 24
Peak memory 200124 kb
Host smart-f233b6a7-5078-4c79-b648-5885375e1020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267539985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.267539985
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2123787100
Short name T467
Test name
Test status
Simulation time 21706698502 ps
CPU time 36.8 seconds
Started Jul 21 07:18:27 PM PDT 24
Finished Jul 21 07:20:21 PM PDT 24
Peak memory 200256 kb
Host smart-c4a64df6-63f4-4b3d-b3b0-0cb9a4da0d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123787100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2123787100
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1813013226
Short name T423
Test name
Test status
Simulation time 176959123477 ps
CPU time 26.13 seconds
Started Jul 21 07:18:27 PM PDT 24
Finished Jul 21 07:20:10 PM PDT 24
Peak memory 200200 kb
Host smart-8aaf5afc-9970-426b-9f15-e73d9596281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813013226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1813013226
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3047976072
Short name T82
Test name
Test status
Simulation time 147428498024 ps
CPU time 2864.63 seconds
Started Jul 21 07:18:27 PM PDT 24
Finished Jul 21 08:07:29 PM PDT 24
Peak memory 226416 kb
Host smart-70905fe0-c521-494f-9fc6-8f4c0b772161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047976072 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3047976072
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1013290561
Short name T601
Test name
Test status
Simulation time 31771261298 ps
CPU time 49.3 seconds
Started Jul 21 07:18:28 PM PDT 24
Finished Jul 21 07:20:33 PM PDT 24
Peak memory 200204 kb
Host smart-94fcf484-7742-48da-8b5d-30d06f4d1212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013290561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1013290561
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.480987145
Short name T59
Test name
Test status
Simulation time 167999679808 ps
CPU time 1954.77 seconds
Started Jul 21 07:18:27 PM PDT 24
Finished Jul 21 07:52:19 PM PDT 24
Peak memory 241424 kb
Host smart-f4f492ee-948b-46d2-a7dc-72450e8871f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480987145 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.480987145
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3610240894
Short name T300
Test name
Test status
Simulation time 97165117916 ps
CPU time 147.59 seconds
Started Jul 21 07:18:28 PM PDT 24
Finished Jul 21 07:22:09 PM PDT 24
Peak memory 200148 kb
Host smart-acc36cb2-3e25-496f-a7f1-dc3cf6d3204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610240894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3610240894
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.579004060
Short name T166
Test name
Test status
Simulation time 83140015945 ps
CPU time 262.4 seconds
Started Jul 21 07:18:33 PM PDT 24
Finished Jul 21 07:24:07 PM PDT 24
Peak memory 216508 kb
Host smart-b68ed104-88d9-45ae-b128-9368bf1bc98b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579004060 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.579004060
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.431055296
Short name T908
Test name
Test status
Simulation time 12738134252 ps
CPU time 26.4 seconds
Started Jul 21 07:18:31 PM PDT 24
Finished Jul 21 07:20:11 PM PDT 24
Peak memory 200164 kb
Host smart-ef605dac-ddc5-448d-a342-7c98bb4dc828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431055296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.431055296
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1193118139
Short name T576
Test name
Test status
Simulation time 209711979073 ps
CPU time 1497.98 seconds
Started Jul 21 07:18:30 PM PDT 24
Finished Jul 21 07:44:42 PM PDT 24
Peak memory 224876 kb
Host smart-3a6b19df-8218-40f3-a859-b7926c01b236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193118139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1193118139
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4282056725
Short name T319
Test name
Test status
Simulation time 76782621129 ps
CPU time 28.65 seconds
Started Jul 21 07:18:34 PM PDT 24
Finished Jul 21 07:20:13 PM PDT 24
Peak memory 198516 kb
Host smart-d26c9e40-8e72-4546-8fa7-0c1444d8a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282056725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4282056725
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3611535097
Short name T973
Test name
Test status
Simulation time 36828692071 ps
CPU time 227.67 seconds
Started Jul 21 07:18:31 PM PDT 24
Finished Jul 21 07:23:34 PM PDT 24
Peak memory 216756 kb
Host smart-45c3c81e-a6f8-47aa-b1d9-da62041e1359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611535097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3611535097
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1927347651
Short name T193
Test name
Test status
Simulation time 43175903327 ps
CPU time 71.14 seconds
Started Jul 21 07:18:31 PM PDT 24
Finished Jul 21 07:20:55 PM PDT 24
Peak memory 200236 kb
Host smart-bb255ff4-e187-4d7b-abb1-fbd2ec431640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927347651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1927347651
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1940724859
Short name T846
Test name
Test status
Simulation time 80238059770 ps
CPU time 698.48 seconds
Started Jul 21 07:18:37 PM PDT 24
Finished Jul 21 07:31:23 PM PDT 24
Peak memory 216644 kb
Host smart-174009e6-e6ec-4708-8bdf-963bfc058f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940724859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1940724859
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3738296775
Short name T794
Test name
Test status
Simulation time 41298971506 ps
CPU time 54.49 seconds
Started Jul 21 07:18:36 PM PDT 24
Finished Jul 21 07:20:37 PM PDT 24
Peak memory 200116 kb
Host smart-4497be21-dc77-4ba7-994c-7559e5b1b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738296775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3738296775
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2338319397
Short name T455
Test name
Test status
Simulation time 26003649909 ps
CPU time 48.65 seconds
Started Jul 21 07:18:37 PM PDT 24
Finished Jul 21 07:20:33 PM PDT 24
Peak memory 200084 kb
Host smart-96e85d25-63a6-415c-aa9d-ccb190ec8dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338319397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2338319397
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1034067051
Short name T29
Test name
Test status
Simulation time 46960379726 ps
CPU time 166.1 seconds
Started Jul 21 07:18:43 PM PDT 24
Finished Jul 21 07:22:30 PM PDT 24
Peak memory 208564 kb
Host smart-dc95953a-8e4f-41a2-bedc-169ec1e767dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034067051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1034067051
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.592385885
Short name T903
Test name
Test status
Simulation time 36139403 ps
CPU time 0.56 seconds
Started Jul 21 07:13:02 PM PDT 24
Finished Jul 21 07:13:03 PM PDT 24
Peak memory 195828 kb
Host smart-bfe2af67-7cc2-4d6e-b0c2-cf396f3e00a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592385885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.592385885
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1805448660
Short name T790
Test name
Test status
Simulation time 97660207574 ps
CPU time 85.6 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:14:28 PM PDT 24
Peak memory 200108 kb
Host smart-8d2c1c56-9767-45a8-8724-b883fd24bb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805448660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1805448660
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2489628912
Short name T937
Test name
Test status
Simulation time 73941792948 ps
CPU time 64.08 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:14:05 PM PDT 24
Peak memory 200136 kb
Host smart-fb163ef6-d149-47f0-b3ff-2400edb8cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489628912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2489628912
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2534211064
Short name T440
Test name
Test status
Simulation time 7362274217 ps
CPU time 4.07 seconds
Started Jul 21 07:13:03 PM PDT 24
Finished Jul 21 07:13:08 PM PDT 24
Peak memory 199856 kb
Host smart-1a23a471-ad16-4648-a9cc-53dec38de197
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534211064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2534211064
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.950344746
Short name T1129
Test name
Test status
Simulation time 78366468701 ps
CPU time 404.86 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:19:45 PM PDT 24
Peak memory 200124 kb
Host smart-ccfaa27b-5d4c-4580-845d-09b59cd65c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950344746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.950344746
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3702900124
Short name T996
Test name
Test status
Simulation time 4839120901 ps
CPU time 3.01 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:13:05 PM PDT 24
Peak memory 199392 kb
Host smart-2e1839d0-4c7b-4de4-96c5-f16712958fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702900124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3702900124
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1928417907
Short name T285
Test name
Test status
Simulation time 61332949624 ps
CPU time 117.38 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:14:58 PM PDT 24
Peak memory 200132 kb
Host smart-30d2e9db-b17d-4d42-a9c8-748acbbf7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928417907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1928417907
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3134367914
Short name T925
Test name
Test status
Simulation time 36322444205 ps
CPU time 535.26 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:21:58 PM PDT 24
Peak memory 200192 kb
Host smart-4c4cb541-7d1a-4150-b896-bbdb0f419037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134367914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3134367914
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1294422941
Short name T962
Test name
Test status
Simulation time 4089146293 ps
CPU time 2.23 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:13:04 PM PDT 24
Peak memory 199356 kb
Host smart-2c828c0c-ad84-4ba4-9e3c-dd956096425f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294422941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1294422941
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3986256433
Short name T1004
Test name
Test status
Simulation time 36860059734 ps
CPU time 17.52 seconds
Started Jul 21 07:12:59 PM PDT 24
Finished Jul 21 07:13:18 PM PDT 24
Peak memory 200084 kb
Host smart-cce364ba-77e5-4066-af8e-62fd08ba9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986256433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3986256433
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3073004034
Short name T678
Test name
Test status
Simulation time 31220991906 ps
CPU time 8.07 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:13:09 PM PDT 24
Peak memory 196292 kb
Host smart-ef2021ca-476c-4230-939f-9c7b4c262ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073004034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3073004034
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.251465187
Short name T933
Test name
Test status
Simulation time 302061273 ps
CPU time 0.94 seconds
Started Jul 21 07:12:58 PM PDT 24
Finished Jul 21 07:12:59 PM PDT 24
Peak memory 199212 kb
Host smart-f0881200-e684-4bb7-848a-0359315045df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251465187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.251465187
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1612049047
Short name T789
Test name
Test status
Simulation time 374553334908 ps
CPU time 1865.02 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:44:07 PM PDT 24
Peak memory 200160 kb
Host smart-b3baf0a4-c4fa-497b-92c5-e54867d8b401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612049047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1612049047
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3346441234
Short name T525
Test name
Test status
Simulation time 6839113809 ps
CPU time 14.9 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:13:17 PM PDT 24
Peak memory 200176 kb
Host smart-fb2ff4fc-d192-402b-b442-cf160f14d546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346441234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3346441234
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.636740963
Short name T473
Test name
Test status
Simulation time 80826542882 ps
CPU time 32.47 seconds
Started Jul 21 07:12:55 PM PDT 24
Finished Jul 21 07:13:29 PM PDT 24
Peak memory 200264 kb
Host smart-c08c77ad-7964-446a-b5f1-094da99166f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636740963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.636740963
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4236415342
Short name T4
Test name
Test status
Simulation time 91902714443 ps
CPU time 69.17 seconds
Started Jul 21 07:18:40 PM PDT 24
Finished Jul 21 07:20:53 PM PDT 24
Peak memory 200080 kb
Host smart-52d41b94-5f76-4ca1-8935-c583c29f1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236415342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4236415342
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3744451311
Short name T692
Test name
Test status
Simulation time 36707865526 ps
CPU time 341.92 seconds
Started Jul 21 07:18:41 PM PDT 24
Finished Jul 21 07:25:28 PM PDT 24
Peak memory 216596 kb
Host smart-95161738-f8f4-4f40-84dc-bb97dee385e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744451311 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3744451311
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.222880179
Short name T907
Test name
Test status
Simulation time 64368373238 ps
CPU time 42.26 seconds
Started Jul 21 07:18:42 PM PDT 24
Finished Jul 21 07:20:26 PM PDT 24
Peak memory 200172 kb
Host smart-58f757a6-56b6-4989-b75d-adce9147332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222880179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.222880179
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.388729320
Short name T1006
Test name
Test status
Simulation time 140754808994 ps
CPU time 656.09 seconds
Started Jul 21 07:18:41 PM PDT 24
Finished Jul 21 07:30:40 PM PDT 24
Peak memory 225036 kb
Host smart-6b6d7472-fadb-4995-937d-86b3d76166af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388729320 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.388729320
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1676157801
Short name T174
Test name
Test status
Simulation time 14360969329 ps
CPU time 22.28 seconds
Started Jul 21 07:18:42 PM PDT 24
Finished Jul 21 07:20:08 PM PDT 24
Peak memory 200068 kb
Host smart-6f019318-6f44-4a47-8b0e-9635b91fe888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676157801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1676157801
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1744683803
Short name T28
Test name
Test status
Simulation time 53413205411 ps
CPU time 938.42 seconds
Started Jul 21 07:18:47 PM PDT 24
Finished Jul 21 07:35:20 PM PDT 24
Peak memory 214776 kb
Host smart-3a85e63e-4970-4931-8552-437c177f9f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744683803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1744683803
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.620008856
Short name T227
Test name
Test status
Simulation time 60151345753 ps
CPU time 12.94 seconds
Started Jul 21 07:18:54 PM PDT 24
Finished Jul 21 07:19:57 PM PDT 24
Peak memory 200140 kb
Host smart-bfd23760-21aa-4225-9d00-8e48cc334a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620008856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.620008856
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1056622173
Short name T527
Test name
Test status
Simulation time 79675475499 ps
CPU time 695.87 seconds
Started Jul 21 07:18:53 PM PDT 24
Finished Jul 21 07:31:20 PM PDT 24
Peak memory 216864 kb
Host smart-8079784a-ce45-4a85-9b25-ecbae904cfc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056622173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1056622173
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2089705905
Short name T232
Test name
Test status
Simulation time 158634512120 ps
CPU time 64.89 seconds
Started Jul 21 07:18:53 PM PDT 24
Finished Jul 21 07:20:49 PM PDT 24
Peak memory 199928 kb
Host smart-6d67604c-29e8-4f32-940f-93d6c54cce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089705905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2089705905
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.17289329
Short name T543
Test name
Test status
Simulation time 17247312903 ps
CPU time 175.9 seconds
Started Jul 21 07:18:54 PM PDT 24
Finished Jul 21 07:22:40 PM PDT 24
Peak memory 216668 kb
Host smart-bed746df-a488-45e7-9451-76c196b4d8de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289329 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.17289329
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2915956050
Short name T1067
Test name
Test status
Simulation time 97302630721 ps
CPU time 75.13 seconds
Started Jul 21 07:18:53 PM PDT 24
Finished Jul 21 07:20:59 PM PDT 24
Peak memory 200180 kb
Host smart-5218d3fb-ca73-43d5-9acf-224829e230aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915956050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2915956050
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3813845466
Short name T978
Test name
Test status
Simulation time 86697475720 ps
CPU time 66.35 seconds
Started Jul 21 07:18:53 PM PDT 24
Finished Jul 21 07:20:50 PM PDT 24
Peak memory 200144 kb
Host smart-28c3827f-5466-416b-917d-b948ea59d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813845466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3813845466
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3781134769
Short name T54
Test name
Test status
Simulation time 207022717673 ps
CPU time 496.51 seconds
Started Jul 21 07:18:54 PM PDT 24
Finished Jul 21 07:28:00 PM PDT 24
Peak memory 216700 kb
Host smart-a9c12db0-0a96-410c-a4fc-2a8290e6a02c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781134769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3781134769
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2810645336
Short name T149
Test name
Test status
Simulation time 23025061009 ps
CPU time 22.74 seconds
Started Jul 21 07:19:01 PM PDT 24
Finished Jul 21 07:20:09 PM PDT 24
Peak memory 200208 kb
Host smart-5c8c4420-e0d2-4f5c-961d-4edcb84902ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810645336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2810645336
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2860373185
Short name T913
Test name
Test status
Simulation time 348854790573 ps
CPU time 1125.52 seconds
Started Jul 21 07:19:01 PM PDT 24
Finished Jul 21 07:38:32 PM PDT 24
Peak memory 225012 kb
Host smart-80c01ba4-ffa1-4c00-a31d-ac97c3a9c5b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860373185 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2860373185
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.893606784
Short name T36
Test name
Test status
Simulation time 147134571557 ps
CPU time 100.38 seconds
Started Jul 21 07:19:00 PM PDT 24
Finished Jul 21 07:21:27 PM PDT 24
Peak memory 200172 kb
Host smart-f3ec755c-a554-43f7-8933-510efe552d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893606784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.893606784
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3534252591
Short name T535
Test name
Test status
Simulation time 150116199418 ps
CPU time 67.71 seconds
Started Jul 21 07:19:07 PM PDT 24
Finished Jul 21 07:20:55 PM PDT 24
Peak memory 200208 kb
Host smart-4bc22f65-fe47-4866-9e74-8a29dc36eee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534252591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3534252591
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1606480092
Short name T646
Test name
Test status
Simulation time 600207821479 ps
CPU time 333.09 seconds
Started Jul 21 07:19:09 PM PDT 24
Finished Jul 21 07:25:20 PM PDT 24
Peak memory 215956 kb
Host smart-5daae4bd-bfb4-4a20-a7c1-a5c4b3c43d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606480092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1606480092
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3558336297
Short name T765
Test name
Test status
Simulation time 29529625 ps
CPU time 0.57 seconds
Started Jul 21 07:13:18 PM PDT 24
Finished Jul 21 07:13:19 PM PDT 24
Peak memory 195556 kb
Host smart-6b7f525a-de36-4710-97d0-e47e6d00353e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558336297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3558336297
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3343558758
Short name T397
Test name
Test status
Simulation time 164617596353 ps
CPU time 110.53 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:14:52 PM PDT 24
Peak memory 200124 kb
Host smart-2316c592-d2b9-40e9-b1b1-6352176acbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343558758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3343558758
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2563617779
Short name T420
Test name
Test status
Simulation time 121038730682 ps
CPU time 97.41 seconds
Started Jul 21 07:13:00 PM PDT 24
Finished Jul 21 07:14:38 PM PDT 24
Peak memory 200176 kb
Host smart-f357e957-948d-40a2-b212-a2c8ffeb0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563617779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2563617779
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1887014557
Short name T203
Test name
Test status
Simulation time 22029469957 ps
CPU time 39.17 seconds
Started Jul 21 07:13:02 PM PDT 24
Finished Jul 21 07:13:42 PM PDT 24
Peak memory 200112 kb
Host smart-bba61731-30ce-438b-920b-4db994bb2b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887014557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1887014557
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.640700325
Short name T986
Test name
Test status
Simulation time 139910602355 ps
CPU time 180.56 seconds
Started Jul 21 07:13:02 PM PDT 24
Finished Jul 21 07:16:03 PM PDT 24
Peak memory 196464 kb
Host smart-d4c699a0-da96-4419-9615-928ef463344b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640700325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.640700325
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1006615433
Short name T425
Test name
Test status
Simulation time 155425575931 ps
CPU time 1079.33 seconds
Started Jul 21 07:13:05 PM PDT 24
Finished Jul 21 07:31:05 PM PDT 24
Peak memory 200112 kb
Host smart-bd1e5ce7-9ddc-4c7e-b33f-c1ffddf57e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006615433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1006615433
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1093479294
Short name T328
Test name
Test status
Simulation time 5806568732 ps
CPU time 13.57 seconds
Started Jul 21 07:13:09 PM PDT 24
Finished Jul 21 07:13:23 PM PDT 24
Peak memory 199820 kb
Host smart-2ed10747-3005-4749-b3db-0ff1802c8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093479294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1093479294
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1898949047
Short name T483
Test name
Test status
Simulation time 269227733643 ps
CPU time 83.93 seconds
Started Jul 21 07:13:08 PM PDT 24
Finished Jul 21 07:14:32 PM PDT 24
Peak memory 200004 kb
Host smart-b13e0146-1e87-417b-8b05-d42014e71023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898949047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1898949047
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.94824215
Short name T679
Test name
Test status
Simulation time 3886141255 ps
CPU time 164.33 seconds
Started Jul 21 07:13:05 PM PDT 24
Finished Jul 21 07:15:50 PM PDT 24
Peak memory 200220 kb
Host smart-e43299aa-0300-4e4e-a0fc-8cc17de9bc4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94824215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.94824215
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2061634722
Short name T332
Test name
Test status
Simulation time 6609793231 ps
CPU time 13.71 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:13:16 PM PDT 24
Peak memory 199372 kb
Host smart-1fe9fda5-c4be-44d8-a22c-a29e6f4c79e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061634722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2061634722
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4219704840
Short name T689
Test name
Test status
Simulation time 133543402774 ps
CPU time 30.4 seconds
Started Jul 21 07:13:06 PM PDT 24
Finished Jul 21 07:13:37 PM PDT 24
Peak memory 200116 kb
Host smart-0a98c9cd-0752-43e4-a04a-295083f80e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219704840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4219704840
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1758950343
Short name T534
Test name
Test status
Simulation time 4547089462 ps
CPU time 2.42 seconds
Started Jul 21 07:13:07 PM PDT 24
Finished Jul 21 07:13:10 PM PDT 24
Peak memory 196680 kb
Host smart-9ca37333-5324-47d9-8858-989959fd941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758950343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1758950343
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1695560853
Short name T263
Test name
Test status
Simulation time 275807432 ps
CPU time 1.36 seconds
Started Jul 21 07:13:01 PM PDT 24
Finished Jul 21 07:13:04 PM PDT 24
Peak memory 198824 kb
Host smart-dcb61d9c-7e68-440a-ade1-ba326acb051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695560853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1695560853
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.920158939
Short name T607
Test name
Test status
Simulation time 163913197273 ps
CPU time 378.14 seconds
Started Jul 21 07:13:12 PM PDT 24
Finished Jul 21 07:19:30 PM PDT 24
Peak memory 208520 kb
Host smart-7bb9a379-db9e-4be9-b74e-21750a2139a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920158939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.920158939
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1978616105
Short name T837
Test name
Test status
Simulation time 1648518359 ps
CPU time 1.76 seconds
Started Jul 21 07:13:07 PM PDT 24
Finished Jul 21 07:13:09 PM PDT 24
Peak memory 198732 kb
Host smart-897c0629-5342-428a-8b94-b70d333e67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978616105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1978616105
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4127859599
Short name T904
Test name
Test status
Simulation time 124190732533 ps
CPU time 75.57 seconds
Started Jul 21 07:12:59 PM PDT 24
Finished Jul 21 07:14:16 PM PDT 24
Peak memory 200196 kb
Host smart-6b80f321-82ab-4537-9c81-e2d9491c1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127859599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4127859599
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.983236477
Short name T178
Test name
Test status
Simulation time 122732297580 ps
CPU time 47.46 seconds
Started Jul 21 07:19:09 PM PDT 24
Finished Jul 21 07:20:35 PM PDT 24
Peak memory 200184 kb
Host smart-61efe233-ed3c-4676-a920-2eff2a717251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983236477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.983236477
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.524964209
Short name T594
Test name
Test status
Simulation time 86684935344 ps
CPU time 1171.57 seconds
Started Jul 21 07:19:18 PM PDT 24
Finished Jul 21 07:39:21 PM PDT 24
Peak memory 226748 kb
Host smart-75312c43-f0fd-4d14-8026-f65d3f2e9116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524964209 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.524964209
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2982135445
Short name T861
Test name
Test status
Simulation time 73078477062 ps
CPU time 131.47 seconds
Started Jul 21 07:19:16 PM PDT 24
Finished Jul 21 07:22:01 PM PDT 24
Peak memory 200068 kb
Host smart-6913f4d8-ea96-4e33-8e88-6b75a6695076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982135445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2982135445
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3353344340
Short name T901
Test name
Test status
Simulation time 22207705717 ps
CPU time 34.42 seconds
Started Jul 21 07:19:19 PM PDT 24
Finished Jul 21 07:20:23 PM PDT 24
Peak memory 200164 kb
Host smart-31d25b5f-d8e0-4be1-b9aa-39d814f82172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353344340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3353344340
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1666004753
Short name T500
Test name
Test status
Simulation time 77953453768 ps
CPU time 775.71 seconds
Started Jul 21 07:19:18 PM PDT 24
Finished Jul 21 07:32:45 PM PDT 24
Peak memory 216680 kb
Host smart-b3d59176-52e4-47b0-9e5c-5dc04f0fbe2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666004753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1666004753
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2177046701
Short name T1049
Test name
Test status
Simulation time 37022994343 ps
CPU time 69.91 seconds
Started Jul 21 07:19:17 PM PDT 24
Finished Jul 21 07:20:59 PM PDT 24
Peak memory 200124 kb
Host smart-6e123aa2-bc41-4804-9d55-707d690fa5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177046701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2177046701
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.682622912
Short name T306
Test name
Test status
Simulation time 26128041500 ps
CPU time 339.51 seconds
Started Jul 21 07:19:16 PM PDT 24
Finished Jul 21 07:25:29 PM PDT 24
Peak memory 216660 kb
Host smart-bba16d3e-5fbf-4bb4-9a3c-e215dfc2d389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682622912 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.682622912
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4261364520
Short name T27
Test name
Test status
Simulation time 48627045318 ps
CPU time 70.6 seconds
Started Jul 21 07:19:15 PM PDT 24
Finished Jul 21 07:21:00 PM PDT 24
Peak memory 200092 kb
Host smart-95ae24de-611e-4522-8298-e980850604c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261364520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4261364520
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.425184593
Short name T629
Test name
Test status
Simulation time 183299090626 ps
CPU time 937.18 seconds
Started Jul 21 07:19:15 PM PDT 24
Finished Jul 21 07:35:27 PM PDT 24
Peak memory 216696 kb
Host smart-3ac39374-3b81-4266-b113-08596ee38068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425184593 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.425184593
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1620966804
Short name T460
Test name
Test status
Simulation time 95283559340 ps
CPU time 10.52 seconds
Started Jul 21 07:19:17 PM PDT 24
Finished Jul 21 07:20:00 PM PDT 24
Peak memory 200208 kb
Host smart-d16dc77c-8a52-49be-88bb-c29a622c3c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620966804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1620966804
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.517393423
Short name T812
Test name
Test status
Simulation time 24869007582 ps
CPU time 377.69 seconds
Started Jul 21 07:19:19 PM PDT 24
Finished Jul 21 07:26:06 PM PDT 24
Peak memory 208604 kb
Host smart-165b07cb-548b-4c83-ba06-fe4ae2904a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517393423 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.517393423
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.416004278
Short name T1083
Test name
Test status
Simulation time 22596361210 ps
CPU time 36.01 seconds
Started Jul 21 07:19:16 PM PDT 24
Finished Jul 21 07:20:25 PM PDT 24
Peak memory 200112 kb
Host smart-4defc762-a196-4cd3-85c2-7a53830bb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416004278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.416004278
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1672170092
Short name T1113
Test name
Test status
Simulation time 130928107410 ps
CPU time 519.37 seconds
Started Jul 21 07:19:16 PM PDT 24
Finished Jul 21 07:28:29 PM PDT 24
Peak memory 227476 kb
Host smart-851a230a-3cb7-4e38-bb16-7d662ed5e72f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672170092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1672170092
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4039482657
Short name T185
Test name
Test status
Simulation time 21895761244 ps
CPU time 86.82 seconds
Started Jul 21 07:19:17 PM PDT 24
Finished Jul 21 07:21:16 PM PDT 24
Peak memory 200220 kb
Host smart-1919f304-a1bc-481c-829f-2fafeb105206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039482657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4039482657
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3577918398
Short name T1151
Test name
Test status
Simulation time 189844721547 ps
CPU time 839.82 seconds
Started Jul 21 07:19:15 PM PDT 24
Finished Jul 21 07:33:49 PM PDT 24
Peak memory 224972 kb
Host smart-9f4b03d1-b489-48e5-9d4e-25f5d831c04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577918398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3577918398
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4006938811
Short name T315
Test name
Test status
Simulation time 159575903083 ps
CPU time 73.71 seconds
Started Jul 21 07:19:19 PM PDT 24
Finished Jul 21 07:21:02 PM PDT 24
Peak memory 200112 kb
Host smart-99780066-0f23-4376-ad29-c37e913dfb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006938811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4006938811
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.213067156
Short name T548
Test name
Test status
Simulation time 129696459815 ps
CPU time 587.01 seconds
Started Jul 21 07:19:18 PM PDT 24
Finished Jul 21 07:29:37 PM PDT 24
Peak memory 216696 kb
Host smart-547f87d2-8ad7-4f18-a46c-9fc24ff401ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213067156 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.213067156
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2088924771
Short name T727
Test name
Test status
Simulation time 7550600497 ps
CPU time 12.04 seconds
Started Jul 21 07:19:18 PM PDT 24
Finished Jul 21 07:20:01 PM PDT 24
Peak memory 198984 kb
Host smart-3fe48656-4b3e-443a-86f8-c9d0e511a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088924771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2088924771
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1539911367
Short name T469
Test name
Test status
Simulation time 53101536320 ps
CPU time 639.1 seconds
Started Jul 21 07:19:23 PM PDT 24
Finished Jul 21 07:30:28 PM PDT 24
Peak memory 216740 kb
Host smart-d2dc36ef-3020-4222-8422-4109abd909f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539911367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1539911367
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%