Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	107176	1			T1	17		T2	74		T3	65
all_values[1]	107176	1			T1	17		T2	74		T3	65
all_values[2]	107176	1			T1	17		T2	74		T3	65
all_values[3]	107176	1			T1	17		T2	74		T3	65
all_values[4]	107176	1			T1	17		T2	74		T3	65
all_values[5]	107176	1			T1	17		T2	74		T3	65
all_values[6]	107176	1			T1	17		T2	74		T3	65
all_values[7]	107176	1			T1	17		T2	74		T3	65
all_values[8]	107176	1			T1	17		T2	74		T3	65

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

492938

1

T1

68

T2

365

T3

332

auto[1]

471646

1

T1

85

T2

301

T3

253

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

868791

1

T1

142

T2

657

T3

456

auto[1]

95793

1

T1

11

T2

9

T3

129

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33128	1			T1	10		T2	56		T4	11
all_values[0]	auto[0]	auto[1]	24823	1			T3	13		T4	16		T5	12
all_values[0]	auto[1]	auto[0]	27042	1			T1	4		T2	17		T3	4
all_values[0]	auto[1]	auto[1]	22183	1			T1	3		T2	1		T3	48
all_values[1]	auto[0]	auto[0]	53381	1			T1	4		T2	44		T3	20
all_values[1]	auto[0]	auto[1]	1599	1			T6	6		T7	2		T10	4
all_values[1]	auto[1]	auto[0]	50257	1			T1	13		T2	30		T3	41
all_values[1]	auto[1]	auto[1]	1939	1			T3	4		T7	3		T10	3
all_values[2]	auto[0]	auto[0]	52699	1			T2	41		T3	52		T4	25
all_values[2]	auto[0]	auto[1]	2862	1			T1	1		T2	6		T4	2
all_values[2]	auto[1]	auto[0]	49163	1			T1	12		T2	26		T3	13
all_values[2]	auto[1]	auto[1]	2452	1			T1	4		T2	1		T5	1
all_values[3]	auto[0]	auto[0]	54286	1			T1	12		T2	3		T3	52
all_values[3]	auto[0]	auto[1]	335	1			T7	2		T10	3		T12	1
all_values[3]	auto[1]	auto[0]	52247	1			T1	5		T2	71		T3	12
all_values[3]	auto[1]	auto[1]	308	1			T3	1		T7	5		T8	1
all_values[4]	auto[0]	auto[0]	52569	1			T1	1		T2	37		T3	52
all_values[4]	auto[0]	auto[1]	464	1			T7	2		T10	6		T12	4
all_values[4]	auto[1]	auto[0]	53610	1			T1	16		T2	37		T3	6
all_values[4]	auto[1]	auto[1]	533	1			T3	7		T7	1		T12	6
all_values[5]	auto[0]	auto[0]	56277	1			T1	14		T2	56		T3	45
all_values[5]	auto[0]	auto[1]	199	1			T7	2		T10	2		T28	2
all_values[5]	auto[1]	auto[0]	50498	1			T1	3		T2	18		T3	20
all_values[5]	auto[1]	auto[1]	202	1			T7	2		T29	1		T31	1
all_values[6]	auto[0]	auto[0]	51758	1			T1	1		T2	52		T4	37
all_values[6]	auto[0]	auto[1]	195	1			T7	2		T10	1		T29	4
all_values[6]	auto[1]	auto[0]	55011	1			T1	16		T2	22		T3	65
all_values[6]	auto[1]	auto[1]	212	1			T7	6		T10	5		T28	7
all_values[7]	auto[0]	auto[0]	57257	1			T1	17		T2	41		T3	33
all_values[7]	auto[0]	auto[1]	370	1			T7	3		T10	4		T12	1
all_values[7]	auto[1]	auto[0]	49090	1			T2	33		T3	32		T4	47
all_values[7]	auto[1]	auto[1]	459	1			T7	2		T10	2		T16	8
all_values[8]	auto[0]	auto[0]	32071	1			T1	5		T2	28		T3	9
all_values[8]	auto[0]	auto[1]	18665	1			T1	3		T2	1		T3	56
all_values[8]	auto[1]	auto[0]	38447	1			T1	9		T2	45		T4	20
all_values[8]	auto[1]	auto[1]	17993	1			T4	7		T5	11		T6	12