Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2276	1			T4	2		T7	11		T8	1
auto[BaudRate115200]	1989	1			T3	1		T6	2		T7	6
auto[BaudRate230400]	2009	1			T4	1		T5	2		T6	1
auto[BaudRate128Kbps]	2071	1			T3	2		T5	2		T6	2
auto[BaudRate256Kbps]	2286	1			T1	8		T5	1		T6	1
auto[BaudRate1Mbps]	1952	1			T2	4		T4	1		T5	1
auto[BaudRate1p5Mbps]	1371	1			T2	6		T4	1		T5	2

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1596	1			T6	7		T9	2		T15	30
freqs[25]	1367	1			T34	10		T113	10		T247	7
freqs[48]	628	1			T265	10		T296	5		T89	2
freqs[50]	447	1			T115	10		T158	7		T43	13
freqs[100]	1166	1			T117	6		T272	2		T297	6

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	294	1			T15	3		T261	2		T116	1
auto[BaudRate9600]	freqs[25]	239	1			T113	1		T247	4		T134	1
auto[BaudRate9600]	freqs[48]	103	1			T296	5		T89	1		T140	2
auto[BaudRate9600]	freqs[50]	76	1			T115	1		T158	3		T63	4
auto[BaudRate9600]	freqs[100]	150	1			T117	2		T272	1		T297	1
auto[BaudRate115200]	freqs[24]	226	1			T6	2		T9	1		T15	15
auto[BaudRate115200]	freqs[25]	164	1			T34	1		T247	1		T124	4
auto[BaudRate115200]	freqs[48]	69	1			T265	2		T93	2		T270	2
auto[BaudRate115200]	freqs[50]	55	1			T115	1		T158	2		T43	3
auto[BaudRate115200]	freqs[100]	166	1			T117	1		T272	1		T104	1
auto[BaudRate230400]	freqs[24]	228	1			T6	1		T15	3		T103	4
auto[BaudRate230400]	freqs[25]	204	1			T34	1		T113	1		T279	1
auto[BaudRate230400]	freqs[48]	77	1			T265	2		T270	3		T97	5
auto[BaudRate230400]	freqs[50]	46	1			T115	1		T43	1		T298	1
auto[BaudRate230400]	freqs[100]	167	1			T297	1		T104	1		T244	2
auto[BaudRate128Kbps]	freqs[24]	201	1			T6	2		T15	3		T103	4
auto[BaudRate128Kbps]	freqs[25]	219	1			T34	4		T113	4		T124	1
auto[BaudRate128Kbps]	freqs[48]	103	1			T265	1		T93	3		T140	3
auto[BaudRate128Kbps]	freqs[50]	60	1			T115	1		T43	2		T90	2
auto[BaudRate128Kbps]	freqs[100]	155	1			T117	2		T297	2		T104	2
auto[BaudRate256Kbps]	freqs[24]	248	1			T6	1		T261	2		T116	2
auto[BaudRate256Kbps]	freqs[25]	209	1			T34	3		T113	3		T134	1
auto[BaudRate256Kbps]	freqs[48]	77	1			T265	2		T89	1		T93	1
auto[BaudRate256Kbps]	freqs[50]	68	1			T115	3		T43	4		T63	1
auto[BaudRate256Kbps]	freqs[100]	163	1			T297	2		T104	1		T244	1
auto[BaudRate1Mbps]	freqs[24]	233	1			T6	1		T9	1		T15	6
auto[BaudRate1Mbps]	freqs[25]	238	1			T34	1		T247	1		T124	3
auto[BaudRate1Mbps]	freqs[48]	89	1			T265	1		T93	1		T270	2
auto[BaudRate1Mbps]	freqs[50]	69	1			T115	1		T158	1		T43	1
auto[BaudRate1Mbps]	freqs[100]	186	1			T244	1		T28	3		T29	1
auto[BaudRate1p5Mbps]	freqs[25]	94	1			T113	1		T247	1		T252	2
auto[BaudRate1p5Mbps]	freqs[48]	110	1			T265	2		T93	1		T276	2
auto[BaudRate1p5Mbps]	freqs[50]	73	1			T115	2		T158	1		T43	2
auto[BaudRate1p5Mbps]	freqs[100]	179	1			T117	1		T271	1		T244	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded