Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30703125	1			T1	16518		T2	98135		T3	2367
all_levels[1]	206094	1			T1	2173		T2	987		T4	8
all_levels[2]	2880	1			T1	10		T4	2		T7	4
all_levels[3]	1111	1			T4	2		T7	1		T11	6
all_levels[4]	789	1			T4	2		T7	1		T11	2
all_levels[5]	572	1			T10	1		T113	1		T16	1
all_levels[6]	424	1			T113	1		T16	3		T17	1
all_levels[7]	392	1			T7	1		T8	1		T11	3
all_levels[8]	294	1			T7	3		T11	2		T34	1
all_levels[9]	225	1			T16	2		T17	1		T18	1
all_levels[10]	220	1			T7	2		T16	1		T17	1
all_levels[11]	198	1			T7	2		T8	1		T16	2
all_levels[12]	179	1			T7	1		T8	1		T16	1
all_levels[13]	166	1			T7	1		T114	1		T115	2
all_levels[14]	136	1			T34	2		T16	1		T114	1
all_levels[15]	108	1			T17	1		T116	1		T103	1
all_levels[16]	126	1			T6	1		T113	1		T18	1
all_levels[17]	104	1			T8	1		T34	1		T18	1
all_levels[18]	88	1			T17	1		T117	1		T118	2
all_levels[19]	90	1			T104	1		T119	1		T120	1
all_levels[20]	75	1			T102	1		T103	1		T118	2
all_levels[21]	78	1			T7	1		T17	1		T116	1
all_levels[22]	70	1			T7	1		T34	1		T106	1
all_levels[23]	81	1			T17	3		T26	1		T121	1
all_levels[24]	46	1			T122	1		T123	2		T31	1
all_levels[25]	42	1			T6	1		T8	1		T16	1
all_levels[26]	30	1			T122	1		T124	1		T125	1
all_levels[27]	57	1			T114	1		T107	1		T90	1
all_levels[28]	32	1			T7	1		T118	1		T30	1
all_levels[29]	39	1			T104	2		T126	2		T127	1
all_levels[30]	37	1			T17	2		T27	1		T120	2
all_levels[31]	25	1			T26	1		T128	1		T129	1
all_levels[32]	26	1			T26	1		T120	2		T107	1
all_levels[33]	24	1			T107	1		T130	2		T131	1
all_levels[34]	32	1			T61	1		T132	1		T128	2
all_levels[35]	43	1			T8	1		T18	1		T122	1
all_levels[36]	21	1			T7	1		T133	1		T134	1
all_levels[37]	29	1			T118	2		T135	1		T133	1
all_levels[38]	26	1			T6	2		T136	1		T137	1
all_levels[39]	25	1			T120	2		T138	2		T94	1
all_levels[40]	22	1			T44	4		T109	1		T137	1
all_levels[41]	24	1			T135	1		T139	1		T140	1
all_levels[42]	16	1			T6	1		T102	1		T141	1
all_levels[43]	19	1			T30	1		T125	1		T142	2
all_levels[44]	7	1			T33	1		T143	1		T144	1
all_levels[45]	11	1			T145	1		T140	1		T146	1
all_levels[46]	16	1			T142	1		T147	1		T148	1
all_levels[47]	4	1			T17	1		T149	1		T150	1
all_levels[48]	10	1			T8	1		T151	1		T152	1
all_levels[49]	6	1			T7	1		T153	1		T154	1
all_levels[50]	11	1			T106	2		T155	2		T156	1
all_levels[51]	16	1			T135	1		T131	1		T157	1
all_levels[52]	19	1			T17	1		T158	1		T139	1
all_levels[53]	8	1			T8	1		T144	1		T159	1
all_levels[54]	12	1			T160	1		T161	3		T162	1
all_levels[55]	7	1			T17	1		T101	1		T163	1
all_levels[56]	7	1			T102	1		T144	1		T164	1
all_levels[57]	13	1			T157	1		T162	2		T49	1
all_levels[58]	10	1			T106	1		T107	1		T165	1
all_levels[59]	10	1			T102	1		T166	2		T49	1
all_levels[60]	7	1			T102	2		T124	1		T144	1
all_levels[61]	10	1			T146	1		T156	1		T167	1
all_levels[62]	7	1			T17	1		T168	1		T156	1
all_levels[63]	9	1			T26	1		T169	1		T150	1
all_levels[64]	95	1			T8	1		T11	1		T170	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30913541

1

T1

18701

T2

99122

T3

2337

auto[1]

4994

1

T3

30

T4

4

T6

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[26]]	[auto[1]]	0	1	1
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47] , all_levels[48] , all_levels[49]]	[auto[1]]	--	--	3
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30698573	1			T1	16518		T2	98135		T3	2337
all_levels[0]	auto[1]	4552	1			T3	30		T4	4		T6	6
all_levels[1]	auto[0]	206005	1			T1	2173		T2	987		T4	8
all_levels[1]	auto[1]	89	1			T171	1		T114	3		T121	1
all_levels[2]	auto[0]	2853	1			T1	10		T4	2		T7	4
all_levels[2]	auto[1]	27	1			T11	3		T104	1		T172	1
all_levels[3]	auto[0]	1083	1			T4	2		T7	1		T11	6
all_levels[3]	auto[1]	28	1			T121	1		T125	1		T45	1
all_levels[4]	auto[0]	773	1			T4	2		T7	1		T11	2
all_levels[4]	auto[1]	16	1			T125	1		T31	3		T129	2
all_levels[5]	auto[0]	548	1			T10	1		T113	1		T16	1
all_levels[5]	auto[1]	24	1			T26	1		T96	1		T173	1
all_levels[6]	auto[0]	407	1			T113	1		T16	3		T17	1
all_levels[6]	auto[1]	17	1			T174	2		T139	1		T175	3
all_levels[7]	auto[0]	368	1			T7	1		T8	1		T11	3
all_levels[7]	auto[1]	24	1			T32	1		T176	2		T177	1
all_levels[8]	auto[0]	283	1			T7	3		T11	2		T34	1
all_levels[8]	auto[1]	11	1			T125	1		T132	2		T178	1
all_levels[9]	auto[0]	221	1			T16	2		T17	1		T18	1
all_levels[9]	auto[1]	4	1			T129	1		T179	1		T180	1
all_levels[10]	auto[0]	204	1			T7	2		T16	1		T17	1
all_levels[10]	auto[1]	16	1			T109	1		T181	1		T182	1
all_levels[11]	auto[0]	189	1			T7	2		T8	1		T16	2
all_levels[11]	auto[1]	9	1			T44	1		T183	1		T184	3
all_levels[12]	auto[0]	166	1			T7	1		T8	1		T16	1
all_levels[12]	auto[1]	13	1			T125	1		T176	1		T109	1
all_levels[13]	auto[0]	161	1			T7	1		T114	1		T115	2
all_levels[13]	auto[1]	5	1			T183	1		T185	1		T186	2
all_levels[14]	auto[0]	128	1			T34	2		T16	1		T114	1
all_levels[14]	auto[1]	8	1			T88	2		T187	1		T188	1
all_levels[15]	auto[0]	101	1			T17	1		T116	1		T103	1
all_levels[15]	auto[1]	7	1			T189	1		T173	1		T190	1
all_levels[16]	auto[0]	114	1			T6	1		T113	1		T18	1
all_levels[16]	auto[1]	12	1			T126	1		T191	2		T153	1
all_levels[17]	auto[0]	95	1			T8	1		T34	1		T18	1
all_levels[17]	auto[1]	9	1			T192	2		T193	3		T194	2
all_levels[18]	auto[0]	82	1			T17	1		T117	1		T118	2
all_levels[18]	auto[1]	6	1			T195	1		T196	1		T197	2
all_levels[19]	auto[0]	84	1			T104	1		T119	1		T120	1
all_levels[19]	auto[1]	6	1			T198	1		T199	1		T200	3
all_levels[20]	auto[0]	70	1			T102	1		T103	1		T118	2
all_levels[20]	auto[1]	5	1			T201	1		T202	3		T203	1
all_levels[21]	auto[0]	70	1			T7	1		T17	1		T116	1
all_levels[21]	auto[1]	8	1			T126	1		T204	1		T190	1
all_levels[22]	auto[0]	67	1			T7	1		T34	1		T106	1
all_levels[22]	auto[1]	3	1			T205	1		T206	1		T207	1
all_levels[23]	auto[0]	73	1			T17	3		T26	1		T121	1
all_levels[23]	auto[1]	8	1			T208	1		T161	1		T198	1
all_levels[24]	auto[0]	42	1			T122	1		T123	2		T31	1
all_levels[24]	auto[1]	4	1			T166	1		T209	1		T210	2
all_levels[25]	auto[0]	38	1			T6	1		T8	1		T16	1
all_levels[25]	auto[1]	4	1			T211	1		T212	3		-	-
all_levels[26]	auto[0]	30	1			T122	1		T124	1		T125	1
all_levels[27]	auto[0]	47	1			T114	1		T107	1		T90	1
all_levels[27]	auto[1]	10	1			T213	1		T214	1		T215	1
all_levels[28]	auto[0]	31	1			T7	1		T118	1		T30	1
all_levels[28]	auto[1]	1	1			T216	1		-	-		-	-
all_levels[29]	auto[0]	33	1			T104	1		T126	2		T127	1
all_levels[29]	auto[1]	6	1			T104	1		T213	1		T217	2
all_levels[30]	auto[0]	34	1			T17	2		T27	1		T120	2
all_levels[30]	auto[1]	3	1			T218	1		T219	1		T220	1
all_levels[31]	auto[0]	22	1			T26	1		T128	1		T129	1
all_levels[31]	auto[1]	3	1			T221	3		-	-		-	-
all_levels[32]	auto[0]	26	1			T26	1		T120	2		T107	1
all_levels[33]	auto[0]	23	1			T107	1		T130	1		T131	1
all_levels[33]	auto[1]	1	1			T130	1		-	-		-	-
all_levels[34]	auto[0]	31	1			T61	1		T132	1		T128	2
all_levels[34]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[35]	auto[0]	31	1			T8	1		T18	1		T122	1
all_levels[35]	auto[1]	12	1			T44	2		T223	5		T224	3
all_levels[36]	auto[0]	20	1			T7	1		T133	1		T134	1
all_levels[36]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[37]	auto[0]	27	1			T118	2		T135	1		T133	1
all_levels[37]	auto[1]	2	1			T226	1		T227	1		-	-
all_levels[38]	auto[0]	25	1			T6	1		T136	1		T137	1
all_levels[38]	auto[1]	1	1			T6	1		-	-		-	-
all_levels[39]	auto[0]	25	1			T120	2		T138	2		T94	1
all_levels[40]	auto[0]	19	1			T44	1		T109	1		T137	1
all_levels[40]	auto[1]	3	1			T44	3		-	-		-	-
all_levels[41]	auto[0]	19	1			T135	1		T139	1		T140	1
all_levels[41]	auto[1]	5	1			T228	5		-	-		-	-
all_levels[42]	auto[0]	15	1			T6	1		T102	1		T141	1
all_levels[42]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[43]	auto[0]	17	1			T30	1		T125	1		T142	2
all_levels[43]	auto[1]	2	1			T199	1		T218	1		-	-
all_levels[44]	auto[0]	6	1			T33	1		T143	1		T144	1
all_levels[44]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[45]	auto[0]	11	1			T145	1		T140	1		T146	1
all_levels[46]	auto[0]	14	1			T142	1		T147	1		T148	1
all_levels[46]	auto[1]	2	1			T231	1		T232	1		-	-
all_levels[47]	auto[0]	4	1			T17	1		T149	1		T150	1
all_levels[48]	auto[0]	10	1			T8	1		T151	1		T152	1
all_levels[49]	auto[0]	6	1			T7	1		T153	1		T154	1
all_levels[50]	auto[0]	9	1			T106	1		T155	1		T156	1
all_levels[50]	auto[1]	2	1			T106	1		T155	1		-	-
all_levels[51]	auto[0]	12	1			T135	1		T131	1		T157	1
all_levels[51]	auto[1]	4	1			T233	3		T234	1		-	-
all_levels[52]	auto[0]	15	1			T17	1		T158	1		T139	1
all_levels[52]	auto[1]	4	1			T126	2		T235	2		-	-
all_levels[53]	auto[0]	7	1			T8	1		T144	1		T159	1
all_levels[53]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T160	1		T161	1		T162	1
all_levels[54]	auto[1]	2	1			T161	2		-	-		-	-
all_levels[55]	auto[0]	7	1			T17	1		T101	1		T163	1
all_levels[56]	auto[0]	7	1			T102	1		T144	1		T164	1
all_levels[57]	auto[0]	11	1			T157	1		T162	1		T49	1
all_levels[57]	auto[1]	2	1			T162	1		T237	1		-	-
all_levels[58]	auto[0]	7	1			T106	1		T107	1		T165	1
all_levels[58]	auto[1]	3	1			T129	1		T238	2		-	-
all_levels[59]	auto[0]	9	1			T102	1		T166	1		T49	1
all_levels[59]	auto[1]	1	1			T166	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T102	2		T124	1		T144	1
all_levels[61]	auto[0]	9	1			T146	1		T156	1		T167	1
all_levels[61]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[62]	auto[0]	7	1			T17	1		T168	1		T156	1
all_levels[63]	auto[0]	9	1			T26	1		T169	1		T150	1
all_levels[64]	auto[0]	91	1			T8	1		T11	1		T170	2
all_levels[64]	auto[1]	4	1			T66	2		T151	1		T129	1