Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	107176	1			T1	17		T2	74		T3	65
all_pins[1]	107176	1			T1	17		T2	74		T3	65
all_pins[2]	107176	1			T1	17		T2	74		T3	65
all_pins[3]	107176	1			T1	17		T2	74		T3	65
all_pins[4]	107176	1			T1	17		T2	74		T3	65
all_pins[5]	107176	1			T1	17		T2	74		T3	65
all_pins[6]	107176	1			T1	17		T2	74		T3	65
all_pins[7]	107176	1			T1	17		T2	74		T3	65
all_pins[8]	107176	1			T1	17		T2	74		T3	65

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	917284	1			T1	144		T2	664		T3	524
values[0x1]	47300	1			T1	9		T2	2		T3	61
transitions[0x0=>0x1]	37997	1			T1	9		T2	2		T3	61
transitions[0x1=>0x0]	37743	1			T1	8		T2	1		T3	60

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84902	1			T1	14		T2	73		T3	16
all_pins[0]	values[0x1]	22274	1			T1	3		T2	1		T3	49
all_pins[0]	transitions[0x0=>0x1]	21616	1			T1	3		T2	1		T3	49
all_pins[0]	transitions[0x1=>0x0]	1279	1			T3	4		T7	1		T10	1
all_pins[1]	values[0x0]	105239	1			T1	17		T2	74		T3	61
all_pins[1]	values[0x1]	1937	1			T3	4		T7	3		T10	3
all_pins[1]	transitions[0x0=>0x1]	1831	1			T3	4		T7	3		T10	3
all_pins[1]	transitions[0x1=>0x0]	2407	1			T1	4		T2	1		T5	1
all_pins[2]	values[0x0]	104663	1			T1	13		T2	73		T3	65
all_pins[2]	values[0x1]	2513	1			T1	4		T2	1		T5	1
all_pins[2]	transitions[0x0=>0x1]	2442	1			T1	4		T2	1		T5	1
all_pins[2]	transitions[0x1=>0x0]	237	1			T3	1		T7	5		T8	1
all_pins[3]	values[0x0]	106868	1			T1	17		T2	74		T3	64
all_pins[3]	values[0x1]	308	1			T3	1		T7	5		T8	1
all_pins[3]	transitions[0x0=>0x1]	261	1			T3	1		T7	5		T8	1
all_pins[3]	transitions[0x1=>0x0]	486	1			T3	7		T7	1		T12	6
all_pins[4]	values[0x0]	106643	1			T1	17		T2	74		T3	58
all_pins[4]	values[0x1]	533	1			T3	7		T7	1		T12	6
all_pins[4]	transitions[0x0=>0x1]	444	1			T3	7		T7	1		T12	5
all_pins[4]	transitions[0x1=>0x0]	168	1			T7	2		T12	1		T29	1
all_pins[5]	values[0x0]	106919	1			T1	17		T2	74		T3	65
all_pins[5]	values[0x1]	257	1			T7	2		T12	2		T29	1
all_pins[5]	transitions[0x0=>0x1]	207	1			T12	2		T29	1		T66	2
all_pins[5]	transitions[0x1=>0x0]	895	1			T1	2		T7	5		T8	3
all_pins[6]	values[0x0]	106231	1			T1	15		T2	74		T3	65
all_pins[6]	values[0x1]	945	1			T1	2		T7	7		T8	3
all_pins[6]	transitions[0x0=>0x1]	860	1			T1	2		T7	5		T8	3
all_pins[6]	transitions[0x1=>0x0]	374	1			T16	7		T17	5		T18	1
all_pins[7]	values[0x0]	106717	1			T1	17		T2	74		T3	65
all_pins[7]	values[0x1]	459	1			T7	2		T10	2		T16	8
all_pins[7]	transitions[0x0=>0x1]	303	1			T7	1		T10	2		T16	6
all_pins[7]	transitions[0x1=>0x0]	17918	1			T4	7		T5	11		T6	12
all_pins[8]	values[0x0]	89102	1			T1	17		T2	74		T3	65
all_pins[8]	values[0x1]	18074	1			T4	7		T5	11		T6	12
all_pins[8]	transitions[0x0=>0x1]	10033	1			T4	7		T5	9		T7	10
all_pins[8]	transitions[0x1=>0x0]	13979	1			T1	2		T3	48		T4	2