Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8518861	1			T1	2094		T2	43		T3	23
all_levels[1]	1638397	1			T1	14		T2	43		T3	1128
all_levels[2]	475482	1			T1	14		T2	49		T5	3935
all_levels[3]	197847	1			T1	18		T2	44		T5	3927
all_levels[4]	249040	1			T1	18		T2	42		T4	1
all_levels[5]	255199	1			T1	13		T2	42		T5	3929
all_levels[6]	204855	1			T1	14		T2	36		T5	3936
all_levels[7]	204533	1			T1	16		T2	37		T5	3927
all_levels[8]	216934	1			T1	18		T2	47		T5	3938
all_levels[9]	256792	1			T1	16		T2	43		T5	3938
all_levels[10]	261042	1			T1	18		T2	41		T5	3920
all_levels[11]	300027	1			T1	20		T2	44		T5	3903
all_levels[12]	188959	1			T1	20		T2	43		T5	1841
all_levels[13]	223573	1			T1	18		T2	40		T5	1854
all_levels[14]	185084	1			T1	20		T2	55		T5	1840
all_levels[15]	188575	1			T1	20		T2	37		T3	6
all_levels[16]	309848	1			T1	21		T2	44		T3	1207
all_levels[17]	178051	1			T1	19		T2	41		T5	1850
all_levels[18]	180365	1			T1	19		T2	39		T4	1
all_levels[19]	242184	1			T1	19		T2	38		T5	1859
all_levels[20]	180736	1			T1	16		T2	48		T5	1846
all_levels[21]	196371	1			T1	15		T2	55		T5	1850
all_levels[22]	203040	1			T1	22		T2	40		T5	1851
all_levels[23]	182277	1			T1	15		T2	39		T5	1859
all_levels[24]	261305	1			T1	17		T2	45		T5	1914
all_levels[25]	159327	1			T1	18		T2	41		T5	3006
all_levels[26]	172063	1			T1	16		T2	46		T5	2975
all_levels[27]	171521	1			T1	20		T2	42		T5	3011
all_levels[28]	646439	1			T1	19		T2	40		T5	3013
all_levels[29]	160436	1			T1	16		T2	42		T5	3011
all_levels[30]	182851	1			T1	24		T2	47		T4	52
all_levels[31]	625782	1			T1	841		T2	1117		T5	14815
all_levels[32]	13300246	1			T1	15234		T2	96673		T5	81405

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30913541

1

T1

18701

T2

99122

T3

2337

auto[1]

4501

1

T1

1

T2

1

T3

27

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8516287	1			T1	2094		T2	43		T3	1
all_levels[0]	auto[1]	2574	1			T3	22		T4	4		T6	4
all_levels[1]	auto[0]	1638068	1			T1	14		T2	43		T3	1128
all_levels[1]	auto[1]	329	1			T6	1		T289	1		T117	1
all_levels[2]	auto[0]	475435	1			T1	14		T2	49		T5	3935
all_levels[2]	auto[1]	47	1			T35	1		T114	2		T26	2
all_levels[3]	auto[0]	197692	1			T1	18		T2	44		T5	3927
all_levels[3]	auto[1]	155	1			T114	1		T18	5		T288	1
all_levels[4]	auto[0]	249011	1			T1	18		T2	42		T4	1
all_levels[4]	auto[1]	29	1			T121	3		T208	3		T66	1
all_levels[5]	auto[0]	255165	1			T1	13		T2	42		T5	3929
all_levels[5]	auto[1]	34	1			T11	4		T113	1		T265	2
all_levels[6]	auto[0]	204829	1			T1	14		T2	36		T5	3936
all_levels[6]	auto[1]	26	1			T104	1		T45	1		T283	4
all_levels[7]	auto[0]	204351	1			T1	16		T2	37		T5	3927
all_levels[7]	auto[1]	182	1			T12	7		T27	5		T125	2
all_levels[8]	auto[0]	216904	1			T1	18		T2	47		T5	3938
all_levels[8]	auto[1]	30	1			T7	1		T124	1		T93	1
all_levels[9]	auto[0]	256763	1			T1	16		T2	43		T5	3938
all_levels[9]	auto[1]	29	1			T102	1		T248	1		T223	1
all_levels[10]	auto[0]	261026	1			T1	18		T2	41		T5	3920
all_levels[10]	auto[1]	16	1			T171	2		T30	1		T248	1
all_levels[11]	auto[0]	300006	1			T1	20		T2	44		T5	3903
all_levels[11]	auto[1]	21	1			T135	1		T300	2		T173	1
all_levels[12]	auto[0]	188935	1			T1	20		T2	43		T5	1841
all_levels[12]	auto[1]	24	1			T93	1		T109	1		T189	1
all_levels[13]	auto[0]	223528	1			T1	18		T2	40		T5	1854
all_levels[13]	auto[1]	45	1			T170	1		T103	1		T30	1
all_levels[14]	auto[0]	185065	1			T1	20		T2	55		T5	1840
all_levels[14]	auto[1]	19	1			T132	1		T129	1		T166	1
all_levels[15]	auto[0]	188480	1			T1	20		T2	37		T3	1
all_levels[15]	auto[1]	95	1			T3	5		T93	2		T131	1
all_levels[16]	auto[0]	309835	1			T1	21		T2	44		T3	1207
all_levels[16]	auto[1]	13	1			T18	1		T189	2		T142	1
all_levels[17]	auto[0]	178026	1			T1	19		T2	41		T5	1850
all_levels[17]	auto[1]	25	1			T26	1		T257	2		T197	1
all_levels[18]	auto[0]	180344	1			T1	19		T2	39		T4	1
all_levels[18]	auto[1]	21	1			T115	1		T18	1		T130	2
all_levels[19]	auto[0]	242172	1			T1	19		T2	38		T5	1859
all_levels[19]	auto[1]	12	1			T118	1		T270	1		T301	1
all_levels[20]	auto[0]	180713	1			T1	16		T2	48		T5	1846
all_levels[20]	auto[1]	23	1			T108	1		T302	1		T303	3
all_levels[21]	auto[0]	196353	1			T1	15		T2	55		T5	1850
all_levels[21]	auto[1]	18	1			T94	1		T130	1		T196	1
all_levels[22]	auto[0]	203018	1			T1	22		T2	40		T5	1851
all_levels[22]	auto[1]	22	1			T106	1		T31	3		T304	1
all_levels[23]	auto[0]	182267	1			T1	15		T2	39		T5	1859
all_levels[23]	auto[1]	10	1			T243	1		T140	1		T305	1
all_levels[24]	auto[0]	261285	1			T1	17		T2	45		T5	1914
all_levels[24]	auto[1]	20	1			T268	2		T205	2		T306	1
all_levels[25]	auto[0]	159297	1			T1	18		T2	41		T5	3006
all_levels[25]	auto[1]	30	1			T288	1		T260	7		T189	2
all_levels[26]	auto[0]	172048	1			T1	16		T2	46		T5	2975
all_levels[26]	auto[1]	15	1			T246	1		T260	1		T205	1
all_levels[27]	auto[0]	171504	1			T1	20		T2	42		T5	3011
all_levels[27]	auto[1]	17	1			T8	1		T249	1		T118	1
all_levels[28]	auto[0]	646407	1			T1	19		T2	40		T5	3013
all_levels[28]	auto[1]	32	1			T6	1		T170	1		T125	1
all_levels[29]	auto[0]	160405	1			T1	16		T2	42		T5	3011
all_levels[29]	auto[1]	31	1			T223	1		T181	2		T307	2
all_levels[30]	auto[0]	182819	1			T1	24		T2	47		T4	50
all_levels[30]	auto[1]	32	1			T4	2		T121	1		T308	1
all_levels[31]	auto[0]	625752	1			T1	841		T2	1117		T5	14815
all_levels[31]	auto[1]	30	1			T170	1		T252	1		T153	3
all_levels[32]	auto[0]	13299751	1			T1	15233		T2	96672		T5	81405
all_levels[32]	auto[1]	495	1			T1	1		T2	1		T7	2