Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	812	1			T7	11		T10	8		T18	7
all_values[1]	812	1			T7	11		T10	8		T18	7
all_values[2]	812	1			T7	11		T10	8		T18	7
all_values[3]	812	1			T7	11		T10	8		T18	7
all_values[4]	812	1			T7	11		T10	8		T18	7
all_values[5]	812	1			T7	11		T10	8		T18	7
all_values[6]	812	1			T7	11		T10	8		T18	7
all_values[7]	812	1			T7	11		T10	8		T18	7
all_values[8]	812	1			T7	11		T10	8		T18	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3910

1

T7

53

T10

42

T18

28

auto[1]

3398

1

T7

46

T10

30

T18

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2256

1

T7

31

T10

27

T18

27

auto[1]

5052

1

T7

68

T10

45

T18

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4231

1

T7

55

T10

44

T18

40

auto[1]

3077

1

T7

44

T10

28

T18

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	224	1			T7	4		T10	2		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	281	1			T7	4		T10	3		T18	3
all_values[0]	auto[1]	auto[0]	auto[1]	161	1			T10	1		T18	2		T28	3
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T7	3		T10	2		T18	1
all_values[1]	auto[0]	auto[0]	auto[0]	256	1			T7	3		T10	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	195	1			T7	3		T10	3		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	189	1			T7	3		T10	2		T28	1
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T7	2		T10	2		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T7	4		T10	2		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T7	1		T18	3		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	131	1			T7	2		T10	2		T28	2
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T18	2		T28	1		T29	6
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T7	2		T10	4		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T7	2		T18	1		T28	2
all_values[3]	auto[0]	auto[0]	auto[0]	185	1			T10	4		T18	2		T28	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T7	1		T10	2		T29	1
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T7	3		T10	1		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T7	2		T28	1		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T7	2		T18	2		T29	6
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T7	3		T10	1		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T7	6		T10	1		T29	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T7	1		T10	2		T29	2
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T7	1		T10	3		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T29	1		T31	2		T64	1
all_values[4]	auto[1]	auto[0]	auto[1]	172	1			T7	1		T10	2		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T7	2		T18	2		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	174	1			T7	4		T10	2		T18	6
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T7	1		T28	1		T29	2
all_values[5]	auto[0]	auto[1]	auto[0]	122	1			T10	2		T28	1		T29	4
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T29	2		T108	1		T109	1
all_values[5]	auto[1]	auto[0]	auto[1]	203	1			T7	3		T10	4		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T7	3		T29	2		T31	1
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T7	1		T18	1		T29	1
all_values[6]	auto[0]	auto[0]	auto[1]	94	1			T29	2		T31	1		T64	2
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T7	1		T18	6		T31	1
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T7	3		T10	2		T28	3
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T7	2		T10	4		T29	3
all_values[6]	auto[1]	auto[1]	auto[1]	167	1			T7	4		T10	2		T28	4
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T7	3		T10	3		T18	1
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T7	1		T108	2		T109	1
all_values[7]	auto[0]	auto[1]	auto[0]	125	1			T10	3		T18	1		T28	4
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T10	1		T18	1		T29	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T7	4		T18	2		T29	2
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T7	3		T10	1		T18	2
all_values[8]	auto[0]	auto[0]	auto[1]	249	1			T7	3		T10	4		T18	1
all_values[8]	auto[0]	auto[1]	auto[1]	216	1			T7	3		T10	1		T18	2
all_values[8]	auto[1]	auto[0]	auto[1]	199	1			T7	3		T10	2		T18	2
all_values[8]	auto[1]	auto[1]	auto[1]	148	1			T7	2		T10	1		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal