Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1315
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T1255 /workspace/coverage/cover_reg_top/3.uart_intr_test.2158091102 Jul 22 06:08:31 PM PDT 24 Jul 22 06:08:32 PM PDT 24 40506076 ps
T1256 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1083756230 Jul 22 06:08:34 PM PDT 24 Jul 22 06:08:35 PM PDT 24 25687933 ps
T1257 /workspace/coverage/cover_reg_top/26.uart_intr_test.2239293122 Jul 22 06:09:21 PM PDT 24 Jul 22 06:09:22 PM PDT 24 28488947 ps
T1258 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2878526205 Jul 22 06:09:12 PM PDT 24 Jul 22 06:09:13 PM PDT 24 43384242 ps
T1259 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1301080744 Jul 22 06:09:10 PM PDT 24 Jul 22 06:09:12 PM PDT 24 59936361 ps
T1260 /workspace/coverage/cover_reg_top/17.uart_intr_test.3575020862 Jul 22 06:09:13 PM PDT 24 Jul 22 06:09:14 PM PDT 24 14528104 ps
T1261 /workspace/coverage/cover_reg_top/34.uart_intr_test.1233265828 Jul 22 06:09:23 PM PDT 24 Jul 22 06:09:25 PM PDT 24 98182843 ps
T1262 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2766833189 Jul 22 06:09:01 PM PDT 24 Jul 22 06:09:03 PM PDT 24 92441786 ps
T83 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3873749050 Jul 22 06:09:03 PM PDT 24 Jul 22 06:09:04 PM PDT 24 92029672 ps
T1263 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2733736907 Jul 22 06:08:44 PM PDT 24 Jul 22 06:08:46 PM PDT 24 495071841 ps
T59 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1167320919 Jul 22 06:08:33 PM PDT 24 Jul 22 06:08:34 PM PDT 24 211980675 ps
T1264 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1498733412 Jul 22 06:09:13 PM PDT 24 Jul 22 06:09:15 PM PDT 24 13496453 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.676357113 Jul 22 06:08:40 PM PDT 24 Jul 22 06:08:42 PM PDT 24 165317925 ps
T1266 /workspace/coverage/cover_reg_top/8.uart_intr_test.3850109675 Jul 22 06:08:51 PM PDT 24 Jul 22 06:08:52 PM PDT 24 12960336 ps
T1267 /workspace/coverage/cover_reg_top/35.uart_intr_test.2190527824 Jul 22 06:09:30 PM PDT 24 Jul 22 06:09:31 PM PDT 24 10411532 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.492791124 Jul 22 06:08:33 PM PDT 24 Jul 22 06:08:35 PM PDT 24 115261963 ps
T1269 /workspace/coverage/cover_reg_top/43.uart_intr_test.4091790653 Jul 22 06:10:03 PM PDT 24 Jul 22 06:10:06 PM PDT 24 32486378 ps
T1270 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.898729831 Jul 22 06:08:44 PM PDT 24 Jul 22 06:08:45 PM PDT 24 17086312 ps
T1271 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1005826140 Jul 22 06:09:10 PM PDT 24 Jul 22 06:09:11 PM PDT 24 295370222 ps
T60 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2839494094 Jul 22 06:08:48 PM PDT 24 Jul 22 06:08:49 PM PDT 24 70848811 ps
T1272 /workspace/coverage/cover_reg_top/27.uart_intr_test.2367196689 Jul 22 06:09:35 PM PDT 24 Jul 22 06:09:36 PM PDT 24 14937664 ps
T1273 /workspace/coverage/cover_reg_top/21.uart_intr_test.120874841 Jul 22 06:10:32 PM PDT 24 Jul 22 06:10:33 PM PDT 24 65527660 ps
T1274 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4255154065 Jul 22 06:08:41 PM PDT 24 Jul 22 06:08:43 PM PDT 24 97564059 ps
T1275 /workspace/coverage/cover_reg_top/4.uart_intr_test.2477733817 Jul 22 06:08:39 PM PDT 24 Jul 22 06:08:40 PM PDT 24 31374019 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_intr_test.268709101 Jul 22 06:09:12 PM PDT 24 Jul 22 06:09:14 PM PDT 24 16041477 ps
T1277 /workspace/coverage/cover_reg_top/40.uart_intr_test.1929476135 Jul 22 06:09:21 PM PDT 24 Jul 22 06:09:23 PM PDT 24 14746751 ps
T1278 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3913756895 Jul 22 06:10:35 PM PDT 24 Jul 22 06:10:37 PM PDT 24 52026009 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2948131024 Jul 22 06:09:02 PM PDT 24 Jul 22 06:09:04 PM PDT 24 256694435 ps
T1280 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4108943991 Jul 22 06:08:38 PM PDT 24 Jul 22 06:08:39 PM PDT 24 48726643 ps
T1281 /workspace/coverage/cover_reg_top/45.uart_intr_test.58412607 Jul 22 06:09:23 PM PDT 24 Jul 22 06:09:24 PM PDT 24 12974216 ps
T1282 /workspace/coverage/cover_reg_top/38.uart_intr_test.1484556869 Jul 22 06:09:29 PM PDT 24 Jul 22 06:09:31 PM PDT 24 12563676 ps
T1283 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3345428458 Jul 22 06:09:03 PM PDT 24 Jul 22 06:09:05 PM PDT 24 59545790 ps
T1284 /workspace/coverage/cover_reg_top/46.uart_intr_test.3899573866 Jul 22 06:09:41 PM PDT 24 Jul 22 06:09:42 PM PDT 24 45521563 ps
T1285 /workspace/coverage/cover_reg_top/36.uart_intr_test.2222165141 Jul 22 06:09:22 PM PDT 24 Jul 22 06:09:23 PM PDT 24 42597047 ps
T1286 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1592470492 Jul 22 06:10:32 PM PDT 24 Jul 22 06:10:35 PM PDT 24 212611858 ps
T84 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1561637068 Jul 22 06:08:50 PM PDT 24 Jul 22 06:08:52 PM PDT 24 206679464 ps
T1287 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1350118021 Jul 22 06:08:42 PM PDT 24 Jul 22 06:08:43 PM PDT 24 75909443 ps
T1288 /workspace/coverage/cover_reg_top/33.uart_intr_test.950738440 Jul 22 06:09:21 PM PDT 24 Jul 22 06:09:22 PM PDT 24 33284842 ps
T1289 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1765463224 Jul 22 06:08:59 PM PDT 24 Jul 22 06:09:01 PM PDT 24 134023483 ps
T1290 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1948151611 Jul 22 06:09:29 PM PDT 24 Jul 22 06:09:31 PM PDT 24 33827985 ps
T1291 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1846020098 Jul 22 06:08:33 PM PDT 24 Jul 22 06:08:34 PM PDT 24 20071646 ps
T1292 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1602052901 Jul 22 06:08:49 PM PDT 24 Jul 22 06:08:50 PM PDT 24 22741293 ps
T1293 /workspace/coverage/cover_reg_top/44.uart_intr_test.348692388 Jul 22 06:09:21 PM PDT 24 Jul 22 06:09:22 PM PDT 24 16196150 ps
T1294 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3840323275 Jul 22 06:09:00 PM PDT 24 Jul 22 06:09:02 PM PDT 24 99940873 ps
T1295 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3918212528 Jul 22 06:08:20 PM PDT 24 Jul 22 06:08:21 PM PDT 24 47492202 ps
T1296 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1337600030 Jul 22 06:08:25 PM PDT 24 Jul 22 06:08:26 PM PDT 24 77077983 ps
T1297 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1513392669 Jul 22 06:08:23 PM PDT 24 Jul 22 06:08:24 PM PDT 24 48214229 ps
T1298 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1874545809 Jul 22 06:09:02 PM PDT 24 Jul 22 06:09:03 PM PDT 24 96152838 ps
T1299 /workspace/coverage/cover_reg_top/48.uart_intr_test.4214344024 Jul 22 06:09:19 PM PDT 24 Jul 22 06:09:20 PM PDT 24 25290809 ps
T1300 /workspace/coverage/cover_reg_top/6.uart_tl_errors.435888762 Jul 22 06:08:40 PM PDT 24 Jul 22 06:08:41 PM PDT 24 168932008 ps
T1301 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2763628274 Jul 22 06:08:28 PM PDT 24 Jul 22 06:08:29 PM PDT 24 74363843 ps
T1302 /workspace/coverage/cover_reg_top/41.uart_intr_test.3881157719 Jul 22 06:09:22 PM PDT 24 Jul 22 06:09:24 PM PDT 24 11584647 ps
T1303 /workspace/coverage/cover_reg_top/9.uart_intr_test.3945941951 Jul 22 06:08:48 PM PDT 24 Jul 22 06:08:49 PM PDT 24 48173591 ps
T1304 /workspace/coverage/cover_reg_top/30.uart_intr_test.1106133048 Jul 22 06:09:22 PM PDT 24 Jul 22 06:09:24 PM PDT 24 41189785 ps
T1305 /workspace/coverage/cover_reg_top/19.uart_csr_rw.43087818 Jul 22 06:09:13 PM PDT 24 Jul 22 06:09:14 PM PDT 24 31156943 ps
T1306 /workspace/coverage/cover_reg_top/5.uart_tl_errors.712395698 Jul 22 06:08:34 PM PDT 24 Jul 22 06:08:36 PM PDT 24 122626680 ps
T1307 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.821133783 Jul 22 06:09:37 PM PDT 24 Jul 22 06:09:38 PM PDT 24 19050612 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_csr_rw.909109280 Jul 22 06:09:12 PM PDT 24 Jul 22 06:09:13 PM PDT 24 17687615 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4021959095 Jul 22 06:09:13 PM PDT 24 Jul 22 06:09:14 PM PDT 24 28844870 ps
T1310 /workspace/coverage/cover_reg_top/39.uart_intr_test.1446547760 Jul 22 06:09:21 PM PDT 24 Jul 22 06:09:22 PM PDT 24 24704495 ps
T1311 /workspace/coverage/cover_reg_top/4.uart_csr_rw.4142454663 Jul 22 06:08:39 PM PDT 24 Jul 22 06:08:40 PM PDT 24 36706180 ps
T1312 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.677795014 Jul 22 06:08:12 PM PDT 24 Jul 22 06:08:13 PM PDT 24 21770880 ps
T1313 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3653234435 Jul 22 06:09:02 PM PDT 24 Jul 22 06:09:03 PM PDT 24 58485422 ps
T1314 /workspace/coverage/cover_reg_top/18.uart_intr_test.2118638410 Jul 22 06:09:13 PM PDT 24 Jul 22 06:09:14 PM PDT 24 21656519 ps
T1315 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.851540094 Jul 22 06:08:23 PM PDT 24 Jul 22 06:08:25 PM PDT 24 57478966 ps

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1148622476
Short name T7
Test name
Test status
Simulation time 152873953800 ps
CPU time 784.9 seconds
Started Jul 22 06:13:06 PM PDT 24
Finished Jul 22 06:26:11 PM PDT 24
Peak memory 216924 kb
Host smart-4238a00f-ca06-4410-804c-53cbcd737309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148622476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1148622476
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2741618968
Short name T30
Test name
Test status
Simulation time 521035379987 ps
CPU time 1988.2 seconds
Started Jul 22 06:15:04 PM PDT 24
Finished Jul 22 06:48:13 PM PDT 24
Peak memory 233128 kb
Host smart-1eff547e-ca01-48b6-a3fb-77204e4056b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741618968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2741618968
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.3206431300
Short name T17
Test name
Test status
Simulation time 378728595807 ps
CPU time 267.58 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 200228 kb
Host smart-db08e7bd-e278-4350-a36c-1bf01a395fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206431300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3206431300
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1004278613
Short name T18
Test name
Test status
Simulation time 640840395723 ps
CPU time 797.19 seconds
Started Jul 22 06:14:01 PM PDT 24
Finished Jul 22 06:27:19 PM PDT 24
Peak memory 216812 kb
Host smart-bad1907a-ab70-458a-a064-941d132a5ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004278613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1004278613
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2798838749
Short name T26
Test name
Test status
Simulation time 494502554549 ps
CPU time 1743.57 seconds
Started Jul 22 06:15:02 PM PDT 24
Finished Jul 22 06:44:06 PM PDT 24
Peak memory 225228 kb
Host smart-8d2e67cc-1e4b-47df-bfbb-b3d3e9a92ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798838749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2798838749
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1098054047
Short name T46
Test name
Test status
Simulation time 1126742964772 ps
CPU time 949.64 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:28:41 PM PDT 24
Peak memory 231256 kb
Host smart-3c427754-1f68-49af-b6b8-f9872a707737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098054047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1098054047
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2099783551
Short name T23
Test name
Test status
Simulation time 132498956 ps
CPU time 0.75 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:11:13 PM PDT 24
Peak memory 218364 kb
Host smart-25fcac98-4acb-4a6f-a014-df2aac79e2f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099783551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2099783551
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/43.uart_stress_all.1965137216
Short name T103
Test name
Test status
Simulation time 455190423087 ps
CPU time 271.13 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 200212 kb
Host smart-7b63faa3-34cd-4246-8b3f-141e2e0e701c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965137216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1965137216
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.343590667
Short name T2
Test name
Test status
Simulation time 54980567066 ps
CPU time 274.22 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:16:25 PM PDT 24
Peak memory 200228 kb
Host smart-97fc7767-c30d-4e8c-a9aa-03fe6f847c18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343590667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.343590667
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2738346744
Short name T141
Test name
Test status
Simulation time 347775659519 ps
CPU time 157.58 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 200136 kb
Host smart-352fcc5b-3f01-4797-a0c8-da4ea038a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738346744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2738346744
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_stress_all.1512799537
Short name T268
Test name
Test status
Simulation time 314781561891 ps
CPU time 787.63 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:24:34 PM PDT 24
Peak memory 200136 kb
Host smart-eec95ab9-f29b-475e-a1f3-c0ce85a1f7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512799537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1512799537
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.1622870678
Short name T66
Test name
Test status
Simulation time 423655474570 ps
CPU time 227.89 seconds
Started Jul 22 06:13:06 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 200224 kb
Host smart-a78f3449-d2cc-42f2-ab39-81b5e006cd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622870678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1622870678
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.330363789
Short name T55
Test name
Test status
Simulation time 38218802 ps
CPU time 0.57 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 196312 kb
Host smart-7eaee5b4-96a9-45b7-a770-7b18edbd7e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330363789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.330363789
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2124847202
Short name T79
Test name
Test status
Simulation time 86595802 ps
CPU time 1.26 seconds
Started Jul 22 06:08:30 PM PDT 24
Finished Jul 22 06:08:32 PM PDT 24
Peak memory 200024 kb
Host smart-fa6dfebd-da2c-4759-9460-6906e33e0e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124847202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2124847202
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3160864761
Short name T28
Test name
Test status
Simulation time 12799207659 ps
CPU time 112.57 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:15:15 PM PDT 24
Peak memory 215752 kb
Host smart-d11c865d-c1b8-4144-b915-b6a42ba543ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160864761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3160864761
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.201889073
Short name T128
Test name
Test status
Simulation time 149067787110 ps
CPU time 394.25 seconds
Started Jul 22 06:14:53 PM PDT 24
Finished Jul 22 06:21:28 PM PDT 24
Peak memory 216688 kb
Host smart-3f09ba16-4584-47ab-a914-a39c01c7209e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201889073 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.201889073
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.915202610
Short name T315
Test name
Test status
Simulation time 12197447 ps
CPU time 0.57 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:11:13 PM PDT 24
Peak memory 195644 kb
Host smart-e4085069-f649-43d9-975d-8018f7c30e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915202610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.915202610
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2043255707
Short name T129
Test name
Test status
Simulation time 232341521729 ps
CPU time 98.24 seconds
Started Jul 22 06:16:05 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 200208 kb
Host smart-cde702e2-e0f3-441a-ae73-671e6e4305dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043255707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2043255707
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3852592759
Short name T196
Test name
Test status
Simulation time 127558791117 ps
CPU time 88.9 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 200184 kb
Host smart-51dbc3f3-38f3-4d92-8cd1-542a87531e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852592759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3852592759
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1870463578
Short name T158
Test name
Test status
Simulation time 206825214180 ps
CPU time 175.09 seconds
Started Jul 22 06:11:51 PM PDT 24
Finished Jul 22 06:14:47 PM PDT 24
Peak memory 200264 kb
Host smart-72e070e0-d8bf-4f27-a670-21b5c41cffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870463578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1870463578
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1284972592
Short name T167
Test name
Test status
Simulation time 59499219013 ps
CPU time 346.68 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:20:29 PM PDT 24
Peak memory 216820 kb
Host smart-fc0c8e36-93f1-4dd0-b56b-546515d1359f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284972592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1284972592
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2674050130
Short name T44
Test name
Test status
Simulation time 97011339030 ps
CPU time 61.99 seconds
Started Jul 22 06:15:24 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200152 kb
Host smart-088fe2f6-2b1a-43e6-9f5a-f960ed1f2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674050130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2674050130
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3873749050
Short name T83
Test name
Test status
Simulation time 92029672 ps
CPU time 1.29 seconds
Started Jul 22 06:09:03 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 200268 kb
Host smart-588b4c8e-0377-43d3-9dc3-dba9065df8de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873749050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3873749050
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4084101771
Short name T281
Test name
Test status
Simulation time 240946948109 ps
CPU time 150.59 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:14:08 PM PDT 24
Peak memory 200200 kb
Host smart-59a0206c-3d28-413a-ab92-3124a780295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084101771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4084101771
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4165737315
Short name T144
Test name
Test status
Simulation time 322290347493 ps
CPU time 1291.33 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:35:27 PM PDT 24
Peak memory 232916 kb
Host smart-a8eab3a2-9a6b-4bbc-a08c-db71a015c417
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165737315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4165737315
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2452132758
Short name T173
Test name
Test status
Simulation time 203998266462 ps
CPU time 167.72 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:18:38 PM PDT 24
Peak memory 200260 kb
Host smart-5d0e3a93-6df2-4adb-964f-c13c4a6dac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452132758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2452132758
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3519216180
Short name T252
Test name
Test status
Simulation time 40230943229 ps
CPU time 23.74 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:15:37 PM PDT 24
Peak memory 200200 kb
Host smart-13d0f9aa-2169-400d-9085-ea9ff837f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519216180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3519216180
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3711432612
Short name T176
Test name
Test status
Simulation time 102876828696 ps
CPU time 195.58 seconds
Started Jul 22 06:15:14 PM PDT 24
Finished Jul 22 06:18:30 PM PDT 24
Peak memory 200348 kb
Host smart-5cc1553f-0ec7-4b19-841e-3aec790aa568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711432612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3711432612
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_perf.725667628
Short name T245
Test name
Test status
Simulation time 23315192160 ps
CPU time 627.85 seconds
Started Jul 22 06:12:03 PM PDT 24
Finished Jul 22 06:22:31 PM PDT 24
Peak memory 200188 kb
Host smart-711b7e1a-e0b9-4a32-a1d1-8803facf60bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725667628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.725667628
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1840073964
Short name T109
Test name
Test status
Simulation time 56830500186 ps
CPU time 849.71 seconds
Started Jul 22 06:14:16 PM PDT 24
Finished Jul 22 06:28:27 PM PDT 24
Peak memory 216916 kb
Host smart-b1309c81-e5f9-450c-9b4d-ceedd55575ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840073964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1840073964
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2529651869
Short name T115
Test name
Test status
Simulation time 62746571295 ps
CPU time 43.71 seconds
Started Jul 22 06:11:51 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 200264 kb
Host smart-95a57a66-93ad-4531-adb4-1d9f440a8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529651869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2529651869
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2462607823
Short name T205
Test name
Test status
Simulation time 62893056674 ps
CPU time 25.21 seconds
Started Jul 22 06:15:26 PM PDT 24
Finished Jul 22 06:15:52 PM PDT 24
Peak memory 200236 kb
Host smart-27292b69-413f-4f4a-b2fb-10b3d28df170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462607823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2462607823
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.2247714511
Short name T630
Test name
Test status
Simulation time 175722460004 ps
CPU time 1180.82 seconds
Started Jul 22 06:12:32 PM PDT 24
Finished Jul 22 06:32:14 PM PDT 24
Peak memory 200088 kb
Host smart-97b6eb17-ca38-4dda-8839-b2d91a7bb432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247714511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2247714511
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2459306189
Short name T106
Test name
Test status
Simulation time 126326828083 ps
CPU time 28.08 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 200180 kb
Host smart-7a268705-f9dd-4970-ac91-60f2e288f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459306189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2459306189
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3892266595
Short name T162
Test name
Test status
Simulation time 95078612124 ps
CPU time 161.7 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:19:00 PM PDT 24
Peak memory 200224 kb
Host smart-f0f0789f-8bd9-41bf-9f40-48af16216bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892266595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3892266595
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3488854598
Short name T185
Test name
Test status
Simulation time 197003275756 ps
CPU time 567.37 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:24:22 PM PDT 24
Peak memory 228892 kb
Host smart-684bc1ae-2bcc-4d3c-a718-113eb187fa22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488854598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3488854598
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.364282620
Short name T62
Test name
Test status
Simulation time 209681401851 ps
CPU time 459.76 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:20:16 PM PDT 24
Peak memory 200188 kb
Host smart-7fd4607c-ad61-4b09-a167-46e5e2fbcc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364282620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.364282620
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4215926241
Short name T166
Test name
Test status
Simulation time 195353679044 ps
CPU time 104.31 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:18:01 PM PDT 24
Peak memory 200256 kb
Host smart-d14037f9-2558-47c5-b8f0-55bf3769fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215926241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4215926241
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2723510473
Short name T213
Test name
Test status
Simulation time 11618575462 ps
CPU time 18.6 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:01 PM PDT 24
Peak memory 200172 kb
Host smart-ead0a874-bd78-42c1-968e-fc72dc9b9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723510473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2723510473
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4114036383
Short name T126
Test name
Test status
Simulation time 38044171651 ps
CPU time 31.5 seconds
Started Jul 22 06:16:06 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 200136 kb
Host smart-f916e48d-d94e-4971-8d16-349fa6b87053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114036383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4114036383
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.851653038
Short name T192
Test name
Test status
Simulation time 88196513729 ps
CPU time 464.81 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:22:34 PM PDT 24
Peak memory 216832 kb
Host smart-46f81edd-ce57-446d-8505-8b9e0b24b6a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851653038 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.851653038
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1574629315
Short name T292
Test name
Test status
Simulation time 131477833087 ps
CPU time 1460.8 seconds
Started Jul 22 06:15:08 PM PDT 24
Finished Jul 22 06:39:29 PM PDT 24
Peak memory 228072 kb
Host smart-5ab0413a-6215-4e41-be5b-d05bb402c7da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574629315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1574629315
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.384945608
Short name T199
Test name
Test status
Simulation time 53814673154 ps
CPU time 133.01 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:17:20 PM PDT 24
Peak memory 200188 kb
Host smart-ac1662bf-0b5f-4fdf-9d05-1a0daa10cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384945608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.384945608
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1738083131
Short name T270
Test name
Test status
Simulation time 39096500572 ps
CPU time 32.41 seconds
Started Jul 22 06:11:52 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 200256 kb
Host smart-191d9058-1ad1-452d-998a-76e1cd4ab255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738083131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1738083131
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.522924778
Short name T236
Test name
Test status
Simulation time 41218403670 ps
CPU time 15.8 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:15:30 PM PDT 24
Peak memory 200080 kb
Host smart-0ae7f64e-515a-4fb3-932c-b388a5b0ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522924778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.522924778
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4154741247
Short name T161
Test name
Test status
Simulation time 19589533394 ps
CPU time 9.39 seconds
Started Jul 22 06:15:24 PM PDT 24
Finished Jul 22 06:15:34 PM PDT 24
Peak memory 200036 kb
Host smart-058039fc-12ba-4430-b594-24486ccd98fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154741247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4154741247
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.909083468
Short name T6
Test name
Test status
Simulation time 33925596603 ps
CPU time 14.26 seconds
Started Jul 22 06:16:09 PM PDT 24
Finished Jul 22 06:16:24 PM PDT 24
Peak memory 200240 kb
Host smart-45cb28c8-ea62-4512-89f9-8648e65940a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909083468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.909083468
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2105699596
Short name T233
Test name
Test status
Simulation time 22393682444 ps
CPU time 30.96 seconds
Started Jul 22 06:13:35 PM PDT 24
Finished Jul 22 06:14:06 PM PDT 24
Peak memory 200224 kb
Host smart-8135374c-9964-48cb-b946-a6bf6f88ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105699596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2105699596
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2720838583
Short name T284
Test name
Test status
Simulation time 64204082347 ps
CPU time 638.63 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:25:28 PM PDT 24
Peak memory 216724 kb
Host smart-61749b3c-987a-4f01-8c8e-97f1f513960a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720838583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2720838583
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2192725232
Short name T367
Test name
Test status
Simulation time 193345010428 ps
CPU time 187.74 seconds
Started Jul 22 06:16:30 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 200264 kb
Host smart-47130793-dca9-4444-8874-9f81e4a47ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192725232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2192725232
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.162362666
Short name T617
Test name
Test status
Simulation time 160612039279 ps
CPU time 525.76 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:20:36 PM PDT 24
Peak memory 216892 kb
Host smart-751adc6d-d688-41db-8611-299660e4247e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162362666 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.162362666
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1602743883
Short name T249
Test name
Test status
Simulation time 67551054150 ps
CPU time 46.95 seconds
Started Jul 22 06:15:17 PM PDT 24
Finished Jul 22 06:16:04 PM PDT 24
Peak memory 199948 kb
Host smart-e221330f-342d-495b-b124-5b119288e35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602743883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1602743883
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3576092853
Short name T190
Test name
Test status
Simulation time 217692053871 ps
CPU time 94.88 seconds
Started Jul 22 06:15:17 PM PDT 24
Finished Jul 22 06:16:53 PM PDT 24
Peak memory 200208 kb
Host smart-bc6736f0-a3f5-4476-9f0e-ed9421afdbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576092853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3576092853
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3134709441
Short name T145
Test name
Test status
Simulation time 118334365504 ps
CPU time 50.42 seconds
Started Jul 22 06:12:01 PM PDT 24
Finished Jul 22 06:12:52 PM PDT 24
Peak memory 200252 kb
Host smart-7f4192fd-4450-4dad-80b2-b682bc0a62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134709441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3134709441
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2656932628
Short name T220
Test name
Test status
Simulation time 24409315941 ps
CPU time 35.91 seconds
Started Jul 22 06:15:58 PM PDT 24
Finished Jul 22 06:16:35 PM PDT 24
Peak memory 200252 kb
Host smart-3449246f-4639-4f32-914e-d8f3abb1b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656932628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2656932628
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.989938060
Short name T203
Test name
Test status
Simulation time 26059355807 ps
CPU time 12.12 seconds
Started Jul 22 06:15:31 PM PDT 24
Finished Jul 22 06:15:44 PM PDT 24
Peak memory 200228 kb
Host smart-c501b277-b103-425d-a07d-65aa89147366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989938060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.989938060
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2107021207
Short name T221
Test name
Test status
Simulation time 106679364975 ps
CPU time 193.32 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:15:39 PM PDT 24
Peak memory 216172 kb
Host smart-6d2d75fa-3b83-4c50-b2f9-f5ca54356f1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107021207 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2107021207
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2862360912
Short name T230
Test name
Test status
Simulation time 36973285864 ps
CPU time 62.24 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:45 PM PDT 24
Peak memory 200200 kb
Host smart-4b79f6f5-67ad-4c33-ba21-08b67d6eda5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862360912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2862360912
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2702754759
Short name T232
Test name
Test status
Simulation time 71692906791 ps
CPU time 31.21 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:13 PM PDT 24
Peak memory 200148 kb
Host smart-fc6fb71b-13f9-40f6-907f-c7299025b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702754759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2702754759
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.690486130
Short name T229
Test name
Test status
Simulation time 55335606423 ps
CPU time 90.23 seconds
Started Jul 22 06:16:14 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 200260 kb
Host smart-f361d713-31ea-4100-87a9-d4dc80748740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690486130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.690486130
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1768937595
Short name T211
Test name
Test status
Simulation time 11205239338 ps
CPU time 20.47 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 200128 kb
Host smart-cebc8439-dfee-4101-aaa1-baa9a3ddf083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768937595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1768937595
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2840739221
Short name T228
Test name
Test status
Simulation time 195373619699 ps
CPU time 31.31 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 200204 kb
Host smart-51c4d21a-666f-414d-8e09-05cc7d64bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840739221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2840739221
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2119813546
Short name T239
Test name
Test status
Simulation time 108422575335 ps
CPU time 10.48 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200172 kb
Host smart-b9367dd8-0055-4da5-aa8f-0aee72c89b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119813546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2119813546
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.4285428935
Short name T216
Test name
Test status
Simulation time 366708272132 ps
CPU time 566.92 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 200228 kb
Host smart-6bcee406-513a-49a6-a0ee-9c6b804524b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285428935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4285428935
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3608748634
Short name T225
Test name
Test status
Simulation time 23217368982 ps
CPU time 16.05 seconds
Started Jul 22 06:14:33 PM PDT 24
Finished Jul 22 06:14:50 PM PDT 24
Peak memory 200048 kb
Host smart-f4618315-2451-493d-b238-81e1fbb20bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608748634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3608748634
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2334335287
Short name T226
Test name
Test status
Simulation time 142612283517 ps
CPU time 111.71 seconds
Started Jul 22 06:14:10 PM PDT 24
Finished Jul 22 06:16:03 PM PDT 24
Peak memory 200252 kb
Host smart-f15c7841-c2fc-4349-9a7c-21ba0805b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334335287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2334335287
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1720619430
Short name T130
Test name
Test status
Simulation time 152462232376 ps
CPU time 41.22 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:15:45 PM PDT 24
Peak memory 200084 kb
Host smart-02157618-4422-43ee-822e-e86b81ac9833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720619430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1720619430
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3909984199
Short name T222
Test name
Test status
Simulation time 22868475788 ps
CPU time 19.52 seconds
Started Jul 22 06:15:04 PM PDT 24
Finished Jul 22 06:15:24 PM PDT 24
Peak memory 200244 kb
Host smart-9b89695a-6306-49ce-ad75-3fdd25c2047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909984199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3909984199
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1808589114
Short name T1252
Test name
Test status
Simulation time 70735669 ps
CPU time 0.64 seconds
Started Jul 22 06:08:13 PM PDT 24
Finished Jul 22 06:08:14 PM PDT 24
Peak memory 195720 kb
Host smart-8f0aa6d9-21fc-4902-81d7-945845d1c71a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808589114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1808589114
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3071222452
Short name T1224
Test name
Test status
Simulation time 95478645 ps
CPU time 1.44 seconds
Started Jul 22 06:08:13 PM PDT 24
Finished Jul 22 06:08:15 PM PDT 24
Peak memory 198560 kb
Host smart-ba0ca418-b7e3-42a2-ab2b-49b4448a4c36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071222452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3071222452
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.677795014
Short name T1312
Test name
Test status
Simulation time 21770880 ps
CPU time 0.57 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 196300 kb
Host smart-f34e01f1-8475-49c0-b99d-ba72c04546ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677795014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.677795014
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.660913222
Short name T1237
Test name
Test status
Simulation time 360740544 ps
CPU time 1.08 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 200960 kb
Host smart-717dbc89-bb27-4016-adc2-31a1d901d422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660913222 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.660913222
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.452496403
Short name T70
Test name
Test status
Simulation time 42993100 ps
CPU time 0.57 seconds
Started Jul 22 06:08:25 PM PDT 24
Finished Jul 22 06:08:26 PM PDT 24
Peak memory 196392 kb
Host smart-921a7a51-fe7d-47d7-b127-df376eba431c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452496403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.452496403
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2851036498
Short name T1254
Test name
Test status
Simulation time 22666590 ps
CPU time 0.56 seconds
Started Jul 22 06:08:11 PM PDT 24
Finished Jul 22 06:08:12 PM PDT 24
Peak memory 195272 kb
Host smart-9585f9e1-df78-4a44-8cce-78ce4d6f63d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851036498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2851036498
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1505689519
Short name T1234
Test name
Test status
Simulation time 14072220 ps
CPU time 0.62 seconds
Started Jul 22 06:08:13 PM PDT 24
Finished Jul 22 06:08:15 PM PDT 24
Peak memory 196320 kb
Host smart-a957d2b2-374d-4073-95e5-121ec7e5b038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505689519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1505689519
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3289239606
Short name T1222
Test name
Test status
Simulation time 46212770 ps
CPU time 1.34 seconds
Started Jul 22 06:08:13 PM PDT 24
Finished Jul 22 06:08:15 PM PDT 24
Peak memory 200928 kb
Host smart-0e4cd0f1-2edc-4d87-9d77-6d73c4cb399d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289239606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3289239606
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2746372415
Short name T110
Test name
Test status
Simulation time 217534300 ps
CPU time 0.95 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:08:30 PM PDT 24
Peak memory 199688 kb
Host smart-574088c6-dcbf-4beb-8d4e-bafde405160f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746372415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2746372415
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2839494094
Short name T60
Test name
Test status
Simulation time 70848811 ps
CPU time 0.64 seconds
Started Jul 22 06:08:48 PM PDT 24
Finished Jul 22 06:08:49 PM PDT 24
Peak memory 195660 kb
Host smart-c857f8bf-d052-4d73-8a98-2cf9e9a746bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839494094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2839494094
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.851540094
Short name T1315
Test name
Test status
Simulation time 57478966 ps
CPU time 2.18 seconds
Started Jul 22 06:08:23 PM PDT 24
Finished Jul 22 06:08:25 PM PDT 24
Peak memory 198584 kb
Host smart-9e85f858-26f5-495a-88bf-48718ed4cd8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851540094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.851540094
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3918212528
Short name T1295
Test name
Test status
Simulation time 47492202 ps
CPU time 0.6 seconds
Started Jul 22 06:08:20 PM PDT 24
Finished Jul 22 06:08:21 PM PDT 24
Peak memory 196544 kb
Host smart-a574655d-a246-4693-aeb7-84c1bd68b264
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918212528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3918212528
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1337600030
Short name T1296
Test name
Test status
Simulation time 77077983 ps
CPU time 0.67 seconds
Started Jul 22 06:08:25 PM PDT 24
Finished Jul 22 06:08:26 PM PDT 24
Peak memory 198808 kb
Host smart-3b63cb2a-d381-4328-8831-09d011e575be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337600030 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1337600030
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2389477252
Short name T57
Test name
Test status
Simulation time 17764734 ps
CPU time 0.6 seconds
Started Jul 22 06:08:24 PM PDT 24
Finished Jul 22 06:08:25 PM PDT 24
Peak memory 196616 kb
Host smart-510fa082-1b26-4922-bc31-cb6a18066181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389477252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2389477252
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1624323507
Short name T1244
Test name
Test status
Simulation time 22056739 ps
CPU time 0.56 seconds
Started Jul 22 06:08:22 PM PDT 24
Finished Jul 22 06:08:23 PM PDT 24
Peak memory 195232 kb
Host smart-71da1b84-fae2-4445-ad34-45d1b74e687f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624323507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1624323507
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1513392669
Short name T1297
Test name
Test status
Simulation time 48214229 ps
CPU time 0.72 seconds
Started Jul 22 06:08:23 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 197888 kb
Host smart-66efbdaf-8d59-4dce-9c41-76f274b966b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513392669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1513392669
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3584038127
Short name T1190
Test name
Test status
Simulation time 51600450 ps
CPU time 1.41 seconds
Started Jul 22 06:08:11 PM PDT 24
Finished Jul 22 06:08:12 PM PDT 24
Peak memory 200912 kb
Host smart-12b63277-efca-48db-87ec-70886045f00f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584038127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3584038127
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2897768377
Short name T85
Test name
Test status
Simulation time 279613465 ps
CPU time 1.22 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:08:30 PM PDT 24
Peak memory 200220 kb
Host smart-f46d33e1-7ea5-42c1-9513-681e4eebabcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897768377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2897768377
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4064334318
Short name T1181
Test name
Test status
Simulation time 34418390 ps
CPU time 0.78 seconds
Started Jul 22 06:09:17 PM PDT 24
Finished Jul 22 06:09:19 PM PDT 24
Peak memory 200548 kb
Host smart-6f5e1a27-4dcb-4ffb-86e7-ddc2350ffc97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064334318 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4064334318
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2625004738
Short name T1218
Test name
Test status
Simulation time 58635144 ps
CPU time 0.59 seconds
Started Jul 22 06:09:05 PM PDT 24
Finished Jul 22 06:09:06 PM PDT 24
Peak memory 195164 kb
Host smart-6bf060a5-0056-421d-8b85-f9c732c92754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625004738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2625004738
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3508270562
Short name T1225
Test name
Test status
Simulation time 14104530 ps
CPU time 0.54 seconds
Started Jul 22 06:09:23 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195184 kb
Host smart-a83e8607-1ac2-481a-bf92-a0b7e17225c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508270562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3508270562
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2757567413
Short name T1226
Test name
Test status
Simulation time 152024996 ps
CPU time 0.73 seconds
Started Jul 22 06:09:05 PM PDT 24
Finished Jul 22 06:09:06 PM PDT 24
Peak memory 196772 kb
Host smart-69cd61fb-89a7-489d-a1b0-099dd5d42fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757567413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2757567413
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1109907934
Short name T1189
Test name
Test status
Simulation time 45929646 ps
CPU time 1.39 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:15 PM PDT 24
Peak memory 200896 kb
Host smart-14f640db-79c3-49c6-b49a-12bb0e6a115d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109907934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1109907934
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.321785670
Short name T1206
Test name
Test status
Simulation time 18657476 ps
CPU time 0.78 seconds
Started Jul 22 06:09:17 PM PDT 24
Finished Jul 22 06:09:19 PM PDT 24
Peak memory 200276 kb
Host smart-a25d089b-036d-446b-813e-339ab51356d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321785670 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.321785670
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.960656613
Short name T1215
Test name
Test status
Simulation time 45873213 ps
CPU time 0.59 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 196304 kb
Host smart-b867a07b-f4c3-4f0a-b91c-fbe301951eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960656613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.960656613
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.556241168
Short name T1201
Test name
Test status
Simulation time 27474279 ps
CPU time 0.58 seconds
Started Jul 22 06:09:03 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 195308 kb
Host smart-056af494-2d31-40e6-9bcb-d6e559848a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556241168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.556241168
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.740128507
Short name T1223
Test name
Test status
Simulation time 32917538 ps
CPU time 0.72 seconds
Started Jul 22 06:09:01 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 197756 kb
Host smart-c26aa1b5-e29d-481e-bdf6-af4c6be775d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740128507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.740128507
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2766833189
Short name T1262
Test name
Test status
Simulation time 92441786 ps
CPU time 0.96 seconds
Started Jul 22 06:09:01 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 200664 kb
Host smart-b40e6a3a-8139-49dc-9dd4-6d90295b2abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766833189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2766833189
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2955678090
Short name T81
Test name
Test status
Simulation time 162616372 ps
CPU time 1.29 seconds
Started Jul 22 06:09:04 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 200316 kb
Host smart-461c2cf5-6d12-4de6-a816-54614cfec8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955678090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2955678090
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1177650808
Short name T1210
Test name
Test status
Simulation time 55766077 ps
CPU time 0.95 seconds
Started Jul 22 06:09:05 PM PDT 24
Finished Jul 22 06:09:07 PM PDT 24
Peak memory 200708 kb
Host smart-e53bac0f-dc46-418d-9a91-22118b0dd4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177650808 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1177650808
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2320894569
Short name T73
Test name
Test status
Simulation time 115959098 ps
CPU time 0.62 seconds
Started Jul 22 06:09:01 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 196332 kb
Host smart-1f8d0d1e-e89e-405a-bacd-e02b6f733f15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320894569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2320894569
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2454050624
Short name T1196
Test name
Test status
Simulation time 14918514 ps
CPU time 0.57 seconds
Started Jul 22 06:09:09 PM PDT 24
Finished Jul 22 06:09:10 PM PDT 24
Peak memory 195300 kb
Host smart-839ff739-5f98-44b4-a8d7-7926c50f821f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454050624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2454050624
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3223830926
Short name T71
Test name
Test status
Simulation time 15322327 ps
CPU time 0.64 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 196608 kb
Host smart-adc28fca-dd54-4029-ae6b-3804efe45815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223830926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3223830926
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1576477881
Short name T1203
Test name
Test status
Simulation time 37031027 ps
CPU time 0.99 seconds
Started Jul 22 06:09:03 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 200696 kb
Host smart-b3640bd7-cbc1-437c-8dce-e0d1987b87a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576477881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1576477881
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2948131024
Short name T1279
Test name
Test status
Simulation time 256694435 ps
CPU time 1.24 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 200276 kb
Host smart-cfd70b7c-a70f-491b-bbde-805473df0511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948131024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2948131024
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3345428458
Short name T1283
Test name
Test status
Simulation time 59545790 ps
CPU time 0.88 seconds
Started Jul 22 06:09:03 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 200736 kb
Host smart-b5c0285e-9a31-45ce-b833-536bc3432d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345428458 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3345428458
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.429105288
Short name T75
Test name
Test status
Simulation time 13793168 ps
CPU time 0.57 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 196312 kb
Host smart-cc8629af-dae7-4dd8-9c78-b76282477905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429105288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.429105288
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3809261988
Short name T1199
Test name
Test status
Simulation time 53458923 ps
CPU time 0.57 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 195304 kb
Host smart-8a31bda5-e7ac-4482-b452-29b889916e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809261988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3809261988
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4041924619
Short name T1240
Test name
Test status
Simulation time 24134715 ps
CPU time 0.62 seconds
Started Jul 22 06:09:05 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 196628 kb
Host smart-e5769870-a42f-4e8d-8ebe-c2fd973ade54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041924619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4041924619
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4181873215
Short name T1250
Test name
Test status
Simulation time 138929018 ps
CPU time 1.36 seconds
Started Jul 22 06:09:01 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 201028 kb
Host smart-5ac5c0d5-687b-40a0-8fad-bbc0eb7c1752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181873215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4181873215
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2425788246
Short name T82
Test name
Test status
Simulation time 263489629 ps
CPU time 1.28 seconds
Started Jul 22 06:09:04 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 200140 kb
Host smart-952b53cb-6abb-4227-9770-c7c72d4a4d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425788246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2425788246
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.821133783
Short name T1307
Test name
Test status
Simulation time 19050612 ps
CPU time 0.78 seconds
Started Jul 22 06:09:37 PM PDT 24
Finished Jul 22 06:09:38 PM PDT 24
Peak memory 200616 kb
Host smart-6d69b188-29fa-43f8-8edf-8c96b8a12a1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821133783 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.821133783
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1237722559
Short name T1243
Test name
Test status
Simulation time 43432678 ps
CPU time 0.65 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 196300 kb
Host smart-9692ae82-93cb-4b9b-a56a-4a2380200338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237722559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1237722559
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.268709101
Short name T1276
Test name
Test status
Simulation time 16041477 ps
CPU time 0.57 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 195340 kb
Host smart-226eed77-3418-41a1-b4a9-b10e3f244e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268709101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.268709101
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3577354260
Short name T1204
Test name
Test status
Simulation time 77083134 ps
CPU time 0.61 seconds
Started Jul 22 06:09:22 PM PDT 24
Finished Jul 22 06:09:23 PM PDT 24
Peak memory 196356 kb
Host smart-d5b9e821-3072-4aaa-905a-5bed866803d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577354260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3577354260
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3840323275
Short name T1294
Test name
Test status
Simulation time 99940873 ps
CPU time 1.13 seconds
Started Jul 22 06:09:00 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 200880 kb
Host smart-4ab1ca33-6052-46cb-b27a-4de86c82e112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840323275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3840323275
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3653234435
Short name T1313
Test name
Test status
Simulation time 58485422 ps
CPU time 1.1 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 199892 kb
Host smart-1f12e445-a96a-4638-8871-c886b6f6db91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653234435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3653234435
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4021959095
Short name T1309
Test name
Test status
Simulation time 28844870 ps
CPU time 0.78 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 200572 kb
Host smart-af26e06e-e519-40d3-8791-12a3a8594dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021959095 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4021959095
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1709644756
Short name T1180
Test name
Test status
Simulation time 14381917 ps
CPU time 0.58 seconds
Started Jul 22 06:09:14 PM PDT 24
Finished Jul 22 06:09:15 PM PDT 24
Peak memory 195316 kb
Host smart-3b51366c-e1bf-4866-a33a-87e8eec91746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709644756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1709644756
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2368235980
Short name T72
Test name
Test status
Simulation time 94844617 ps
CPU time 0.75 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 198584 kb
Host smart-61cedd98-fb75-4878-a4d9-c1a70b4e608a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368235980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2368235980
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1948151611
Short name T1290
Test name
Test status
Simulation time 33827985 ps
CPU time 1.56 seconds
Started Jul 22 06:09:29 PM PDT 24
Finished Jul 22 06:09:31 PM PDT 24
Peak memory 200924 kb
Host smart-edacf041-18a3-4f3a-ba48-3afd86f2eb64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948151611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1948151611
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1005826140
Short name T1271
Test name
Test status
Simulation time 295370222 ps
CPU time 1.35 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 200396 kb
Host smart-d373d30a-c54a-472a-a74c-5b47a998a107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005826140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1005826140
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1701223550
Short name T1249
Test name
Test status
Simulation time 145050434 ps
CPU time 0.79 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 200560 kb
Host smart-5ff9bce6-71fd-4af0-a4ea-8f340949bb27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701223550 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1701223550
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.909109280
Short name T1308
Test name
Test status
Simulation time 17687615 ps
CPU time 0.61 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 196308 kb
Host smart-ad96455c-b441-458d-8861-5abe697e2bcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909109280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.909109280
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2934470116
Short name T1187
Test name
Test status
Simulation time 15333682 ps
CPU time 0.59 seconds
Started Jul 22 06:09:37 PM PDT 24
Finished Jul 22 06:09:38 PM PDT 24
Peak memory 195224 kb
Host smart-80ff581e-07d6-4876-9ebb-595770066b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934470116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2934470116
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1498733412
Short name T1264
Test name
Test status
Simulation time 13496453 ps
CPU time 0.61 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:15 PM PDT 24
Peak memory 196632 kb
Host smart-be805860-b680-46aa-855a-6759075fc51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498733412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1498733412
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4024357460
Short name T1216
Test name
Test status
Simulation time 99978588 ps
CPU time 1.18 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 200648 kb
Host smart-43ec1b84-becc-4044-bb73-0d31ff6a4d54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024357460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4024357460
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3859677000
Short name T78
Test name
Test status
Simulation time 95788319 ps
CPU time 0.95 seconds
Started Jul 22 06:09:09 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 199836 kb
Host smart-5b40af14-a444-41f4-9945-5bd275339948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859677000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3859677000
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3570313601
Short name T1182
Test name
Test status
Simulation time 173152847 ps
CPU time 0.63 seconds
Started Jul 22 06:09:29 PM PDT 24
Finished Jul 22 06:09:30 PM PDT 24
Peak memory 198248 kb
Host smart-0a7121ef-1c49-4fc9-a406-b5e1b0c408d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570313601 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3570313601
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1203677991
Short name T1233
Test name
Test status
Simulation time 16604706 ps
CPU time 0.61 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 196308 kb
Host smart-f4750062-789d-4084-8330-542eb271d0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203677991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1203677991
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3575020862
Short name T1260
Test name
Test status
Simulation time 14528104 ps
CPU time 0.56 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 195068 kb
Host smart-03c8aaea-f151-4f73-bb11-8a4928214b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575020862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3575020862
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1301080744
Short name T1259
Test name
Test status
Simulation time 59936361 ps
CPU time 0.63 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 196768 kb
Host smart-3e515e03-3ee4-4375-bf6f-2ef797bdd5bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301080744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1301080744
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3861668989
Short name T1238
Test name
Test status
Simulation time 55920256 ps
CPU time 1.3 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 200956 kb
Host smart-ff0c209e-d821-47b0-98c2-781a7430132a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861668989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3861668989
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2574098954
Short name T77
Test name
Test status
Simulation time 441211628 ps
CPU time 1.27 seconds
Started Jul 22 06:09:31 PM PDT 24
Finished Jul 22 06:09:34 PM PDT 24
Peak memory 200132 kb
Host smart-a7a58c00-c7ae-40c8-a464-37372ddfd790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574098954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2574098954
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3035831728
Short name T1219
Test name
Test status
Simulation time 29735696 ps
CPU time 1.33 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 200952 kb
Host smart-99b92a4b-1982-4e2d-b106-bc56b443c72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035831728 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3035831728
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3913756895
Short name T1278
Test name
Test status
Simulation time 52026009 ps
CPU time 0.61 seconds
Started Jul 22 06:10:35 PM PDT 24
Finished Jul 22 06:10:37 PM PDT 24
Peak memory 196692 kb
Host smart-440a58dd-2af2-434d-984c-dc1e24a836b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913756895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3913756895
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2118638410
Short name T1314
Test name
Test status
Simulation time 21656519 ps
CPU time 0.58 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 195272 kb
Host smart-0b1a2ffb-0e87-4e6b-9b84-e1a3e4965650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118638410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2118638410
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1343542818
Short name T1242
Test name
Test status
Simulation time 14932168 ps
CPU time 0.64 seconds
Started Jul 22 06:09:48 PM PDT 24
Finished Jul 22 06:09:50 PM PDT 24
Peak memory 196448 kb
Host smart-769c954c-eb47-4968-a2d8-f99df106d586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343542818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1343542818
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1592470492
Short name T1286
Test name
Test status
Simulation time 212611858 ps
CPU time 2.04 seconds
Started Jul 22 06:10:32 PM PDT 24
Finished Jul 22 06:10:35 PM PDT 24
Peak memory 200956 kb
Host smart-828ca817-d5c8-4b40-bf8c-aadd819813d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592470492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1592470492
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3940472782
Short name T1239
Test name
Test status
Simulation time 42903186 ps
CPU time 0.9 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 199816 kb
Host smart-bfb607fa-ff86-4f0e-bb26-3e6a72b344c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940472782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3940472782
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1960033676
Short name T1241
Test name
Test status
Simulation time 39668811 ps
CPU time 0.74 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 200008 kb
Host smart-9afc61bd-0f75-4c8e-839b-8d968be3c41b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960033676 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1960033676
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.43087818
Short name T1305
Test name
Test status
Simulation time 31156943 ps
CPU time 0.6 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 196304 kb
Host smart-9add13f0-4802-4ef4-ae89-a5aaf3e28a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43087818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.43087818
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2810767757
Short name T1251
Test name
Test status
Simulation time 46775038 ps
CPU time 0.57 seconds
Started Jul 22 06:09:48 PM PDT 24
Finished Jul 22 06:09:49 PM PDT 24
Peak memory 195264 kb
Host smart-cea22d06-323c-482f-8a83-7bcbdbfb6232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810767757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2810767757
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1658609202
Short name T1211
Test name
Test status
Simulation time 60687876 ps
CPU time 0.73 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 198396 kb
Host smart-35138bfc-7efc-4dfd-922c-9962cbe6513a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658609202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1658609202
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2430367238
Short name T1197
Test name
Test status
Simulation time 37187017 ps
CPU time 1.68 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 200956 kb
Host smart-40f6d90a-8e89-43bb-8283-4790b8f78e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430367238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2430367238
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2878526205
Short name T1258
Test name
Test status
Simulation time 43384242 ps
CPU time 0.93 seconds
Started Jul 22 06:09:12 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 199944 kb
Host smart-0bb19bc9-ac3c-45a1-b781-8c0783752e35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878526205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2878526205
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3289910377
Short name T69
Test name
Test status
Simulation time 15656778 ps
CPU time 0.65 seconds
Started Jul 22 06:08:19 PM PDT 24
Finished Jul 22 06:08:20 PM PDT 24
Peak memory 195956 kb
Host smart-27442076-bb7a-4b56-9d85-95192f2d803c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289910377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3289910377
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2603901973
Short name T1200
Test name
Test status
Simulation time 64924998 ps
CPU time 1.4 seconds
Started Jul 22 06:08:59 PM PDT 24
Finished Jul 22 06:09:01 PM PDT 24
Peak memory 198668 kb
Host smart-b571ea99-f945-41ce-8b8a-ad598050bff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603901973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2603901973
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1604638303
Short name T1212
Test name
Test status
Simulation time 37603037 ps
CPU time 0.62 seconds
Started Jul 22 06:08:21 PM PDT 24
Finished Jul 22 06:08:22 PM PDT 24
Peak memory 196296 kb
Host smart-0f333a41-2a5f-45a3-adb3-259164a08c30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604638303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1604638303
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2378769305
Short name T1245
Test name
Test status
Simulation time 17485419 ps
CPU time 0.66 seconds
Started Jul 22 06:08:23 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 198852 kb
Host smart-f7d4a144-23d8-46cb-874e-8761e00d4e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378769305 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2378769305
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1469026205
Short name T54
Test name
Test status
Simulation time 54518684 ps
CPU time 0.61 seconds
Started Jul 22 06:08:24 PM PDT 24
Finished Jul 22 06:08:25 PM PDT 24
Peak memory 196232 kb
Host smart-42415c36-0c17-462f-98e5-13a12b9d2759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469026205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1469026205
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3745840726
Short name T1229
Test name
Test status
Simulation time 79093566 ps
CPU time 0.54 seconds
Started Jul 22 06:08:26 PM PDT 24
Finished Jul 22 06:08:27 PM PDT 24
Peak memory 195204 kb
Host smart-4a0efdd5-8c2d-4d94-a583-cf0a335a82d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745840726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3745840726
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2763628274
Short name T1301
Test name
Test status
Simulation time 74363843 ps
CPU time 0.62 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:08:29 PM PDT 24
Peak memory 196364 kb
Host smart-7faa2736-0fd6-4cdb-8a13-5b91cee33d50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763628274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2763628274
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3525569363
Short name T1253
Test name
Test status
Simulation time 1091494763 ps
CPU time 2.4 seconds
Started Jul 22 06:08:48 PM PDT 24
Finished Jul 22 06:08:51 PM PDT 24
Peak memory 200904 kb
Host smart-ed7a205d-35d9-4db5-b757-ab9e138ed49b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525569363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3525569363
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1511170667
Short name T80
Test name
Test status
Simulation time 166727694 ps
CPU time 1.28 seconds
Started Jul 22 06:08:22 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 200120 kb
Host smart-924098f6-810c-47e7-8a4f-f33a43e7622c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511170667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1511170667
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2509285947
Short name T1192
Test name
Test status
Simulation time 33517460 ps
CPU time 0.55 seconds
Started Jul 22 06:09:10 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 195288 kb
Host smart-56e79cd2-915d-4be8-b144-a680514eefbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509285947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2509285947
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.120874841
Short name T1273
Test name
Test status
Simulation time 65527660 ps
CPU time 0.55 seconds
Started Jul 22 06:10:32 PM PDT 24
Finished Jul 22 06:10:33 PM PDT 24
Peak memory 195312 kb
Host smart-3557337b-3644-400e-ae34-ab7abee6af8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120874841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.120874841
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1138449032
Short name T1232
Test name
Test status
Simulation time 16094026 ps
CPU time 0.6 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 195308 kb
Host smart-3582af47-8ad5-4ba7-9665-75c5592a3151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138449032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1138449032
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.610806626
Short name T1193
Test name
Test status
Simulation time 18576069 ps
CPU time 0.56 seconds
Started Jul 22 06:09:11 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 195256 kb
Host smart-3d9fe9fc-a445-4dbf-bca5-1edca9ecccb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610806626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.610806626
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.427184161
Short name T1208
Test name
Test status
Simulation time 41042985 ps
CPU time 0.55 seconds
Started Jul 22 06:09:13 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 195220 kb
Host smart-d00def95-5b33-44a5-a2ec-b9b0ce4969c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427184161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.427184161
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1501971683
Short name T1205
Test name
Test status
Simulation time 36183807 ps
CPU time 0.54 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195244 kb
Host smart-78a57361-254e-4821-9ada-72f30f39e09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501971683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1501971683
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2239293122
Short name T1257
Test name
Test status
Simulation time 28488947 ps
CPU time 0.57 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195288 kb
Host smart-64a17664-ab06-40ce-a3f6-5bb4af9fe540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239293122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2239293122
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2367196689
Short name T1272
Test name
Test status
Simulation time 14937664 ps
CPU time 0.58 seconds
Started Jul 22 06:09:35 PM PDT 24
Finished Jul 22 06:09:36 PM PDT 24
Peak memory 195260 kb
Host smart-dc4c9952-fcdf-4be5-b248-6b6284475ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367196689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2367196689
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2799992400
Short name T1194
Test name
Test status
Simulation time 11875190 ps
CPU time 0.57 seconds
Started Jul 22 06:09:23 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195224 kb
Host smart-4386dee9-3f3f-4f23-b18a-a7a26d2cf168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799992400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2799992400
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1082264533
Short name T1179
Test name
Test status
Simulation time 41922308 ps
CPU time 0.55 seconds
Started Jul 22 06:09:22 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195356 kb
Host smart-fe8bdd71-6729-4e34-9392-e7bc6ec927e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082264533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1082264533
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1167320919
Short name T59
Test name
Test status
Simulation time 211980675 ps
CPU time 0.74 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 197192 kb
Host smart-f28fd5e9-3245-4765-8b6c-4e3f4ea68843
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167320919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1167320919
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.892533660
Short name T1207
Test name
Test status
Simulation time 539689206 ps
CPU time 1.54 seconds
Started Jul 22 06:08:35 PM PDT 24
Finished Jul 22 06:08:37 PM PDT 24
Peak memory 198540 kb
Host smart-ca9fb71b-426c-4129-9f48-4e539c9a7b9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892533660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.892533660
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4240202341
Short name T1220
Test name
Test status
Simulation time 13739698 ps
CPU time 0.57 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 196296 kb
Host smart-ef4199c2-83e4-48a7-a81e-deace0e3b693
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240202341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4240202341
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1956690401
Short name T1230
Test name
Test status
Simulation time 107662441 ps
CPU time 0.75 seconds
Started Jul 22 06:08:32 PM PDT 24
Finished Jul 22 06:08:33 PM PDT 24
Peak memory 200660 kb
Host smart-218cdb4e-e13a-4bf1-bd55-2334b7510199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956690401 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1956690401
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.524171440
Short name T76
Test name
Test status
Simulation time 22391988 ps
CPU time 0.59 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 196496 kb
Host smart-90c9da68-5fee-4163-b605-de8a71a6836d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524171440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.524171440
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2158091102
Short name T1255
Test name
Test status
Simulation time 40506076 ps
CPU time 0.54 seconds
Started Jul 22 06:08:31 PM PDT 24
Finished Jul 22 06:08:32 PM PDT 24
Peak memory 195288 kb
Host smart-3345608f-efea-4c32-8ef0-8349c25ce498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158091102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2158091102
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3410977617
Short name T1221
Test name
Test status
Simulation time 19254159 ps
CPU time 0.73 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 197152 kb
Host smart-2a8e5776-7c05-4f39-955e-676339eb36f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410977617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3410977617
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2089453515
Short name T1214
Test name
Test status
Simulation time 52673047 ps
CPU time 1.18 seconds
Started Jul 22 06:08:24 PM PDT 24
Finished Jul 22 06:08:25 PM PDT 24
Peak memory 200904 kb
Host smart-18e6dbcc-8a9d-45e8-aa48-530520eaa861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089453515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2089453515
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3504505800
Short name T112
Test name
Test status
Simulation time 143017682 ps
CPU time 1.27 seconds
Started Jul 22 06:08:24 PM PDT 24
Finished Jul 22 06:08:26 PM PDT 24
Peak memory 200212 kb
Host smart-381040a1-50c0-4da8-af15-41ec090b8af2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504505800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3504505800
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1106133048
Short name T1304
Test name
Test status
Simulation time 41189785 ps
CPU time 0.53 seconds
Started Jul 22 06:09:22 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195184 kb
Host smart-73858a61-4905-4ede-aa79-4f7cf556ca2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106133048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1106133048
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1926483923
Short name T1247
Test name
Test status
Simulation time 12004560 ps
CPU time 0.54 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195200 kb
Host smart-c34bd464-1d9c-4dad-a32d-b1d09a7a4442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926483923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1926483923
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1143258206
Short name T1183
Test name
Test status
Simulation time 21433721 ps
CPU time 0.57 seconds
Started Jul 22 06:09:30 PM PDT 24
Finished Jul 22 06:09:31 PM PDT 24
Peak memory 195284 kb
Host smart-c5865408-1881-479f-8379-5cd140a42906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143258206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1143258206
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.950738440
Short name T1288
Test name
Test status
Simulation time 33284842 ps
CPU time 0.57 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195304 kb
Host smart-7639b8e6-3c63-47b5-b006-0c208ab5fc14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950738440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.950738440
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1233265828
Short name T1261
Test name
Test status
Simulation time 98182843 ps
CPU time 0.56 seconds
Started Jul 22 06:09:23 PM PDT 24
Finished Jul 22 06:09:25 PM PDT 24
Peak memory 195192 kb
Host smart-e6299421-6870-463a-accc-e7c0ccf5c455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233265828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1233265828
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2190527824
Short name T1267
Test name
Test status
Simulation time 10411532 ps
CPU time 0.55 seconds
Started Jul 22 06:09:30 PM PDT 24
Finished Jul 22 06:09:31 PM PDT 24
Peak memory 195296 kb
Host smart-b81a9e5f-f18e-45c0-bb44-1bad3021debd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190527824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2190527824
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2222165141
Short name T1285
Test name
Test status
Simulation time 42597047 ps
CPU time 0.56 seconds
Started Jul 22 06:09:22 PM PDT 24
Finished Jul 22 06:09:23 PM PDT 24
Peak memory 195288 kb
Host smart-1215cdf8-bc0f-4a7a-84bd-7c6de1cc9940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222165141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2222165141
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1113230839
Short name T1188
Test name
Test status
Simulation time 14142393 ps
CPU time 0.56 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195192 kb
Host smart-61304f35-683f-4d27-88b3-791aaed7a9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113230839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1113230839
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1484556869
Short name T1282
Test name
Test status
Simulation time 12563676 ps
CPU time 0.56 seconds
Started Jul 22 06:09:29 PM PDT 24
Finished Jul 22 06:09:31 PM PDT 24
Peak memory 195292 kb
Host smart-82c98f5c-0ddd-469d-9dc2-dea13e942732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484556869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1484556869
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1446547760
Short name T1310
Test name
Test status
Simulation time 24704495 ps
CPU time 0.54 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195328 kb
Host smart-ac8641c2-1ae0-4180-8643-092a296f999e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446547760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1446547760
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1083756230
Short name T1256
Test name
Test status
Simulation time 25687933 ps
CPU time 0.78 seconds
Started Jul 22 06:08:34 PM PDT 24
Finished Jul 22 06:08:35 PM PDT 24
Peak memory 197220 kb
Host smart-30111235-c157-4edd-877f-37fbef0c1aa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083756230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1083756230
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.161521233
Short name T58
Test name
Test status
Simulation time 135604806 ps
CPU time 1.3 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 198572 kb
Host smart-6f21276e-6bcc-491a-89d4-441b01d57145
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161521233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.161521233
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2605734252
Short name T1186
Test name
Test status
Simulation time 43275509 ps
CPU time 0.58 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 196296 kb
Host smart-622953c1-9930-4c65-a5fb-93862b980e95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605734252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2605734252
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3694544927
Short name T1191
Test name
Test status
Simulation time 21570297 ps
CPU time 1.07 seconds
Started Jul 22 06:08:35 PM PDT 24
Finished Jul 22 06:08:36 PM PDT 24
Peak memory 200944 kb
Host smart-1ce25d3c-5f64-420b-b79f-9763a68fbaa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694544927 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3694544927
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.4142454663
Short name T1311
Test name
Test status
Simulation time 36706180 ps
CPU time 0.57 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 196304 kb
Host smart-a2e4635e-0b54-4f86-a893-5d67bc4436ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142454663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.4142454663
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2477733817
Short name T1275
Test name
Test status
Simulation time 31374019 ps
CPU time 0.54 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 195292 kb
Host smart-b3795487-6c60-4ad0-9522-dc53ae3b58ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477733817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2477733817
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2243835562
Short name T74
Test name
Test status
Simulation time 62120833 ps
CPU time 0.62 seconds
Started Jul 22 06:08:39 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 195540 kb
Host smart-7767bfd5-8103-4132-afc9-4f9882a86182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243835562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2243835562
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3137676550
Short name T1184
Test name
Test status
Simulation time 55572303 ps
CPU time 1.5 seconds
Started Jul 22 06:08:32 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 200984 kb
Host smart-2b8a8d83-5e45-4ddd-81f2-00b5b76fcc96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137676550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3137676550
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1929476135
Short name T1277
Test name
Test status
Simulation time 14746751 ps
CPU time 0.58 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:23 PM PDT 24
Peak memory 195248 kb
Host smart-fb5df611-24fb-409e-ace6-313e5d7bf203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929476135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1929476135
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3881157719
Short name T1302
Test name
Test status
Simulation time 11584647 ps
CPU time 0.57 seconds
Started Jul 22 06:09:22 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195240 kb
Host smart-f1bd06be-4941-4116-803c-1ac224e8d82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881157719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3881157719
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.686835682
Short name T1228
Test name
Test status
Simulation time 10823752 ps
CPU time 0.57 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195284 kb
Host smart-403b0edc-9487-4b70-b3e6-4ef65cc07270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686835682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.686835682
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4091790653
Short name T1269
Test name
Test status
Simulation time 32486378 ps
CPU time 0.55 seconds
Started Jul 22 06:10:03 PM PDT 24
Finished Jul 22 06:10:06 PM PDT 24
Peak memory 195320 kb
Host smart-8b544f71-3e06-439e-a089-a7bdee5357a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091790653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4091790653
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.348692388
Short name T1293
Test name
Test status
Simulation time 16196150 ps
CPU time 0.59 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:22 PM PDT 24
Peak memory 195296 kb
Host smart-b74e8768-1323-4eb7-8cea-4ccc1f56cc17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348692388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.348692388
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.58412607
Short name T1281
Test name
Test status
Simulation time 12974216 ps
CPU time 0.57 seconds
Started Jul 22 06:09:23 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 195436 kb
Host smart-66941947-bfb6-466a-8f3b-371f89e49630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58412607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.58412607
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3899573866
Short name T1284
Test name
Test status
Simulation time 45521563 ps
CPU time 0.55 seconds
Started Jul 22 06:09:41 PM PDT 24
Finished Jul 22 06:09:42 PM PDT 24
Peak memory 195284 kb
Host smart-0ac819fa-7761-426c-a0ef-c6015821c987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899573866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3899573866
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.737434930
Short name T1213
Test name
Test status
Simulation time 11039857 ps
CPU time 0.53 seconds
Started Jul 22 06:09:39 PM PDT 24
Finished Jul 22 06:09:40 PM PDT 24
Peak memory 195268 kb
Host smart-b3929fea-ed8b-46e0-8bb3-48cb253be481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737434930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.737434930
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4214344024
Short name T1299
Test name
Test status
Simulation time 25290809 ps
CPU time 0.57 seconds
Started Jul 22 06:09:19 PM PDT 24
Finished Jul 22 06:09:20 PM PDT 24
Peak memory 195352 kb
Host smart-776688d2-193e-4a43-b2c4-09def364ff4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214344024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4214344024
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3267730211
Short name T1248
Test name
Test status
Simulation time 17920341 ps
CPU time 0.58 seconds
Started Jul 22 06:09:21 PM PDT 24
Finished Jul 22 06:09:23 PM PDT 24
Peak memory 195284 kb
Host smart-33f39185-0d4d-4f4a-b331-f28f60962541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267730211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3267730211
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1350118021
Short name T1287
Test name
Test status
Simulation time 75909443 ps
CPU time 0.67 seconds
Started Jul 22 06:08:42 PM PDT 24
Finished Jul 22 06:08:43 PM PDT 24
Peak memory 199180 kb
Host smart-0fc1f5c0-2083-41f2-af61-5452fdb2d376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350118021 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1350118021
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1846020098
Short name T1291
Test name
Test status
Simulation time 20071646 ps
CPU time 0.57 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 196400 kb
Host smart-56a92c3a-7935-498c-8b8e-66c50395f8b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846020098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1846020098
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4201685110
Short name T1209
Test name
Test status
Simulation time 53455708 ps
CPU time 0.56 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 195256 kb
Host smart-c98391a8-ae77-477e-b87f-55fc564e954a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201685110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4201685110
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.898729831
Short name T1270
Test name
Test status
Simulation time 17086312 ps
CPU time 0.63 seconds
Started Jul 22 06:08:44 PM PDT 24
Finished Jul 22 06:08:45 PM PDT 24
Peak memory 196628 kb
Host smart-96aebbf0-ebb6-4820-9e4a-567feae1e866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898729831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.898729831
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.712395698
Short name T1306
Test name
Test status
Simulation time 122626680 ps
CPU time 1.44 seconds
Started Jul 22 06:08:34 PM PDT 24
Finished Jul 22 06:08:36 PM PDT 24
Peak memory 200900 kb
Host smart-c5552b1b-4616-44cd-ba55-690009f59085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712395698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.712395698
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.492791124
Short name T1268
Test name
Test status
Simulation time 115261963 ps
CPU time 1.27 seconds
Started Jul 22 06:08:33 PM PDT 24
Finished Jul 22 06:08:35 PM PDT 24
Peak memory 200168 kb
Host smart-6221dadc-e0a4-43ac-94d6-09626600bb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492791124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.492791124
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.752260057
Short name T1246
Test name
Test status
Simulation time 24589369 ps
CPU time 1.14 seconds
Started Jul 22 06:08:45 PM PDT 24
Finished Jul 22 06:08:46 PM PDT 24
Peak memory 200896 kb
Host smart-1a7fed81-13aa-414f-b1ec-b6fca324bd9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752260057 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.752260057
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3625527259
Short name T53
Test name
Test status
Simulation time 22028582 ps
CPU time 0.55 seconds
Started Jul 22 06:09:09 PM PDT 24
Finished Jul 22 06:09:10 PM PDT 24
Peak memory 196332 kb
Host smart-5b81cbe3-f924-4940-b097-35eee2b3abe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625527259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3625527259
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3629311317
Short name T1217
Test name
Test status
Simulation time 39634780 ps
CPU time 0.53 seconds
Started Jul 22 06:08:40 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 195208 kb
Host smart-b319ecc7-9008-425d-a3cd-67770264b773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629311317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3629311317
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4108943991
Short name T1280
Test name
Test status
Simulation time 48726643 ps
CPU time 0.65 seconds
Started Jul 22 06:08:38 PM PDT 24
Finished Jul 22 06:08:39 PM PDT 24
Peak memory 195620 kb
Host smart-a3d18b98-26dc-4f9a-a816-8e7a9ba63017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108943991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4108943991
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.435888762
Short name T1300
Test name
Test status
Simulation time 168932008 ps
CPU time 1.02 seconds
Started Jul 22 06:08:40 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 200688 kb
Host smart-a444bb43-769d-4932-b18d-0c8f56d32b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435888762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.435888762
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.676357113
Short name T1265
Test name
Test status
Simulation time 165317925 ps
CPU time 0.88 seconds
Started Jul 22 06:08:40 PM PDT 24
Finished Jul 22 06:08:42 PM PDT 24
Peak memory 199904 kb
Host smart-7a2423dd-5980-4412-968e-e39ca6c76a55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676357113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.676357113
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1370081834
Short name T1235
Test name
Test status
Simulation time 17579794 ps
CPU time 0.65 seconds
Started Jul 22 06:08:41 PM PDT 24
Finished Jul 22 06:08:43 PM PDT 24
Peak memory 198132 kb
Host smart-f93dd78c-56eb-4643-b501-46844d55d611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370081834 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1370081834
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2834930410
Short name T1231
Test name
Test status
Simulation time 35003215 ps
CPU time 0.57 seconds
Started Jul 22 06:08:41 PM PDT 24
Finished Jul 22 06:08:42 PM PDT 24
Peak memory 196264 kb
Host smart-745f0692-0cbe-41e9-b049-c8965d0d6aaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834930410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2834930410
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.931589877
Short name T1195
Test name
Test status
Simulation time 26166460 ps
CPU time 0.62 seconds
Started Jul 22 06:08:41 PM PDT 24
Finished Jul 22 06:08:42 PM PDT 24
Peak memory 195300 kb
Host smart-9e8a23bb-a9b4-45a5-bed1-894e376bb927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931589877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.931589877
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2911826103
Short name T1202
Test name
Test status
Simulation time 22269192 ps
CPU time 0.69 seconds
Started Jul 22 06:08:40 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 196708 kb
Host smart-16434de8-9dcc-44bc-9506-e0b87ed37c71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911826103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2911826103
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4255154065
Short name T1274
Test name
Test status
Simulation time 97564059 ps
CPU time 1.96 seconds
Started Jul 22 06:08:41 PM PDT 24
Finished Jul 22 06:08:43 PM PDT 24
Peak memory 201004 kb
Host smart-d56fcf51-acce-4a82-80a5-8fed5fd9c7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255154065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4255154065
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3852959441
Short name T111
Test name
Test status
Simulation time 155498335 ps
CPU time 0.95 seconds
Started Jul 22 06:08:43 PM PDT 24
Finished Jul 22 06:08:44 PM PDT 24
Peak memory 200016 kb
Host smart-d504d060-c5bf-4a49-ae41-7e4c0f5c4c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852959441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3852959441
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1247551958
Short name T1185
Test name
Test status
Simulation time 116098465 ps
CPU time 0.93 seconds
Started Jul 22 06:08:51 PM PDT 24
Finished Jul 22 06:08:52 PM PDT 24
Peak memory 200780 kb
Host smart-e0ce90b5-2006-473b-86fd-0af64f8593c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247551958 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1247551958
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1051953048
Short name T56
Test name
Test status
Simulation time 48923450 ps
CPU time 0.6 seconds
Started Jul 22 06:08:52 PM PDT 24
Finished Jul 22 06:08:53 PM PDT 24
Peak memory 196592 kb
Host smart-dbd5f633-b157-4001-8904-6a92c9884191
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051953048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1051953048
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3850109675
Short name T1266
Test name
Test status
Simulation time 12960336 ps
CPU time 0.56 seconds
Started Jul 22 06:08:51 PM PDT 24
Finished Jul 22 06:08:52 PM PDT 24
Peak memory 195304 kb
Host smart-72e62ae9-0ef8-46f1-9835-6e4a4d76418e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850109675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3850109675
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1874545809
Short name T1298
Test name
Test status
Simulation time 96152838 ps
CPU time 0.64 seconds
Started Jul 22 06:09:02 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 196640 kb
Host smart-89d084e8-46f1-42a3-988d-47d6c406c3cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874545809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1874545809
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2733736907
Short name T1263
Test name
Test status
Simulation time 495071841 ps
CPU time 1.84 seconds
Started Jul 22 06:08:44 PM PDT 24
Finished Jul 22 06:08:46 PM PDT 24
Peak memory 201020 kb
Host smart-de554d62-2826-4ff9-8d0c-fa0bbb9418ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733736907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2733736907
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1561637068
Short name T84
Test name
Test status
Simulation time 206679464 ps
CPU time 1.3 seconds
Started Jul 22 06:08:50 PM PDT 24
Finished Jul 22 06:08:52 PM PDT 24
Peak memory 200264 kb
Host smart-c999abeb-edd3-409f-9efd-dd7e76c87b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561637068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1561637068
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1155264382
Short name T1227
Test name
Test status
Simulation time 100085224 ps
CPU time 0.73 seconds
Started Jul 22 06:08:50 PM PDT 24
Finished Jul 22 06:08:51 PM PDT 24
Peak memory 199776 kb
Host smart-36c8e00c-e28a-4a2d-98c4-b26d6a6b973a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155264382 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1155264382
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3654298586
Short name T1236
Test name
Test status
Simulation time 13541074 ps
CPU time 0.59 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:08:48 PM PDT 24
Peak memory 196372 kb
Host smart-98e2f96f-f715-43e4-a487-f77f299b3fd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654298586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3654298586
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3945941951
Short name T1303
Test name
Test status
Simulation time 48173591 ps
CPU time 0.55 seconds
Started Jul 22 06:08:48 PM PDT 24
Finished Jul 22 06:08:49 PM PDT 24
Peak memory 195308 kb
Host smart-3fff9ea4-a694-4f03-93ed-e5bb9e42f68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945941951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3945941951
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1602052901
Short name T1292
Test name
Test status
Simulation time 22741293 ps
CPU time 0.68 seconds
Started Jul 22 06:08:49 PM PDT 24
Finished Jul 22 06:08:50 PM PDT 24
Peak memory 196708 kb
Host smart-7f8e3fa8-2c22-4190-afb9-6c75a289de4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602052901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1602052901
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.908427660
Short name T1198
Test name
Test status
Simulation time 23083891 ps
CPU time 1.12 seconds
Started Jul 22 06:08:52 PM PDT 24
Finished Jul 22 06:08:54 PM PDT 24
Peak memory 200920 kb
Host smart-cea8012c-3335-4d8b-ae2a-46757a161f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908427660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.908427660
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1765463224
Short name T1289
Test name
Test status
Simulation time 134023483 ps
CPU time 0.85 seconds
Started Jul 22 06:08:59 PM PDT 24
Finished Jul 22 06:09:01 PM PDT 24
Peak memory 199792 kb
Host smart-fc349784-947f-48fd-af90-f3bf6f7cbf98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765463224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1765463224
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1327913599
Short name T926
Test name
Test status
Simulation time 21102191 ps
CPU time 0.59 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:11:14 PM PDT 24
Peak memory 195636 kb
Host smart-8e37f9e2-f0cf-4257-b78b-1ee5d7d860a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327913599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1327913599
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.723677185
Short name T860
Test name
Test status
Simulation time 29793564061 ps
CPU time 12.98 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:18 PM PDT 24
Peak memory 200176 kb
Host smart-799c1cd8-7b3e-475a-b235-838c88a275d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723677185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.723677185
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4166493897
Short name T34
Test name
Test status
Simulation time 33704281594 ps
CPU time 19.44 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:25 PM PDT 24
Peak memory 200172 kb
Host smart-15645266-af47-49ed-941c-920316dddf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166493897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4166493897
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3556759511
Short name T772
Test name
Test status
Simulation time 38154051221 ps
CPU time 15.77 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:21 PM PDT 24
Peak memory 200204 kb
Host smart-d0a8c087-7901-455f-a1b7-d7cdd8ad9e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556759511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3556759511
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3354386565
Short name T352
Test name
Test status
Simulation time 14414615740 ps
CPU time 12.57 seconds
Started Jul 22 06:11:04 PM PDT 24
Finished Jul 22 06:11:17 PM PDT 24
Peak memory 199548 kb
Host smart-c7e2a887-b532-4f0c-8f44-083a42f08fb9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354386565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3354386565
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.406643165
Short name T1055
Test name
Test status
Simulation time 36647412285 ps
CPU time 234.92 seconds
Started Jul 22 06:11:14 PM PDT 24
Finished Jul 22 06:15:10 PM PDT 24
Peak memory 200244 kb
Host smart-010f17b4-2432-4f22-8ce5-93d7e391d443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406643165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.406643165
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3252197924
Short name T953
Test name
Test status
Simulation time 7183752263 ps
CPU time 22.2 seconds
Started Jul 22 06:11:06 PM PDT 24
Finished Jul 22 06:11:29 PM PDT 24
Peak memory 200088 kb
Host smart-78a9bb94-9c3a-4e96-9e7d-5b36f0f46f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252197924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3252197924
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1048459288
Short name T837
Test name
Test status
Simulation time 168334453200 ps
CPU time 37.34 seconds
Started Jul 22 06:11:03 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 200348 kb
Host smart-288aa695-d92c-48e4-a763-74bb3dc6fcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048459288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1048459288
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.719446089
Short name T1041
Test name
Test status
Simulation time 19712099811 ps
CPU time 1098.92 seconds
Started Jul 22 06:11:17 PM PDT 24
Finished Jul 22 06:29:37 PM PDT 24
Peak memory 200256 kb
Host smart-69a32ea7-bd5c-43c7-bdc0-20cda7304b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719446089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.719446089
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.324479487
Short name T1088
Test name
Test status
Simulation time 1376671335 ps
CPU time 5.45 seconds
Started Jul 22 06:11:01 PM PDT 24
Finished Jul 22 06:11:07 PM PDT 24
Peak memory 199204 kb
Host smart-b86d509c-1603-4d5b-8e3d-77a76aba91f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324479487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.324479487
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2039242382
Short name T122
Test name
Test status
Simulation time 68744618425 ps
CPU time 25.69 seconds
Started Jul 22 06:11:02 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 200244 kb
Host smart-d38f6600-79d0-4521-9c58-47a9e0117171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039242382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2039242382
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1818897078
Short name T921
Test name
Test status
Simulation time 2153521481 ps
CPU time 1.24 seconds
Started Jul 22 06:11:04 PM PDT 24
Finished Jul 22 06:11:05 PM PDT 24
Peak memory 195916 kb
Host smart-54fc84bd-d328-4fdc-a6a1-d32b756e41f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818897078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1818897078
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3271207105
Short name T767
Test name
Test status
Simulation time 654034976 ps
CPU time 1.97 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:11:07 PM PDT 24
Peak memory 198924 kb
Host smart-7c0507a4-bf18-405e-b98e-60919129ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271207105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3271207105
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.230496664
Short name T725
Test name
Test status
Simulation time 270769692060 ps
CPU time 970.87 seconds
Started Jul 22 06:11:14 PM PDT 24
Finished Jul 22 06:27:25 PM PDT 24
Peak memory 200208 kb
Host smart-a8931683-85cf-46e5-bfe3-a6d71ca3d2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230496664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.230496664
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2756169092
Short name T1073
Test name
Test status
Simulation time 67987023919 ps
CPU time 323.72 seconds
Started Jul 22 06:11:17 PM PDT 24
Finished Jul 22 06:16:41 PM PDT 24
Peak memory 209668 kb
Host smart-f75bbdb1-34bc-45ef-811a-59ab5da315c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756169092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2756169092
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2912437469
Short name T1134
Test name
Test status
Simulation time 6462814165 ps
CPU time 18.64 seconds
Started Jul 22 06:11:58 PM PDT 24
Finished Jul 22 06:12:17 PM PDT 24
Peak memory 200208 kb
Host smart-4564722e-ec66-4ffc-88b6-1a449e7dae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912437469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2912437469
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2342042759
Short name T246
Test name
Test status
Simulation time 108140065084 ps
CPU time 61.28 seconds
Started Jul 22 06:11:05 PM PDT 24
Finished Jul 22 06:12:07 PM PDT 24
Peak memory 200248 kb
Host smart-eab6fa49-a120-4a24-a63c-0b117af1848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342042759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2342042759
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3482961601
Short name T1144
Test name
Test status
Simulation time 42154720764 ps
CPU time 34.48 seconds
Started Jul 22 06:12:47 PM PDT 24
Finished Jul 22 06:13:22 PM PDT 24
Peak memory 200256 kb
Host smart-daca6e08-edc1-488a-9db0-6e5d67788579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482961601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3482961601
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.461924224
Short name T843
Test name
Test status
Simulation time 115571653838 ps
CPU time 135.33 seconds
Started Jul 22 06:11:17 PM PDT 24
Finished Jul 22 06:13:33 PM PDT 24
Peak memory 200216 kb
Host smart-27a90b17-a03c-4251-baa7-c8f8cff6216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461924224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.461924224
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2056879518
Short name T458
Test name
Test status
Simulation time 28663681800 ps
CPU time 26.09 seconds
Started Jul 22 06:11:13 PM PDT 24
Finished Jul 22 06:11:39 PM PDT 24
Peak memory 200180 kb
Host smart-dc5d590a-548c-4b1d-ba4b-17b684fbeb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056879518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2056879518
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1339250335
Short name T706
Test name
Test status
Simulation time 29456747482 ps
CPU time 13.98 seconds
Started Jul 22 06:11:13 PM PDT 24
Finished Jul 22 06:11:27 PM PDT 24
Peak memory 200252 kb
Host smart-8d74fa3e-6a1f-43fb-9e37-4387fc50f732
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339250335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1339250335
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2735794932
Short name T572
Test name
Test status
Simulation time 85539656353 ps
CPU time 218.52 seconds
Started Jul 22 06:11:13 PM PDT 24
Finished Jul 22 06:14:52 PM PDT 24
Peak memory 200232 kb
Host smart-632480a7-db3e-4ac6-b1f2-9f7ff98f0405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735794932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2735794932
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2092738936
Short name T375
Test name
Test status
Simulation time 4009160760 ps
CPU time 4.27 seconds
Started Jul 22 06:11:14 PM PDT 24
Finished Jul 22 06:11:19 PM PDT 24
Peak memory 199488 kb
Host smart-5fd65a3b-d618-49ef-8578-7f67304ef441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092738936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2092738936
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1417532266
Short name T603
Test name
Test status
Simulation time 100468880491 ps
CPU time 43.88 seconds
Started Jul 22 06:11:15 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 199364 kb
Host smart-763a2462-3576-4f2d-96dc-c7963d6c2831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417532266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1417532266
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1973841612
Short name T895
Test name
Test status
Simulation time 21760200751 ps
CPU time 274.92 seconds
Started Jul 22 06:11:13 PM PDT 24
Finished Jul 22 06:15:49 PM PDT 24
Peak memory 200132 kb
Host smart-6093f2eb-c153-47f7-9359-3565dc20cd03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973841612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1973841612
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.968732821
Short name T957
Test name
Test status
Simulation time 1698488137 ps
CPU time 9.4 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:11:22 PM PDT 24
Peak memory 198328 kb
Host smart-61437f9e-0f42-4da8-be6d-13b75a6fbfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968732821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.968732821
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2499424035
Short name T823
Test name
Test status
Simulation time 90463346310 ps
CPU time 87.76 seconds
Started Jul 22 06:11:17 PM PDT 24
Finished Jul 22 06:12:45 PM PDT 24
Peak memory 200156 kb
Host smart-2e985938-fb54-4d56-b082-8e218871fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499424035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2499424035
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.878519340
Short name T253
Test name
Test status
Simulation time 5518615054 ps
CPU time 2.24 seconds
Started Jul 22 06:11:18 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 196396 kb
Host smart-7ef68694-0330-4cfb-b254-50a6c7a480d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878519340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.878519340
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3020862591
Short name T86
Test name
Test status
Simulation time 71633140 ps
CPU time 0.77 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:11:13 PM PDT 24
Peak memory 218468 kb
Host smart-fe0c0874-a567-4ab2-bba1-19657fca8b28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020862591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3020862591
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1337360388
Short name T509
Test name
Test status
Simulation time 476623267 ps
CPU time 1.88 seconds
Started Jul 22 06:11:15 PM PDT 24
Finished Jul 22 06:11:17 PM PDT 24
Peak memory 198444 kb
Host smart-b3f14a21-b118-4d68-9f99-464f9af939a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337360388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1337360388
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1803664656
Short name T1145
Test name
Test status
Simulation time 162143844657 ps
CPU time 153.96 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:13:46 PM PDT 24
Peak memory 200304 kb
Host smart-021bdbc2-a765-4c3a-8a5a-780e89d6ca59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803664656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1803664656
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1775414315
Short name T955
Test name
Test status
Simulation time 63972468551 ps
CPU time 356.17 seconds
Started Jul 22 06:11:12 PM PDT 24
Finished Jul 22 06:17:09 PM PDT 24
Peak memory 216864 kb
Host smart-99f8d0a2-55ea-448c-afd3-64af419d61b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775414315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1775414315
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2578549116
Short name T1022
Test name
Test status
Simulation time 905189585 ps
CPU time 2.54 seconds
Started Jul 22 06:11:14 PM PDT 24
Finished Jul 22 06:11:17 PM PDT 24
Peak memory 198892 kb
Host smart-2a2f9bb7-afe0-42e8-ac2d-bcbdb69b2706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578549116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2578549116
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.720460280
Short name T966
Test name
Test status
Simulation time 69850530488 ps
CPU time 52.93 seconds
Started Jul 22 06:11:14 PM PDT 24
Finished Jul 22 06:12:08 PM PDT 24
Peak memory 200160 kb
Host smart-083079ee-d3d9-4913-b6c6-d2a2e1e9ae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720460280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.720460280
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.764951195
Short name T632
Test name
Test status
Simulation time 27109089 ps
CPU time 0.56 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:43 PM PDT 24
Peak memory 195580 kb
Host smart-a02bb818-0dc4-412d-987e-0ae5f67e58d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764951195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.764951195
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2855094968
Short name T537
Test name
Test status
Simulation time 221793546978 ps
CPU time 1308.79 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:33:29 PM PDT 24
Peak memory 200120 kb
Host smart-ce0e0af9-b7d7-45ab-a0df-b95b9adce787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855094968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2855094968
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3184876877
Short name T975
Test name
Test status
Simulation time 79091748142 ps
CPU time 63.1 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:12:43 PM PDT 24
Peak memory 200120 kb
Host smart-32392eb2-1a00-4b85-a8b9-975c020af592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184876877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3184876877
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2981603753
Short name T441
Test name
Test status
Simulation time 52884702035 ps
CPU time 42.8 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:12:24 PM PDT 24
Peak memory 200148 kb
Host smart-f2467e7d-3c5b-44fb-b158-45c223e3d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981603753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2981603753
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3959313926
Short name T582
Test name
Test status
Simulation time 65223219457 ps
CPU time 354.37 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:17:38 PM PDT 24
Peak memory 200196 kb
Host smart-823ecb87-5e05-4739-8938-20b04c4d1db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959313926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3959313926
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2256729557
Short name T849
Test name
Test status
Simulation time 7268861617 ps
CPU time 8.24 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:11:53 PM PDT 24
Peak memory 199368 kb
Host smart-d8515213-7a63-47f0-b49f-d0ef3643d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256729557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2256729557
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.523343319
Short name T523
Test name
Test status
Simulation time 77166768657 ps
CPU time 30.05 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:12:12 PM PDT 24
Peak memory 200228 kb
Host smart-68484a0d-e8d5-418b-85f9-fc6d049fd68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523343319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.523343319
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.320993471
Short name T925
Test name
Test status
Simulation time 14036310943 ps
CPU time 171.38 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:14:35 PM PDT 24
Peak memory 200220 kb
Host smart-5dbec90e-f774-46cc-a749-73a365148eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320993471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.320993471
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3963980011
Short name T365
Test name
Test status
Simulation time 5657909749 ps
CPU time 12.47 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 199464 kb
Host smart-56f413f9-d688-4ea5-ab4c-828851d44854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963980011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3963980011
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.76921013
Short name T662
Test name
Test status
Simulation time 31626447656 ps
CPU time 64.01 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:12:47 PM PDT 24
Peak memory 200196 kb
Host smart-88a6267a-7de8-47b6-9c72-e2b00c55ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76921013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.76921013
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1783335975
Short name T1113
Test name
Test status
Simulation time 31651572993 ps
CPU time 14.24 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 196552 kb
Host smart-0b6602e0-6874-484f-9ee6-b7339a5e549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783335975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1783335975
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2894939554
Short name T585
Test name
Test status
Simulation time 5968809383 ps
CPU time 21.47 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:12:02 PM PDT 24
Peak memory 199836 kb
Host smart-009a08c2-38b8-4180-82ae-a27ad0407786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894939554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2894939554
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3580619221
Short name T970
Test name
Test status
Simulation time 431308338916 ps
CPU time 535.19 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:20:39 PM PDT 24
Peak memory 200176 kb
Host smart-b6120085-43a6-4204-9202-e10406e69d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580619221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3580619221
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.966826968
Short name T781
Test name
Test status
Simulation time 46460617640 ps
CPU time 410.06 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:18:33 PM PDT 24
Peak memory 216748 kb
Host smart-07c7ba67-4032-4ea5-b24e-0f0e9eb7f85e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966826968 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.966826968
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4188710698
Short name T413
Test name
Test status
Simulation time 6326115078 ps
CPU time 18.46 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 200044 kb
Host smart-5a2f96c1-1d06-48f9-99ee-59c007f5d117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188710698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4188710698
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1156277814
Short name T384
Test name
Test status
Simulation time 22017609903 ps
CPU time 8.99 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:11:50 PM PDT 24
Peak memory 197924 kb
Host smart-2a2f80ce-bffd-4ef4-8adc-13223bdc7570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156277814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1156277814
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2935830069
Short name T273
Test name
Test status
Simulation time 71464223071 ps
CPU time 6.55 seconds
Started Jul 22 06:15:08 PM PDT 24
Finished Jul 22 06:15:15 PM PDT 24
Peak memory 200044 kb
Host smart-6324d699-4d8b-46b0-9b2d-ca04a646175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935830069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2935830069
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1720536188
Short name T728
Test name
Test status
Simulation time 11486417716 ps
CPU time 34.02 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:40 PM PDT 24
Peak memory 200188 kb
Host smart-cbf3376d-272a-443c-ac74-18f66768bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720536188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1720536188
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4154656851
Short name T127
Test name
Test status
Simulation time 38113384941 ps
CPU time 26.74 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:33 PM PDT 24
Peak memory 200288 kb
Host smart-9a9ee56f-2f89-4094-a499-fc8c70358032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154656851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4154656851
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.822455000
Short name T610
Test name
Test status
Simulation time 115742877010 ps
CPU time 23.37 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:15:30 PM PDT 24
Peak memory 200068 kb
Host smart-fd5922cc-af62-4c41-a1d6-d26d5e37a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822455000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.822455000
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3515872188
Short name T484
Test name
Test status
Simulation time 64849089721 ps
CPU time 42.4 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:47 PM PDT 24
Peak memory 200200 kb
Host smart-d2e0b085-587e-47a0-a22b-cc3c2ee63e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515872188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3515872188
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.557268429
Short name T714
Test name
Test status
Simulation time 19064950724 ps
CPU time 8.24 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:15:15 PM PDT 24
Peak memory 200184 kb
Host smart-6e1044ef-e809-4e13-bfea-3c3ae7b0fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557268429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.557268429
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3018889548
Short name T215
Test name
Test status
Simulation time 111043871111 ps
CPU time 79.03 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:16:42 PM PDT 24
Peak memory 200180 kb
Host smart-68c757fb-b284-43a6-8dc6-027d18ee264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018889548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3018889548
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4155327184
Short name T451
Test name
Test status
Simulation time 39864489464 ps
CPU time 21.1 seconds
Started Jul 22 06:15:12 PM PDT 24
Finished Jul 22 06:15:33 PM PDT 24
Peak memory 200012 kb
Host smart-968e0ea9-248b-4695-929a-1d710fb290f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155327184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4155327184
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1588276098
Short name T515
Test name
Test status
Simulation time 97093136427 ps
CPU time 217.19 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:19:00 PM PDT 24
Peak memory 200244 kb
Host smart-cbf16e03-1e36-4f21-b925-bd8e6f9dcea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588276098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1588276098
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4077160944
Short name T578
Test name
Test status
Simulation time 12615755 ps
CPU time 0.54 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:11:46 PM PDT 24
Peak memory 195072 kb
Host smart-ec453de0-563b-4ecb-b0b1-2b7a51177c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077160944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4077160944
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1196825947
Short name T602
Test name
Test status
Simulation time 28960908172 ps
CPU time 39.94 seconds
Started Jul 22 06:11:43 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 200148 kb
Host smart-edc1e7fc-b7a4-4b08-a859-34d823dffd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196825947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1196825947
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3865349474
Short name T855
Test name
Test status
Simulation time 49635264596 ps
CPU time 52.4 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 200252 kb
Host smart-45398537-5116-402b-a383-184a97249e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865349474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3865349474
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.876257418
Short name T1137
Test name
Test status
Simulation time 94510714763 ps
CPU time 136.96 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:14:03 PM PDT 24
Peak memory 200264 kb
Host smart-aff34c5d-a66f-4340-9791-a97c777d2d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876257418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.876257418
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3405207856
Short name T740
Test name
Test status
Simulation time 53556936353 ps
CPU time 17.08 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:12:02 PM PDT 24
Peak memory 198828 kb
Host smart-7cd79055-a101-4152-8333-c7b84e8dee45
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405207856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3405207856
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1715657125
Short name T1014
Test name
Test status
Simulation time 104092877031 ps
CPU time 612.07 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:22:03 PM PDT 24
Peak memory 200048 kb
Host smart-9b9b1746-e86d-481d-bf07-9ea6d2f293a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715657125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1715657125
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1649806757
Short name T727
Test name
Test status
Simulation time 4734747307 ps
CPU time 5.43 seconds
Started Jul 22 06:11:43 PM PDT 24
Finished Jul 22 06:11:50 PM PDT 24
Peak memory 199908 kb
Host smart-797812a5-0c87-4605-a284-36eb19dce1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649806757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1649806757
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.176764128
Short name T609
Test name
Test status
Simulation time 26781048721 ps
CPU time 10.1 seconds
Started Jul 22 06:11:43 PM PDT 24
Finished Jul 22 06:11:54 PM PDT 24
Peak memory 194800 kb
Host smart-001df22e-1ca0-4e8a-9a8b-4d9a43636ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176764128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.176764128
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3789575169
Short name T927
Test name
Test status
Simulation time 21904649847 ps
CPU time 1143.88 seconds
Started Jul 22 06:11:49 PM PDT 24
Finished Jul 22 06:30:54 PM PDT 24
Peak memory 200232 kb
Host smart-138240e6-f69f-4183-848b-b5b3204bb11d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789575169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3789575169
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.502784533
Short name T331
Test name
Test status
Simulation time 1272212019 ps
CPU time 5.03 seconds
Started Jul 22 06:11:53 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 197064 kb
Host smart-4574c0ff-00fd-426e-9d3a-475490532d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502784533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.502784533
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1163181987
Short name T545
Test name
Test status
Simulation time 180230831597 ps
CPU time 92.52 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 200256 kb
Host smart-ff8a7bdd-824b-49f5-9223-17cc12514aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163181987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1163181987
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3751387842
Short name T409
Test name
Test status
Simulation time 43326886055 ps
CPU time 33.83 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:12:20 PM PDT 24
Peak memory 195988 kb
Host smart-66132e00-df37-4496-bd01-f4ea0f9b8a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751387842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3751387842
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.409238835
Short name T1026
Test name
Test status
Simulation time 11059207334 ps
CPU time 19.91 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:12:03 PM PDT 24
Peak memory 200060 kb
Host smart-9a0f7e02-772c-4501-b71b-1e2feb2e4833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409238835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.409238835
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3490828722
Short name T672
Test name
Test status
Simulation time 344531354801 ps
CPU time 603.32 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:21:50 PM PDT 24
Peak memory 208576 kb
Host smart-5f49c4d2-aa04-408d-bf83-18a72d9cfa5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490828722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3490828722
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.368345028
Short name T97
Test name
Test status
Simulation time 21672093488 ps
CPU time 85.57 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:13:09 PM PDT 24
Peak memory 216228 kb
Host smart-7e40c30e-d230-4e8d-87d7-ae836a47087a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368345028 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.368345028
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2787096663
Short name T271
Test name
Test status
Simulation time 6548329183 ps
CPU time 19.62 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:12:05 PM PDT 24
Peak memory 200168 kb
Host smart-79094458-0074-4c5f-a93a-5379ad8ba6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787096663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2787096663
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3395967196
Short name T717
Test name
Test status
Simulation time 68256863474 ps
CPU time 51.16 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:14:47 PM PDT 24
Peak memory 200256 kb
Host smart-e9c8d29e-3100-442f-8f73-f56019c50f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395967196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3395967196
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1625075782
Short name T775
Test name
Test status
Simulation time 43447654000 ps
CPU time 75.08 seconds
Started Jul 22 06:15:09 PM PDT 24
Finished Jul 22 06:16:24 PM PDT 24
Peak memory 200000 kb
Host smart-d0180c26-1b7f-496e-a5cb-ab471148e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625075782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1625075782
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3326646315
Short name T1018
Test name
Test status
Simulation time 22737466101 ps
CPU time 38.85 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:45 PM PDT 24
Peak memory 200252 kb
Host smart-9319abd1-6165-4c02-9366-44ebf9ffa579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326646315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3326646315
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3016918574
Short name T829
Test name
Test status
Simulation time 117369752294 ps
CPU time 184.51 seconds
Started Jul 22 06:15:12 PM PDT 24
Finished Jul 22 06:18:17 PM PDT 24
Peak memory 199948 kb
Host smart-5465f90a-b266-4492-a4bf-766e2477811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016918574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3016918574
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3070252696
Short name T114
Test name
Test status
Simulation time 20185363154 ps
CPU time 20.64 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:15:37 PM PDT 24
Peak memory 200216 kb
Host smart-cb0196b6-0b49-4160-988e-d6d896449cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070252696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3070252696
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1956531136
Short name T858
Test name
Test status
Simulation time 359871643266 ps
CPU time 98.79 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:16:52 PM PDT 24
Peak memory 200260 kb
Host smart-aaee1711-de09-46bc-8403-e1df81f65449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956531136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1956531136
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3367039369
Short name T183
Test name
Test status
Simulation time 27373124672 ps
CPU time 32.2 seconds
Started Jul 22 06:15:15 PM PDT 24
Finished Jul 22 06:15:48 PM PDT 24
Peak memory 200236 kb
Host smart-ce63583c-8145-4dd5-b4b1-c1323857e32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367039369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3367039369
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2651766507
Short name T1004
Test name
Test status
Simulation time 44863230634 ps
CPU time 40.73 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:15:57 PM PDT 24
Peak memory 199680 kb
Host smart-f3341428-013f-4481-8b10-374873953885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651766507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2651766507
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.109573951
Short name T259
Test name
Test status
Simulation time 38245623496 ps
CPU time 17.4 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:15:40 PM PDT 24
Peak memory 200256 kb
Host smart-152259a8-f517-4f0a-8d48-c0bb53a9620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109573951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.109573951
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1307031844
Short name T918
Test name
Test status
Simulation time 7414714461 ps
CPU time 12.26 seconds
Started Jul 22 06:15:12 PM PDT 24
Finished Jul 22 06:15:25 PM PDT 24
Peak memory 200288 kb
Host smart-fcec6c79-5dd5-40a7-ad59-e2a8ae542109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307031844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1307031844
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1688440792
Short name T648
Test name
Test status
Simulation time 118431303 ps
CPU time 0.55 seconds
Started Jul 22 06:11:53 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 195912 kb
Host smart-bbd56123-3e65-466a-a89a-9c8f6aab53d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688440792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1688440792
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.178155428
Short name T160
Test name
Test status
Simulation time 252411473400 ps
CPU time 361.49 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 200236 kb
Host smart-f0f6aa26-f834-4d5f-9c5f-70e7da7c99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178155428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.178155428
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.14389540
Short name T983
Test name
Test status
Simulation time 99242719794 ps
CPU time 50.9 seconds
Started Jul 22 06:11:49 PM PDT 24
Finished Jul 22 06:12:41 PM PDT 24
Peak memory 200156 kb
Host smart-823cd531-d0eb-45ee-8641-6b1d8f5fcc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14389540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.14389540
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4210516467
Short name T618
Test name
Test status
Simulation time 55211359170 ps
CPU time 89.2 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:13:16 PM PDT 24
Peak memory 200256 kb
Host smart-cecd3505-24fb-4694-9944-d4cf2e85fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210516467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4210516467
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2341333817
Short name T1069
Test name
Test status
Simulation time 21725575195 ps
CPU time 10.36 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 200164 kb
Host smart-fffa8c78-8692-4653-854f-18d43d2d1531
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341333817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2341333817
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_loopback.2158663930
Short name T15
Test name
Test status
Simulation time 5003367205 ps
CPU time 3.61 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:11:50 PM PDT 24
Peak memory 199160 kb
Host smart-9e5d286d-2054-44e4-a3d9-ba8d0d5dbf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158663930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2158663930
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.996715589
Short name T383
Test name
Test status
Simulation time 267167546312 ps
CPU time 126.05 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:13:53 PM PDT 24
Peak memory 200284 kb
Host smart-f1cefb5a-2ce2-41c6-8c0c-8d2cfe131ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996715589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.996715589
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.517842800
Short name T845
Test name
Test status
Simulation time 14545202421 ps
CPU time 611.15 seconds
Started Jul 22 06:11:48 PM PDT 24
Finished Jul 22 06:22:01 PM PDT 24
Peak memory 200248 kb
Host smart-842c3bbf-7b38-4537-8d63-16245c79ba95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517842800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.517842800
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1572290946
Short name T507
Test name
Test status
Simulation time 4646583419 ps
CPU time 2.55 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:11:58 PM PDT 24
Peak memory 198452 kb
Host smart-55b012c0-7f88-4a34-b69d-bf6d8581a435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572290946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1572290946
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.201353223
Short name T120
Test name
Test status
Simulation time 24716104962 ps
CPU time 38.57 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:12:23 PM PDT 24
Peak memory 200128 kb
Host smart-c35f2b42-9d6c-44a2-84c1-193c79154b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201353223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.201353223
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3842665568
Short name T325
Test name
Test status
Simulation time 3547367861 ps
CPU time 1.22 seconds
Started Jul 22 06:11:44 PM PDT 24
Finished Jul 22 06:11:46 PM PDT 24
Peak memory 196352 kb
Host smart-746dcd78-72a3-429a-9078-933654dc5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842665568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3842665568
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2576888358
Short name T642
Test name
Test status
Simulation time 5323970642 ps
CPU time 11.03 seconds
Started Jul 22 06:11:47 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 200176 kb
Host smart-bb3c67c9-9598-45d9-ac41-19e26060ab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576888358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2576888358
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.92971537
Short name T1172
Test name
Test status
Simulation time 58480891291 ps
CPU time 51.26 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 200216 kb
Host smart-7bcf0ab7-4c44-4e26-8729-4f1db7c9e548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92971537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.92971537
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1576583205
Short name T100
Test name
Test status
Simulation time 33394211569 ps
CPU time 390.83 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:18:21 PM PDT 24
Peak memory 216752 kb
Host smart-ffd55802-784b-4994-970b-d8ab6314b3ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576583205 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1576583205
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2054925962
Short name T9
Test name
Test status
Simulation time 1043125510 ps
CPU time 1.44 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:11:45 PM PDT 24
Peak memory 199712 kb
Host smart-54d17146-4bfb-4a46-843c-59f5c0ba06b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054925962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2054925962
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2900577940
Short name T696
Test name
Test status
Simulation time 85388296400 ps
CPU time 41.79 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:12:27 PM PDT 24
Peak memory 200104 kb
Host smart-2fd2e552-1d24-4c86-9366-5ef13a7ccf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900577940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2900577940
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3919286165
Short name T556
Test name
Test status
Simulation time 311215855917 ps
CPU time 141.17 seconds
Started Jul 22 06:15:25 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 200108 kb
Host smart-47402444-062b-4195-8f99-9dc664220a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919286165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3919286165
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2358254908
Short name T517
Test name
Test status
Simulation time 69899294066 ps
CPU time 55.91 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:16:09 PM PDT 24
Peak memory 200184 kb
Host smart-e8d573bc-eb37-4c69-9e81-2511b585dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358254908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2358254908
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2889593263
Short name T886
Test name
Test status
Simulation time 80061241669 ps
CPU time 63.01 seconds
Started Jul 22 06:15:12 PM PDT 24
Finished Jul 22 06:16:15 PM PDT 24
Peak memory 200160 kb
Host smart-5e17961d-916e-4967-a177-41e501f21a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889593263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2889593263
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1823874653
Short name T477
Test name
Test status
Simulation time 35527354806 ps
CPU time 6.21 seconds
Started Jul 22 06:15:55 PM PDT 24
Finished Jul 22 06:16:02 PM PDT 24
Peak memory 199892 kb
Host smart-e8291eeb-7c82-4f31-8799-abd310be8172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823874653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1823874653
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1376708143
Short name T119
Test name
Test status
Simulation time 25477284241 ps
CPU time 61.79 seconds
Started Jul 22 06:15:20 PM PDT 24
Finished Jul 22 06:16:22 PM PDT 24
Peak memory 200196 kb
Host smart-8693c511-8b51-4c8c-a673-9305c863365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376708143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1376708143
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.293516201
Short name T288
Test name
Test status
Simulation time 17155588968 ps
CPU time 14.62 seconds
Started Jul 22 06:15:15 PM PDT 24
Finished Jul 22 06:15:31 PM PDT 24
Peak memory 200024 kb
Host smart-9ab99b92-b979-4576-b6e8-7861e5278f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293516201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.293516201
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.110155293
Short name T511
Test name
Test status
Simulation time 17764564950 ps
CPU time 29.3 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:15:42 PM PDT 24
Peak memory 200184 kb
Host smart-0ef1e8b8-01ee-4b7a-b4c7-893608965611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110155293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.110155293
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2207374206
Short name T629
Test name
Test status
Simulation time 35534309033 ps
CPU time 27.63 seconds
Started Jul 22 06:15:12 PM PDT 24
Finished Jul 22 06:15:39 PM PDT 24
Peak memory 200196 kb
Host smart-b6313ed2-345c-4a9f-ab17-78fb691f6b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207374206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2207374206
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.438942489
Short name T770
Test name
Test status
Simulation time 58687002078 ps
CPU time 92.25 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:16:49 PM PDT 24
Peak memory 200196 kb
Host smart-64e5f0cb-7272-4658-a9b9-8b4cc59e3154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438942489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.438942489
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.168386357
Short name T195
Test name
Test status
Simulation time 43369093364 ps
CPU time 64.48 seconds
Started Jul 22 06:15:15 PM PDT 24
Finished Jul 22 06:16:20 PM PDT 24
Peak memory 200164 kb
Host smart-9eebd26a-4ae2-4dbd-9792-7c4ea3461523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168386357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.168386357
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2268074662
Short name T1037
Test name
Test status
Simulation time 32319398 ps
CPU time 0.56 seconds
Started Jul 22 06:11:53 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 195628 kb
Host smart-b01eaa99-4424-4948-ac07-4f79a5768828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268074662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2268074662
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3897486803
Short name T402
Test name
Test status
Simulation time 56984248994 ps
CPU time 39.13 seconds
Started Jul 22 06:11:45 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 200176 kb
Host smart-5c2a24d6-04d6-4be4-b3b7-e8a2c2085df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897486803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3897486803
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3502612373
Short name T168
Test name
Test status
Simulation time 90039942659 ps
CPU time 78.75 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:13:05 PM PDT 24
Peak memory 200264 kb
Host smart-5a173fbb-438b-4ccf-bbdb-dc471d9983a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502612373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3502612373
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2114069748
Short name T317
Test name
Test status
Simulation time 160544513272 ps
CPU time 37.12 seconds
Started Jul 22 06:11:51 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 199736 kb
Host smart-ddf07839-9afb-4262-aa6b-4e1556bbd047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114069748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2114069748
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2153399151
Short name T442
Test name
Test status
Simulation time 32752489880 ps
CPU time 34.01 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 200184 kb
Host smart-82b9ccd5-4dd6-49f7-a46e-a6d4f82f7e45
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153399151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2153399151
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.630995870
Short name T1011
Test name
Test status
Simulation time 97161074406 ps
CPU time 163.35 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:14:39 PM PDT 24
Peak memory 200160 kb
Host smart-99d39f4d-add4-4893-8fa4-a11d4831f3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630995870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.630995870
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1735919713
Short name T534
Test name
Test status
Simulation time 3470713943 ps
CPU time 6.4 seconds
Started Jul 22 06:11:53 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 199308 kb
Host smart-c22dde9c-00c6-41ae-9538-a05ec0039c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735919713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1735919713
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1398408029
Short name T689
Test name
Test status
Simulation time 48602619626 ps
CPU time 14.43 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:12:05 PM PDT 24
Peak memory 199512 kb
Host smart-6747c28b-44a7-4230-933e-9f068e37e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398408029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1398408029
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2832163294
Short name T944
Test name
Test status
Simulation time 23138344466 ps
CPU time 1230.72 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:32:26 PM PDT 24
Peak memory 200148 kb
Host smart-6b33539a-fe08-45bf-90e6-4e7d7885bffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832163294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2832163294
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.933856661
Short name T804
Test name
Test status
Simulation time 3063720419 ps
CPU time 10.13 seconds
Started Jul 22 06:11:49 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 198692 kb
Host smart-735ec064-015f-4d17-8aaf-9b491e085ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933856661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.933856661
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.728836004
Short name T877
Test name
Test status
Simulation time 234327766675 ps
CPU time 154.41 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:14:21 PM PDT 24
Peak memory 200148 kb
Host smart-98ab167c-4e9d-4155-9c3b-17d1fdb5a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728836004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.728836004
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1152924616
Short name T749
Test name
Test status
Simulation time 38247573329 ps
CPU time 31.42 seconds
Started Jul 22 06:11:48 PM PDT 24
Finished Jul 22 06:12:20 PM PDT 24
Peak memory 197036 kb
Host smart-42146a3f-9e12-41d5-95d2-51530860bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152924616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1152924616
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2704929860
Short name T864
Test name
Test status
Simulation time 489871620 ps
CPU time 1.19 seconds
Started Jul 22 06:11:46 PM PDT 24
Finished Jul 22 06:11:48 PM PDT 24
Peak memory 199012 kb
Host smart-deffd062-5e88-42ad-ba0a-79de59b73311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704929860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2704929860
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2989572439
Short name T1157
Test name
Test status
Simulation time 318946112587 ps
CPU time 1741.72 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:40:57 PM PDT 24
Peak memory 215824 kb
Host smart-eefc80da-ff23-401f-8a48-473023c6f1cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989572439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2989572439
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3174952352
Short name T937
Test name
Test status
Simulation time 1129929341 ps
CPU time 1.82 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 199140 kb
Host smart-ace48c8d-8d43-4d69-ad83-1cc2ad002eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174952352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3174952352
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1953145948
Short name T1077
Test name
Test status
Simulation time 46821598989 ps
CPU time 82.3 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:13:14 PM PDT 24
Peak memory 200076 kb
Host smart-2e95002a-589c-4654-b462-79d6078e469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953145948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1953145948
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2015081591
Short name T692
Test name
Test status
Simulation time 49891076003 ps
CPU time 22.56 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:15:36 PM PDT 24
Peak memory 200188 kb
Host smart-86612589-bbc7-4ccc-b2b8-e63cb03d81ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015081591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2015081591
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4096134579
Short name T391
Test name
Test status
Simulation time 22878007297 ps
CPU time 21.91 seconds
Started Jul 22 06:15:55 PM PDT 24
Finished Jul 22 06:16:17 PM PDT 24
Peak memory 200052 kb
Host smart-2f345108-67a1-4362-b3d3-7d724b3df0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096134579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4096134579
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.145426001
Short name T135
Test name
Test status
Simulation time 16868546520 ps
CPU time 6.09 seconds
Started Jul 22 06:16:30 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 200032 kb
Host smart-fcabcec6-82ba-4406-a822-dea4fb247c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145426001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.145426001
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4051195769
Short name T1053
Test name
Test status
Simulation time 22630889078 ps
CPU time 55.69 seconds
Started Jul 22 06:15:20 PM PDT 24
Finished Jul 22 06:16:16 PM PDT 24
Peak memory 200192 kb
Host smart-f0a00587-d682-4a38-89b8-7f71004d4eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051195769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4051195769
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.843967631
Short name T1130
Test name
Test status
Simulation time 25684244291 ps
CPU time 51.57 seconds
Started Jul 22 06:15:45 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 200152 kb
Host smart-ee02aaaa-3a9f-45ee-8391-22acfb4f3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843967631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.843967631
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2641271312
Short name T151
Test name
Test status
Simulation time 307302069113 ps
CPU time 415.73 seconds
Started Jul 22 06:15:14 PM PDT 24
Finished Jul 22 06:22:10 PM PDT 24
Peak memory 200240 kb
Host smart-12909e7f-3388-4d86-bfc8-dc4c2dd03d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641271312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2641271312
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1314577016
Short name T1059
Test name
Test status
Simulation time 29136123790 ps
CPU time 22.12 seconds
Started Jul 22 06:15:15 PM PDT 24
Finished Jul 22 06:15:38 PM PDT 24
Peak memory 200228 kb
Host smart-cec6cf28-3cb4-4d3d-8d8b-954d40f8344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314577016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1314577016
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1364190372
Short name T964
Test name
Test status
Simulation time 11799512 ps
CPU time 0.61 seconds
Started Jul 22 06:12:44 PM PDT 24
Finished Jul 22 06:12:45 PM PDT 24
Peak memory 195072 kb
Host smart-8f1f5373-968f-48c7-9f97-a09cff10f764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364190372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1364190372
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3454737063
Short name T738
Test name
Test status
Simulation time 20195299546 ps
CPU time 32.74 seconds
Started Jul 22 06:11:55 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 200204 kb
Host smart-2c39f911-f952-4c0a-95cc-6e5305d00199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454737063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3454737063
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2901990111
Short name T1061
Test name
Test status
Simulation time 98679184280 ps
CPU time 36.82 seconds
Started Jul 22 06:11:55 PM PDT 24
Finished Jul 22 06:12:33 PM PDT 24
Peak memory 200156 kb
Host smart-697bb798-4d8b-4003-8a86-69c9fc9a2275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901990111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2901990111
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.696191326
Short name T94
Test name
Test status
Simulation time 148347085417 ps
CPU time 13.64 seconds
Started Jul 22 06:11:57 PM PDT 24
Finished Jul 22 06:12:11 PM PDT 24
Peak memory 200248 kb
Host smart-f43f177f-386b-433d-be56-03a4eca44649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696191326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.696191326
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.950889881
Short name T608
Test name
Test status
Simulation time 16857778901 ps
CPU time 25.98 seconds
Started Jul 22 06:11:52 PM PDT 24
Finished Jul 22 06:12:18 PM PDT 24
Peak memory 199108 kb
Host smart-427db089-8d34-4b90-a74f-93b0ae6760f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950889881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.950889881
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.934588609
Short name T978
Test name
Test status
Simulation time 117928794701 ps
CPU time 255.67 seconds
Started Jul 22 06:11:57 PM PDT 24
Finished Jul 22 06:16:13 PM PDT 24
Peak memory 200220 kb
Host smart-608181e3-e265-4f06-a632-17132c879b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934588609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.934588609
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3822373251
Short name T310
Test name
Test status
Simulation time 5108389490 ps
CPU time 8.73 seconds
Started Jul 22 06:11:55 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 199828 kb
Host smart-510d6864-73ff-46d4-a208-a6384cc0ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822373251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3822373251
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1193843799
Short name T601
Test name
Test status
Simulation time 64094097952 ps
CPU time 63.03 seconds
Started Jul 22 06:11:55 PM PDT 24
Finished Jul 22 06:12:59 PM PDT 24
Peak memory 200136 kb
Host smart-a1e12523-11c0-41f6-8584-597e0c2c8186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193843799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1193843799
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1514993990
Short name T742
Test name
Test status
Simulation time 2293939868 ps
CPU time 104.03 seconds
Started Jul 22 06:11:51 PM PDT 24
Finished Jul 22 06:13:35 PM PDT 24
Peak memory 200140 kb
Host smart-555ecfb0-2615-4501-9a78-b8a1a935ba4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514993990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1514993990
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2403309433
Short name T1020
Test name
Test status
Simulation time 1808780614 ps
CPU time 2.73 seconds
Started Jul 22 06:11:56 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 199320 kb
Host smart-1f02658a-77cc-46df-8c66-89d072f0f550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403309433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2403309433
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.294730541
Short name T16
Test name
Test status
Simulation time 22140803766 ps
CPU time 31.55 seconds
Started Jul 22 06:11:52 PM PDT 24
Finished Jul 22 06:12:24 PM PDT 24
Peak memory 200188 kb
Host smart-4bb20b16-bbf5-4a61-a3e5-5cc1a320fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294730541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.294730541
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.81270809
Short name T660
Test name
Test status
Simulation time 45187252025 ps
CPU time 16.11 seconds
Started Jul 22 06:11:52 PM PDT 24
Finished Jul 22 06:12:08 PM PDT 24
Peak memory 196104 kb
Host smart-d053cbc6-b31c-44dd-bac8-921a3683bda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81270809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.81270809
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3268121522
Short name T697
Test name
Test status
Simulation time 517216761 ps
CPU time 1.27 seconds
Started Jul 22 06:11:57 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 199012 kb
Host smart-9de54756-6c71-404d-b267-6792d1cb223f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268121522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3268121522
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1063269794
Short name T564
Test name
Test status
Simulation time 48792752511 ps
CPU time 27.71 seconds
Started Jul 22 06:11:51 PM PDT 24
Finished Jul 22 06:12:19 PM PDT 24
Peak memory 216680 kb
Host smart-aae1d58e-01b3-4e17-a071-999272d5cdad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063269794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1063269794
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.496551423
Short name T108
Test name
Test status
Simulation time 19732128557 ps
CPU time 187.49 seconds
Started Jul 22 06:11:50 PM PDT 24
Finished Jul 22 06:14:59 PM PDT 24
Peak memory 216864 kb
Host smart-b8570171-49ba-4bfd-a4fc-cbe1bdd072e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496551423 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.496551423
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1921181659
Short name T764
Test name
Test status
Simulation time 792643475 ps
CPU time 2.74 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:11:58 PM PDT 24
Peak memory 198560 kb
Host smart-6c5a8ad2-993b-4284-960d-4361f7b642f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921181659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1921181659
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3314978473
Short name T931
Test name
Test status
Simulation time 7731775343 ps
CPU time 11.88 seconds
Started Jul 22 06:15:13 PM PDT 24
Finished Jul 22 06:15:26 PM PDT 24
Peak memory 199380 kb
Host smart-993e3dda-dee9-46f4-8bf4-1d0c7023d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314978473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3314978473
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.566208809
Short name T449
Test name
Test status
Simulation time 252715128812 ps
CPU time 159.59 seconds
Started Jul 22 06:15:20 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 200208 kb
Host smart-2f23d66b-4c75-40fc-ac57-02b05f37bd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566208809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.566208809
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2926123235
Short name T1079
Test name
Test status
Simulation time 8696783426 ps
CPU time 7.84 seconds
Started Jul 22 06:15:17 PM PDT 24
Finished Jul 22 06:15:25 PM PDT 24
Peak memory 199940 kb
Host smart-f020fd9d-3486-4121-8af2-d1ea87742c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926123235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2926123235
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3935999398
Short name T995
Test name
Test status
Simulation time 14291815781 ps
CPU time 29.41 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 200088 kb
Host smart-41a61b8a-dfeb-41de-a008-c631064942ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935999398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3935999398
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1682814887
Short name T1101
Test name
Test status
Simulation time 28564910564 ps
CPU time 51.14 seconds
Started Jul 22 06:15:17 PM PDT 24
Finished Jul 22 06:16:08 PM PDT 24
Peak memory 200136 kb
Host smart-324ee98f-c78d-4a72-ad81-e01c8b70fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682814887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1682814887
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3741637608
Short name T1051
Test name
Test status
Simulation time 22275291096 ps
CPU time 38.76 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:15:55 PM PDT 24
Peak memory 200176 kb
Host smart-4987dc90-f384-4fbc-9623-736a04fe00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741637608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3741637608
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3198094299
Short name T634
Test name
Test status
Simulation time 16255856169 ps
CPU time 26.46 seconds
Started Jul 22 06:15:16 PM PDT 24
Finished Jul 22 06:15:43 PM PDT 24
Peak memory 200088 kb
Host smart-d6422cae-265d-498e-9206-20a922b9cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198094299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3198094299
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1842099400
Short name T395
Test name
Test status
Simulation time 24717000761 ps
CPU time 35.43 seconds
Started Jul 22 06:15:41 PM PDT 24
Finished Jul 22 06:16:17 PM PDT 24
Peak memory 200240 kb
Host smart-975b42a2-c0fe-405c-a1db-915e843d8f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842099400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1842099400
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4290980656
Short name T956
Test name
Test status
Simulation time 15860423 ps
CPU time 0.54 seconds
Started Jul 22 06:12:00 PM PDT 24
Finished Jul 22 06:12:01 PM PDT 24
Peak memory 195872 kb
Host smart-35f631b7-d3c6-4f85-8de6-9ea768ffad63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290980656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4290980656
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2975075762
Short name T665
Test name
Test status
Simulation time 24034980336 ps
CPU time 11.4 seconds
Started Jul 22 06:11:57 PM PDT 24
Finished Jul 22 06:12:09 PM PDT 24
Peak memory 200248 kb
Host smart-8a1c9066-e9f5-4249-b0d3-3b1f91bc9222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975075762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2975075762
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.778964453
Short name T1138
Test name
Test status
Simulation time 25582698898 ps
CPU time 35.62 seconds
Started Jul 22 06:11:55 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 199728 kb
Host smart-e1e32d02-c475-45ae-be4b-935d450842ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778964453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.778964453
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.707671794
Short name T12
Test name
Test status
Simulation time 271249432042 ps
CPU time 99.14 seconds
Started Jul 22 06:11:52 PM PDT 24
Finished Jul 22 06:13:32 PM PDT 24
Peak memory 200176 kb
Host smart-fdf42976-0d0e-4644-b431-3eba20fd51ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707671794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.707671794
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4205480502
Short name T930
Test name
Test status
Simulation time 195412558311 ps
CPU time 237.89 seconds
Started Jul 22 06:12:03 PM PDT 24
Finished Jul 22 06:16:01 PM PDT 24
Peak memory 200244 kb
Host smart-07886e87-cce4-462a-9eb3-359bd270c564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205480502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4205480502
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2680052807
Short name T861
Test name
Test status
Simulation time 1901595186 ps
CPU time 1.48 seconds
Started Jul 22 06:12:01 PM PDT 24
Finished Jul 22 06:12:03 PM PDT 24
Peak memory 196184 kb
Host smart-fc53010c-649c-41ba-89af-f97c72565699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680052807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2680052807
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3823079084
Short name T465
Test name
Test status
Simulation time 4902360797 ps
CPU time 8.09 seconds
Started Jul 22 06:11:54 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 195324 kb
Host smart-0d73e6c2-70bf-4bc7-b96c-cd5bcb018cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823079084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3823079084
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2663608509
Short name T1109
Test name
Test status
Simulation time 2645537355 ps
CPU time 9.21 seconds
Started Jul 22 06:11:53 PM PDT 24
Finished Jul 22 06:12:03 PM PDT 24
Peak memory 198344 kb
Host smart-6cac8c9e-62ca-42d1-9843-f1f82d85ae5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663608509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2663608509
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1063508894
Short name T825
Test name
Test status
Simulation time 154368403102 ps
CPU time 13.62 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:12:16 PM PDT 24
Peak memory 200188 kb
Host smart-866b7d50-f4e9-42c0-8e1b-03e646e223f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063508894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1063508894
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3179905564
Short name T421
Test name
Test status
Simulation time 43585806916 ps
CPU time 29.19 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 196060 kb
Host smart-b8722846-bc75-4fbc-b0b7-fffe042794e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179905564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3179905564
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3588823321
Short name T376
Test name
Test status
Simulation time 134281828 ps
CPU time 0.75 seconds
Started Jul 22 06:11:56 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 198124 kb
Host smart-20486be2-9c0d-483e-8572-a1f167b0dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588823321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3588823321
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3552899979
Short name T885
Test name
Test status
Simulation time 62300457277 ps
CPU time 71.19 seconds
Started Jul 22 06:12:01 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 208432 kb
Host smart-f7218a24-006b-430f-ac4c-5fa7aea58814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552899979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3552899979
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1495726533
Short name T51
Test name
Test status
Simulation time 42050486088 ps
CPU time 262.15 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:16:25 PM PDT 24
Peak memory 216744 kb
Host smart-cc219a88-4568-4aeb-8212-3215b2bcf855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495726533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1495726533
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.11997964
Short name T688
Test name
Test status
Simulation time 488301861 ps
CPU time 1.72 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 198756 kb
Host smart-4416d4aa-e82d-48fd-83f1-296ee7101a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11997964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.11997964
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1118577801
Short name T1143
Test name
Test status
Simulation time 46374569889 ps
CPU time 20.19 seconds
Started Jul 22 06:15:58 PM PDT 24
Finished Jul 22 06:16:19 PM PDT 24
Peak memory 200168 kb
Host smart-c2ac93be-9492-4466-8f38-f193051b1eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118577801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1118577801
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.930700821
Short name T223
Test name
Test status
Simulation time 19534178782 ps
CPU time 31.34 seconds
Started Jul 22 06:15:24 PM PDT 24
Finished Jul 22 06:15:56 PM PDT 24
Peak memory 200184 kb
Host smart-952ad83b-628c-449f-b890-009fcb2a04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930700821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.930700821
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3678587030
Short name T287
Test name
Test status
Simulation time 37606987732 ps
CPU time 56.79 seconds
Started Jul 22 06:15:52 PM PDT 24
Finished Jul 22 06:16:50 PM PDT 24
Peak memory 200088 kb
Host smart-410d9882-4ec5-4a58-accf-ec166e013d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678587030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3678587030
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2658849673
Short name T592
Test name
Test status
Simulation time 14934267082 ps
CPU time 15.12 seconds
Started Jul 22 06:15:29 PM PDT 24
Finished Jul 22 06:15:44 PM PDT 24
Peak memory 200232 kb
Host smart-47e22dac-c051-4005-a7a8-18919709d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658849673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2658849673
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3381260453
Short name T1091
Test name
Test status
Simulation time 21317878196 ps
CPU time 10.22 seconds
Started Jul 22 06:15:58 PM PDT 24
Finished Jul 22 06:16:08 PM PDT 24
Peak memory 200136 kb
Host smart-d8acd5e9-9eed-45c7-a436-38ca6145b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381260453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3381260453
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1820145801
Short name T705
Test name
Test status
Simulation time 9785647573 ps
CPU time 19.03 seconds
Started Jul 22 06:15:41 PM PDT 24
Finished Jul 22 06:16:01 PM PDT 24
Peak memory 200260 kb
Host smart-8d9f004a-d89b-4633-97b1-afbf7e227c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820145801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1820145801
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.97291589
Short name T266
Test name
Test status
Simulation time 7430019735 ps
CPU time 11.81 seconds
Started Jul 22 06:15:25 PM PDT 24
Finished Jul 22 06:15:37 PM PDT 24
Peak memory 199988 kb
Host smart-72d4a662-066b-49e8-a2c0-07f8205a7f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97291589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.97291589
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.459753395
Short name T553
Test name
Test status
Simulation time 60823814471 ps
CPU time 73.83 seconds
Started Jul 22 06:15:25 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200256 kb
Host smart-64bab5f2-cdf1-4d41-90e6-c4e6af988942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459753395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.459753395
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1228789239
Short name T431
Test name
Test status
Simulation time 17950927 ps
CPU time 0.6 seconds
Started Jul 22 06:12:05 PM PDT 24
Finished Jul 22 06:12:06 PM PDT 24
Peak memory 194588 kb
Host smart-eadd7b88-58b8-44e2-a0d4-32403174534e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228789239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1228789239
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4151726756
Short name T401
Test name
Test status
Simulation time 210204550410 ps
CPU time 142.7 seconds
Started Jul 22 06:12:07 PM PDT 24
Finished Jul 22 06:14:30 PM PDT 24
Peak memory 200292 kb
Host smart-e8675e80-b331-4903-99a9-02ffa9ee8b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151726756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4151726756
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2062973834
Short name T154
Test name
Test status
Simulation time 72493106156 ps
CPU time 20.32 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:12:23 PM PDT 24
Peak memory 200172 kb
Host smart-fafe780d-daf5-436f-8923-6d42e05b036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062973834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2062973834
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2098906797
Short name T1161
Test name
Test status
Simulation time 60764022920 ps
CPU time 23.39 seconds
Started Jul 22 06:12:03 PM PDT 24
Finished Jul 22 06:12:27 PM PDT 24
Peak memory 196792 kb
Host smart-abd6f84c-df28-4c7e-b364-e57acc823ed7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098906797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2098906797
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2263898055
Short name T544
Test name
Test status
Simulation time 63157771811 ps
CPU time 413.36 seconds
Started Jul 22 06:11:56 PM PDT 24
Finished Jul 22 06:18:50 PM PDT 24
Peak memory 200160 kb
Host smart-a43aedba-282f-415a-89a2-e1f8ca54f915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263898055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2263898055
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.737392817
Short name T997
Test name
Test status
Simulation time 1883053395 ps
CPU time 3.49 seconds
Started Jul 22 06:12:03 PM PDT 24
Finished Jul 22 06:12:07 PM PDT 24
Peak memory 197496 kb
Host smart-9cb50330-59f7-4c93-9329-b115e6615dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737392817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.737392817
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4226431996
Short name T392
Test name
Test status
Simulation time 283662572248 ps
CPU time 49.49 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:12:53 PM PDT 24
Peak memory 208588 kb
Host smart-66c551bc-75f8-468c-a6a4-1271e241f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226431996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4226431996
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.683214863
Short name T732
Test name
Test status
Simulation time 30866199754 ps
CPU time 447.01 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 200240 kb
Host smart-b0cc7625-a6c0-4b52-ab1b-02b89cfc4540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683214863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.683214863
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.4196775188
Short name T487
Test name
Test status
Simulation time 5123552633 ps
CPU time 29.66 seconds
Started Jul 22 06:12:08 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 199592 kb
Host smart-e3e9be11-1956-4e76-ba22-c57b1aeac6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196775188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.4196775188
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.952703125
Short name T828
Test name
Test status
Simulation time 109960638708 ps
CPU time 60.19 seconds
Started Jul 22 06:12:05 PM PDT 24
Finished Jul 22 06:13:06 PM PDT 24
Peak memory 200252 kb
Host smart-da93628d-b0fd-4544-b966-b41a62670b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952703125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.952703125
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1161060973
Short name T1076
Test name
Test status
Simulation time 818951372 ps
CPU time 1.37 seconds
Started Jul 22 06:12:06 PM PDT 24
Finished Jul 22 06:12:08 PM PDT 24
Peak memory 195968 kb
Host smart-26e2c512-c8eb-49d8-96ac-46e7b084d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161060973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1161060973
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3817608427
Short name T555
Test name
Test status
Simulation time 292324311 ps
CPU time 1.01 seconds
Started Jul 22 06:12:06 PM PDT 24
Finished Jul 22 06:12:08 PM PDT 24
Peak memory 199428 kb
Host smart-b4806e84-7ab8-47c5-9342-c8885f5a3e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817608427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3817608427
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.4164904718
Short name T499
Test name
Test status
Simulation time 103784876982 ps
CPU time 1190.8 seconds
Started Jul 22 06:12:00 PM PDT 24
Finished Jul 22 06:31:52 PM PDT 24
Peak memory 200228 kb
Host smart-e451e50d-3f10-4f64-a7ec-bdfb3bdd9398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164904718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4164904718
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2629337020
Short name T68
Test name
Test status
Simulation time 178349577389 ps
CPU time 255.54 seconds
Started Jul 22 06:12:02 PM PDT 24
Finished Jul 22 06:16:18 PM PDT 24
Peak memory 216856 kb
Host smart-86c2e86a-5972-460a-9c1f-b178d0b82d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629337020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2629337020
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.922074519
Short name T339
Test name
Test status
Simulation time 7994777363 ps
CPU time 10.66 seconds
Started Jul 22 06:12:01 PM PDT 24
Finished Jul 22 06:12:12 PM PDT 24
Peak memory 200080 kb
Host smart-b379eea5-c4f2-438d-939b-624806863cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922074519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.922074519
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2653567754
Short name T1119
Test name
Test status
Simulation time 57597623726 ps
CPU time 19.5 seconds
Started Jul 22 06:12:08 PM PDT 24
Finished Jul 22 06:12:28 PM PDT 24
Peak memory 200164 kb
Host smart-8ac44549-1362-4619-9df9-8f2aa0dd6943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653567754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2653567754
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2524029214
Short name T303
Test name
Test status
Simulation time 21937098212 ps
CPU time 8.17 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:15:31 PM PDT 24
Peak memory 200200 kb
Host smart-94f4d91c-52b5-4b07-b58e-d616be0b6ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524029214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2524029214
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1951587816
Short name T209
Test name
Test status
Simulation time 159213869535 ps
CPU time 80.73 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:16:44 PM PDT 24
Peak memory 200256 kb
Host smart-4864077f-ae09-4fa8-988b-c44ac7a6e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951587816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1951587816
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1526319520
Short name T757
Test name
Test status
Simulation time 46120595333 ps
CPU time 18.76 seconds
Started Jul 22 06:15:27 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 200128 kb
Host smart-5ee72540-3c29-434e-8713-04a24bd6d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526319520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1526319520
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.4090787892
Short name T217
Test name
Test status
Simulation time 59806388634 ps
CPU time 15.07 seconds
Started Jul 22 06:15:23 PM PDT 24
Finished Jul 22 06:15:39 PM PDT 24
Peak memory 200164 kb
Host smart-4313ee53-4306-48f5-908b-ca4fb476cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090787892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4090787892
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3050038656
Short name T1154
Test name
Test status
Simulation time 99919310931 ps
CPU time 63.31 seconds
Started Jul 22 06:15:24 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200260 kb
Host smart-a99c5527-2084-4798-975d-a2aed7711f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050038656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3050038656
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3385713000
Short name T712
Test name
Test status
Simulation time 109906503242 ps
CPU time 178.54 seconds
Started Jul 22 06:15:26 PM PDT 24
Finished Jul 22 06:18:25 PM PDT 24
Peak memory 200128 kb
Host smart-e7f551b3-d41d-4e41-8849-edb47a75a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385713000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3385713000
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2327270932
Short name T304
Test name
Test status
Simulation time 150418665385 ps
CPU time 217.94 seconds
Started Jul 22 06:15:39 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 200256 kb
Host smart-8cdfd253-72cd-4b1f-b7f0-f67ee7bb4800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327270932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2327270932
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3807888674
Short name T494
Test name
Test status
Simulation time 67120686405 ps
CPU time 29.2 seconds
Started Jul 22 06:15:36 PM PDT 24
Finished Jul 22 06:16:06 PM PDT 24
Peak memory 200004 kb
Host smart-5d03bb12-fe53-468e-95de-c17d6a33c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807888674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3807888674
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1188420804
Short name T448
Test name
Test status
Simulation time 34789662 ps
CPU time 0.56 seconds
Started Jul 22 06:14:21 PM PDT 24
Finished Jul 22 06:14:22 PM PDT 24
Peak memory 195640 kb
Host smart-9fa3f391-8b94-4cde-aef0-f4b907a79dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188420804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1188420804
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.621201524
Short name T760
Test name
Test status
Simulation time 100274717378 ps
CPU time 66 seconds
Started Jul 22 06:12:17 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 199648 kb
Host smart-44be483b-a27a-4e27-acbe-f3d7f485f900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621201524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.621201524
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3149622370
Short name T1083
Test name
Test status
Simulation time 174404508371 ps
CPU time 181.36 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:15:18 PM PDT 24
Peak memory 200200 kb
Host smart-56ec8360-91b4-42c8-8570-b29d841a31d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149622370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3149622370
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1541300111
Short name T720
Test name
Test status
Simulation time 50000755101 ps
CPU time 76.64 seconds
Started Jul 22 06:12:17 PM PDT 24
Finished Jul 22 06:13:35 PM PDT 24
Peak memory 199688 kb
Host smart-3355be3b-5df8-4422-a228-ade224f2a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541300111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1541300111
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3223424255
Short name T852
Test name
Test status
Simulation time 30949821123 ps
CPU time 15.79 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 200184 kb
Host smart-25722604-8355-401e-97b3-a958648ede41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223424255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3223424255
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2721495448
Short name T951
Test name
Test status
Simulation time 323501108841 ps
CPU time 368.93 seconds
Started Jul 22 06:12:16 PM PDT 24
Finished Jul 22 06:18:26 PM PDT 24
Peak memory 200228 kb
Host smart-51dc9a94-9fcf-42c2-89d1-df9c9a14a85f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721495448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2721495448
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.377988114
Short name T408
Test name
Test status
Simulation time 2896945427 ps
CPU time 6.38 seconds
Started Jul 22 06:12:12 PM PDT 24
Finished Jul 22 06:12:19 PM PDT 24
Peak memory 199412 kb
Host smart-0f8c2a32-b5af-4cd2-bba4-e8dd1f531552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377988114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.377988114
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.319728344
Short name T827
Test name
Test status
Simulation time 16488986349 ps
CPU time 24.67 seconds
Started Jul 22 06:13:56 PM PDT 24
Finished Jul 22 06:14:22 PM PDT 24
Peak memory 195808 kb
Host smart-62084073-4b75-42bb-90ea-f791723a3c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319728344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.319728344
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.988165523
Short name T736
Test name
Test status
Simulation time 9078844844 ps
CPU time 108.07 seconds
Started Jul 22 06:12:16 PM PDT 24
Finished Jul 22 06:14:05 PM PDT 24
Peak memory 200224 kb
Host smart-5b9a6651-d9e7-4e90-abe9-6cef5a55f809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988165523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.988165523
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.561921741
Short name T346
Test name
Test status
Simulation time 4302882572 ps
CPU time 22.46 seconds
Started Jul 22 06:13:56 PM PDT 24
Finished Jul 22 06:14:19 PM PDT 24
Peak memory 199448 kb
Host smart-22cb5886-63e8-4119-93a2-18533224d977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561921741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.561921741
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4253059696
Short name T254
Test name
Test status
Simulation time 234203805908 ps
CPU time 176.62 seconds
Started Jul 22 06:13:42 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200172 kb
Host smart-b07f108c-b8ef-4c6a-97b4-d99f610bf5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253059696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4253059696
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3573008222
Short name T19
Test name
Test status
Simulation time 2141158426 ps
CPU time 1.74 seconds
Started Jul 22 06:12:18 PM PDT 24
Finished Jul 22 06:12:20 PM PDT 24
Peak memory 195928 kb
Host smart-8dfe244c-5a17-4d70-be79-a84be27c5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573008222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3573008222
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3181439904
Short name T902
Test name
Test status
Simulation time 882021371 ps
CPU time 2.7 seconds
Started Jul 22 06:12:17 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 199824 kb
Host smart-12364023-a957-4995-9716-83b41903de15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181439904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3181439904
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2066757115
Short name T1072
Test name
Test status
Simulation time 124447244088 ps
CPU time 251.89 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 200204 kb
Host smart-d0a7b9ef-29e3-40db-87eb-0f1f9ac45f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066757115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2066757115
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.700625296
Short name T1087
Test name
Test status
Simulation time 31195436745 ps
CPU time 191.11 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:15:27 PM PDT 24
Peak memory 216916 kb
Host smart-97e43af6-c643-4dfd-b952-6433369d3630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700625296 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.700625296
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1836111562
Short name T282
Test name
Test status
Simulation time 2666601300 ps
CPU time 2.38 seconds
Started Jul 22 06:12:17 PM PDT 24
Finished Jul 22 06:12:20 PM PDT 24
Peak memory 199132 kb
Host smart-b4c9ccdc-41a1-40d8-904a-483e00ac1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836111562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1836111562
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4000923162
Short name T571
Test name
Test status
Simulation time 93585774914 ps
CPU time 186.93 seconds
Started Jul 22 06:12:16 PM PDT 24
Finished Jul 22 06:15:23 PM PDT 24
Peak memory 200232 kb
Host smart-1cdc106c-6378-4370-b61c-390933850df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000923162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4000923162
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2476599853
Short name T841
Test name
Test status
Simulation time 21931155559 ps
CPU time 33.44 seconds
Started Jul 22 06:15:38 PM PDT 24
Finished Jul 22 06:16:12 PM PDT 24
Peak memory 200252 kb
Host smart-e80c964e-0f62-4ea7-b349-5b51cfa25af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476599853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2476599853
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.19734400
Short name T557
Test name
Test status
Simulation time 36862165538 ps
CPU time 30.49 seconds
Started Jul 22 06:15:38 PM PDT 24
Finished Jul 22 06:16:09 PM PDT 24
Peak memory 200196 kb
Host smart-c109ea61-86be-44f5-a23d-8b0206ccca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19734400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.19734400
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3034426970
Short name T615
Test name
Test status
Simulation time 177438486236 ps
CPU time 19.97 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:16:20 PM PDT 24
Peak memory 200112 kb
Host smart-1e2f6bc9-09bf-4bd6-baa6-56f455ae4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034426970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3034426970
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1768360356
Short name T889
Test name
Test status
Simulation time 169498405665 ps
CPU time 62.09 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:17:03 PM PDT 24
Peak memory 200164 kb
Host smart-f9e2a87b-9671-4675-ae74-cd444006b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768360356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1768360356
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.845679248
Short name T258
Test name
Test status
Simulation time 31820966681 ps
CPU time 29.9 seconds
Started Jul 22 06:15:35 PM PDT 24
Finished Jul 22 06:16:05 PM PDT 24
Peak memory 200280 kb
Host smart-aae4a438-f96d-4c5e-bc99-752a58783d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845679248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.845679248
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3813566197
Short name T404
Test name
Test status
Simulation time 57645231387 ps
CPU time 19.06 seconds
Started Jul 22 06:15:38 PM PDT 24
Finished Jul 22 06:15:58 PM PDT 24
Peak memory 200256 kb
Host smart-093b6dc1-560e-461f-9101-f114b268c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813566197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3813566197
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.514864862
Short name T93
Test name
Test status
Simulation time 21763447078 ps
CPU time 18.68 seconds
Started Jul 22 06:15:34 PM PDT 24
Finished Jul 22 06:15:54 PM PDT 24
Peak memory 200256 kb
Host smart-f3fd5b02-afd1-4dc7-80f8-f9e8011efab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514864862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.514864862
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1883583794
Short name T235
Test name
Test status
Simulation time 139952570715 ps
CPU time 110.66 seconds
Started Jul 22 06:15:32 PM PDT 24
Finished Jul 22 06:17:23 PM PDT 24
Peak memory 200180 kb
Host smart-b8b5fc4a-f488-44a3-8aba-f0e0532aad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883583794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1883583794
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4288920212
Short name T963
Test name
Test status
Simulation time 164284210318 ps
CPU time 46.29 seconds
Started Jul 22 06:15:37 PM PDT 24
Finished Jul 22 06:16:24 PM PDT 24
Peak memory 200128 kb
Host smart-d50681d3-b3d8-43a2-881d-720cd4eb6ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288920212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4288920212
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2014991577
Short name T791
Test name
Test status
Simulation time 29656195 ps
CPU time 0.55 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 195640 kb
Host smart-16bfba81-9b02-4969-9634-ead8f163c85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014991577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2014991577
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.4068606859
Short name T387
Test name
Test status
Simulation time 9086660996 ps
CPU time 13.27 seconds
Started Jul 22 06:12:11 PM PDT 24
Finished Jul 22 06:12:24 PM PDT 24
Peak memory 200224 kb
Host smart-57818c02-4691-4ebd-b65d-ebe8e39d0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068606859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4068606859
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.637239791
Short name T622
Test name
Test status
Simulation time 3179644555 ps
CPU time 5.29 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 199484 kb
Host smart-51527c63-9bdc-4f17-8b48-8974848e29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637239791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.637239791
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.681441333
Short name T800
Test name
Test status
Simulation time 61082309916 ps
CPU time 34.65 seconds
Started Jul 22 06:12:13 PM PDT 24
Finished Jul 22 06:12:48 PM PDT 24
Peak memory 200244 kb
Host smart-4b30d933-d313-4dfc-8b78-ce99201bae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681441333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.681441333
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.701480412
Short name T821
Test name
Test status
Simulation time 14364484743 ps
CPU time 29.76 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:12:46 PM PDT 24
Peak memory 200232 kb
Host smart-f25377d9-7df7-4c14-b871-f6222401a079
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701480412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.701480412
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2310733813
Short name T1028
Test name
Test status
Simulation time 236152176067 ps
CPU time 341.6 seconds
Started Jul 22 06:12:14 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 200280 kb
Host smart-8a999eaa-e403-42d8-ad54-8ec9e113e660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310733813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2310733813
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1546955672
Short name T782
Test name
Test status
Simulation time 10061717853 ps
CPU time 20.45 seconds
Started Jul 22 06:12:14 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 200268 kb
Host smart-cd032f75-cd09-483a-8732-be3f58731b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546955672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1546955672
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4130977783
Short name T1153
Test name
Test status
Simulation time 75077505492 ps
CPU time 32.31 seconds
Started Jul 22 06:12:16 PM PDT 24
Finished Jul 22 06:12:49 PM PDT 24
Peak memory 200396 kb
Host smart-b0c4c504-fcf6-411f-ab10-1a8045f2568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130977783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4130977783
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3215729812
Short name T1178
Test name
Test status
Simulation time 13267497895 ps
CPU time 181.27 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200232 kb
Host smart-698896e0-d460-470e-8bdd-f6a5135a046e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215729812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3215729812
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1595695755
Short name T337
Test name
Test status
Simulation time 2020788606 ps
CPU time 4.8 seconds
Started Jul 22 06:12:15 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 198072 kb
Host smart-3441a07c-8b40-4162-855d-ab5659f09276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595695755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1595695755
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.606564206
Short name T528
Test name
Test status
Simulation time 48579896079 ps
CPU time 91.1 seconds
Started Jul 22 06:12:18 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 200172 kb
Host smart-8a20d04d-f89f-4ebb-a31f-811f7bfa1c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606564206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.606564206
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.483976653
Short name T628
Test name
Test status
Simulation time 647878394 ps
CPU time 1.5 seconds
Started Jul 22 06:12:16 PM PDT 24
Finished Jul 22 06:12:18 PM PDT 24
Peak memory 195744 kb
Host smart-004d0786-4801-4c7b-954d-3c1d234cd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483976653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.483976653
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.902445231
Short name T840
Test name
Test status
Simulation time 271410332 ps
CPU time 1.68 seconds
Started Jul 22 06:12:14 PM PDT 24
Finished Jul 22 06:12:16 PM PDT 24
Peak memory 200124 kb
Host smart-d2b0e37d-ded9-4e4e-a496-c108c5036391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902445231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.902445231
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.966598126
Short name T440
Test name
Test status
Simulation time 174481078293 ps
CPU time 185.78 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:15:32 PM PDT 24
Peak memory 208484 kb
Host smart-b8393225-c2d4-4853-a5de-bffd1ff05a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966598126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.966598126
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4237514971
Short name T996
Test name
Test status
Simulation time 7789899529 ps
CPU time 12.9 seconds
Started Jul 22 06:12:14 PM PDT 24
Finished Jul 22 06:12:27 PM PDT 24
Peak memory 200140 kb
Host smart-e5c6970d-a82d-4905-92ba-1295aa1c7f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237514971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4237514971
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4090967982
Short name T308
Test name
Test status
Simulation time 15447760596 ps
CPU time 21.95 seconds
Started Jul 22 06:12:17 PM PDT 24
Finished Jul 22 06:12:40 PM PDT 24
Peak memory 199124 kb
Host smart-6f341f55-8e93-422a-8690-738f62437690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090967982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4090967982
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.982720815
Short name T297
Test name
Test status
Simulation time 16989973982 ps
CPU time 26.8 seconds
Started Jul 22 06:15:33 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 198580 kb
Host smart-e620a529-fa14-4380-928f-be76a7425cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982720815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.982720815
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3504436196
Short name T202
Test name
Test status
Simulation time 88311107031 ps
CPU time 174.03 seconds
Started Jul 22 06:15:35 PM PDT 24
Finished Jul 22 06:18:29 PM PDT 24
Peak memory 200200 kb
Host smart-ccf2accd-1655-4fb1-b472-2a2488baf4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504436196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3504436196
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1245119092
Short name T147
Test name
Test status
Simulation time 20499627006 ps
CPU time 27.24 seconds
Started Jul 22 06:15:33 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 200100 kb
Host smart-1bfeba8a-530f-43a3-a515-662419cc9230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245119092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1245119092
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1905743763
Short name T739
Test name
Test status
Simulation time 88186912318 ps
CPU time 133.04 seconds
Started Jul 22 06:15:52 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 199976 kb
Host smart-97658e34-6fdf-47f2-af51-45c37caca084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905743763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1905743763
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3790737435
Short name T178
Test name
Test status
Simulation time 136657920821 ps
CPU time 219.08 seconds
Started Jul 22 06:15:39 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 200196 kb
Host smart-f1fe0e83-a0f3-47a4-87d8-efc9ba77c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790737435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3790737435
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.165909290
Short name T588
Test name
Test status
Simulation time 51696491575 ps
CPU time 37.73 seconds
Started Jul 22 06:15:34 PM PDT 24
Finished Jul 22 06:16:12 PM PDT 24
Peak memory 200196 kb
Host smart-a948ec07-907a-431b-8ada-b1fa5c500392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165909290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.165909290
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1020170296
Short name T1108
Test name
Test status
Simulation time 60414832650 ps
CPU time 60.08 seconds
Started Jul 22 06:15:40 PM PDT 24
Finished Jul 22 06:16:40 PM PDT 24
Peak memory 200160 kb
Host smart-8dd5cb87-6fb8-4179-8b46-116a7e6a988a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020170296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1020170296
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2412678077
Short name T445
Test name
Test status
Simulation time 72094464152 ps
CPU time 27.67 seconds
Started Jul 22 06:15:32 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 200164 kb
Host smart-abb06a99-5c00-45fc-9bd0-15b5b0c01892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412678077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2412678077
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4067988634
Short name T420
Test name
Test status
Simulation time 119330013847 ps
CPU time 251.88 seconds
Started Jul 22 06:15:38 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 200184 kb
Host smart-02352ac6-895d-4b3f-a668-6936d10ae4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067988634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4067988634
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1433355027
Short name T104
Test name
Test status
Simulation time 24711369915 ps
CPU time 38.39 seconds
Started Jul 22 06:15:34 PM PDT 24
Finished Jul 22 06:16:13 PM PDT 24
Peak memory 200248 kb
Host smart-b61a7ee0-6c96-4632-8a5c-62c1ab60687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433355027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1433355027
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1963120306
Short name T826
Test name
Test status
Simulation time 42939200 ps
CPU time 0.56 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 195628 kb
Host smart-52c66d42-2018-4217-8c0b-1c075d8bb675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963120306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1963120306
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.39953614
Short name T496
Test name
Test status
Simulation time 74765317465 ps
CPU time 27.41 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:54 PM PDT 24
Peak memory 200188 kb
Host smart-ca19a1f9-786a-4223-b924-c76d890f8173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39953614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.39953614
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1899876634
Short name T291
Test name
Test status
Simulation time 117426807385 ps
CPU time 166.88 seconds
Started Jul 22 06:12:23 PM PDT 24
Finished Jul 22 06:15:11 PM PDT 24
Peak memory 200124 kb
Host smart-c77d9fa1-cd1d-4ec0-a293-8c0f2baf1e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899876634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1899876634
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2292519589
Short name T224
Test name
Test status
Simulation time 69313983313 ps
CPU time 31.6 seconds
Started Jul 22 06:12:28 PM PDT 24
Finished Jul 22 06:13:00 PM PDT 24
Peak memory 200084 kb
Host smart-e4f02b69-d1fa-4b73-8ab8-d5cdd59727ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292519589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2292519589
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3844494922
Short name T1010
Test name
Test status
Simulation time 921298448 ps
CPU time 1.99 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 195976 kb
Host smart-125637b7-f923-4a15-aa71-b4d254580d32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844494922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3844494922
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1502976218
Short name T961
Test name
Test status
Simulation time 111281545405 ps
CPU time 674.94 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:23:40 PM PDT 24
Peak memory 200132 kb
Host smart-14abb246-1563-4e6c-9fc6-813da15e8eca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1502976218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1502976218
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3028874298
Short name T39
Test name
Test status
Simulation time 7597872829 ps
CPU time 5.92 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 200136 kb
Host smart-25a2e6f4-f162-45d2-9d75-c15d8cc1fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028874298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3028874298
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3637771847
Short name T302
Test name
Test status
Simulation time 21092286523 ps
CPU time 33.46 seconds
Started Jul 22 06:12:28 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 198044 kb
Host smart-9ee0120b-85c7-4354-8ccf-10369fa33c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637771847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3637771847
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2549901437
Short name T243
Test name
Test status
Simulation time 10621958277 ps
CPU time 258.45 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 200204 kb
Host smart-687b5b7a-6f1a-4e1e-9aab-8696427bde58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549901437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2549901437
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.50106211
Short name T700
Test name
Test status
Simulation time 6790265931 ps
CPU time 63.83 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:13:31 PM PDT 24
Peak memory 198492 kb
Host smart-d23a9980-2f24-4119-834c-6f8442903b7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50106211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.50106211
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4274879512
Short name T834
Test name
Test status
Simulation time 104747521294 ps
CPU time 52.94 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:13:18 PM PDT 24
Peak memory 200252 kb
Host smart-33262e7f-83a9-46b1-9818-88a252972276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274879512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4274879512
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4069072473
Short name T683
Test name
Test status
Simulation time 4805620907 ps
CPU time 2.67 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 196532 kb
Host smart-57065fed-5f48-47c7-b134-0720faea1c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069072473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4069072473
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1744250332
Short name T397
Test name
Test status
Simulation time 150041540 ps
CPU time 0.79 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:12:28 PM PDT 24
Peak memory 197652 kb
Host smart-b27d439b-2aae-4d22-ad34-04e2039281a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744250332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1744250332
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3485837970
Short name T137
Test name
Test status
Simulation time 445573193673 ps
CPU time 102.84 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:15:41 PM PDT 24
Peak memory 200228 kb
Host smart-cf5cb3a5-43f3-4f55-bdf2-b763bbaad9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485837970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3485837970
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3396003172
Short name T934
Test name
Test status
Simulation time 104571292608 ps
CPU time 342 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:18:09 PM PDT 24
Peak memory 216676 kb
Host smart-f60ac2d3-f502-4a49-9f51-aa96de877171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396003172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3396003172
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.389961325
Short name T835
Test name
Test status
Simulation time 655055693 ps
CPU time 1.85 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 198992 kb
Host smart-42eeedb6-38f8-4ff1-af48-d01bdd13621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389961325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.389961325
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1962939420
Short name T541
Test name
Test status
Simulation time 54992471754 ps
CPU time 29.57 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 200228 kb
Host smart-147d97a0-6d02-4f23-a381-fb5d7fcd023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962939420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1962939420
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.297444051
Short name T1127
Test name
Test status
Simulation time 154577648819 ps
CPU time 55.58 seconds
Started Jul 22 06:15:37 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 200128 kb
Host smart-d7837a9e-ce90-4e78-96d9-dfbf35d16020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297444051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.297444051
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1503507449
Short name T186
Test name
Test status
Simulation time 42614787295 ps
CPU time 16.2 seconds
Started Jul 22 06:15:35 PM PDT 24
Finished Jul 22 06:15:52 PM PDT 24
Peak memory 199128 kb
Host smart-92a38ff4-e4fb-4244-9883-d2eaca0c26e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503507449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1503507449
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4220605336
Short name T210
Test name
Test status
Simulation time 10930585822 ps
CPU time 12.74 seconds
Started Jul 22 06:15:43 PM PDT 24
Finished Jul 22 06:15:57 PM PDT 24
Peak memory 200176 kb
Host smart-a95eec32-85fe-4800-b38b-6240c6595946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220605336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4220605336
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3743077224
Short name T881
Test name
Test status
Simulation time 4545881794 ps
CPU time 7.11 seconds
Started Jul 22 06:15:43 PM PDT 24
Finished Jul 22 06:15:50 PM PDT 24
Peak memory 199604 kb
Host smart-2359c45d-1dd0-43d2-ae7e-3ce0f388a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743077224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3743077224
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3134102074
Short name T187
Test name
Test status
Simulation time 40410895659 ps
CPU time 16.18 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:16:06 PM PDT 24
Peak memory 200156 kb
Host smart-b0365b40-eab8-4a3d-98d9-33df82458199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134102074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3134102074
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2005062315
Short name T1146
Test name
Test status
Simulation time 59640402958 ps
CPU time 21.56 seconds
Started Jul 22 06:15:43 PM PDT 24
Finished Jul 22 06:16:05 PM PDT 24
Peak memory 200196 kb
Host smart-65648b56-fa07-4726-bc91-b03ae3d83ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005062315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2005062315
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1618894437
Short name T871
Test name
Test status
Simulation time 139461118128 ps
CPU time 17.81 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 200184 kb
Host smart-b0293d98-d65e-4b1f-a81a-e63603ac392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618894437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1618894437
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2721800657
Short name T773
Test name
Test status
Simulation time 23711286112 ps
CPU time 42.71 seconds
Started Jul 22 06:15:59 PM PDT 24
Finished Jul 22 06:16:42 PM PDT 24
Peak memory 200196 kb
Host smart-a775a320-497c-4d5d-86e7-75513feb88aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721800657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2721800657
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.567688625
Short name T20
Test name
Test status
Simulation time 87553049 ps
CPU time 0.55 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:11:27 PM PDT 24
Peak memory 195644 kb
Host smart-c15e935a-7a4f-4450-b5fc-48661db88065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567688625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.567688625
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.154775157
Short name T140
Test name
Test status
Simulation time 130490159130 ps
CPU time 182.82 seconds
Started Jul 22 06:13:15 PM PDT 24
Finished Jul 22 06:16:18 PM PDT 24
Peak memory 200264 kb
Host smart-9dc79385-a726-422f-8589-bfa77f9c4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154775157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.154775157
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4272999505
Short name T508
Test name
Test status
Simulation time 16325860853 ps
CPU time 7.84 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:34 PM PDT 24
Peak memory 200236 kb
Host smart-4bbbaed2-1b09-4ece-a08e-f45f77c49e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272999505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4272999505
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4181571183
Short name T539
Test name
Test status
Simulation time 77770141267 ps
CPU time 52.86 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:12:22 PM PDT 24
Peak memory 200080 kb
Host smart-b4f9941f-a7ea-4c72-aa09-60387a7d6ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181571183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4181571183
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.821603959
Short name T503
Test name
Test status
Simulation time 51171406820 ps
CPU time 76.64 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:12:45 PM PDT 24
Peak memory 199880 kb
Host smart-273a5bf2-c7ff-46b2-80a3-836608da87c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821603959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.821603959
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3393333251
Short name T476
Test name
Test status
Simulation time 156919488112 ps
CPU time 208.1 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:14:55 PM PDT 24
Peak memory 200088 kb
Host smart-ed75478f-ce07-4c53-be27-1831f2c6e474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393333251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3393333251
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4078601308
Short name T776
Test name
Test status
Simulation time 686970066 ps
CPU time 1.04 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 196380 kb
Host smart-b26403f3-a0fd-4c7c-b3dc-53357fbaca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078601308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4078601308
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1726301186
Short name T704
Test name
Test status
Simulation time 138603171439 ps
CPU time 111.94 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 200380 kb
Host smart-824adc08-c90f-4f01-9ad5-3625256a97ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726301186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1726301186
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.809092186
Short name T244
Test name
Test status
Simulation time 21252058980 ps
CPU time 932.09 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:26:57 PM PDT 24
Peak memory 200076 kb
Host smart-1d2b8b06-ea59-4bf5-8a56-3e903ed31b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809092186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.809092186
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.830067449
Short name T817
Test name
Test status
Simulation time 4718687457 ps
CPU time 17.89 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 199576 kb
Host smart-35480a6e-d833-425b-8e32-34215ddc97f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830067449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.830067449
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.438761842
Short name T546
Test name
Test status
Simulation time 44942476495 ps
CPU time 74.04 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:12:41 PM PDT 24
Peak memory 200180 kb
Host smart-c2751483-78c8-47c3-b61c-4f9c2e8ec8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438761842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.438761842
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.611874800
Short name T447
Test name
Test status
Simulation time 31207058671 ps
CPU time 20.44 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:46 PM PDT 24
Peak memory 196148 kb
Host smart-fca40344-0796-46cb-a627-897fd2e0a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611874800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.611874800
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.505464845
Short name T87
Test name
Test status
Simulation time 63596687 ps
CPU time 0.84 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:27 PM PDT 24
Peak memory 218472 kb
Host smart-e6395b01-ae7f-473a-ab71-9ccfb63b8fd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505464845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.505464845
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1980442253
Short name T999
Test name
Test status
Simulation time 666402133 ps
CPU time 1.7 seconds
Started Jul 22 06:11:15 PM PDT 24
Finished Jul 22 06:11:17 PM PDT 24
Peak memory 198704 kb
Host smart-aa97d03d-d595-4746-b3cc-034d68f819c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980442253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1980442253
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3415343326
Short name T31
Test name
Test status
Simulation time 207780093878 ps
CPU time 434.36 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:18:40 PM PDT 24
Peak memory 226972 kb
Host smart-baf79b7a-829b-4677-9b3e-94c89656e9f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415343326 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3415343326
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2889032494
Short name T1031
Test name
Test status
Simulation time 919733429 ps
CPU time 1.71 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 198672 kb
Host smart-204f88dc-0351-44d7-85f3-192b29645177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889032494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2889032494
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3940726869
Short name T909
Test name
Test status
Simulation time 34451632658 ps
CPU time 13.7 seconds
Started Jul 22 06:11:17 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 199356 kb
Host smart-af3884e0-db87-4a23-843d-7d279ee5172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940726869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3940726869
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1632185983
Short name T506
Test name
Test status
Simulation time 48164658 ps
CPU time 0.54 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:27 PM PDT 24
Peak memory 195636 kb
Host smart-8c87b386-da62-43b7-ba8b-a1d1e2f1ddf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632185983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1632185983
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2666952415
Short name T880
Test name
Test status
Simulation time 33197914330 ps
CPU time 30.89 seconds
Started Jul 22 06:12:28 PM PDT 24
Finished Jul 22 06:13:00 PM PDT 24
Peak memory 200248 kb
Host smart-26f1c6aa-8fda-4483-9d1b-1891074b7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666952415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2666952415
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.937248881
Short name T945
Test name
Test status
Simulation time 125391991715 ps
CPU time 284.68 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:17:12 PM PDT 24
Peak memory 200176 kb
Host smart-5d9913b6-1e58-4db2-a7d3-4c810d0acd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937248881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.937248881
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1060966298
Short name T283
Test name
Test status
Simulation time 27525202384 ps
CPU time 20.12 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:46 PM PDT 24
Peak memory 200220 kb
Host smart-bcb90749-ae46-4c0d-a1b4-3ef7d45a6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060966298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1060966298
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3483170898
Short name T498
Test name
Test status
Simulation time 396400317875 ps
CPU time 51.88 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 200216 kb
Host smart-c1361917-280a-4e6c-ba4f-9b7ddacc9642
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483170898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3483170898
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2617274802
Short name T1021
Test name
Test status
Simulation time 106410153025 ps
CPU time 660.45 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:23:37 PM PDT 24
Peak memory 200112 kb
Host smart-096ac58c-320a-48dd-8805-7215627b10e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617274802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2617274802
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2339062269
Short name T893
Test name
Test status
Simulation time 10236816594 ps
CPU time 24.62 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:50 PM PDT 24
Peak memory 199280 kb
Host smart-59d849ff-f341-4293-9b19-7f0becab2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339062269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2339062269
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.926618525
Short name T405
Test name
Test status
Simulation time 422263985610 ps
CPU time 104.91 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 208772 kb
Host smart-c309b1d8-6c60-47c3-80fd-1367b26ea86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926618525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.926618525
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.819573285
Short name T965
Test name
Test status
Simulation time 12098056573 ps
CPU time 543.64 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:21:30 PM PDT 24
Peak memory 200264 kb
Host smart-a6971b17-5b35-4d61-a579-00642712e40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819573285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.819573285
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3721505365
Short name T626
Test name
Test status
Simulation time 3245540221 ps
CPU time 2.73 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:12:30 PM PDT 24
Peak memory 198464 kb
Host smart-d046adcd-e5d7-4d6c-8473-2a71c907103b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721505365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3721505365
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.518626857
Short name T935
Test name
Test status
Simulation time 151216525142 ps
CPU time 124.78 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 200164 kb
Host smart-4bbdcd74-6510-430b-b3cb-d5ff5e72f50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518626857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.518626857
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1041301087
Short name T1089
Test name
Test status
Simulation time 35285064845 ps
CPU time 14.51 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:01 PM PDT 24
Peak memory 196320 kb
Host smart-26900f6a-28f6-485b-be24-fe2d94f191d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041301087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1041301087
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3994063386
Short name T985
Test name
Test status
Simulation time 697732099 ps
CPU time 1.97 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:12:53 PM PDT 24
Peak memory 198472 kb
Host smart-775bb0d8-ea90-4a6c-8d61-3f019f50a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994063386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3994063386
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2750864218
Short name T468
Test name
Test status
Simulation time 155252896283 ps
CPU time 273.32 seconds
Started Jul 22 06:12:27 PM PDT 24
Finished Jul 22 06:17:01 PM PDT 24
Peak memory 200228 kb
Host smart-a8631e14-2870-49c0-8388-7a96133f9c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750864218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2750864218
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.4016780299
Short name T1148
Test name
Test status
Simulation time 38319611896 ps
CPU time 561.11 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:21:47 PM PDT 24
Peak memory 216884 kb
Host smart-6f6e5c6a-6206-4d9a-8cac-8cafcb7a8c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016780299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.4016780299
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3659295397
Short name T1054
Test name
Test status
Simulation time 1490160392 ps
CPU time 2.94 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 199984 kb
Host smart-114d9cf4-05a1-493c-a3f1-02fc61b0f4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659295397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3659295397
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.980022334
Short name T540
Test name
Test status
Simulation time 60522513214 ps
CPU time 24.46 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:14:23 PM PDT 24
Peak memory 200236 kb
Host smart-afca01a1-5d45-4982-94d1-5d134c847d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980022334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.980022334
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.437919096
Short name T33
Test name
Test status
Simulation time 486276055762 ps
CPU time 78.58 seconds
Started Jul 22 06:15:41 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 200144 kb
Host smart-4836e0d3-3d73-4e59-95c3-6e430af60dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437919096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.437919096
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1578204912
Short name T174
Test name
Test status
Simulation time 88178938079 ps
CPU time 438.01 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:23:01 PM PDT 24
Peak memory 200248 kb
Host smart-8703f4a8-fd6e-4df3-8998-593ba4d291f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578204912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1578204912
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2174244310
Short name T495
Test name
Test status
Simulation time 40046770873 ps
CPU time 63.81 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 198776 kb
Host smart-d96efa4f-2324-44ec-b93c-e77549f1959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174244310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2174244310
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.273461886
Short name T207
Test name
Test status
Simulation time 103374287013 ps
CPU time 133.17 seconds
Started Jul 22 06:15:41 PM PDT 24
Finished Jul 22 06:17:54 PM PDT 24
Peak memory 200260 kb
Host smart-8959105b-c5a6-40fe-a0aa-2bbd7338297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273461886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.273461886
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1899542265
Short name T1047
Test name
Test status
Simulation time 28935475122 ps
CPU time 44.02 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200132 kb
Host smart-a05f70c7-85a1-442f-99b7-496ba519123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899542265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1899542265
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3804545081
Short name T188
Test name
Test status
Simulation time 72468076759 ps
CPU time 57.9 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 200212 kb
Host smart-19acaf95-d265-4ddd-b718-8ad985c454d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804545081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3804545081
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1034753383
Short name T873
Test name
Test status
Simulation time 33092518468 ps
CPU time 37.15 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200216 kb
Host smart-8909d703-c8af-491f-b0fd-d000a772dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034753383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1034753383
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.262486974
Short name T851
Test name
Test status
Simulation time 76593930436 ps
CPU time 51.68 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:34 PM PDT 24
Peak memory 200180 kb
Host smart-5818ddd6-e0ad-49e0-a8e9-acc564e3fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262486974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.262486974
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.186755632
Short name T474
Test name
Test status
Simulation time 49696258 ps
CPU time 0.55 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:12:49 PM PDT 24
Peak memory 195648 kb
Host smart-bcccf57b-383f-4540-9d26-4dcce9609af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186755632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.186755632
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2256568993
Short name T124
Test name
Test status
Simulation time 56344868465 ps
CPU time 22.94 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:12:48 PM PDT 24
Peak memory 200252 kb
Host smart-1e745326-aa38-4e20-8b03-dd8120f50f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256568993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2256568993
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2510881108
Short name T1030
Test name
Test status
Simulation time 92735752501 ps
CPU time 129.42 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:14:36 PM PDT 24
Peak memory 200408 kb
Host smart-3c300334-5897-47b4-b66c-2dacda013ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510881108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2510881108
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2946221563
Short name T816
Test name
Test status
Simulation time 29916238669 ps
CPU time 27.81 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:13:04 PM PDT 24
Peak memory 200256 kb
Host smart-068a4b6e-2917-4e4f-b054-a7adf54559ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946221563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2946221563
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.397126639
Short name T3
Test name
Test status
Simulation time 48327769097 ps
CPU time 75.23 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 200232 kb
Host smart-b2b777fc-e8d1-4cb0-9f2b-36a99eab6189
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397126639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.397126639
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3250237864
Short name T538
Test name
Test status
Simulation time 163741040014 ps
CPU time 1022.88 seconds
Started Jul 22 06:12:27 PM PDT 24
Finished Jul 22 06:29:30 PM PDT 24
Peak memory 200228 kb
Host smart-69664da3-1044-4885-a903-7e0791eb7a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250237864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3250237864
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.806056961
Short name T533
Test name
Test status
Simulation time 2405050775 ps
CPU time 4.33 seconds
Started Jul 22 06:12:27 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 198916 kb
Host smart-3b334b82-0d7a-4212-ad0b-a7111bc012d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806056961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.806056961
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3000710675
Short name T450
Test name
Test status
Simulation time 402605952470 ps
CPU time 49.22 seconds
Started Jul 22 06:12:26 PM PDT 24
Finished Jul 22 06:13:16 PM PDT 24
Peak memory 200256 kb
Host smart-cc348f34-4776-4a11-acb1-6ca8ced81474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000710675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3000710675
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2409516018
Short name T355
Test name
Test status
Simulation time 16435501340 ps
CPU time 44.36 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:13:21 PM PDT 24
Peak memory 200236 kb
Host smart-4abdb2f6-d451-4171-8dad-4298bc290034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409516018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2409516018
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3153329246
Short name T327
Test name
Test status
Simulation time 4860161493 ps
CPU time 43.43 seconds
Started Jul 22 06:12:24 PM PDT 24
Finished Jul 22 06:13:08 PM PDT 24
Peak memory 198648 kb
Host smart-8f692161-6424-4266-9ad1-9ca608cedf7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153329246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3153329246
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.489308936
Short name T596
Test name
Test status
Simulation time 271261386763 ps
CPU time 39.26 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:13:16 PM PDT 24
Peak memory 200108 kb
Host smart-d522b3b8-7ef0-4e6c-afe2-dfbb53e56287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489308936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.489308936
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2524713290
Short name T492
Test name
Test status
Simulation time 29853376590 ps
CPU time 45.59 seconds
Started Jul 22 06:12:27 PM PDT 24
Finished Jul 22 06:13:14 PM PDT 24
Peak memory 196428 kb
Host smart-4bc20baf-a8d1-4e19-9a51-219fe3d61c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524713290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2524713290
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2316468603
Short name T691
Test name
Test status
Simulation time 714021543 ps
CPU time 2.42 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:32 PM PDT 24
Peak memory 199232 kb
Host smart-75e53d9c-a043-47d3-89bc-59c33a86d54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316468603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2316468603
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1141850440
Short name T679
Test name
Test status
Simulation time 135136831619 ps
CPU time 395.44 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 216816 kb
Host smart-52762590-eb59-4dca-87ba-d86c114c4afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141850440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1141850440
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3533921095
Short name T616
Test name
Test status
Simulation time 241201312 ps
CPU time 1.17 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 198656 kb
Host smart-a511e001-b8ee-4787-b9d4-8666cb214765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533921095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3533921095
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3733767193
Short name T524
Test name
Test status
Simulation time 47566113961 ps
CPU time 11.66 seconds
Started Jul 22 06:12:25 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 200064 kb
Host smart-4da7cb86-d790-4b34-bc65-a0bd9b431595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733767193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3733767193
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1734978012
Short name T932
Test name
Test status
Simulation time 23448857686 ps
CPU time 40.21 seconds
Started Jul 22 06:15:43 PM PDT 24
Finished Jul 22 06:16:24 PM PDT 24
Peak memory 200288 kb
Host smart-c6cf018a-116e-49e4-9704-ceda41bd8554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734978012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1734978012
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1264368190
Short name T1002
Test name
Test status
Simulation time 24602706498 ps
CPU time 63.97 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 200216 kb
Host smart-f4209882-94a7-4185-8a77-b1ce4ce82f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264368190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1264368190
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3240481224
Short name T118
Test name
Test status
Simulation time 32061367257 ps
CPU time 40.8 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:23 PM PDT 24
Peak memory 200172 kb
Host smart-83192750-cc98-45f0-84ee-7f3c64339c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240481224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3240481224
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4016492674
Short name T170
Test name
Test status
Simulation time 91556041126 ps
CPU time 29.92 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 200148 kb
Host smart-9e0e64a9-3f74-44f3-9177-7d46e1e5fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016492674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4016492674
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.177004904
Short name T759
Test name
Test status
Simulation time 87734860631 ps
CPU time 37.42 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:20 PM PDT 24
Peak memory 200268 kb
Host smart-2b594c00-b4ec-401d-99ae-88106dae2340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177004904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.177004904
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2780862693
Short name T947
Test name
Test status
Simulation time 39694516564 ps
CPU time 17.11 seconds
Started Jul 22 06:15:42 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 200128 kb
Host smart-9ad11270-be66-4fe2-93f7-27c9a9bdcf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780862693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2780862693
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3989357297
Short name T255
Test name
Test status
Simulation time 134818573799 ps
CPU time 82.91 seconds
Started Jul 22 06:17:47 PM PDT 24
Finished Jul 22 06:19:11 PM PDT 24
Peak memory 200188 kb
Host smart-1b0d6806-abd0-4eb3-8872-4b122a94f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989357297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3989357297
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.632827355
Short name T1035
Test name
Test status
Simulation time 87448061761 ps
CPU time 120.08 seconds
Started Jul 22 06:15:55 PM PDT 24
Finished Jul 22 06:17:55 PM PDT 24
Peak memory 200212 kb
Host smart-9b0f243a-a68b-4774-bc18-d85fa8ea7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632827355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.632827355
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3399388103
Short name T234
Test name
Test status
Simulation time 30513551578 ps
CPU time 23 seconds
Started Jul 22 06:15:54 PM PDT 24
Finished Jul 22 06:16:18 PM PDT 24
Peak memory 200212 kb
Host smart-1d3d62f5-bb77-4033-bb8c-c6bee308a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399388103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3399388103
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2435257860
Short name T329
Test name
Test status
Simulation time 19915101 ps
CPU time 0.54 seconds
Started Jul 22 06:12:32 PM PDT 24
Finished Jul 22 06:12:33 PM PDT 24
Peak memory 195080 kb
Host smart-980feb8e-a1dc-4222-9155-c247cda6ab94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435257860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2435257860
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2312834308
Short name T755
Test name
Test status
Simulation time 90805379021 ps
CPU time 48.09 seconds
Started Jul 22 06:12:34 PM PDT 24
Finished Jul 22 06:13:22 PM PDT 24
Peak memory 200128 kb
Host smart-d5c2892b-1656-425d-b3cb-917bdac59098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312834308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2312834308
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.903339689
Short name T394
Test name
Test status
Simulation time 19428613152 ps
CPU time 14.77 seconds
Started Jul 22 06:12:50 PM PDT 24
Finished Jul 22 06:13:05 PM PDT 24
Peak memory 199992 kb
Host smart-88a644bc-ae68-4505-af80-bf1327e301a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903339689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.903339689
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1875533035
Short name T290
Test name
Test status
Simulation time 38716515483 ps
CPU time 35.8 seconds
Started Jul 22 06:12:31 PM PDT 24
Finished Jul 22 06:13:07 PM PDT 24
Peak memory 200148 kb
Host smart-f6bbdc18-13c1-4900-b6fa-229e3a09bf79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875533035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1875533035
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.842489170
Short name T377
Test name
Test status
Simulation time 160679756479 ps
CPU time 598.42 seconds
Started Jul 22 06:12:29 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 200176 kb
Host smart-cbf3d9bd-1c18-475a-a97b-e1f23ebfdf10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842489170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.842489170
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2859880123
Short name T878
Test name
Test status
Simulation time 8906316168 ps
CPU time 9.36 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:46 PM PDT 24
Peak memory 199420 kb
Host smart-8b4b03ca-3652-4b83-a7c1-cc13176b42cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859880123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2859880123
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2350756583
Short name T1025
Test name
Test status
Simulation time 86012327130 ps
CPU time 64.97 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:13:54 PM PDT 24
Peak memory 199736 kb
Host smart-bd9f393e-36cc-495c-a8fb-134a998a312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350756583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2350756583
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2447944268
Short name T580
Test name
Test status
Simulation time 19066771690 ps
CPU time 918.41 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:27:53 PM PDT 24
Peak memory 200204 kb
Host smart-776f027b-4e7c-40a0-a92b-a8b6352ce070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447944268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2447944268
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2606492324
Short name T867
Test name
Test status
Simulation time 2119740195 ps
CPU time 6.08 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 197932 kb
Host smart-63aabca0-cc6d-4cc8-a9ff-e05200ccab45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606492324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2606492324
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.147785920
Short name T456
Test name
Test status
Simulation time 105939884455 ps
CPU time 58.18 seconds
Started Jul 22 06:12:31 PM PDT 24
Finished Jul 22 06:13:29 PM PDT 24
Peak memory 200192 kb
Host smart-26a87d8b-bdc6-416e-99c6-84155785f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147785920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.147785920
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.76099697
Short name T666
Test name
Test status
Simulation time 3058733669 ps
CPU time 1.73 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 196264 kb
Host smart-5fef169e-92cd-4755-956f-e7ce7ebb6e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76099697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.76099697
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2455347197
Short name T436
Test name
Test status
Simulation time 291421260 ps
CPU time 0.98 seconds
Started Jul 22 06:12:33 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 198760 kb
Host smart-0352369f-d31a-43f2-a42d-1b9afe23e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455347197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2455347197
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3061383836
Short name T787
Test name
Test status
Simulation time 415344653063 ps
CPU time 363.13 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:18:38 PM PDT 24
Peak memory 200244 kb
Host smart-2304f954-386b-468d-9075-5f21026ab478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061383836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3061383836
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2160376854
Short name T519
Test name
Test status
Simulation time 65366995477 ps
CPU time 967.99 seconds
Started Jul 22 06:12:34 PM PDT 24
Finished Jul 22 06:28:43 PM PDT 24
Peak memory 225072 kb
Host smart-e1095aa1-9291-4014-a3d3-2755a67ea870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160376854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2160376854
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1353799050
Short name T298
Test name
Test status
Simulation time 1446264560 ps
CPU time 2.78 seconds
Started Jul 22 06:12:32 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 198852 kb
Host smart-d9d7fdd7-dc3a-4cbc-bada-8e8d29973b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353799050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1353799050
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2008614027
Short name T766
Test name
Test status
Simulation time 2298584236 ps
CPU time 4.13 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:12:54 PM PDT 24
Peak memory 198608 kb
Host smart-f9074bed-4f14-49a3-a0c6-b1d32adcf0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008614027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2008614027
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1740035855
Short name T257
Test name
Test status
Simulation time 23172214287 ps
CPU time 26.1 seconds
Started Jul 22 06:16:34 PM PDT 24
Finished Jul 22 06:17:00 PM PDT 24
Peak memory 200244 kb
Host smart-9ff81e84-c28a-4b94-925a-f8f0431573c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740035855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1740035855
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.376860908
Short name T250
Test name
Test status
Simulation time 37919698531 ps
CPU time 26.7 seconds
Started Jul 22 06:15:54 PM PDT 24
Finished Jul 22 06:16:21 PM PDT 24
Peak memory 200212 kb
Host smart-6ca99c5f-e808-4530-b682-1f7a38ca4d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376860908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.376860908
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4025840712
Short name T1139
Test name
Test status
Simulation time 29558064633 ps
CPU time 25.36 seconds
Started Jul 22 06:15:51 PM PDT 24
Finished Jul 22 06:16:16 PM PDT 24
Peak memory 200256 kb
Host smart-d43d2aab-a6cf-4d37-a6fd-d8dc5c1f7d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025840712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4025840712
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2820351462
Short name T136
Test name
Test status
Simulation time 40819291189 ps
CPU time 64.86 seconds
Started Jul 22 06:16:12 PM PDT 24
Finished Jul 22 06:17:17 PM PDT 24
Peak memory 200168 kb
Host smart-35fc0215-f6d1-4392-b429-f45275e98669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820351462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2820351462
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1487137632
Short name T960
Test name
Test status
Simulation time 27214924644 ps
CPU time 55.92 seconds
Started Jul 22 06:15:51 PM PDT 24
Finished Jul 22 06:16:47 PM PDT 24
Peak memory 200148 kb
Host smart-0929d591-262a-493e-a525-e91691e1ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487137632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1487137632
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1428099299
Short name T844
Test name
Test status
Simulation time 13504061682 ps
CPU time 24.08 seconds
Started Jul 22 06:16:14 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 200136 kb
Host smart-f491141e-5940-4d64-8a77-99ab2c8559f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428099299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1428099299
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1172245115
Short name T193
Test name
Test status
Simulation time 26114849395 ps
CPU time 11.79 seconds
Started Jul 22 06:15:50 PM PDT 24
Finished Jul 22 06:16:02 PM PDT 24
Peak memory 200268 kb
Host smart-d787b632-0808-46a2-9bee-f56467ccfba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172245115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1172245115
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2030276272
Short name T1019
Test name
Test status
Simulation time 37497534992 ps
CPU time 349.32 seconds
Started Jul 22 06:16:07 PM PDT 24
Finished Jul 22 06:21:57 PM PDT 24
Peak memory 200200 kb
Host smart-b908d71d-1a0d-412d-9729-19bed22ad69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030276272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2030276272
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2715750936
Short name T899
Test name
Test status
Simulation time 141716680773 ps
CPU time 96.59 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 200136 kb
Host smart-48043511-34e2-4202-9514-1536630413e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715750936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2715750936
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.4112003604
Short name T898
Test name
Test status
Simulation time 29688019 ps
CPU time 0.55 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 195896 kb
Host smart-052855e6-3f94-45c5-b3bf-b98ff458bee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112003604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4112003604
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2213688762
Short name T1169
Test name
Test status
Simulation time 45124301874 ps
CPU time 37.15 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:13:29 PM PDT 24
Peak memory 200012 kb
Host smart-caa1fcdd-52c2-4077-bf7f-858e379b8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213688762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2213688762
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4007646952
Short name T897
Test name
Test status
Simulation time 261794021229 ps
CPU time 56.26 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:13:31 PM PDT 24
Peak memory 200228 kb
Host smart-8ec37aa3-bc86-4e93-a48d-b5c83fcb93aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007646952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4007646952
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1109771732
Short name T657
Test name
Test status
Simulation time 108918410075 ps
CPU time 434.23 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:20:04 PM PDT 24
Peak memory 200000 kb
Host smart-d05678fc-1ef1-4d61-85f4-d10609069e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109771732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1109771732
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2192098274
Short name T1023
Test name
Test status
Simulation time 14931332194 ps
CPU time 12.17 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:48 PM PDT 24
Peak memory 200060 kb
Host smart-5740861a-9f84-4b17-9a57-bd24147b49da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192098274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2192098274
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.924246533
Short name T991
Test name
Test status
Simulation time 83468977049 ps
CPU time 387.69 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 200092 kb
Host smart-e68c95f6-9ffe-4f32-8e68-ff2774c7a456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924246533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.924246533
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3270626622
Short name T587
Test name
Test status
Simulation time 558522551 ps
CPU time 0.83 seconds
Started Jul 22 06:12:36 PM PDT 24
Finished Jul 22 06:12:37 PM PDT 24
Peak memory 195844 kb
Host smart-2a5fe1e6-277e-4866-a0e4-bb819ba4c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270626622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3270626622
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1963715093
Short name T280
Test name
Test status
Simulation time 30847170000 ps
CPU time 52.47 seconds
Started Jul 22 06:12:33 PM PDT 24
Finished Jul 22 06:13:26 PM PDT 24
Peak memory 199160 kb
Host smart-7951b51d-ba56-4876-8de3-f85016d3a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963715093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1963715093
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1927123959
Short name T988
Test name
Test status
Simulation time 17135514686 ps
CPU time 140.08 seconds
Started Jul 22 06:12:33 PM PDT 24
Finished Jul 22 06:14:54 PM PDT 24
Peak memory 200284 kb
Host smart-7fa5a748-2993-410d-bcb6-9e39d3d211e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927123959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1927123959
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2935950865
Short name T901
Test name
Test status
Simulation time 3590042285 ps
CPU time 12.94 seconds
Started Jul 22 06:12:33 PM PDT 24
Finished Jul 22 06:12:46 PM PDT 24
Peak memory 199224 kb
Host smart-0c2dd497-7dee-4bb7-90f0-b3136bb05065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935950865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2935950865
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.664553801
Short name T378
Test name
Test status
Simulation time 24742565272 ps
CPU time 37.24 seconds
Started Jul 22 06:12:32 PM PDT 24
Finished Jul 22 06:13:10 PM PDT 24
Peak memory 200172 kb
Host smart-b608e331-6848-48fe-8a7b-316eeb3f1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664553801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.664553801
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2082952905
Short name T674
Test name
Test status
Simulation time 6086542542 ps
CPU time 10.67 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:13:00 PM PDT 24
Peak memory 196124 kb
Host smart-35d9164e-1ffd-4dd8-9b9c-0743bf89e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082952905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2082952905
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3146751092
Short name T748
Test name
Test status
Simulation time 5758069993 ps
CPU time 12.74 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 199992 kb
Host smart-8f710be6-4491-4fad-971a-4982ff0b551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146751092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3146751092
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2571582676
Short name T943
Test name
Test status
Simulation time 105886466768 ps
CPU time 309.3 seconds
Started Jul 22 06:12:35 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 215024 kb
Host smart-256b9e9a-9d48-4003-b991-93c1646a4149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571582676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2571582676
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3259094414
Short name T765
Test name
Test status
Simulation time 931379432 ps
CPU time 2.43 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:12:54 PM PDT 24
Peak memory 200176 kb
Host smart-edc5e22d-ff47-40f3-9609-72297c5f43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259094414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3259094414
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4288081268
Short name T693
Test name
Test status
Simulation time 41081318479 ps
CPU time 105.88 seconds
Started Jul 22 06:12:50 PM PDT 24
Finished Jul 22 06:14:36 PM PDT 24
Peak memory 200024 kb
Host smart-b8ab2cb4-79f1-4c74-8d4b-5267edbf5d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288081268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4288081268
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2096081953
Short name T342
Test name
Test status
Simulation time 36071702214 ps
CPU time 12.07 seconds
Started Jul 22 06:15:58 PM PDT 24
Finished Jul 22 06:16:11 PM PDT 24
Peak memory 200368 kb
Host smart-a7c25683-a5b8-4e9a-bbd6-ff13abd445db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096081953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2096081953
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1426675563
Short name T1043
Test name
Test status
Simulation time 21162869938 ps
CPU time 15.55 seconds
Started Jul 22 06:16:02 PM PDT 24
Finished Jul 22 06:16:17 PM PDT 24
Peak memory 199744 kb
Host smart-657ad3ba-0b40-4edd-88c2-4af2c365b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426675563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1426675563
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.341579818
Short name T814
Test name
Test status
Simulation time 113633628347 ps
CPU time 99.98 seconds
Started Jul 22 06:15:59 PM PDT 24
Finished Jul 22 06:17:40 PM PDT 24
Peak memory 200260 kb
Host smart-447080cc-6bf3-48a5-a3f7-6766c5498f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341579818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.341579818
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2052591695
Short name T661
Test name
Test status
Simulation time 111354073799 ps
CPU time 87.36 seconds
Started Jul 22 06:15:59 PM PDT 24
Finished Jul 22 06:17:27 PM PDT 24
Peak memory 200184 kb
Host smart-a0d2a4ec-81b9-43e2-a0ad-111852e66cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052591695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2052591695
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3058449483
Short name T396
Test name
Test status
Simulation time 19499910409 ps
CPU time 31.83 seconds
Started Jul 22 06:16:06 PM PDT 24
Finished Jul 22 06:16:38 PM PDT 24
Peak memory 200128 kb
Host smart-de9f192e-2881-46e7-8a13-007f43c22915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058449483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3058449483
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.557063746
Short name T1074
Test name
Test status
Simulation time 26218870039 ps
CPU time 39.15 seconds
Started Jul 22 06:16:06 PM PDT 24
Finished Jul 22 06:16:45 PM PDT 24
Peak memory 200216 kb
Host smart-6e6aa500-7205-4407-b9f9-ed808929000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557063746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.557063746
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3952625454
Short name T452
Test name
Test status
Simulation time 46639176968 ps
CPU time 34.36 seconds
Started Jul 22 06:15:59 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 200228 kb
Host smart-871a6572-35a7-46cf-b99a-51c9f328929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952625454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3952625454
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3194902960
Short name T848
Test name
Test status
Simulation time 22547066649 ps
CPU time 22.14 seconds
Started Jul 22 06:16:49 PM PDT 24
Finished Jul 22 06:17:12 PM PDT 24
Peak memory 200240 kb
Host smart-6953728d-c308-4914-91d9-4fdd5fc70ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194902960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3194902960
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2772293951
Short name T1000
Test name
Test status
Simulation time 29130262 ps
CPU time 0.53 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:12:47 PM PDT 24
Peak memory 195240 kb
Host smart-cacd47b3-8081-4209-81bb-e426ba5c950f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772293951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2772293951
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.82465869
Short name T1120
Test name
Test status
Simulation time 44488262173 ps
CPU time 71.87 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 200136 kb
Host smart-0158eead-9fd0-4dd2-b393-9c20c0ebd8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82465869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.82465869
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1152334853
Short name T977
Test name
Test status
Simulation time 209884180297 ps
CPU time 374.68 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:19:00 PM PDT 24
Peak memory 200260 kb
Host smart-c28cac74-88f7-4660-bd42-d84788a327ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152334853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1152334853
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.916654129
Short name T551
Test name
Test status
Simulation time 11453530323 ps
CPU time 15.22 seconds
Started Jul 22 06:12:41 PM PDT 24
Finished Jul 22 06:12:56 PM PDT 24
Peak memory 200048 kb
Host smart-aaec059e-edf3-44e9-a03e-2232efbe4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916654129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.916654129
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4129678570
Short name T875
Test name
Test status
Simulation time 55126439847 ps
CPU time 30.2 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 200004 kb
Host smart-98a066a0-8fe8-4828-97ac-51c597b33fd7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129678570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4129678570
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.937214741
Short name T946
Test name
Test status
Simulation time 64211486423 ps
CPU time 519.77 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 200244 kb
Host smart-cec7e454-18d1-4bca-9e4b-7297c9d4ca38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937214741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.937214741
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3777021021
Short name T38
Test name
Test status
Simulation time 8113409913 ps
CPU time 4.51 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:12:56 PM PDT 24
Peak memory 199120 kb
Host smart-038c73b6-eab5-4f88-bd9c-372a92436ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777021021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3777021021
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1843064325
Short name T883
Test name
Test status
Simulation time 97294641427 ps
CPU time 53.27 seconds
Started Jul 22 06:12:44 PM PDT 24
Finished Jul 22 06:13:37 PM PDT 24
Peak memory 200324 kb
Host smart-895a69b2-18d7-4d8d-bf8b-70db62ef08be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843064325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1843064325
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2930510564
Short name T485
Test name
Test status
Simulation time 29075855053 ps
CPU time 1707.72 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:41:19 PM PDT 24
Peak memory 200164 kb
Host smart-392f2541-47e4-492e-a88a-571c17bf6a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930510564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2930510564
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1116369453
Short name T600
Test name
Test status
Simulation time 3074546758 ps
CPU time 5.59 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:14:38 PM PDT 24
Peak memory 199092 kb
Host smart-54c237b8-91b9-4d95-86b9-afb0266f375c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116369453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1116369453
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1714684649
Short name T928
Test name
Test status
Simulation time 59764345710 ps
CPU time 50.73 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 200248 kb
Host smart-3e911750-b2d7-45d0-ac99-188d054a91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714684649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1714684649
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2835013556
Short name T330
Test name
Test status
Simulation time 2900690520 ps
CPU time 4.47 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:12:51 PM PDT 24
Peak memory 196748 kb
Host smart-b7fac560-ecee-4832-92cc-c7454034e845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835013556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2835013556
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1254708796
Short name T670
Test name
Test status
Simulation time 5342944922 ps
CPU time 20.72 seconds
Started Jul 22 06:12:34 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 200100 kb
Host smart-04597d4a-a0e0-47d1-a90a-f8a4b717c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254708796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1254708796
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1995847345
Short name T463
Test name
Test status
Simulation time 174989331473 ps
CPU time 131.07 seconds
Started Jul 22 06:12:51 PM PDT 24
Finished Jul 22 06:15:03 PM PDT 24
Peak memory 208580 kb
Host smart-c2eb2311-22c2-4cde-8798-d38a4f2ecd85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995847345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1995847345
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1973984434
Short name T1105
Test name
Test status
Simulation time 1047405966 ps
CPU time 3.43 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:12:51 PM PDT 24
Peak memory 198628 kb
Host smart-155cb9e2-26c7-47fc-acc2-b5c1bd55d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973984434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1973984434
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.514634166
Short name T733
Test name
Test status
Simulation time 55544106394 ps
CPU time 88.46 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:14:18 PM PDT 24
Peak memory 200016 kb
Host smart-dbf6ca66-7485-4ad2-af99-e1b5646d180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514634166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.514634166
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3184805019
Short name T134
Test name
Test status
Simulation time 20219395105 ps
CPU time 12.18 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:16:13 PM PDT 24
Peak memory 200244 kb
Host smart-ea54b1f5-f846-4b61-b101-45b3c7b0793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184805019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3184805019
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4040219992
Short name T1173
Test name
Test status
Simulation time 46166316149 ps
CPU time 31.42 seconds
Started Jul 22 06:16:02 PM PDT 24
Finished Jul 22 06:16:34 PM PDT 24
Peak memory 200244 kb
Host smart-1ca606cd-7fdd-4cf0-b5ce-5c5625168973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040219992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4040219992
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2023218954
Short name T385
Test name
Test status
Simulation time 52792388743 ps
CPU time 25.05 seconds
Started Jul 22 06:16:06 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 199912 kb
Host smart-04075624-7031-4414-93cd-145a07095f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023218954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2023218954
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2851067829
Short name T198
Test name
Test status
Simulation time 82068956145 ps
CPU time 49.14 seconds
Started Jul 22 06:15:58 PM PDT 24
Finished Jul 22 06:16:48 PM PDT 24
Peak memory 200136 kb
Host smart-978a72a7-7cea-4ed9-8e97-5e8dc8440242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851067829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2851067829
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3849147901
Short name T887
Test name
Test status
Simulation time 17467318071 ps
CPU time 26.53 seconds
Started Jul 22 06:16:01 PM PDT 24
Finished Jul 22 06:16:28 PM PDT 24
Peak memory 200012 kb
Host smart-bfce3812-7c78-4ea3-8d09-18cccb9289b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849147901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3849147901
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3454711144
Short name T658
Test name
Test status
Simulation time 37840804669 ps
CPU time 67.59 seconds
Started Jul 22 06:16:00 PM PDT 24
Finished Jul 22 06:17:08 PM PDT 24
Peak memory 200188 kb
Host smart-ab21aa21-3902-4c7e-ba9d-6aed19746eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454711144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3454711144
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2432622431
Short name T88
Test name
Test status
Simulation time 68080523110 ps
CPU time 58.04 seconds
Started Jul 22 06:16:05 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 200148 kb
Host smart-515b058c-b332-40f8-81da-053db6d8c8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432622431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2432622431
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.506416137
Short name T780
Test name
Test status
Simulation time 28727973508 ps
CPU time 44.29 seconds
Started Jul 22 06:17:47 PM PDT 24
Finished Jul 22 06:18:32 PM PDT 24
Peak memory 200200 kb
Host smart-a9b25ebc-9a3e-403f-8a29-b937b2997919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506416137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.506416137
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2709500744
Short name T1094
Test name
Test status
Simulation time 40023415747 ps
CPU time 16.53 seconds
Started Jul 22 06:16:06 PM PDT 24
Finished Jul 22 06:16:23 PM PDT 24
Peak memory 200216 kb
Host smart-569e2a5a-dae4-469d-94a2-d0e68eb6d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709500744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2709500744
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2312032861
Short name T473
Test name
Test status
Simulation time 11831190622 ps
CPU time 15.82 seconds
Started Jul 22 06:15:59 PM PDT 24
Finished Jul 22 06:16:15 PM PDT 24
Peak memory 200280 kb
Host smart-08f20e0a-927d-4911-b2ee-0c79b1382e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312032861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2312032861
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1355598927
Short name T531
Test name
Test status
Simulation time 14173703 ps
CPU time 0.53 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:12:47 PM PDT 24
Peak memory 195660 kb
Host smart-541d6842-1cc5-42ec-8605-2a15aca439a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355598927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1355598927
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.56783933
Short name T847
Test name
Test status
Simulation time 17973819811 ps
CPU time 23.99 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 200248 kb
Host smart-c65cb1e5-c42c-49b7-85df-cbced0e51675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56783933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.56783933
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2436846204
Short name T1033
Test name
Test status
Simulation time 108373002064 ps
CPU time 180.36 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:15:48 PM PDT 24
Peak memory 200196 kb
Host smart-00bbb76b-a238-486e-848d-90e9f1166112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436846204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2436846204
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2184964466
Short name T916
Test name
Test status
Simulation time 77532559267 ps
CPU time 208.62 seconds
Started Jul 22 06:13:10 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200256 kb
Host smart-a141024c-f150-428b-8e0b-06b7bfcbe996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184964466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2184964466
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1388327910
Short name T1140
Test name
Test status
Simulation time 38587514632 ps
CPU time 16.99 seconds
Started Jul 22 06:12:44 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 200240 kb
Host smart-ec1104d8-7e88-455f-b084-8bf1ff2a699d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388327910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1388327910
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2662268969
Short name T690
Test name
Test status
Simulation time 88442047298 ps
CPU time 691.56 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:24:19 PM PDT 24
Peak memory 200168 kb
Host smart-d8f0cfe4-289d-4ed0-be24-22fbcd4efaae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662268969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2662268969
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3029391674
Short name T968
Test name
Test status
Simulation time 1952477188 ps
CPU time 2.11 seconds
Started Jul 22 06:12:47 PM PDT 24
Finished Jul 22 06:12:50 PM PDT 24
Peak memory 198692 kb
Host smart-2191a9cc-cd96-47ee-92e8-c344f9a3af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029391674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3029391674
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.4272546074
Short name T911
Test name
Test status
Simulation time 393775959756 ps
CPU time 111.04 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:14:37 PM PDT 24
Peak memory 208224 kb
Host smart-05f4106d-88c3-42e9-8e8e-2021730c212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272546074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.4272546074
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4145435145
Short name T793
Test name
Test status
Simulation time 21937748145 ps
CPU time 1067.67 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:32:20 PM PDT 24
Peak memory 200208 kb
Host smart-88a954e5-9a53-4cd2-953b-ff4c0aa39ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145435145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4145435145
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.444606543
Short name T296
Test name
Test status
Simulation time 2653976817 ps
CPU time 8.91 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:12:56 PM PDT 24
Peak memory 198132 kb
Host smart-03ed0857-3b32-4d0b-aab6-8617840c07a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444606543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.444606543
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3928054675
Short name T1029
Test name
Test status
Simulation time 34840142802 ps
CPU time 13.49 seconds
Started Jul 22 06:12:59 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 199424 kb
Host smart-afa8649a-f53e-42e0-9174-53107c7c335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928054675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3928054675
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1673186541
Short name T922
Test name
Test status
Simulation time 6175226790 ps
CPU time 10.54 seconds
Started Jul 22 06:12:44 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 196560 kb
Host smart-2c7773d0-4523-46bc-ac21-e3fecf973dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673186541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1673186541
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3091581037
Short name T89
Test name
Test status
Simulation time 6062436850 ps
CPU time 13.36 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:00 PM PDT 24
Peak memory 200240 kb
Host smart-58ba228f-6ab2-41df-a907-16cfe84b7328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091581037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3091581037
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.139867251
Short name T906
Test name
Test status
Simulation time 538030845985 ps
CPU time 1157.93 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:32:05 PM PDT 24
Peak memory 200180 kb
Host smart-12547749-3dee-4928-8d9f-b3db0ac29f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139867251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.139867251
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3791399438
Short name T48
Test name
Test status
Simulation time 90699885034 ps
CPU time 996.25 seconds
Started Jul 22 06:12:43 PM PDT 24
Finished Jul 22 06:29:20 PM PDT 24
Peak memory 216824 kb
Host smart-f6b0a437-418d-46bb-a2b0-354a96afe4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791399438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3791399438
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2710046567
Short name T486
Test name
Test status
Simulation time 6564499376 ps
CPU time 19.01 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:05 PM PDT 24
Peak memory 200132 kb
Host smart-b2fb0e06-8a36-4f01-9efa-1c1ee1f397d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710046567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2710046567
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2012860334
Short name T349
Test name
Test status
Simulation time 30120851156 ps
CPU time 12.65 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 200300 kb
Host smart-f2df0bb2-248c-4baf-ac66-7145495563b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012860334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2012860334
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2164790700
Short name T521
Test name
Test status
Simulation time 124336504301 ps
CPU time 164.42 seconds
Started Jul 22 06:16:07 PM PDT 24
Finished Jul 22 06:18:51 PM PDT 24
Peak memory 199924 kb
Host smart-8afe7572-e6a7-4d6c-b94a-912364bfa479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164790700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2164790700
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2764418469
Short name T153
Test name
Test status
Simulation time 35527549379 ps
CPU time 27.42 seconds
Started Jul 22 06:16:13 PM PDT 24
Finished Jul 22 06:16:41 PM PDT 24
Peak memory 200200 kb
Host smart-b4d2be00-18fc-48f5-9bbe-1d11b7198d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764418469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2764418469
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.411663907
Short name T307
Test name
Test status
Simulation time 79471376709 ps
CPU time 199.97 seconds
Started Jul 22 06:16:09 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 200196 kb
Host smart-149608d0-a812-412a-84f6-bb84d96584c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411663907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.411663907
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.36662173
Short name T360
Test name
Test status
Simulation time 41904314716 ps
CPU time 16.22 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:25 PM PDT 24
Peak memory 200240 kb
Host smart-7e073315-8ea8-46da-87bc-def1096b2c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36662173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.36662173
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1550312900
Short name T464
Test name
Test status
Simulation time 79825551370 ps
CPU time 114.42 seconds
Started Jul 22 06:16:11 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 200204 kb
Host smart-ac3c4d96-04ad-444b-9b01-0adeaa000f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550312900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1550312900
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3558545222
Short name T1068
Test name
Test status
Simulation time 45244461716 ps
CPU time 69.97 seconds
Started Jul 22 06:16:09 PM PDT 24
Finished Jul 22 06:17:19 PM PDT 24
Peak memory 200008 kb
Host smart-fa5bd458-a383-496b-a2de-63c9f0319afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558545222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3558545222
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1880290428
Short name T605
Test name
Test status
Simulation time 110221552320 ps
CPU time 181.99 seconds
Started Jul 22 06:16:14 PM PDT 24
Finished Jul 22 06:19:16 PM PDT 24
Peak memory 200040 kb
Host smart-36301f50-2a74-4235-8ae1-b49386dd24d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880290428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1880290428
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1002277611
Short name T703
Test name
Test status
Simulation time 31951733115 ps
CPU time 51 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:59 PM PDT 24
Peak memory 200204 kb
Host smart-18c2bcc0-4800-4eb9-8639-78c290afdf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002277611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1002277611
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3011409689
Short name T172
Test name
Test status
Simulation time 144642961969 ps
CPU time 222.16 seconds
Started Jul 22 06:16:10 PM PDT 24
Finished Jul 22 06:19:53 PM PDT 24
Peak memory 200284 kb
Host smart-ab50fd31-107f-47b1-b179-ff90e44e97e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011409689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3011409689
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4036604311
Short name T1001
Test name
Test status
Simulation time 262434995229 ps
CPU time 178.36 seconds
Started Jul 22 06:16:13 PM PDT 24
Finished Jul 22 06:19:12 PM PDT 24
Peak memory 200200 kb
Host smart-f82001c1-46b5-412e-a644-42cb1e78030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036604311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4036604311
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1680080235
Short name T1052
Test name
Test status
Simulation time 50464126 ps
CPU time 0.54 seconds
Started Jul 22 06:12:52 PM PDT 24
Finished Jul 22 06:12:53 PM PDT 24
Peak memory 195248 kb
Host smart-fddc1fcd-4e6b-4bb6-88bc-6f127027f9e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680080235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1680080235
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4292609359
Short name T799
Test name
Test status
Simulation time 32676373783 ps
CPU time 46.65 seconds
Started Jul 22 06:13:17 PM PDT 24
Finished Jul 22 06:14:04 PM PDT 24
Peak memory 200184 kb
Host smart-688f1de0-bad6-4a46-8b71-6c0cf1939e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292609359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4292609359
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3258584754
Short name T461
Test name
Test status
Simulation time 100033961749 ps
CPU time 60.25 seconds
Started Jul 22 06:12:48 PM PDT 24
Finished Jul 22 06:13:49 PM PDT 24
Peak memory 200196 kb
Host smart-16ae1c93-2e8a-4828-a455-f9c6283af9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258584754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3258584754
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2937959862
Short name T1155
Test name
Test status
Simulation time 11736730335 ps
CPU time 12.6 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:20 PM PDT 24
Peak memory 200004 kb
Host smart-7af99b54-295b-424b-bfac-2181325035fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937959862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2937959862
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3200167966
Short name T326
Test name
Test status
Simulation time 10764341625 ps
CPU time 16.24 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 198988 kb
Host smart-85e275bc-890d-4f29-a3f2-a85a1039d8a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200167966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3200167966
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1103539446
Short name T710
Test name
Test status
Simulation time 44500645880 ps
CPU time 375.14 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 200196 kb
Host smart-9364cb96-ad07-4fa4-a0b3-3279e5a313d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103539446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1103539446
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1779885263
Short name T676
Test name
Test status
Simulation time 8613243882 ps
CPU time 10.51 seconds
Started Jul 22 06:12:47 PM PDT 24
Finished Jul 22 06:12:58 PM PDT 24
Peak memory 200152 kb
Host smart-c7f88c3c-9231-4f5b-bc85-5ac54bfe3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779885263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1779885263
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.765145542
Short name T820
Test name
Test status
Simulation time 127426654917 ps
CPU time 54.15 seconds
Started Jul 22 06:12:47 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 199896 kb
Host smart-06b1edb7-f8b1-4813-906d-b13d1226a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765145542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.765145542
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3026526356
Short name T923
Test name
Test status
Simulation time 8632730557 ps
CPU time 488.98 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:20:58 PM PDT 24
Peak memory 200228 kb
Host smart-b95669d6-1b10-467b-a45e-69235623b4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026526356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3026526356
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1475462700
Short name T358
Test name
Test status
Simulation time 7441251434 ps
CPU time 7.89 seconds
Started Jul 22 06:12:44 PM PDT 24
Finished Jul 22 06:12:53 PM PDT 24
Peak memory 200200 kb
Host smart-8392b135-0862-4ec5-a02b-4b76c3086641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475462700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1475462700
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4172465189
Short name T913
Test name
Test status
Simulation time 122632335900 ps
CPU time 29.49 seconds
Started Jul 22 06:12:45 PM PDT 24
Finished Jul 22 06:13:16 PM PDT 24
Peak memory 200244 kb
Host smart-e7ba9237-dfe6-4cb5-8fdb-66572b02e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172465189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4172465189
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2098395622
Short name T65
Test name
Test status
Simulation time 1964348109 ps
CPU time 1.48 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:12:49 PM PDT 24
Peak memory 195740 kb
Host smart-c5ac16dd-6db9-4d5b-b677-8616006875ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098395622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2098395622
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2580163796
Short name T1164
Test name
Test status
Simulation time 5980274409 ps
CPU time 11.68 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:18 PM PDT 24
Peak memory 199916 kb
Host smart-8d60a35e-5d88-4f5a-a4de-66dd091350f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580163796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2580163796
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1017910290
Short name T838
Test name
Test status
Simulation time 109263581282 ps
CPU time 420.65 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:19:54 PM PDT 24
Peak memory 200148 kb
Host smart-30292df9-9a95-4cb1-befd-be32acad5998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017910290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1017910290
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2609280316
Short name T550
Test name
Test status
Simulation time 317952965483 ps
CPU time 318.68 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:18:12 PM PDT 24
Peak memory 216776 kb
Host smart-71b434f3-323f-41bb-a125-9959cfdea55f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609280316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2609280316
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3316263518
Short name T430
Test name
Test status
Simulation time 638171801 ps
CPU time 2.27 seconds
Started Jul 22 06:12:47 PM PDT 24
Finished Jul 22 06:12:50 PM PDT 24
Peak memory 198764 kb
Host smart-86f0d1d0-2e37-4515-8c0f-64a0f6bc87a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316263518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3316263518
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3079061593
Short name T892
Test name
Test status
Simulation time 8137014183 ps
CPU time 11.83 seconds
Started Jul 22 06:12:46 PM PDT 24
Finished Jul 22 06:12:59 PM PDT 24
Peak memory 199984 kb
Host smart-ba964e7f-4ac3-4930-b2b4-0df28b179a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079061593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3079061593
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2786896101
Short name T819
Test name
Test status
Simulation time 87735633062 ps
CPU time 132.58 seconds
Started Jul 22 06:16:07 PM PDT 24
Finished Jul 22 06:18:20 PM PDT 24
Peak memory 200260 kb
Host smart-1818f574-e502-45c3-abd2-b435acd85f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786896101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2786896101
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3506856201
Short name T979
Test name
Test status
Simulation time 16540938553 ps
CPU time 6.21 seconds
Started Jul 22 06:16:12 PM PDT 24
Finished Jul 22 06:16:19 PM PDT 24
Peak memory 200044 kb
Host smart-fab0dca6-e572-409c-8879-c7eb11b6ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506856201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3506856201
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2460415638
Short name T639
Test name
Test status
Simulation time 55621833371 ps
CPU time 7.58 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:17 PM PDT 24
Peak memory 200044 kb
Host smart-d645ca97-f706-4765-a191-da9bd1cb038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460415638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2460415638
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2193112462
Short name T182
Test name
Test status
Simulation time 13381247817 ps
CPU time 29.65 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200196 kb
Host smart-11e9c2f2-529a-4feb-818e-6d1cb95cdc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193112462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2193112462
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.731884605
Short name T716
Test name
Test status
Simulation time 57598468542 ps
CPU time 25.25 seconds
Started Jul 22 06:16:07 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 200164 kb
Host smart-54d3da2d-2f17-4b1a-8fef-88b3f4af6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731884605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.731884605
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3736065496
Short name T214
Test name
Test status
Simulation time 76743128168 ps
CPU time 216.1 seconds
Started Jul 22 06:16:13 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 200260 kb
Host smart-a4c3d76a-16e4-49bf-819d-3d69287acea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736065496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3736065496
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2767293384
Short name T146
Test name
Test status
Simulation time 170053575232 ps
CPU time 41.75 seconds
Started Jul 22 06:16:12 PM PDT 24
Finished Jul 22 06:16:55 PM PDT 24
Peak memory 200124 kb
Host smart-8010380f-101e-4793-91b5-8020ef48c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767293384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2767293384
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2714421912
Short name T248
Test name
Test status
Simulation time 23843578323 ps
CPU time 51.33 seconds
Started Jul 22 06:16:13 PM PDT 24
Finished Jul 22 06:17:05 PM PDT 24
Peak memory 200168 kb
Host smart-4c37179f-0891-4ebc-a18d-bd21081b2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714421912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2714421912
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2412254736
Short name T194
Test name
Test status
Simulation time 88899229913 ps
CPU time 30.31 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200164 kb
Host smart-08ab51c5-fa80-4559-a1ff-c8b1b7f57e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412254736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2412254736
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1476371354
Short name T750
Test name
Test status
Simulation time 46022386 ps
CPU time 0.53 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:12:57 PM PDT 24
Peak memory 195076 kb
Host smart-3cbe3ed6-14a1-4a0a-a576-b62a04213fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476371354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1476371354
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1345529796
Short name T433
Test name
Test status
Simulation time 58428004514 ps
CPU time 80.44 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 200164 kb
Host smart-09a3ebe5-f515-44cd-9b5e-dd798e288f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345529796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1345529796
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.854539424
Short name T850
Test name
Test status
Simulation time 94615182107 ps
CPU time 120.17 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:14:57 PM PDT 24
Peak memory 200172 kb
Host smart-033724a0-419c-48cf-adba-ac6049b6fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854539424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.854539424
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.701665938
Short name T549
Test name
Test status
Simulation time 49360326006 ps
CPU time 86.51 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:14:23 PM PDT 24
Peak memory 200248 kb
Host smart-29f02b47-10d5-4ae5-b7ff-5dd9022204e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701665938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.701665938
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.52325807
Short name T741
Test name
Test status
Simulation time 12466012424 ps
CPU time 5.91 seconds
Started Jul 22 06:12:54 PM PDT 24
Finished Jul 22 06:13:00 PM PDT 24
Peak memory 198812 kb
Host smart-d3756aeb-6106-4db2-a2f7-fe079dcc6397
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52325807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.52325807
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4055706701
Short name T251
Test name
Test status
Simulation time 199370846355 ps
CPU time 200.65 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:16:14 PM PDT 24
Peak memory 200232 kb
Host smart-afc91102-e02c-4784-890e-7f7eb66e0bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055706701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4055706701
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2039867254
Short name T363
Test name
Test status
Simulation time 636210499 ps
CPU time 0.93 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:14:51 PM PDT 24
Peak memory 196284 kb
Host smart-1a3a5576-7b3d-4b50-b7b9-183265e32dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039867254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2039867254
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3320738463
Short name T289
Test name
Test status
Simulation time 3004136839 ps
CPU time 5.32 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:13:01 PM PDT 24
Peak memory 194800 kb
Host smart-9309df71-6471-431c-961f-604f5e69a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320738463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3320738463
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.192532371
Short name T708
Test name
Test status
Simulation time 29536356314 ps
CPU time 379.27 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 200248 kb
Host smart-68a65a55-99d3-44f9-bfad-a1e244470c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192532371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.192532371
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3728725311
Short name T830
Test name
Test status
Simulation time 5051094761 ps
CPU time 10.13 seconds
Started Jul 22 06:12:55 PM PDT 24
Finished Jul 22 06:13:06 PM PDT 24
Peak memory 199496 kb
Host smart-2baabe39-6147-4bdf-a9df-cd052953f4f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728725311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3728725311
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2189808410
Short name T646
Test name
Test status
Simulation time 21296667999 ps
CPU time 29.55 seconds
Started Jul 22 06:12:49 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 200168 kb
Host smart-0aacaa06-4816-40df-84cc-44e012ed3e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189808410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2189808410
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4163228653
Short name T454
Test name
Test status
Simulation time 35616299517 ps
CPU time 57.57 seconds
Started Jul 22 06:12:53 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 196332 kb
Host smart-c902ddd7-4ece-47c0-b3f5-caea356ab9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163228653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4163228653
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4280271525
Short name T1102
Test name
Test status
Simulation time 695612271 ps
CPU time 1.47 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:13:05 PM PDT 24
Peak memory 199908 kb
Host smart-811d798d-2317-4843-8c70-c73917ea8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280271525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4280271525
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3921192870
Short name T904
Test name
Test status
Simulation time 301897625457 ps
CPU time 971.05 seconds
Started Jul 22 06:12:57 PM PDT 24
Finished Jul 22 06:29:08 PM PDT 24
Peak memory 200228 kb
Host smart-2af9c79c-3fa8-4244-80ad-4a1662eb4ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921192870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3921192870
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2811877558
Short name T1149
Test name
Test status
Simulation time 157259844841 ps
CPU time 469.77 seconds
Started Jul 22 06:12:56 PM PDT 24
Finished Jul 22 06:20:46 PM PDT 24
Peak memory 216664 kb
Host smart-8d2bc6a6-f94b-4e63-b271-ee14a60a40f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811877558 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2811877558
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3704315117
Short name T698
Test name
Test status
Simulation time 12251059811 ps
CPU time 53.43 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:15:25 PM PDT 24
Peak memory 200104 kb
Host smart-1e16ecf1-5b8d-4772-b4ef-c3e220a2524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704315117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3704315117
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1427948348
Short name T882
Test name
Test status
Simulation time 33681066973 ps
CPU time 14.62 seconds
Started Jul 22 06:14:21 PM PDT 24
Finished Jul 22 06:14:37 PM PDT 24
Peak memory 200248 kb
Host smart-b6e6b8bd-3f7a-448c-9059-53ff46d4ddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427948348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1427948348
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.587366062
Short name T1056
Test name
Test status
Simulation time 56995543975 ps
CPU time 43.87 seconds
Started Jul 22 06:16:09 PM PDT 24
Finished Jul 22 06:16:53 PM PDT 24
Peak memory 200208 kb
Host smart-4db16c06-2329-4e90-a4e6-c63f328632cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587366062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.587366062
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.61310335
Short name T627
Test name
Test status
Simulation time 192746939972 ps
CPU time 74.62 seconds
Started Jul 22 06:16:08 PM PDT 24
Finished Jul 22 06:17:23 PM PDT 24
Peak memory 200172 kb
Host smart-e6445b57-a3e4-4791-afd9-7bb3ad679360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61310335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.61310335
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2197017797
Short name T407
Test name
Test status
Simulation time 10683074928 ps
CPU time 17.92 seconds
Started Jul 22 06:16:09 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200028 kb
Host smart-6715786d-63c1-46bc-87b9-d2fdf4b15081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197017797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2197017797
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.383223719
Short name T306
Test name
Test status
Simulation time 42558983902 ps
CPU time 67.07 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:17:25 PM PDT 24
Peak memory 200272 kb
Host smart-b8d5698f-00db-4611-9e66-2e2b51a07008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383223719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.383223719
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4057204743
Short name T300
Test name
Test status
Simulation time 28214448862 ps
CPU time 12.84 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:16:30 PM PDT 24
Peak memory 200244 kb
Host smart-64fb16ab-4e7a-44dd-9896-d92dae0848f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057204743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4057204743
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1764351954
Short name T574
Test name
Test status
Simulation time 16566791724 ps
CPU time 23.66 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:16:42 PM PDT 24
Peak memory 200264 kb
Host smart-9bde6e39-13fb-438b-ba7a-4c3850bb4c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764351954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1764351954
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.566821878
Short name T191
Test name
Test status
Simulation time 223215871243 ps
CPU time 32.63 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:16:52 PM PDT 24
Peak memory 200092 kb
Host smart-b1f835ba-6d99-4869-bbd5-01c81201fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566821878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.566821878
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.20483164
Short name T149
Test name
Test status
Simulation time 20132741080 ps
CPU time 26.81 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:16:44 PM PDT 24
Peak memory 200256 kb
Host smart-13a397b1-81ee-4fed-a954-1bbe68fc943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20483164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.20483164
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4179860128
Short name T832
Test name
Test status
Simulation time 15279464 ps
CPU time 0.55 seconds
Started Jul 22 06:13:04 PM PDT 24
Finished Jul 22 06:13:05 PM PDT 24
Peak memory 195796 kb
Host smart-683315a7-c1ba-4285-8ecb-4d69358cfb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179860128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4179860128
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2234296831
Short name T510
Test name
Test status
Simulation time 159503569179 ps
CPU time 319.47 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:18:23 PM PDT 24
Peak memory 200116 kb
Host smart-a3c51f5b-833d-486e-aabe-bd7b5aaf6bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234296831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2234296831
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3474393189
Short name T668
Test name
Test status
Simulation time 19930418415 ps
CPU time 28.74 seconds
Started Jul 22 06:12:57 PM PDT 24
Finished Jul 22 06:13:26 PM PDT 24
Peak memory 200184 kb
Host smart-f9c2e717-36bd-4826-bcf7-e5bec40b7976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474393189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3474393189
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.315500173
Short name T1142
Test name
Test status
Simulation time 26995020690 ps
CPU time 22.42 seconds
Started Jul 22 06:13:02 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 200200 kb
Host smart-a0bdfb70-0835-45cf-a183-826023b2e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315500173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.315500173
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3476998798
Short name T669
Test name
Test status
Simulation time 55004074099 ps
CPU time 85.19 seconds
Started Jul 22 06:13:02 PM PDT 24
Finished Jul 22 06:14:27 PM PDT 24
Peak memory 200000 kb
Host smart-a01f8191-d2f0-4417-9f87-92efc88bc854
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476998798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3476998798
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1635421469
Short name T637
Test name
Test status
Simulation time 61506897380 ps
CPU time 407.44 seconds
Started Jul 22 06:14:53 PM PDT 24
Finished Jul 22 06:21:44 PM PDT 24
Peak memory 200072 kb
Host smart-5908c375-22bb-42a1-ba93-f762ba736210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635421469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1635421469
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1768673936
Short name T410
Test name
Test status
Simulation time 894993413 ps
CPU time 1.16 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:13:04 PM PDT 24
Peak memory 195556 kb
Host smart-c828cbbc-2aba-48b4-a272-bfa1f5de11be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768673936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1768673936
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.488277451
Short name T598
Test name
Test status
Simulation time 12211503095 ps
CPU time 17.89 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 199204 kb
Host smart-1a5cd2e4-2e8c-4ac2-bcb6-dca2030d9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488277451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.488277451
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2614830077
Short name T1163
Test name
Test status
Simulation time 10233774629 ps
CPU time 576.89 seconds
Started Jul 22 06:13:04 PM PDT 24
Finished Jul 22 06:22:41 PM PDT 24
Peak memory 200208 kb
Host smart-ead2a5f2-a318-4eef-a663-9a71542011a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614830077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2614830077
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3559995895
Short name T319
Test name
Test status
Simulation time 5879349112 ps
CPU time 13.84 seconds
Started Jul 22 06:13:01 PM PDT 24
Finished Jul 22 06:13:15 PM PDT 24
Peak memory 198612 kb
Host smart-dcb1e594-356f-4a4f-9e0e-41eac1831201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559995895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3559995895
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.180387903
Short name T593
Test name
Test status
Simulation time 116501359077 ps
CPU time 72.52 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 199952 kb
Host smart-e9b2c789-24a1-4f10-ad6a-a0080d0fe4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180387903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.180387903
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2405334343
Short name T1097
Test name
Test status
Simulation time 3450134612 ps
CPU time 1.75 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:13:07 PM PDT 24
Peak memory 196316 kb
Host smart-2f7e038c-e6e8-4152-a002-9457e13e0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405334343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2405334343
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2171070630
Short name T1032
Test name
Test status
Simulation time 105058035 ps
CPU time 0.98 seconds
Started Jul 22 06:14:24 PM PDT 24
Finished Jul 22 06:14:25 PM PDT 24
Peak memory 199488 kb
Host smart-8814f181-8e08-4580-b2fc-160be0e1d4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171070630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2171070630
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1675055757
Short name T1151
Test name
Test status
Simulation time 7522167300 ps
CPU time 16.68 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 199964 kb
Host smart-93203064-0cde-43cd-9eea-f0516d8e7957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675055757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1675055757
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1285926318
Short name T332
Test name
Test status
Simulation time 10162898769 ps
CPU time 17.88 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:15:08 PM PDT 24
Peak memory 200128 kb
Host smart-1d9ae40b-5bb3-425d-92b4-b25345d2a5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285926318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1285926318
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3918952497
Short name T11
Test name
Test status
Simulation time 106513514699 ps
CPU time 172.68 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:19:09 PM PDT 24
Peak memory 200128 kb
Host smart-f4967a1c-9173-48f4-80e0-b36a950ae00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918952497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3918952497
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1982706670
Short name T206
Test name
Test status
Simulation time 42223126983 ps
CPU time 68.67 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:17:28 PM PDT 24
Peak memory 200192 kb
Host smart-6843e161-0883-4cb3-8b1e-32d7976f480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982706670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1982706670
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1599882763
Short name T362
Test name
Test status
Simulation time 38552966173 ps
CPU time 15.98 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:16:32 PM PDT 24
Peak memory 200280 kb
Host smart-bfc5ba58-bd06-4b74-83ff-b4a50249be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599882763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1599882763
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1514871750
Short name T1171
Test name
Test status
Simulation time 8044558568 ps
CPU time 11 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 199172 kb
Host smart-73aa5f2f-eedf-4f1d-b99e-158f03b126e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514871750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1514871750
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.13918770
Short name T971
Test name
Test status
Simulation time 266791022117 ps
CPU time 34.69 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:16:52 PM PDT 24
Peak memory 200268 kb
Host smart-6734687c-cdca-4db6-b06a-67e46a55b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13918770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.13918770
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1478423295
Short name T811
Test name
Test status
Simulation time 15865534167 ps
CPU time 23.98 seconds
Started Jul 22 06:16:18 PM PDT 24
Finished Jul 22 06:16:43 PM PDT 24
Peak memory 198792 kb
Host smart-8c7b0b07-653d-4b16-a45c-6b41bf4be2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478423295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1478423295
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1989451625
Short name T924
Test name
Test status
Simulation time 217348502539 ps
CPU time 59.22 seconds
Started Jul 22 06:16:22 PM PDT 24
Finished Jul 22 06:17:21 PM PDT 24
Peak memory 200160 kb
Host smart-4c082047-8449-47e9-9999-3327d2ad3e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989451625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1989451625
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3694506385
Short name T133
Test name
Test status
Simulation time 64175890525 ps
CPU time 111.2 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:18:09 PM PDT 24
Peak memory 200104 kb
Host smart-5c7e8351-e3d6-48f1-a558-9990dbe2148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694506385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3694506385
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.169864385
Short name T874
Test name
Test status
Simulation time 22310402255 ps
CPU time 15.12 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 200180 kb
Host smart-1c52f3df-cbeb-4817-97f4-94c3139d7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169864385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.169864385
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.142188021
Short name T312
Test name
Test status
Simulation time 26482640 ps
CPU time 0.56 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:13:06 PM PDT 24
Peak memory 195044 kb
Host smart-756ba1ab-2d16-4a01-97c1-03f462130e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142188021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.142188021
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4119267717
Short name T1159
Test name
Test status
Simulation time 143395138599 ps
CPU time 206.62 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 200080 kb
Host smart-a82eab5b-935a-45a6-b061-32bfca241932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119267717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4119267717
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4120546440
Short name T90
Test name
Test status
Simulation time 18111150078 ps
CPU time 16.91 seconds
Started Jul 22 06:13:04 PM PDT 24
Finished Jul 22 06:13:21 PM PDT 24
Peak memory 200160 kb
Host smart-14406703-f346-466b-93bb-35e3422e8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120546440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4120546440
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3281758356
Short name T155
Test name
Test status
Simulation time 130857287179 ps
CPU time 68.16 seconds
Started Jul 22 06:13:02 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 200260 kb
Host smart-185fe036-c865-43f9-9149-275f3614d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281758356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3281758356
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1959350073
Short name T426
Test name
Test status
Simulation time 49636666169 ps
CPU time 76.62 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:15:16 PM PDT 24
Peak memory 200204 kb
Host smart-04ea5e69-8acf-4a43-b09e-1e1658228f15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959350073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1959350073
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3453130356
Short name T320
Test name
Test status
Simulation time 123999890807 ps
CPU time 1296.63 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:34:40 PM PDT 24
Peak memory 200228 kb
Host smart-5082ae65-c0d8-4436-92db-a778d4ac1c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453130356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3453130356
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.617424354
Short name T479
Test name
Test status
Simulation time 5042532422 ps
CPU time 3.92 seconds
Started Jul 22 06:13:07 PM PDT 24
Finished Jul 22 06:13:11 PM PDT 24
Peak memory 199776 kb
Host smart-0130e8a2-cf40-44c3-8081-d4234be21c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617424354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.617424354
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.89783397
Short name T866
Test name
Test status
Simulation time 34719536436 ps
CPU time 14.19 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:15:04 PM PDT 24
Peak memory 194968 kb
Host smart-75dcc4ff-3bb4-4d03-a23b-502775bb6fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89783397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.89783397
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4263584912
Short name T543
Test name
Test status
Simulation time 13333802966 ps
CPU time 579.37 seconds
Started Jul 22 06:13:02 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 200268 kb
Host smart-f76953fe-a155-4fab-a9f5-60e662955a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263584912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4263584912
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1476452533
Short name T1177
Test name
Test status
Simulation time 3522815154 ps
CPU time 25.81 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:13:32 PM PDT 24
Peak memory 198220 kb
Host smart-5d77ddf8-9910-4789-b647-f69e30d52ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476452533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1476452533
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2090188065
Short name T671
Test name
Test status
Simulation time 125824914529 ps
CPU time 37.67 seconds
Started Jul 22 06:13:06 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 200188 kb
Host smart-fb46ca43-a943-4d15-ab84-b98e848ac140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090188065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2090188065
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2971616160
Short name T1132
Test name
Test status
Simulation time 29784012929 ps
CPU time 10.4 seconds
Started Jul 22 06:13:03 PM PDT 24
Finished Jul 22 06:13:14 PM PDT 24
Peak memory 196100 kb
Host smart-b14d7c34-229e-4aee-9727-5f3974c06df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971616160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2971616160
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2918076822
Short name T815
Test name
Test status
Simulation time 739070380 ps
CPU time 1.89 seconds
Started Jul 22 06:13:04 PM PDT 24
Finished Jul 22 06:13:06 PM PDT 24
Peak memory 198876 kb
Host smart-88ac2135-5456-4a54-b3d6-79fe321f91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918076822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2918076822
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2078197983
Short name T1044
Test name
Test status
Simulation time 208782870744 ps
CPU time 351.36 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 200192 kb
Host smart-5356ddfd-32a6-4898-97f0-327bbb3127c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078197983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2078197983
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1770394302
Short name T641
Test name
Test status
Simulation time 32564878259 ps
CPU time 187.34 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:17:07 PM PDT 24
Peak memory 216920 kb
Host smart-f1b358d3-a101-4bd3-8ebc-3792391bc241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770394302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1770394302
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3538816522
Short name T1040
Test name
Test status
Simulation time 476422219 ps
CPU time 1.64 seconds
Started Jul 22 06:13:05 PM PDT 24
Finished Jul 22 06:13:07 PM PDT 24
Peak memory 198012 kb
Host smart-f7921a9d-0b82-44a8-809b-5a81f055dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538816522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3538816522
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1713563745
Short name T361
Test name
Test status
Simulation time 32111159289 ps
CPU time 17.31 seconds
Started Jul 22 06:13:02 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 200256 kb
Host smart-22dbd966-8431-49ab-a752-18cb7613eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713563745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1713563745
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1030526787
Short name T907
Test name
Test status
Simulation time 63825426130 ps
CPU time 91.85 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:17:49 PM PDT 24
Peak memory 200196 kb
Host smart-95cb2db4-264c-42a1-9131-cbc7138d49f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030526787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1030526787
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1624463037
Short name T613
Test name
Test status
Simulation time 122487022513 ps
CPU time 54.75 seconds
Started Jul 22 06:17:04 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 200164 kb
Host smart-cf54cb6f-e7c4-4ebc-9be3-73e9b9d54056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624463037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1624463037
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2015669155
Short name T412
Test name
Test status
Simulation time 96500969316 ps
CPU time 137.82 seconds
Started Jul 22 06:16:19 PM PDT 24
Finished Jul 22 06:18:37 PM PDT 24
Peak memory 200176 kb
Host smart-369cc323-7028-4718-875f-ea53c5efdee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015669155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2015669155
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3963670110
Short name T422
Test name
Test status
Simulation time 61933006053 ps
CPU time 50.94 seconds
Started Jul 22 06:16:19 PM PDT 24
Finished Jul 22 06:17:10 PM PDT 24
Peak memory 200016 kb
Host smart-04c85e4f-9627-4ebf-bd7c-2efc9d4777b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963670110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3963670110
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.239973478
Short name T774
Test name
Test status
Simulation time 33285092205 ps
CPU time 24.1 seconds
Started Jul 22 06:16:17 PM PDT 24
Finished Jul 22 06:16:42 PM PDT 24
Peak memory 200284 kb
Host smart-d4cfce1e-3e19-4476-8d83-74fb442fca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239973478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.239973478
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1928164991
Short name T237
Test name
Test status
Simulation time 131796314493 ps
CPU time 105.45 seconds
Started Jul 22 06:16:16 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 200196 kb
Host smart-02c560e4-d412-45cc-a901-b3fc466c453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928164991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1928164991
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1269593501
Short name T179
Test name
Test status
Simulation time 125222808084 ps
CPU time 154.22 seconds
Started Jul 22 06:16:27 PM PDT 24
Finished Jul 22 06:19:02 PM PDT 24
Peak memory 200256 kb
Host smart-037a8bc1-6486-4b27-822b-6a502aa65b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269593501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1269593501
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1849857176
Short name T438
Test name
Test status
Simulation time 13546014 ps
CPU time 0.55 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 195548 kb
Host smart-de1dc288-a171-46e9-b49b-f652e3831653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849857176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1849857176
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2020036228
Short name T869
Test name
Test status
Simulation time 175849076705 ps
CPU time 62.9 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 200224 kb
Host smart-f48d74ff-9f35-45ca-8639-ab0c0f25f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020036228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2020036228
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.487434226
Short name T612
Test name
Test status
Simulation time 76079879274 ps
CPU time 33.66 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 200236 kb
Host smart-9ac2749f-04e3-4ac7-9277-0df86722b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487434226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.487434226
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.823919008
Short name T491
Test name
Test status
Simulation time 146194160277 ps
CPU time 95.86 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:13:03 PM PDT 24
Peak memory 200172 kb
Host smart-ad6a482c-24c7-4898-a7ea-f7556826abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823919008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.823919008
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1846144675
Short name T380
Test name
Test status
Simulation time 41081558591 ps
CPU time 60.64 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 200316 kb
Host smart-f69c98ea-c973-4c44-bc68-c2086f5d0253
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846144675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1846144675
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.426838601
Short name T730
Test name
Test status
Simulation time 72509189545 ps
CPU time 129.15 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:13:38 PM PDT 24
Peak memory 200172 kb
Host smart-37ea65c7-4b39-4217-908f-2bec34d0b4ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426838601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.426838601
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1194021986
Short name T699
Test name
Test status
Simulation time 5029012258 ps
CPU time 7.29 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 200068 kb
Host smart-925c92f7-d050-45e6-bf9d-518f93a6a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194021986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1194021986
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1004760278
Short name T497
Test name
Test status
Simulation time 41972371269 ps
CPU time 30.05 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 198704 kb
Host smart-c1cc9b97-7bec-4159-a0f6-6f3d819fdb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004760278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1004760278
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2662835870
Short name T908
Test name
Test status
Simulation time 14570704277 ps
CPU time 404.11 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:18:13 PM PDT 24
Peak memory 200240 kb
Host smart-4440bc39-6e52-4c5e-8e89-c4cdaf55eea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662835870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2662835870
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2176695731
Short name T91
Test name
Test status
Simulation time 1481339817 ps
CPU time 5.76 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 198048 kb
Host smart-18c50a53-f1d3-42da-9a54-96428500082c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176695731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2176695731
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.241082571
Short name T862
Test name
Test status
Simulation time 104237020229 ps
CPU time 165.1 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 200196 kb
Host smart-53f74311-ff3d-4763-a20f-bdb7c852cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241082571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.241082571
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3638057038
Short name T418
Test name
Test status
Simulation time 1886343444 ps
CPU time 1.96 seconds
Started Jul 22 06:11:30 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 195708 kb
Host smart-988222de-5d8b-4ee9-99b7-40ec8eb1c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638057038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3638057038
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3178954278
Short name T24
Test name
Test status
Simulation time 328837665 ps
CPU time 0.87 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:26 PM PDT 24
Peak memory 218468 kb
Host smart-add355a7-acc6-485c-b51b-a9759cd113f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178954278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3178954278
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2464890954
Short name T277
Test name
Test status
Simulation time 970935160 ps
CPU time 1.68 seconds
Started Jul 22 06:11:29 PM PDT 24
Finished Jul 22 06:11:31 PM PDT 24
Peak memory 200164 kb
Host smart-af357e0e-7c0b-40f5-98a1-257ec02ff0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464890954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2464890954
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2223220627
Short name T428
Test name
Test status
Simulation time 132465433443 ps
CPU time 124.49 seconds
Started Jul 22 06:12:43 PM PDT 24
Finished Jul 22 06:14:47 PM PDT 24
Peak memory 200120 kb
Host smart-fa8ceafb-eaca-4ebf-a4e0-769983c7a4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223220627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2223220627
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4145761408
Short name T32
Test name
Test status
Simulation time 121252811756 ps
CPU time 748.3 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:23:57 PM PDT 24
Peak memory 216832 kb
Host smart-55c1c8b8-d034-428b-b57f-88020d1ba3b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145761408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4145761408
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2498359327
Short name T398
Test name
Test status
Simulation time 477630641 ps
CPU time 1.41 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:26 PM PDT 24
Peak memory 198624 kb
Host smart-2f4442f0-572f-4407-b704-fd329e613b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498359327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2498359327
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1617699776
Short name T1110
Test name
Test status
Simulation time 9238384890 ps
CPU time 6.72 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:11:34 PM PDT 24
Peak memory 199056 kb
Host smart-d5410ffb-83e2-4f18-b6c0-c52729df022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617699776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1617699776
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1188948819
Short name T311
Test name
Test status
Simulation time 15883638 ps
CPU time 0.54 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 195904 kb
Host smart-9d3c61de-aa71-4d47-a18f-795b1918fbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188948819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1188948819
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.528088977
Short name T606
Test name
Test status
Simulation time 45563526575 ps
CPU time 15.04 seconds
Started Jul 22 06:13:10 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 200248 kb
Host smart-d225cd14-f0f2-49a1-9b39-5db64ab733b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528088977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.528088977
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3236996555
Short name T659
Test name
Test status
Simulation time 183854280107 ps
CPU time 62.97 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:15:06 PM PDT 24
Peak memory 199884 kb
Host smart-a995a47f-d6f9-4a24-b5fb-29d67a485aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236996555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3236996555
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2741188722
Short name T184
Test name
Test status
Simulation time 5779942984 ps
CPU time 10.52 seconds
Started Jul 22 06:13:10 PM PDT 24
Finished Jul 22 06:13:21 PM PDT 24
Peak memory 200256 kb
Host smart-e4a022c0-fc4b-411f-9cae-ca651161a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741188722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2741188722
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.979830185
Short name T1117
Test name
Test status
Simulation time 9480027290 ps
CPU time 7.29 seconds
Started Jul 22 06:13:09 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 197236 kb
Host smart-b1d228b6-ca82-4ab3-a8e4-4b4463a0205f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979830185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.979830185
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2626325620
Short name T737
Test name
Test status
Simulation time 99234360436 ps
CPU time 499.68 seconds
Started Jul 22 06:13:13 PM PDT 24
Finished Jul 22 06:21:34 PM PDT 24
Peak memory 200196 kb
Host smart-cb6c5364-5954-40e7-bbd4-0dfd02ca550b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626325620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2626325620
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4087090261
Short name T808
Test name
Test status
Simulation time 11022659809 ps
CPU time 5.74 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 200040 kb
Host smart-fcf24f9a-b309-48d7-b6ee-0f643029770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087090261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4087090261
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1773075382
Short name T403
Test name
Test status
Simulation time 86510262476 ps
CPU time 78.63 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:14:30 PM PDT 24
Peak memory 200248 kb
Host smart-a1c3a1a6-23a1-492e-9db3-c32189a6cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773075382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1773075382
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.875301451
Short name T344
Test name
Test status
Simulation time 13578770401 ps
CPU time 152.86 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:15:45 PM PDT 24
Peak memory 200192 kb
Host smart-c1f1c050-fb5b-49e3-a180-cc68943b1c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875301451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.875301451
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2442325491
Short name T423
Test name
Test status
Simulation time 2749025804 ps
CPU time 4.49 seconds
Started Jul 22 06:13:17 PM PDT 24
Finished Jul 22 06:13:22 PM PDT 24
Peak memory 198436 kb
Host smart-078857d5-fc83-454d-b137-3ad289fba66f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442325491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2442325491
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3954595097
Short name T1103
Test name
Test status
Simulation time 213624876339 ps
CPU time 71.85 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:14:25 PM PDT 24
Peak memory 200248 kb
Host smart-03f6b413-ddb3-47bf-b5d5-fddbb5c534a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954595097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3954595097
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4246507738
Short name T981
Test name
Test status
Simulation time 3220301236 ps
CPU time 3.02 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:14 PM PDT 24
Peak memory 196512 kb
Host smart-2e51999e-1154-4617-b7cf-9fc9d069cdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246507738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4246507738
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1667584713
Short name T1106
Test name
Test status
Simulation time 991108401 ps
CPU time 1.64 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 199048 kb
Host smart-860e8692-4d42-4690-838e-177be02bb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667584713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1667584713
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3713529414
Short name T1104
Test name
Test status
Simulation time 7585832590 ps
CPU time 14.1 seconds
Started Jul 22 06:13:10 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 200200 kb
Host smart-af92bbae-5827-4d07-bdc0-89004d95bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713529414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3713529414
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.984854513
Short name T950
Test name
Test status
Simulation time 75752664514 ps
CPU time 59.45 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 200172 kb
Host smart-eb00bec8-6b72-4ed1-bf22-4a36c464ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984854513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.984854513
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.408274272
Short name T903
Test name
Test status
Simulation time 54740062 ps
CPU time 0.52 seconds
Started Jul 22 06:13:34 PM PDT 24
Finished Jul 22 06:13:35 PM PDT 24
Peak memory 195892 kb
Host smart-1c05f956-5943-4873-9063-72cae2148695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408274272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.408274272
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1019777393
Short name T919
Test name
Test status
Simulation time 122341769395 ps
CPU time 321.52 seconds
Started Jul 22 06:13:13 PM PDT 24
Finished Jul 22 06:18:35 PM PDT 24
Peak memory 200248 kb
Host smart-3368d325-3331-4553-bd1c-693d3a6fc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019777393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1019777393
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4180287820
Short name T269
Test name
Test status
Simulation time 143348709152 ps
CPU time 668.6 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:24:21 PM PDT 24
Peak memory 200208 kb
Host smart-2f100810-783d-4ab2-b7ca-14b7205f3e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180287820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4180287820
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3013075411
Short name T189
Test name
Test status
Simulation time 28203447740 ps
CPU time 31.24 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 200152 kb
Host smart-3480807b-01d7-4c95-9f7a-1d7b75b6c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013075411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3013075411
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1285322100
Short name T1107
Test name
Test status
Simulation time 29791718509 ps
CPU time 12.64 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 200208 kb
Host smart-fb17bd47-bdce-4b10-b421-d6294578dd5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285322100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1285322100
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3368339219
Short name T1027
Test name
Test status
Simulation time 90422119034 ps
CPU time 189.61 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:16:21 PM PDT 24
Peak memory 200188 kb
Host smart-79f609d4-7a4e-4874-8421-1478819b1dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368339219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3368339219
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.826594524
Short name T493
Test name
Test status
Simulation time 4412085588 ps
CPU time 5.23 seconds
Started Jul 22 06:13:13 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 199924 kb
Host smart-30c3afae-1ba2-4cbc-a7c8-238b28a72680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826594524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.826594524
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1929741480
Short name T1116
Test name
Test status
Simulation time 286264036249 ps
CPU time 65.83 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:14:18 PM PDT 24
Peak memory 200224 kb
Host smart-0003c156-2ae0-46c4-8763-0763345e9cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929741480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1929741480
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1475264320
Short name T731
Test name
Test status
Simulation time 20195219850 ps
CPU time 147.24 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:15:40 PM PDT 24
Peak memory 200184 kb
Host smart-129381eb-7ec7-4e5a-80e3-f0ab3d52b33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475264320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1475264320
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3619564752
Short name T761
Test name
Test status
Simulation time 4858812731 ps
CPU time 21.06 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:33 PM PDT 24
Peak memory 199060 kb
Host smart-5161d042-d73c-4cf7-b35a-403ba07721e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619564752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3619564752
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2827853342
Short name T915
Test name
Test status
Simulation time 258957350845 ps
CPU time 231.65 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:17:04 PM PDT 24
Peak memory 200220 kb
Host smart-f707451d-d8ba-40bb-81da-27e7fd0f82df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827853342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2827853342
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1631403533
Short name T379
Test name
Test status
Simulation time 6398804453 ps
CPU time 1.17 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 196312 kb
Host smart-cb104093-3d6f-4301-8798-cd5a17e8c3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631403533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1631403533
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1085777255
Short name T350
Test name
Test status
Simulation time 290976864 ps
CPU time 1.32 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 198944 kb
Host smart-8eb39319-eb6a-46c5-b44b-fc971d0c6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085777255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1085777255
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3098109475
Short name T958
Test name
Test status
Simulation time 154918295072 ps
CPU time 111.56 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:15:54 PM PDT 24
Peak memory 200228 kb
Host smart-82c1bb61-fc4e-4134-85b1-87ec8ea17bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098109475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3098109475
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2773064851
Short name T157
Test name
Test status
Simulation time 63964631976 ps
CPU time 477.11 seconds
Started Jul 22 06:13:12 PM PDT 24
Finished Jul 22 06:21:09 PM PDT 24
Peak memory 216204 kb
Host smart-10cb5b66-da79-4e9a-8ade-d2ff4456dcf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773064851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2773064851
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1009612159
Short name T831
Test name
Test status
Simulation time 6415447423 ps
CPU time 10.66 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:29 PM PDT 24
Peak memory 199820 kb
Host smart-2ab36061-f729-4324-a8c1-89dc291d4553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009612159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1009612159
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2444637418
Short name T389
Test name
Test status
Simulation time 116539078819 ps
CPU time 560.35 seconds
Started Jul 22 06:13:09 PM PDT 24
Finished Jul 22 06:22:30 PM PDT 24
Peak memory 200268 kb
Host smart-3b882d63-271f-4a94-a9e5-7b9971337d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444637418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2444637418
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2216988085
Short name T1114
Test name
Test status
Simulation time 14595151 ps
CPU time 0.55 seconds
Started Jul 22 06:13:17 PM PDT 24
Finished Jul 22 06:13:18 PM PDT 24
Peak memory 195628 kb
Host smart-775e1526-ff14-445e-a494-abb92f5cea02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216988085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2216988085
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2038190207
Short name T654
Test name
Test status
Simulation time 21685918228 ps
CPU time 8.71 seconds
Started Jul 22 06:13:10 PM PDT 24
Finished Jul 22 06:13:20 PM PDT 24
Peak memory 200348 kb
Host smart-4d45f062-4e26-4b18-b9f8-8a8c85191b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038190207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2038190207
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.730561993
Short name T247
Test name
Test status
Simulation time 71810700690 ps
CPU time 29.92 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:48 PM PDT 24
Peak memory 200192 kb
Host smart-2a0c1654-408c-42c8-ae78-909de3afcf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730561993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.730561993
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.2161309920
Short name T680
Test name
Test status
Simulation time 12817204399 ps
CPU time 6.79 seconds
Started Jul 22 06:13:35 PM PDT 24
Finished Jul 22 06:13:43 PM PDT 24
Peak memory 199980 kb
Host smart-42d62d1c-8a75-42bc-8d5d-f540b70749eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161309920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2161309920
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3311782018
Short name T681
Test name
Test status
Simulation time 79202870839 ps
CPU time 680.9 seconds
Started Jul 22 06:14:03 PM PDT 24
Finished Jul 22 06:25:25 PM PDT 24
Peak memory 200168 kb
Host smart-b7218a66-3bb1-4b60-9dae-145b46f80f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311782018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3311782018
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.912254228
Short name T645
Test name
Test status
Simulation time 8552754286 ps
CPU time 15.55 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:13:37 PM PDT 24
Peak memory 200084 kb
Host smart-3846a120-956c-4c0f-af06-de50c2299e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912254228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.912254228
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.899333639
Short name T43
Test name
Test status
Simulation time 92448957022 ps
CPU time 82.81 seconds
Started Jul 22 06:13:08 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 199984 kb
Host smart-56420151-4842-4055-b74e-917d88f40f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899333639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.899333639
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1091332751
Short name T416
Test name
Test status
Simulation time 21949235922 ps
CPU time 136.14 seconds
Started Jul 22 06:14:53 PM PDT 24
Finished Jul 22 06:17:10 PM PDT 24
Peak memory 200212 kb
Host smart-2653f603-c7ab-412b-92c5-45c4c2ea72ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091332751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1091332751
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.182149618
Short name T684
Test name
Test status
Simulation time 6940158296 ps
CPU time 15.29 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:27 PM PDT 24
Peak memory 198376 kb
Host smart-c13882ef-a737-446e-bfa7-7db6cd92f92c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182149618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.182149618
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1660988392
Short name T40
Test name
Test status
Simulation time 90910776726 ps
CPU time 52.15 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:14:16 PM PDT 24
Peak memory 200224 kb
Host smart-8dbe4aa5-16e7-4ec6-8a94-792dd23610df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660988392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1660988392
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.603296471
Short name T807
Test name
Test status
Simulation time 5932276844 ps
CPU time 2.84 seconds
Started Jul 22 06:13:11 PM PDT 24
Finished Jul 22 06:13:15 PM PDT 24
Peak memory 196352 kb
Host smart-718e6818-f1da-4828-a12b-720608718a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603296471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.603296471
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.75276907
Short name T1112
Test name
Test status
Simulation time 481039244 ps
CPU time 1.24 seconds
Started Jul 22 06:13:18 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 198512 kb
Host smart-16a844ee-52a0-41a4-bb5d-dbd58f92ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75276907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.75276907
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.748675519
Short name T470
Test name
Test status
Simulation time 24558820242 ps
CPU time 12.82 seconds
Started Jul 22 06:13:21 PM PDT 24
Finished Jul 22 06:13:35 PM PDT 24
Peak memory 200192 kb
Host smart-596196dd-00af-4640-8ded-6bf28c6a78a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748675519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.748675519
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3277991620
Short name T1156
Test name
Test status
Simulation time 126919436469 ps
CPU time 421.02 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:20:56 PM PDT 24
Peak memory 216900 kb
Host smart-9e208871-9176-4805-b48f-196eb84dd7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277991620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3277991620
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1961518447
Short name T790
Test name
Test status
Simulation time 2041342388 ps
CPU time 2.21 seconds
Started Jul 22 06:13:20 PM PDT 24
Finished Jul 22 06:13:22 PM PDT 24
Peak memory 200024 kb
Host smart-26f5f949-35ce-4479-adee-9a6ee720c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961518447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1961518447
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.930743636
Short name T562
Test name
Test status
Simulation time 74200785836 ps
CPU time 32.3 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:14:28 PM PDT 24
Peak memory 200248 kb
Host smart-f1ebafde-8625-4783-a534-9f4c295a1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930743636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.930743636
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2464191878
Short name T335
Test name
Test status
Simulation time 14236170 ps
CPU time 0.56 seconds
Started Jul 22 06:13:26 PM PDT 24
Finished Jul 22 06:13:27 PM PDT 24
Peak memory 195620 kb
Host smart-2bf73b74-714d-4ec2-8ecd-d63d32999cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464191878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2464191878
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.928684487
Short name T802
Test name
Test status
Simulation time 71108217711 ps
CPU time 25.64 seconds
Started Jul 22 06:13:24 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 200248 kb
Host smart-f3e43848-a21d-47fa-a318-50e7fa428af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928684487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.928684487
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4037242821
Short name T156
Test name
Test status
Simulation time 153276007184 ps
CPU time 42.32 seconds
Started Jul 22 06:13:20 PM PDT 24
Finished Jul 22 06:14:03 PM PDT 24
Peak memory 200252 kb
Host smart-5987091e-2a0c-4325-84fd-d9551b4e1586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037242821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4037242821
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2692193552
Short name T4
Test name
Test status
Simulation time 82470378580 ps
CPU time 54.92 seconds
Started Jul 22 06:13:24 PM PDT 24
Finished Jul 22 06:14:19 PM PDT 24
Peak memory 199740 kb
Host smart-1ea2b24f-a79a-4cee-9f34-724735981289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692193552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2692193552
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.912689747
Short name T836
Test name
Test status
Simulation time 11266063458 ps
CPU time 4.95 seconds
Started Jul 22 06:13:46 PM PDT 24
Finished Jul 22 06:13:52 PM PDT 24
Peak memory 200052 kb
Host smart-c7076729-b1be-43b4-aa55-7f814cc5b1fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912689747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.912689747
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2951886667
Short name T890
Test name
Test status
Simulation time 122686514211 ps
CPU time 266.55 seconds
Started Jul 22 06:13:20 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 200180 kb
Host smart-bfabed8f-8aae-4e92-bebe-db45df21721f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951886667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2951886667
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4142836113
Short name T481
Test name
Test status
Simulation time 11357043935 ps
CPU time 12.38 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:13:36 PM PDT 24
Peak memory 200236 kb
Host smart-1820d525-00b8-4e30-a846-765f211c7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142836113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4142836113
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3591114115
Short name T809
Test name
Test status
Simulation time 9495751300 ps
CPU time 12.35 seconds
Started Jul 22 06:13:21 PM PDT 24
Finished Jul 22 06:13:34 PM PDT 24
Peak memory 194808 kb
Host smart-166a5bb2-ccb1-4bf6-82bd-9f442fceb269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591114115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3591114115
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3847350430
Short name T912
Test name
Test status
Simulation time 16263489571 ps
CPU time 252.9 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 200156 kb
Host smart-32bd17f4-1f13-4426-9ab1-2d14eb188f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847350430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3847350430
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.905853758
Short name T784
Test name
Test status
Simulation time 2445211395 ps
CPU time 18.66 seconds
Started Jul 22 06:13:24 PM PDT 24
Finished Jul 22 06:13:43 PM PDT 24
Peak memory 198156 kb
Host smart-5f764712-2cdb-4e9c-b6ce-b6a86c0a3ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905853758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.905853758
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3510057486
Short name T267
Test name
Test status
Simulation time 19766237645 ps
CPU time 29.4 seconds
Started Jul 22 06:13:20 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 200156 kb
Host smart-a74d8adb-d773-434c-ba02-f0b5b7fbc9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510057486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3510057486
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1391592777
Short name T719
Test name
Test status
Simulation time 43797906226 ps
CPU time 18.46 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:13:41 PM PDT 24
Peak memory 196020 kb
Host smart-73b5de23-aab9-4bf4-aa4d-97765a8bb6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391592777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1391592777
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3347607493
Short name T1090
Test name
Test status
Simulation time 701560068 ps
CPU time 1.59 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 198564 kb
Host smart-6743682a-6a0b-4ee3-8f88-cd81f48a4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347607493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3347607493
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3594201060
Short name T512
Test name
Test status
Simulation time 46285407289 ps
CPU time 33.51 seconds
Started Jul 22 06:13:26 PM PDT 24
Finished Jul 22 06:14:00 PM PDT 24
Peak memory 200172 kb
Host smart-80a8c663-dcc9-400e-b567-d3206547884d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594201060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3594201060
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.4228868861
Short name T359
Test name
Test status
Simulation time 842438655 ps
CPU time 3.02 seconds
Started Jul 22 06:14:53 PM PDT 24
Finished Jul 22 06:14:57 PM PDT 24
Peak memory 199996 kb
Host smart-d6dcad85-678c-42ac-9568-50760b519b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228868861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4228868861
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.177582878
Short name T715
Test name
Test status
Simulation time 34107921484 ps
CPU time 56.3 seconds
Started Jul 22 06:13:20 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 200384 kb
Host smart-b9fe84f5-fd83-4bc9-bed7-c79ecc802f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177582878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.177582878
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3949746453
Short name T42
Test name
Test status
Simulation time 35938061 ps
CPU time 0.53 seconds
Started Jul 22 06:13:29 PM PDT 24
Finished Jul 22 06:13:30 PM PDT 24
Peak memory 195388 kb
Host smart-22d15e48-d8ab-4f5e-91e7-8be814fe6a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949746453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3949746453
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.27888697
Short name T419
Test name
Test status
Simulation time 29132546367 ps
CPU time 15.07 seconds
Started Jul 22 06:13:26 PM PDT 24
Finished Jul 22 06:13:41 PM PDT 24
Peak memory 200256 kb
Host smart-24ec276f-4075-4615-8d82-d7122d449d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27888697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.27888697
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.313667999
Short name T758
Test name
Test status
Simulation time 11470541625 ps
CPU time 9.62 seconds
Started Jul 22 06:13:26 PM PDT 24
Finished Jul 22 06:13:36 PM PDT 24
Peak memory 200168 kb
Host smart-0fa7fa38-f1ae-4813-84ae-7801ea23446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313667999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.313667999
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.625415919
Short name T980
Test name
Test status
Simulation time 48071573972 ps
CPU time 16.62 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 200204 kb
Host smart-1c1323a9-0fdf-4acc-89e9-d5e19cbe3c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625415919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.625415919
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3767102069
Short name T338
Test name
Test status
Simulation time 12735519879 ps
CPU time 4.31 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:13:27 PM PDT 24
Peak memory 196928 kb
Host smart-ec2a1ccf-9ba0-4794-b0c2-12bb09f00dfc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767102069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3767102069
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1540537204
Short name T241
Test name
Test status
Simulation time 122145877342 ps
CPU time 221.04 seconds
Started Jul 22 06:13:32 PM PDT 24
Finished Jul 22 06:17:14 PM PDT 24
Peak memory 200244 kb
Host smart-b0b5c0d4-f0f3-450e-a9dd-dde42a99e81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540537204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1540537204
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1913423954
Short name T1125
Test name
Test status
Simulation time 6132069657 ps
CPU time 2.68 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 200084 kb
Host smart-51b565df-5665-447b-ba60-d8d76d78da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913423954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1913423954
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2468859866
Short name T1038
Test name
Test status
Simulation time 21913167204 ps
CPU time 15.64 seconds
Started Jul 22 06:13:31 PM PDT 24
Finished Jul 22 06:13:47 PM PDT 24
Peak memory 195320 kb
Host smart-c0421d5b-5fdc-40e4-bd50-fcd4d168ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468859866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2468859866
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2773322292
Short name T623
Test name
Test status
Simulation time 13330166129 ps
CPU time 252.34 seconds
Started Jul 22 06:13:31 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 200188 kb
Host smart-e69577f1-9936-4d7a-b0d0-02fa0b804edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773322292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2773322292
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.525442677
Short name T554
Test name
Test status
Simulation time 2400781266 ps
CPU time 1.95 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 198452 kb
Host smart-8b323575-3418-4912-b0f0-c7fe0016718f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525442677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.525442677
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3492205984
Short name T1118
Test name
Test status
Simulation time 149096261100 ps
CPU time 59.03 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:14:29 PM PDT 24
Peak memory 200252 kb
Host smart-fb814e03-b4fa-41a6-92e2-3e43db48c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492205984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3492205984
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1074723782
Short name T949
Test name
Test status
Simulation time 1535949681 ps
CPU time 3.06 seconds
Started Jul 22 06:13:27 PM PDT 24
Finished Jul 22 06:13:30 PM PDT 24
Peak memory 195908 kb
Host smart-bd9095f1-6ac6-4b7c-b76f-e4483fda015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074723782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1074723782
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3908003316
Short name T516
Test name
Test status
Simulation time 484129450 ps
CPU time 1.12 seconds
Started Jul 22 06:13:22 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 200040 kb
Host smart-732001ef-8044-48cb-ab4f-aa42c287e332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908003316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3908003316
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3265413586
Short name T201
Test name
Test status
Simulation time 140833593396 ps
CPU time 113.39 seconds
Started Jul 22 06:13:38 PM PDT 24
Finished Jul 22 06:15:32 PM PDT 24
Peak memory 200152 kb
Host smart-e74a2239-89fe-4dbd-8f6f-cd0569cbd334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265413586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3265413586
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1028364837
Short name T801
Test name
Test status
Simulation time 260014213648 ps
CPU time 808.5 seconds
Started Jul 22 06:13:32 PM PDT 24
Finished Jul 22 06:27:01 PM PDT 24
Peak memory 225124 kb
Host smart-1ee68dd1-50b2-408a-830b-aadc68579a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028364837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1028364837
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.620363803
Short name T794
Test name
Test status
Simulation time 7337742313 ps
CPU time 20.83 seconds
Started Jul 22 06:13:34 PM PDT 24
Finished Jul 22 06:13:56 PM PDT 24
Peak memory 199988 kb
Host smart-55cd3425-4088-4447-b113-7fe25abeb319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620363803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.620363803
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1017816083
Short name T854
Test name
Test status
Simulation time 44027285334 ps
CPU time 49.04 seconds
Started Jul 22 06:13:23 PM PDT 24
Finished Jul 22 06:14:12 PM PDT 24
Peak memory 200204 kb
Host smart-2ec663cb-6973-4daf-bcbe-50a0c4370029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017816083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1017816083
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3299918894
Short name T313
Test name
Test status
Simulation time 18930741 ps
CPU time 0.54 seconds
Started Jul 22 06:14:01 PM PDT 24
Finished Jul 22 06:14:02 PM PDT 24
Peak memory 194608 kb
Host smart-9cac81a1-b51d-43a1-becf-9471d464e963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299918894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3299918894
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3364446336
Short name T1063
Test name
Test status
Simulation time 74104867042 ps
CPU time 134.97 seconds
Started Jul 22 06:13:38 PM PDT 24
Finished Jul 22 06:15:53 PM PDT 24
Peak memory 200216 kb
Host smart-66aa418e-f2f1-4ef2-bb2a-18c76fc971ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364446336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3364446336
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1961583
Short name T480
Test name
Test status
Simulation time 9798411398 ps
CPU time 18.2 seconds
Started Jul 22 06:13:32 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 200056 kb
Host smart-6aedeb4f-47f6-4e15-9688-f787c1d11f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1961583
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1150928025
Short name T984
Test name
Test status
Simulation time 103372488036 ps
CPU time 120.35 seconds
Started Jul 22 06:14:11 PM PDT 24
Finished Jul 22 06:16:12 PM PDT 24
Peak memory 200176 kb
Host smart-2d1817bc-bad8-4a2d-9f9f-5f983629aa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150928025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1150928025
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2483562816
Short name T974
Test name
Test status
Simulation time 26078343755 ps
CPU time 46.37 seconds
Started Jul 22 06:13:31 PM PDT 24
Finished Jul 22 06:14:18 PM PDT 24
Peak memory 200188 kb
Host smart-ae726ea5-a740-4d5d-b441-38499749770e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483562816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2483562816
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3431330146
Short name T713
Test name
Test status
Simulation time 106169075777 ps
CPU time 296.18 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:18:27 PM PDT 24
Peak memory 200244 kb
Host smart-96e6b29e-e59f-4ee6-929d-3757a369216f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431330146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3431330146
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3878565094
Short name T1008
Test name
Test status
Simulation time 6756409223 ps
CPU time 5.38 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:13:35 PM PDT 24
Peak memory 199708 kb
Host smart-80f39b05-3ed7-4050-b2b1-2b1466e2acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878565094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3878565094
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1282792447
Short name T651
Test name
Test status
Simulation time 34123090060 ps
CPU time 14.55 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:13:45 PM PDT 24
Peak memory 198860 kb
Host smart-ea0ed3a9-f226-4b10-a324-218dc96a6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282792447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1282792447
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1634181359
Short name T518
Test name
Test status
Simulation time 13342171549 ps
CPU time 185.03 seconds
Started Jul 22 06:13:38 PM PDT 24
Finished Jul 22 06:16:43 PM PDT 24
Peak memory 200236 kb
Host smart-75a6d7db-0e0e-4ac3-8dba-9a9f38f196ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634181359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1634181359
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1055472107
Short name T1141
Test name
Test status
Simulation time 7827602628 ps
CPU time 18.41 seconds
Started Jul 22 06:14:11 PM PDT 24
Finished Jul 22 06:14:30 PM PDT 24
Peak memory 199352 kb
Host smart-27e2bf8c-acae-42bc-8cda-f36dfcac1df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055472107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1055472107
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.60515648
Short name T439
Test name
Test status
Simulation time 46404958260 ps
CPU time 19.29 seconds
Started Jul 22 06:13:31 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 200176 kb
Host smart-60cce043-bdf5-4e51-949b-7a54d4247660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60515648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.60515648
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1097749525
Short name T1039
Test name
Test status
Simulation time 3835094406 ps
CPU time 2.56 seconds
Started Jul 22 06:14:11 PM PDT 24
Finished Jul 22 06:14:14 PM PDT 24
Peak memory 196460 kb
Host smart-d7ae8409-91e9-47ee-898d-a13448ff0784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097749525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1097749525
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.496785962
Short name T962
Test name
Test status
Simulation time 465447183 ps
CPU time 1.75 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:13:32 PM PDT 24
Peak memory 198508 kb
Host smart-68333ba1-4a84-4f9b-822f-6025c9f6d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496785962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.496785962
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3046648215
Short name T165
Test name
Test status
Simulation time 221756905331 ps
CPU time 55.4 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:14:26 PM PDT 24
Peak memory 200204 kb
Host smart-1afdd52e-9392-43b7-a13c-635e758015f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046648215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3046648215
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1087498097
Short name T45
Test name
Test status
Simulation time 119738672752 ps
CPU time 1063.42 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:31:14 PM PDT 24
Peak memory 228412 kb
Host smart-119dcb8a-ae65-4f16-af9b-a7269c7b7c40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087498097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1087498097
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.681599601
Short name T655
Test name
Test status
Simulation time 6838202073 ps
CPU time 23.04 seconds
Started Jul 22 06:13:32 PM PDT 24
Finished Jul 22 06:13:55 PM PDT 24
Peak memory 200020 kb
Host smart-18348da0-578a-4b1c-a1a4-1cf1a48e0df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681599601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.681599601
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2027641222
Short name T682
Test name
Test status
Simulation time 28518401738 ps
CPU time 15.32 seconds
Started Jul 22 06:13:28 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 200296 kb
Host smart-e4b0e766-0503-479d-b2e8-d0a0b0b97020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027641222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2027641222
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1020411692
Short name T336
Test name
Test status
Simulation time 14366467 ps
CPU time 0.55 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 195236 kb
Host smart-c549ad0c-7127-4921-94e2-543518a407be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020411692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1020411692
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1993901134
Short name T783
Test name
Test status
Simulation time 18901231289 ps
CPU time 14.76 seconds
Started Jul 22 06:13:29 PM PDT 24
Finished Jul 22 06:13:45 PM PDT 24
Peak memory 200200 kb
Host smart-1e0044cb-4c9a-467d-8256-bd8b3cc6cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993901134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1993901134
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4181233722
Short name T779
Test name
Test status
Simulation time 34274830552 ps
CPU time 49.96 seconds
Started Jul 22 06:13:37 PM PDT 24
Finished Jul 22 06:14:28 PM PDT 24
Peak memory 200136 kb
Host smart-97e96b17-c2c5-4747-bc33-c3361f4948e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181233722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4181233722
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2473436246
Short name T1005
Test name
Test status
Simulation time 8909352858 ps
CPU time 17.38 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:13:48 PM PDT 24
Peak memory 200204 kb
Host smart-388ecfd9-58fb-4a10-b58e-033fc1a101d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473436246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2473436246
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1079995858
Short name T1058
Test name
Test status
Simulation time 22561259369 ps
CPU time 14.3 seconds
Started Jul 22 06:14:07 PM PDT 24
Finished Jul 22 06:14:22 PM PDT 24
Peak memory 200248 kb
Host smart-c46f6fee-924f-4c6c-8700-c8f57c52359e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079995858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1079995858
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.702721367
Short name T500
Test name
Test status
Simulation time 44982397884 ps
CPU time 193.85 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:16:55 PM PDT 24
Peak memory 200236 kb
Host smart-f715ae11-49fc-4bf2-b6a9-edc73322caab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702721367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.702721367
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3386906969
Short name T857
Test name
Test status
Simulation time 876853668 ps
CPU time 0.91 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 196488 kb
Host smart-b91702bf-98a4-4b30-ac28-8f033f1d5e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386906969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3386906969
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3672898449
Short name T969
Test name
Test status
Simulation time 84391677995 ps
CPU time 33.1 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:14:14 PM PDT 24
Peak memory 200284 kb
Host smart-861a738b-d904-4410-8f2a-4f13b9319fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672898449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3672898449
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.497873335
Short name T581
Test name
Test status
Simulation time 4419418123 ps
CPU time 57.62 seconds
Started Jul 22 06:13:42 PM PDT 24
Finished Jul 22 06:14:40 PM PDT 24
Peak memory 200240 kb
Host smart-64167d09-473a-4c6f-8a42-a017efc7d267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497873335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.497873335
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.267845159
Short name T824
Test name
Test status
Simulation time 3757697121 ps
CPU time 27.91 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:14:07 PM PDT 24
Peak memory 198320 kb
Host smart-adcbe23c-c249-495f-bf7b-a2994b3752f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267845159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.267845159
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3738952235
Short name T138
Test name
Test status
Simulation time 95608176607 ps
CPU time 41.34 seconds
Started Jul 22 06:13:42 PM PDT 24
Finished Jul 22 06:14:24 PM PDT 24
Peak memory 200200 kb
Host smart-99810503-2cb7-40a1-b5a8-d5cff5675a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738952235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3738952235
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.293472549
Short name T1174
Test name
Test status
Simulation time 2295999207 ps
CPU time 2.25 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 195760 kb
Host smart-679df124-763e-461b-a9e5-4611853a8bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293472549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.293472549
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3566767141
Short name T381
Test name
Test status
Simulation time 450007472 ps
CPU time 1.12 seconds
Started Jul 22 06:13:30 PM PDT 24
Finished Jul 22 06:13:32 PM PDT 24
Peak memory 198852 kb
Host smart-66e319da-3b92-4532-a52c-13daf1da92a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566767141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3566767141
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.301598900
Short name T301
Test name
Test status
Simulation time 374367209484 ps
CPU time 242.43 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:17:52 PM PDT 24
Peak memory 208516 kb
Host smart-76bdd1df-b9db-4ae9-b2b2-e237ce68424c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301598900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.301598900
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2128133155
Short name T47
Test name
Test status
Simulation time 32653063836 ps
CPU time 472.62 seconds
Started Jul 22 06:13:43 PM PDT 24
Finished Jul 22 06:21:36 PM PDT 24
Peak memory 212892 kb
Host smart-5e407ef1-448f-4e50-94d9-4e665667507c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128133155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2128133155
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.146725255
Short name T432
Test name
Test status
Simulation time 1136475737 ps
CPU time 4.01 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:13:43 PM PDT 24
Peak memory 199084 kb
Host smart-a924628b-47a4-487e-a2c0-65e31dbba869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146725255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.146725255
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.454811088
Short name T888
Test name
Test status
Simulation time 29818563183 ps
CPU time 5.92 seconds
Started Jul 22 06:13:38 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 199856 kb
Host smart-3ef0e56f-fe1a-43ba-b2c0-c7f32880198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454811088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.454811088
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.439104251
Short name T471
Test name
Test status
Simulation time 11730203 ps
CPU time 0.54 seconds
Started Jul 22 06:13:40 PM PDT 24
Finished Jul 22 06:13:41 PM PDT 24
Peak memory 195912 kb
Host smart-64ce8306-7a1e-4ec4-818b-66dcecceddd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439104251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.439104251
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2534247411
Short name T526
Test name
Test status
Simulation time 26729801510 ps
CPU time 15.14 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:13:57 PM PDT 24
Peak memory 200240 kb
Host smart-53aae5f1-860b-4bbe-bb12-7d825b05b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534247411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2534247411
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2624957199
Short name T117
Test name
Test status
Simulation time 101793665714 ps
CPU time 217.86 seconds
Started Jul 22 06:13:42 PM PDT 24
Finished Jul 22 06:17:21 PM PDT 24
Peak memory 200200 kb
Host smart-919c21b9-a3a0-435a-8003-d5c6f970a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624957199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2624957199
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1196027012
Short name T180
Test name
Test status
Simulation time 15954905451 ps
CPU time 30.86 seconds
Started Jul 22 06:14:01 PM PDT 24
Finished Jul 22 06:14:33 PM PDT 24
Peak memory 200108 kb
Host smart-5e0b55ff-2c08-4c47-a323-33dc9869c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196027012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1196027012
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2502065352
Short name T488
Test name
Test status
Simulation time 24554579330 ps
CPU time 21.62 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:14:04 PM PDT 24
Peak memory 200248 kb
Host smart-121a4a3a-47d1-4bf3-8e64-045faa597560
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502065352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2502065352
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3023625896
Short name T675
Test name
Test status
Simulation time 109540126302 ps
CPU time 369.41 seconds
Started Jul 22 06:13:40 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 200092 kb
Host smart-68b8d993-640e-43a1-ae5f-998cece3e906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023625896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3023625896
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1699220740
Short name T345
Test name
Test status
Simulation time 5218891393 ps
CPU time 9.54 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 199192 kb
Host smart-3c3877c7-b210-4ddb-bf7e-c8a7e7138b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699220740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1699220740
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3521770451
Short name T753
Test name
Test status
Simulation time 386105476678 ps
CPU time 30.85 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:14:13 PM PDT 24
Peak memory 200680 kb
Host smart-0ae653dc-4ee8-4b2c-8fe0-e3a152799ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521770451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3521770451
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1997647589
Short name T1099
Test name
Test status
Simulation time 16255104818 ps
CPU time 992.97 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:30:13 PM PDT 24
Peak memory 200256 kb
Host smart-cb51df32-8bc0-4dc2-96ac-4a705353968b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997647589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1997647589
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.228568087
Short name T530
Test name
Test status
Simulation time 2224867113 ps
CPU time 1.91 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 198324 kb
Host smart-64a87969-8472-42e8-b1d6-aa3c281f16c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228568087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.228568087
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1427674404
Short name T788
Test name
Test status
Simulation time 92478569339 ps
CPU time 76.9 seconds
Started Jul 22 06:13:37 PM PDT 24
Finished Jul 22 06:14:54 PM PDT 24
Peak memory 200224 kb
Host smart-70c75dcc-54b8-4c58-8605-b4660a78d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427674404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1427674404
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2063357023
Short name T597
Test name
Test status
Simulation time 4892729083 ps
CPU time 2.4 seconds
Started Jul 22 06:14:43 PM PDT 24
Finished Jul 22 06:14:46 PM PDT 24
Peak memory 197056 kb
Host smart-0e31867e-6c12-49f8-b14c-c44788b229f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063357023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2063357023
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2447946282
Short name T1007
Test name
Test status
Simulation time 481007152 ps
CPU time 1.32 seconds
Started Jul 22 06:13:40 PM PDT 24
Finished Jul 22 06:13:42 PM PDT 24
Peak memory 198840 kb
Host smart-633c372f-9b5e-4711-93d1-8a5ac6a1ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447946282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2447946282
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2057510304
Short name T1152
Test name
Test status
Simulation time 357416038928 ps
CPU time 231.29 seconds
Started Jul 22 06:13:50 PM PDT 24
Finished Jul 22 06:17:42 PM PDT 24
Peak memory 208536 kb
Host smart-04506e10-24cf-4127-b98e-3d49377b1596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057510304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2057510304
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2103585433
Short name T743
Test name
Test status
Simulation time 111096450363 ps
CPU time 371.26 seconds
Started Jul 22 06:13:41 PM PDT 24
Finished Jul 22 06:19:53 PM PDT 24
Peak memory 216748 kb
Host smart-608ce674-374b-4c4f-9028-f2c99f013eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103585433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2103585433
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1456505580
Short name T973
Test name
Test status
Simulation time 9279722569 ps
CPU time 5.7 seconds
Started Jul 22 06:13:39 PM PDT 24
Finished Jul 22 06:13:45 PM PDT 24
Peak memory 200208 kb
Host smart-4929eaab-ef95-4919-bb4e-da5fef05d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456505580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1456505580
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3509195541
Short name T455
Test name
Test status
Simulation time 60425432237 ps
CPU time 20.46 seconds
Started Jul 22 06:13:38 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 200168 kb
Host smart-c6878dea-be20-417d-9b31-a74d874b77bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509195541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3509195541
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1635371950
Short name T92
Test name
Test status
Simulation time 17175423 ps
CPU time 0.55 seconds
Started Jul 22 06:13:45 PM PDT 24
Finished Jul 22 06:13:45 PM PDT 24
Peak memory 195908 kb
Host smart-1598e77b-dd95-4f27-82d8-b8fffb9e14e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635371950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1635371950
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.185283424
Short name T936
Test name
Test status
Simulation time 200055283663 ps
CPU time 633.53 seconds
Started Jul 22 06:13:48 PM PDT 24
Finished Jul 22 06:24:22 PM PDT 24
Peak memory 200132 kb
Host smart-82430553-8bdc-4727-8124-ee6cb0958b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185283424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.185283424
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3927715731
Short name T261
Test name
Test status
Simulation time 106841188273 ps
CPU time 66.6 seconds
Started Jul 22 06:13:51 PM PDT 24
Finished Jul 22 06:14:58 PM PDT 24
Peak memory 200256 kb
Host smart-c861cb94-5d5c-4d2b-8d9f-7cb768cee036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927715731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3927715731
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.3538374403
Short name T400
Test name
Test status
Simulation time 22483662364 ps
CPU time 36.34 seconds
Started Jul 22 06:13:51 PM PDT 24
Finished Jul 22 06:14:28 PM PDT 24
Peak memory 198092 kb
Host smart-5dece2d9-3b7e-4ee8-856d-cda3dcc54ddd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538374403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3538374403
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.558323635
Short name T366
Test name
Test status
Simulation time 152204996148 ps
CPU time 1264.57 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:35:01 PM PDT 24
Peak memory 200200 kb
Host smart-b8ee2cb3-fe44-4bbc-8c18-87ee16adf10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558323635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.558323635
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1533275622
Short name T1084
Test name
Test status
Simulation time 7411393800 ps
CPU time 5.6 seconds
Started Jul 22 06:13:46 PM PDT 24
Finished Jul 22 06:13:52 PM PDT 24
Peak memory 200184 kb
Host smart-474ac483-60ec-4e25-adb3-e353726d1023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533275622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1533275622
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4180571998
Short name T502
Test name
Test status
Simulation time 219258609990 ps
CPU time 120.49 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:15:51 PM PDT 24
Peak memory 200324 kb
Host smart-088a6062-584d-4ceb-9c45-9fd7963df2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180571998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4180571998
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.565952287
Short name T5
Test name
Test status
Simulation time 9180355522 ps
CPU time 447.51 seconds
Started Jul 22 06:15:08 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 200160 kb
Host smart-6b78b302-ed96-42ee-9a4d-b3634a50b0ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565952287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.565952287
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.894577282
Short name T529
Test name
Test status
Simulation time 1193731704 ps
CPU time 1.04 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 195828 kb
Host smart-c2f6b19b-bf31-4b70-9eac-2df369409209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894577282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.894577282
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2723253417
Short name T41
Test name
Test status
Simulation time 230929655754 ps
CPU time 396.38 seconds
Started Jul 22 06:13:48 PM PDT 24
Finished Jul 22 06:20:24 PM PDT 24
Peak memory 200196 kb
Host smart-c420a22c-d581-42a0-87b4-91b9e1045684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723253417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2723253417
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1754642766
Short name T1133
Test name
Test status
Simulation time 3016306800 ps
CPU time 1.43 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:14:00 PM PDT 24
Peak memory 196164 kb
Host smart-9b55112a-bcd0-42a8-bbb7-ecfc9e27c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754642766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1754642766
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.437879549
Short name T1147
Test name
Test status
Simulation time 6333597034 ps
CPU time 13.03 seconds
Started Jul 22 06:13:42 PM PDT 24
Finished Jul 22 06:13:55 PM PDT 24
Peak memory 200208 kb
Host smart-df03fa5b-e8b2-47af-9031-97e475e8ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437879549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.437879549
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3055048813
Short name T879
Test name
Test status
Simulation time 239484797427 ps
CPU time 308.03 seconds
Started Jul 22 06:13:48 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 200240 kb
Host smart-2d993ce4-3bd0-4f25-be05-3f773644b5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055048813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3055048813
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2161659731
Short name T653
Test name
Test status
Simulation time 121624906201 ps
CPU time 382.37 seconds
Started Jul 22 06:13:55 PM PDT 24
Finished Jul 22 06:20:18 PM PDT 24
Peak memory 216664 kb
Host smart-6a3df5da-f8c7-4bd5-ad50-d0ed093de45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161659731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2161659731
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1068857989
Short name T625
Test name
Test status
Simulation time 2432417060 ps
CPU time 2.32 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:13:52 PM PDT 24
Peak memory 198956 kb
Host smart-70342535-0e1c-4c12-aa53-4c1edc7889de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068857989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1068857989
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1975896243
Short name T370
Test name
Test status
Simulation time 143435337103 ps
CPU time 36.99 seconds
Started Jul 22 06:13:47 PM PDT 24
Finished Jul 22 06:14:24 PM PDT 24
Peak memory 200448 kb
Host smart-1584ad6a-d967-412c-a07b-39b3c0e585f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975896243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1975896243
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1138117826
Short name T520
Test name
Test status
Simulation time 45866825 ps
CPU time 0.55 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:14:01 PM PDT 24
Peak memory 195624 kb
Host smart-44edc4ef-e065-4e28-b608-4fa44c6d03ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138117826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1138117826
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1403424001
Short name T754
Test name
Test status
Simulation time 149875729056 ps
CPU time 118.99 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:15:48 PM PDT 24
Peak memory 200268 kb
Host smart-bf96ab56-9202-44cf-a5c7-a28a5dd421c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403424001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1403424001
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3803735462
Short name T982
Test name
Test status
Simulation time 97154564276 ps
CPU time 69.29 seconds
Started Jul 22 06:13:50 PM PDT 24
Finished Jul 22 06:15:00 PM PDT 24
Peak memory 200204 kb
Host smart-140f20e9-289d-4d70-9570-28d76ef0874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803735462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3803735462
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.112095490
Short name T95
Test name
Test status
Simulation time 26531836269 ps
CPU time 11.79 seconds
Started Jul 22 06:13:50 PM PDT 24
Finished Jul 22 06:14:03 PM PDT 24
Peak memory 200164 kb
Host smart-9e52d807-0827-45ee-bbde-df6792653ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112095490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.112095490
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.803990308
Short name T652
Test name
Test status
Simulation time 49657550868 ps
CPU time 67.81 seconds
Started Jul 22 06:13:48 PM PDT 24
Finished Jul 22 06:14:57 PM PDT 24
Peak memory 200200 kb
Host smart-e5f4bebe-3fa9-4830-a9c7-9e678fc2e9c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803990308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.803990308
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1185812929
Short name T563
Test name
Test status
Simulation time 116263031718 ps
CPU time 188.32 seconds
Started Jul 22 06:14:28 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 200112 kb
Host smart-cd7f0e88-7b3d-43eb-9ef6-27cf4eaca069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185812929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1185812929
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4293852485
Short name T638
Test name
Test status
Simulation time 10741227330 ps
CPU time 7.32 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:13:57 PM PDT 24
Peak memory 199692 kb
Host smart-45caaa57-d08a-44d9-8ba3-1a5379ddc035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293852485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4293852485
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2694752939
Short name T113
Test name
Test status
Simulation time 116220864348 ps
CPU time 49.59 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:14:40 PM PDT 24
Peak memory 200396 kb
Host smart-65609be1-165f-4c5c-8e00-016734a793ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694752939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2694752939
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1467962284
Short name T1160
Test name
Test status
Simulation time 18282999016 ps
CPU time 365.31 seconds
Started Jul 22 06:13:49 PM PDT 24
Finished Jul 22 06:19:55 PM PDT 24
Peak memory 200228 kb
Host smart-da8739a0-c568-454e-a609-300e7046a5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467962284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1467962284
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1643634181
Short name T812
Test name
Test status
Simulation time 5849434634 ps
CPU time 10.83 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 199380 kb
Host smart-1891cc4b-eabb-4701-9b72-0dd9f143123c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643634181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1643634181
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2909871779
Short name T169
Test name
Test status
Simulation time 39882502493 ps
CPU time 24.09 seconds
Started Jul 22 06:14:14 PM PDT 24
Finished Jul 22 06:14:38 PM PDT 24
Peak memory 200244 kb
Host smart-593fcd2e-25b1-4379-88f5-42692632f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909871779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2909871779
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1189101588
Short name T427
Test name
Test status
Simulation time 45113701591 ps
CPU time 15.94 seconds
Started Jul 22 06:14:45 PM PDT 24
Finished Jul 22 06:15:02 PM PDT 24
Peak memory 196388 kb
Host smart-d9dc4c80-9c55-485c-ab17-ffabf574fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189101588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1189101588
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1819049315
Short name T444
Test name
Test status
Simulation time 292036218 ps
CPU time 1.49 seconds
Started Jul 22 06:14:10 PM PDT 24
Finished Jul 22 06:14:12 PM PDT 24
Peak memory 198996 kb
Host smart-05e0ba39-2c95-4323-8fa0-d309ec19aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819049315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1819049315
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2940889860
Short name T721
Test name
Test status
Simulation time 290704902919 ps
CPU time 152.44 seconds
Started Jul 22 06:14:01 PM PDT 24
Finished Jul 22 06:16:34 PM PDT 24
Peak memory 200244 kb
Host smart-66ede97d-8ce9-43e5-81b4-8161cf1544fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940889860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2940889860
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2749494892
Short name T803
Test name
Test status
Simulation time 1001257067901 ps
CPU time 829.35 seconds
Started Jul 22 06:13:48 PM PDT 24
Finished Jul 22 06:27:38 PM PDT 24
Peak memory 216780 kb
Host smart-55784ec6-f94b-47bf-b976-0d61672e6e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749494892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2749494892
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3664252382
Short name T276
Test name
Test status
Simulation time 492003114 ps
CPU time 1.04 seconds
Started Jul 22 06:13:51 PM PDT 24
Finished Jul 22 06:13:53 PM PDT 24
Peak memory 197424 kb
Host smart-b69f73d5-1012-45d4-8650-f2588fd6584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664252382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3664252382
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3126341434
Short name T663
Test name
Test status
Simulation time 104591156214 ps
CPU time 194.16 seconds
Started Jul 22 06:15:08 PM PDT 24
Finished Jul 22 06:18:23 PM PDT 24
Peak memory 200208 kb
Host smart-60606295-8383-492c-b4b4-5318eb09434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126341434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3126341434
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4210796345
Short name T620
Test name
Test status
Simulation time 35239749 ps
CPU time 0.57 seconds
Started Jul 22 06:13:51 PM PDT 24
Finished Jul 22 06:13:52 PM PDT 24
Peak memory 195876 kb
Host smart-e0d260d3-177b-4f1b-8dfa-7f63f4167d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210796345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4210796345
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.499572248
Short name T678
Test name
Test status
Simulation time 75177333984 ps
CPU time 107.44 seconds
Started Jul 22 06:11:23 PM PDT 24
Finished Jul 22 06:13:11 PM PDT 24
Peak memory 200288 kb
Host smart-1c132545-e8e8-4a6f-95e3-705c9178686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499572248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.499572248
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1658107144
Short name T256
Test name
Test status
Simulation time 37626135958 ps
CPU time 66.25 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:12:35 PM PDT 24
Peak memory 200240 kb
Host smart-540004ae-b561-49bf-8565-e87f093b77f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658107144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1658107144
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3565928660
Short name T1034
Test name
Test status
Simulation time 214372909940 ps
CPU time 108.11 seconds
Started Jul 22 06:11:30 PM PDT 24
Finished Jul 22 06:13:18 PM PDT 24
Peak memory 200232 kb
Host smart-f8ca7703-9b30-469f-839f-9508def02682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565928660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3565928660
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2045552912
Short name T701
Test name
Test status
Simulation time 23476855630 ps
CPU time 24.19 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:11:53 PM PDT 24
Peak memory 200084 kb
Host smart-2970d7ff-f4b1-4ba6-8901-cbcfe0b99a5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045552912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2045552912
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1736691498
Short name T242
Test name
Test status
Simulation time 53502262416 ps
CPU time 358.87 seconds
Started Jul 22 06:13:52 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 200244 kb
Host smart-a07e9e11-52e5-4fe5-b289-7d45695f7292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736691498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1736691498
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2866137404
Short name T457
Test name
Test status
Simulation time 12730109843 ps
CPU time 13.26 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 199848 kb
Host smart-50671285-9a2a-423a-8428-cc85b28811eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866137404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2866137404
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.376815811
Short name T35
Test name
Test status
Simulation time 123425857559 ps
CPU time 63.94 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:12:30 PM PDT 24
Peak memory 200404 kb
Host smart-cee9410a-7a6e-49f2-bca9-cd823a4b492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376815811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.376815811
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3385800827
Short name T364
Test name
Test status
Simulation time 11090125673 ps
CPU time 298.1 seconds
Started Jul 22 06:12:43 PM PDT 24
Finished Jul 22 06:17:41 PM PDT 24
Peak memory 200204 kb
Host smart-1b192490-447f-4310-a3f6-44404ee11080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385800827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3385800827
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4156402095
Short name T36
Test name
Test status
Simulation time 4387799006 ps
CPU time 8.86 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:33 PM PDT 24
Peak memory 198336 kb
Host smart-3c2316ea-e3af-4b89-9593-4b93e6c87602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156402095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4156402095
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1563245123
Short name T647
Test name
Test status
Simulation time 99867030589 ps
CPU time 137.64 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 199756 kb
Host smart-5eddfa46-73d5-46e9-af68-d297fe096227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563245123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1563245123
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1270858729
Short name T1046
Test name
Test status
Simulation time 6000678157 ps
CPU time 2.69 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:27 PM PDT 24
Peak memory 196556 kb
Host smart-7c1c5e35-38c1-412c-b045-cf9a0321d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270858729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1270858729
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.672691572
Short name T25
Test name
Test status
Simulation time 130757611 ps
CPU time 0.86 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 218328 kb
Host smart-c037075a-2cca-4351-b4b6-4a64a7194232
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672691572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.672691572
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1777913471
Short name T333
Test name
Test status
Simulation time 332773716 ps
CPU time 0.99 seconds
Started Jul 22 06:11:26 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 198372 kb
Host smart-89ce6a5c-b934-4838-a52c-0c593a29bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777913471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1777913471
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.218620011
Short name T959
Test name
Test status
Simulation time 66243011718 ps
CPU time 1266.52 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:32:35 PM PDT 24
Peak memory 200144 kb
Host smart-b1b255a2-8969-489c-8b07-32a95cecce95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218620011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.218620011
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.260857957
Short name T10
Test name
Test status
Simulation time 55885512551 ps
CPU time 630.94 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:21:56 PM PDT 24
Peak memory 216884 kb
Host smart-bbc51587-525a-4d9e-9402-7a0fd74f7798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260857957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.260857957
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2623973450
Short name T354
Test name
Test status
Simulation time 988339684 ps
CPU time 2.43 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 199364 kb
Host smart-19474ddd-2315-460c-be60-1cf289030a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623973450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2623973450
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2201595582
Short name T324
Test name
Test status
Simulation time 25386343899 ps
CPU time 11.61 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:11:41 PM PDT 24
Peak memory 200184 kb
Host smart-54e2b9d8-bc9a-4667-a31c-8537cf6dc674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201595582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2201595582
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1526271469
Short name T21
Test name
Test status
Simulation time 13392254 ps
CPU time 0.59 seconds
Started Jul 22 06:14:04 PM PDT 24
Finished Jul 22 06:14:05 PM PDT 24
Peak memory 195388 kb
Host smart-48c21ffe-d4f2-4901-b217-f8fdd07f6bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526271469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1526271469
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2552721117
Short name T640
Test name
Test status
Simulation time 43230527563 ps
CPU time 80.63 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:15:20 PM PDT 24
Peak memory 200176 kb
Host smart-78da6f5e-e4d7-4b75-b7c6-55d7e168d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552721117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2552721117
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2737573630
Short name T286
Test name
Test status
Simulation time 196907007568 ps
CPU time 218.1 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:17:38 PM PDT 24
Peak memory 200248 kb
Host smart-7e1638d8-ca40-4b55-9c86-be2e5ea133fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737573630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2737573630
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3778490735
Short name T260
Test name
Test status
Simulation time 109123035448 ps
CPU time 81.3 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:15:20 PM PDT 24
Peak memory 200284 kb
Host smart-5c882001-b399-4bae-b182-aaf02f06a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778490735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3778490735
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.500572519
Short name T535
Test name
Test status
Simulation time 22994522196 ps
CPU time 27.8 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:28 PM PDT 24
Peak memory 199180 kb
Host smart-3b842467-ff02-4e28-a5c0-dc7c749a47d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500572519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.500572519
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1446064115
Short name T940
Test name
Test status
Simulation time 66244727564 ps
CPU time 210.39 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:17:33 PM PDT 24
Peak memory 200236 kb
Host smart-d230e5d5-c944-403f-b49b-ef2a0bc8a6a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446064115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1446064115
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1513608680
Short name T1176
Test name
Test status
Simulation time 1632763419 ps
CPU time 2.07 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:03 PM PDT 24
Peak memory 195916 kb
Host smart-92980110-4fe2-4057-be9c-3a75476e2772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513608680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1513608680
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2234202296
Short name T285
Test name
Test status
Simulation time 37492894059 ps
CPU time 59.59 seconds
Started Jul 22 06:14:47 PM PDT 24
Finished Jul 22 06:15:47 PM PDT 24
Peak memory 200384 kb
Host smart-01591ca5-c39d-44ef-9606-2f390dd361ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234202296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2234202296
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2345437660
Short name T453
Test name
Test status
Simulation time 2706983291 ps
CPU time 112.23 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:15:53 PM PDT 24
Peak memory 200152 kb
Host smart-9311f147-3b21-42b7-900f-f4a8521a68d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345437660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2345437660
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3680300726
Short name T751
Test name
Test status
Simulation time 5070678070 ps
CPU time 11.36 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:12 PM PDT 24
Peak memory 198592 kb
Host smart-b735a268-21bb-46ae-8792-0d2d05667b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680300726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3680300726
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3436251214
Short name T105
Test name
Test status
Simulation time 23161987413 ps
CPU time 16.86 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:23 PM PDT 24
Peak memory 199576 kb
Host smart-b1948c8c-dfd9-4fd8-954b-331f109d8dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436251214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3436251214
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2375615232
Short name T1095
Test name
Test status
Simulation time 5836265525 ps
CPU time 9.82 seconds
Started Jul 22 06:13:56 PM PDT 24
Finished Jul 22 06:14:07 PM PDT 24
Peak memory 196392 kb
Host smart-b76d7714-6357-406c-bf3b-7e65dc78d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375615232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2375615232
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.936743555
Short name T536
Test name
Test status
Simulation time 5817598159 ps
CPU time 8.94 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:09 PM PDT 24
Peak memory 200204 kb
Host smart-043b537b-442b-4cc3-ba03-727a1a24d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936743555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.936743555
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3149052354
Short name T469
Test name
Test status
Simulation time 329727475568 ps
CPU time 438.85 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:21:25 PM PDT 24
Peak memory 200008 kb
Host smart-8fda05aa-393f-4371-98ca-7e5e3802d59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149052354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3149052354
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2481250866
Short name T667
Test name
Test status
Simulation time 282691300588 ps
CPU time 1166.74 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:33:27 PM PDT 24
Peak memory 216720 kb
Host smart-194a022f-6a68-438f-b822-88d000fa257a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481250866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2481250866
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1206634184
Short name T13
Test name
Test status
Simulation time 681960822 ps
CPU time 1.95 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:14:19 PM PDT 24
Peak memory 198568 kb
Host smart-2d1d2303-60f7-4722-bfab-9af945120e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206634184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1206634184
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4128769053
Short name T769
Test name
Test status
Simulation time 219622539015 ps
CPU time 77.63 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:15:18 PM PDT 24
Peak memory 200388 kb
Host smart-8e4e6411-4cb7-4f73-ae9d-93aa50994b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128769053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4128769053
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2261047000
Short name T328
Test name
Test status
Simulation time 33799123 ps
CPU time 0.54 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 195928 kb
Host smart-594fd53b-ddf7-4652-a7c9-d6681b0f9028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261047000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2261047000
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3414401942
Short name T542
Test name
Test status
Simulation time 213756094842 ps
CPU time 239 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 200204 kb
Host smart-95aa034a-d21c-4cce-9d6e-24f97279b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414401942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3414401942
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2934633760
Short name T8
Test name
Test status
Simulation time 352940221876 ps
CPU time 41.44 seconds
Started Jul 22 06:13:58 PM PDT 24
Finished Jul 22 06:14:41 PM PDT 24
Peak memory 200164 kb
Host smart-dc18351f-6c18-4b04-bc53-4d38d0b3afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934633760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2934633760
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.59708797
Short name T467
Test name
Test status
Simulation time 118513094011 ps
CPU time 56.02 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:15:39 PM PDT 24
Peak memory 200112 kb
Host smart-b6b8c1a3-a653-47b5-8215-c328b7ef1ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59708797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.59708797
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.583310956
Short name T586
Test name
Test status
Simulation time 22937918776 ps
CPU time 14.57 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:15 PM PDT 24
Peak memory 200204 kb
Host smart-a7db7b3e-da6c-47e7-bc4c-8c558a26cc52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583310956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.583310956
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4092145772
Short name T870
Test name
Test status
Simulation time 157311831260 ps
CPU time 1310.2 seconds
Started Jul 22 06:13:57 PM PDT 24
Finished Jul 22 06:35:48 PM PDT 24
Peak memory 200180 kb
Host smart-88b94cf8-0d44-4631-a870-0a2ec6f9581d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092145772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4092145772
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3316681026
Short name T356
Test name
Test status
Simulation time 6694675534 ps
CPU time 12.24 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:14:13 PM PDT 24
Peak memory 200116 kb
Host smart-991c6827-0273-419e-9373-bc9690ad586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316681026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3316681026
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3672557637
Short name T910
Test name
Test status
Simulation time 106024405123 ps
CPU time 187.44 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:17:50 PM PDT 24
Peak memory 200144 kb
Host smart-a32f6fda-3c5c-4292-b539-e080f3c28cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672557637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3672557637
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2361757950
Short name T664
Test name
Test status
Simulation time 15665896789 ps
CPU time 217.46 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:17:40 PM PDT 24
Peak memory 200264 kb
Host smart-1f7dd8d7-ca00-444f-84e2-d9d148dde72b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361757950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2361757950
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2401982498
Short name T368
Test name
Test status
Simulation time 3573338744 ps
CPU time 9.82 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:10 PM PDT 24
Peak memory 199156 kb
Host smart-e579d213-f1d8-42fa-a79a-f2918758ad4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401982498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2401982498
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2864726809
Short name T948
Test name
Test status
Simulation time 169285331557 ps
CPU time 160.38 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:16:41 PM PDT 24
Peak memory 200156 kb
Host smart-7442e824-0c38-4e5e-8c2b-1fb4ec1af733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864726809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2864726809
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3889164002
Short name T353
Test name
Test status
Simulation time 41187551117 ps
CPU time 51.92 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:14:53 PM PDT 24
Peak memory 197040 kb
Host smart-a958b502-2a0d-433e-adf0-24139a545860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889164002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3889164002
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3691501529
Short name T371
Test name
Test status
Simulation time 6045059805 ps
CPU time 6.26 seconds
Started Jul 22 06:14:13 PM PDT 24
Finished Jul 22 06:14:20 PM PDT 24
Peak memory 200252 kb
Host smart-c1289e40-7a23-4b3f-931b-03da54c812b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691501529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3691501529
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3708107482
Short name T619
Test name
Test status
Simulation time 152398172258 ps
CPU time 61.34 seconds
Started Jul 22 06:14:01 PM PDT 24
Finished Jul 22 06:15:02 PM PDT 24
Peak memory 200168 kb
Host smart-6e10e50f-e55d-47b5-9738-f6acab4f2e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708107482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3708107482
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1326156339
Short name T1013
Test name
Test status
Simulation time 12630575436 ps
CPU time 23.94 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:14:25 PM PDT 24
Peak memory 199900 kb
Host smart-3e1d257c-5b6e-4655-b4a2-f941bd204cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326156339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1326156339
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.4199301860
Short name T813
Test name
Test status
Simulation time 19497652695 ps
CPU time 14.74 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 197184 kb
Host smart-2f3db895-d6e5-4933-beb5-fc33160a536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199301860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.4199301860
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3567847917
Short name T579
Test name
Test status
Simulation time 18768136 ps
CPU time 0.57 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:10 PM PDT 24
Peak memory 195912 kb
Host smart-63304c88-c5b4-4780-a158-8357a57d5151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567847917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3567847917
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.677679654
Short name T1081
Test name
Test status
Simulation time 66424250248 ps
CPU time 90.02 seconds
Started Jul 22 06:14:00 PM PDT 24
Finished Jul 22 06:15:31 PM PDT 24
Peak memory 200248 kb
Host smart-70ead2d8-672c-42b6-90e3-59271f5e04dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677679654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.677679654
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.953541671
Short name T116
Test name
Test status
Simulation time 73165652416 ps
CPU time 28.48 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:35 PM PDT 24
Peak memory 199892 kb
Host smart-f51d98db-5fff-4c8c-912b-3c40c3c650c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953541671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.953541671
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4247400468
Short name T548
Test name
Test status
Simulation time 97798145731 ps
CPU time 35.27 seconds
Started Jul 22 06:14:02 PM PDT 24
Finished Jul 22 06:14:38 PM PDT 24
Peak memory 200228 kb
Host smart-3213fc7c-b5fc-4d4e-b0ed-8c931b2e6c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247400468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4247400468
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3242750930
Short name T527
Test name
Test status
Simulation time 32665165401 ps
CPU time 51.15 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:56 PM PDT 24
Peak memory 200108 kb
Host smart-3c93c484-8435-4979-9032-1b263c39b2fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242750930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3242750930
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4227044475
Short name T723
Test name
Test status
Simulation time 120708526475 ps
CPU time 635.03 seconds
Started Jul 22 06:14:10 PM PDT 24
Finished Jul 22 06:24:46 PM PDT 24
Peak memory 200100 kb
Host smart-1f84689e-e507-437f-8f87-4ac106b3471b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227044475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4227044475
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3510577609
Short name T792
Test name
Test status
Simulation time 1176948616 ps
CPU time 2.84 seconds
Started Jul 22 06:14:08 PM PDT 24
Finished Jul 22 06:14:11 PM PDT 24
Peak memory 199616 kb
Host smart-4772e481-dfe9-45ee-a8cc-fc745cb19f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510577609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3510577609
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1000098564
Short name T694
Test name
Test status
Simulation time 110185377035 ps
CPU time 60.27 seconds
Started Jul 22 06:14:45 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 199780 kb
Host smart-b6c32fd8-afa2-463f-9850-c2f518940536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000098564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1000098564
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1074822426
Short name T914
Test name
Test status
Simulation time 14180800860 ps
CPU time 780.92 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:27:11 PM PDT 24
Peak memory 200188 kb
Host smart-eabade12-1227-49d8-b39e-68955c1d5448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074822426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1074822426
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1002251018
Short name T839
Test name
Test status
Simulation time 4770209926 ps
CPU time 11.46 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:17 PM PDT 24
Peak memory 198268 kb
Host smart-be64a6d7-187c-4e5d-a061-8b2242c7229d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002251018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1002251018
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.11657390
Short name T718
Test name
Test status
Simulation time 34872820226 ps
CPU time 25.67 seconds
Started Jul 22 06:14:08 PM PDT 24
Finished Jul 22 06:14:34 PM PDT 24
Peak memory 199760 kb
Host smart-fd600947-24fe-4bc7-badf-5cb48e5abeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11657390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.11657390
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2047560271
Short name T272
Test name
Test status
Simulation time 36428956875 ps
CPU time 56.7 seconds
Started Jul 22 06:13:59 PM PDT 24
Finished Jul 22 06:14:57 PM PDT 24
Peak memory 196544 kb
Host smart-f3846407-637b-4442-b710-288542d8e4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047560271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2047560271
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.395311053
Short name T263
Test name
Test status
Simulation time 714754759 ps
CPU time 3.31 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:14:46 PM PDT 24
Peak memory 199068 kb
Host smart-9a87d0e9-f59d-4677-a634-01c7f24a9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395311053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.395311053
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.744854906
Short name T896
Test name
Test status
Simulation time 151594208710 ps
CPU time 71.22 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:16:09 PM PDT 24
Peak memory 200180 kb
Host smart-bfb114ac-1556-4290-af1b-e444c278c2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744854906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.744854906
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.806169990
Short name T952
Test name
Test status
Simulation time 57373652409 ps
CPU time 601.14 seconds
Started Jul 22 06:14:06 PM PDT 24
Finished Jul 22 06:24:08 PM PDT 24
Peak memory 216752 kb
Host smart-8618df6c-64c7-43dc-be5d-49fe4e14328a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806169990 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.806169990
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.843810714
Short name T348
Test name
Test status
Simulation time 8444803768 ps
CPU time 8.55 seconds
Started Jul 22 06:14:14 PM PDT 24
Finished Jul 22 06:14:23 PM PDT 24
Peak memory 199964 kb
Host smart-b5b08adc-a6b7-42bd-af66-df08e24add06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843810714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.843810714
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1161140643
Short name T1158
Test name
Test status
Simulation time 79556620117 ps
CPU time 33.45 seconds
Started Jul 22 06:14:05 PM PDT 24
Finished Jul 22 06:14:39 PM PDT 24
Peak memory 200132 kb
Host smart-072baf40-bb42-4935-801f-58730ff80eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161140643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1161140643
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2628819629
Short name T314
Test name
Test status
Simulation time 41540524 ps
CPU time 0.57 seconds
Started Jul 22 06:15:28 PM PDT 24
Finished Jul 22 06:15:29 PM PDT 24
Peak memory 195168 kb
Host smart-4caa769a-cb30-4390-baf1-aa4c5380a977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628819629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2628819629
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1132650258
Short name T1003
Test name
Test status
Simulation time 62437476998 ps
CPU time 23.85 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:33 PM PDT 24
Peak memory 200184 kb
Host smart-2988813a-577e-4e0b-b457-a6c9d55936ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132650258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1132650258
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.672956215
Short name T1075
Test name
Test status
Simulation time 123533807936 ps
CPU time 122.59 seconds
Started Jul 22 06:14:06 PM PDT 24
Finished Jul 22 06:16:09 PM PDT 24
Peak memory 200148 kb
Host smart-413fdfac-8b67-4512-8c59-299d1e7fc250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672956215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.672956215
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2008207104
Short name T1066
Test name
Test status
Simulation time 162289573793 ps
CPU time 31.81 seconds
Started Jul 22 06:14:06 PM PDT 24
Finished Jul 22 06:14:39 PM PDT 24
Peak memory 200252 kb
Host smart-fa6958bb-218a-4897-9f88-4a9274d020c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008207104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2008207104
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1059632312
Short name T677
Test name
Test status
Simulation time 21921857002 ps
CPU time 3.84 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:14 PM PDT 24
Peak memory 200232 kb
Host smart-35cd5b3e-56ce-4d2c-94be-58862690861f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059632312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1059632312
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4121818314
Short name T777
Test name
Test status
Simulation time 52194052174 ps
CPU time 153.34 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:16:43 PM PDT 24
Peak memory 200236 kb
Host smart-e9cb2746-0564-4467-855b-1a7ebcf76e5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121818314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4121818314
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1326504747
Short name T636
Test name
Test status
Simulation time 697194003 ps
CPU time 0.98 seconds
Started Jul 22 06:14:38 PM PDT 24
Finished Jul 22 06:14:39 PM PDT 24
Peak memory 196376 kb
Host smart-ca300f64-7291-45da-a0e4-389b933020a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326504747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1326504747
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3815742210
Short name T411
Test name
Test status
Simulation time 53483593752 ps
CPU time 20.47 seconds
Started Jul 22 06:14:07 PM PDT 24
Finished Jul 22 06:14:28 PM PDT 24
Peak memory 197904 kb
Host smart-f5ccde69-3fd9-44f9-aecb-16f0842a77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815742210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3815742210
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.641278779
Short name T1136
Test name
Test status
Simulation time 12387914318 ps
CPU time 174.45 seconds
Started Jul 22 06:15:28 PM PDT 24
Finished Jul 22 06:18:23 PM PDT 24
Peak memory 199860 kb
Host smart-c090e1f3-1fba-48af-b175-e41a3c590307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641278779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.641278779
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3435256383
Short name T726
Test name
Test status
Simulation time 3376136078 ps
CPU time 6.48 seconds
Started Jul 22 06:14:08 PM PDT 24
Finished Jul 22 06:14:15 PM PDT 24
Peak memory 198676 kb
Host smart-e2f4ab20-953d-41b6-8095-f87c4d207eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435256383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3435256383
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.942827812
Short name T687
Test name
Test status
Simulation time 7963878507 ps
CPU time 7.08 seconds
Started Jul 22 06:14:06 PM PDT 24
Finished Jul 22 06:14:14 PM PDT 24
Peak memory 200172 kb
Host smart-064c7e76-8c40-4339-afe8-d940c8f69840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942827812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.942827812
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.817225909
Short name T275
Test name
Test status
Simulation time 33962485155 ps
CPU time 29.06 seconds
Started Jul 22 06:14:16 PM PDT 24
Finished Jul 22 06:14:45 PM PDT 24
Peak memory 196320 kb
Host smart-c59164b0-dd5d-426f-b13d-1afc76dcae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817225909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.817225909
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3021467286
Short name T599
Test name
Test status
Simulation time 142296922 ps
CPU time 0.73 seconds
Started Jul 22 06:14:07 PM PDT 24
Finished Jul 22 06:14:09 PM PDT 24
Peak memory 197372 kb
Host smart-5bc6dd1b-2c54-4f6e-b151-66fd8e29f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021467286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3021467286
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3504576198
Short name T357
Test name
Test status
Simulation time 288470789 ps
CPU time 1.42 seconds
Started Jul 22 06:14:14 PM PDT 24
Finished Jul 22 06:14:15 PM PDT 24
Peak memory 198912 kb
Host smart-7b33394a-263e-4d8a-8974-de751db6ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504576198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3504576198
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3626448314
Short name T644
Test name
Test status
Simulation time 49304669208 ps
CPU time 77.27 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:15:27 PM PDT 24
Peak memory 200248 kb
Host smart-104658d6-a651-46dc-8cc8-3b2a72c4ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626448314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3626448314
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1054933816
Short name T709
Test name
Test status
Simulation time 13297628 ps
CPU time 0.55 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:06 PM PDT 24
Peak memory 195644 kb
Host smart-80877007-dac2-4c8b-9d69-3d5e9e2645ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054933816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1054933816
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.453003773
Short name T929
Test name
Test status
Simulation time 79667899095 ps
CPU time 30.47 seconds
Started Jul 22 06:14:10 PM PDT 24
Finished Jul 22 06:14:41 PM PDT 24
Peak memory 200068 kb
Host smart-5cdeb2c3-fd95-4222-9c9a-df61f279468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453003773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.453003773
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2771326190
Short name T107
Test name
Test status
Simulation time 100167067743 ps
CPU time 190.23 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:18:07 PM PDT 24
Peak memory 200256 kb
Host smart-ec26d956-3de3-4120-aac2-1348ed85581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771326190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2771326190
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.190382890
Short name T1128
Test name
Test status
Simulation time 23925577773 ps
CPU time 25.88 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:36 PM PDT 24
Peak memory 200036 kb
Host smart-5b6efaee-ad30-4520-987c-f79da48a505b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190382890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.190382890
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3088427065
Short name T747
Test name
Test status
Simulation time 120646819393 ps
CPU time 338.17 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:20:35 PM PDT 24
Peak memory 200248 kb
Host smart-1adc663f-77f5-4e4f-8752-80cb0f73de0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088427065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3088427065
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1197191636
Short name T744
Test name
Test status
Simulation time 7392774012 ps
CPU time 2.58 seconds
Started Jul 22 06:14:16 PM PDT 24
Finished Jul 22 06:14:19 PM PDT 24
Peak memory 199920 kb
Host smart-b2d6298d-9859-4061-b387-6a078a74efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197191636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1197191636
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2054039814
Short name T702
Test name
Test status
Simulation time 8629707426 ps
CPU time 14.11 seconds
Started Jul 22 06:14:15 PM PDT 24
Finished Jul 22 06:14:30 PM PDT 24
Peak memory 195704 kb
Host smart-8a1f0d02-6e08-4782-9933-aabee39055d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054039814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2054039814
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4292819334
Short name T1098
Test name
Test status
Simulation time 13916553767 ps
CPU time 354.02 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:20:11 PM PDT 24
Peak memory 200152 kb
Host smart-22f6f878-ab28-44b1-83c1-7a2dc961d51e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292819334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4292819334
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2484303602
Short name T388
Test name
Test status
Simulation time 1279091889 ps
CPU time 1.6 seconds
Started Jul 22 06:14:07 PM PDT 24
Finished Jul 22 06:14:09 PM PDT 24
Peak memory 196776 kb
Host smart-0beb2bb1-2897-41df-bb73-48d9c82cf303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484303602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2484303602
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1918042369
Short name T61
Test name
Test status
Simulation time 151696548556 ps
CPU time 51.49 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 200248 kb
Host smart-431c7004-7748-459c-8142-703cd1193135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918042369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1918042369
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.657474212
Short name T321
Test name
Test status
Simulation time 1924737936 ps
CPU time 3.45 seconds
Started Jul 22 06:14:36 PM PDT 24
Finished Jul 22 06:14:40 PM PDT 24
Peak memory 195720 kb
Host smart-00e1562a-9fed-4177-9694-cefba32087fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657474212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.657474212
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2549362007
Short name T343
Test name
Test status
Simulation time 247373245 ps
CPU time 1.37 seconds
Started Jul 22 06:14:09 PM PDT 24
Finished Jul 22 06:14:10 PM PDT 24
Peak memory 198644 kb
Host smart-a60bf6c4-0e45-4fda-a098-d4a7ab3a817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549362007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2549362007
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3333301597
Short name T559
Test name
Test status
Simulation time 358794082796 ps
CPU time 599.29 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:24:17 PM PDT 24
Peak memory 200228 kb
Host smart-92260977-1cd6-47e6-8388-d7650087cd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333301597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3333301597
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.70404099
Short name T504
Test name
Test status
Simulation time 38550179213 ps
CPU time 437.22 seconds
Started Jul 22 06:14:19 PM PDT 24
Finished Jul 22 06:21:37 PM PDT 24
Peak memory 216740 kb
Host smart-d15205fa-a473-477f-b2b0-1be6a7d4d3fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70404099 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.70404099
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1322676628
Short name T373
Test name
Test status
Simulation time 858462599 ps
CPU time 1.72 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:14:21 PM PDT 24
Peak memory 199240 kb
Host smart-d1f502a2-8376-4e67-b025-7b8fa461c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322676628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1322676628
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1102353576
Short name T568
Test name
Test status
Simulation time 12035527867 ps
CPU time 19.27 seconds
Started Jul 22 06:15:28 PM PDT 24
Finished Jul 22 06:15:48 PM PDT 24
Peak memory 199856 kb
Host smart-489c4c57-9b5d-4297-aaf3-bf1271f721d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102353576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1102353576
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1264672462
Short name T900
Test name
Test status
Simulation time 15834415 ps
CPU time 0.56 seconds
Started Jul 22 06:14:39 PM PDT 24
Finished Jul 22 06:14:40 PM PDT 24
Peak memory 195640 kb
Host smart-0f4f1d90-dae1-4b7d-97ac-c169dc06757a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264672462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1264672462
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3919413942
Short name T1062
Test name
Test status
Simulation time 204456194009 ps
CPU time 38.86 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:14:57 PM PDT 24
Peak memory 200184 kb
Host smart-dc348746-15e4-4d54-bca9-b7ae313dcb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919413942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3919413942
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3689996256
Short name T123
Test name
Test status
Simulation time 138008660012 ps
CPU time 94.39 seconds
Started Jul 22 06:14:23 PM PDT 24
Finished Jul 22 06:15:58 PM PDT 24
Peak memory 200140 kb
Host smart-2afb9848-6d37-4b86-8444-7fe92ad336c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689996256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3689996256
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1183901805
Short name T735
Test name
Test status
Simulation time 39180746044 ps
CPU time 15.14 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:14:33 PM PDT 24
Peak memory 200196 kb
Host smart-19c6b646-a70a-4ec8-b6a5-12b787d11b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183901805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1183901805
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.788262402
Short name T1123
Test name
Test status
Simulation time 27637362221 ps
CPU time 69.28 seconds
Started Jul 22 06:15:26 PM PDT 24
Finished Jul 22 06:16:35 PM PDT 24
Peak memory 200268 kb
Host smart-6ecbee9f-f324-4ad3-a2fe-43aa51b1b81d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788262402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.788262402
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3112508570
Short name T631
Test name
Test status
Simulation time 146016616393 ps
CPU time 442.68 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:21:41 PM PDT 24
Peak memory 200248 kb
Host smart-bd5d8bf2-3334-48c9-b3c3-e1585a113856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112508570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3112508570
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.604466309
Short name T443
Test name
Test status
Simulation time 1172415218 ps
CPU time 1.19 seconds
Started Jul 22 06:14:19 PM PDT 24
Finished Jul 22 06:14:21 PM PDT 24
Peak memory 197124 kb
Host smart-d0050221-c20f-4798-9e77-d375ef318ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604466309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.604466309
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2857369924
Short name T305
Test name
Test status
Simulation time 71260796997 ps
CPU time 164.94 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:17:42 PM PDT 24
Peak memory 199364 kb
Host smart-4d155643-a69d-48a7-912f-9b5987519291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857369924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2857369924
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3681284389
Short name T1168
Test name
Test status
Simulation time 15848489562 ps
CPU time 238.15 seconds
Started Jul 22 06:15:09 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 200268 kb
Host smart-ef80c32a-1eca-411b-b14d-0510ecca7824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681284389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3681284389
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3150075538
Short name T425
Test name
Test status
Simulation time 2124591310 ps
CPU time 3.49 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:14:22 PM PDT 24
Peak memory 198116 kb
Host smart-3c312444-5b64-4dbb-8c85-32f3411d89e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150075538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3150075538
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3682544922
Short name T131
Test name
Test status
Simulation time 32183677912 ps
CPU time 59.4 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200176 kb
Host smart-cdd5c6e6-e500-4590-ba69-5786ee24adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682544922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3682544922
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3424696212
Short name T415
Test name
Test status
Simulation time 2927277911 ps
CPU time 1.82 seconds
Started Jul 22 06:15:26 PM PDT 24
Finished Jul 22 06:15:28 PM PDT 24
Peak memory 196316 kb
Host smart-a96e571c-0e91-4abf-a6dd-851c1f5c964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424696212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3424696212
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3025397147
Short name T853
Test name
Test status
Simulation time 647682591 ps
CPU time 2.67 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:14:20 PM PDT 24
Peak memory 199032 kb
Host smart-0aa99975-6917-4cd4-bdb4-3daff5c7aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025397147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3025397147
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2520251398
Short name T1049
Test name
Test status
Simulation time 129683240505 ps
CPU time 38.27 seconds
Started Jul 22 06:14:17 PM PDT 24
Finished Jul 22 06:14:55 PM PDT 24
Peak memory 200208 kb
Host smart-96895be5-b506-4d6e-8e92-052bf4ff9db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520251398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2520251398
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1616357051
Short name T532
Test name
Test status
Simulation time 121624803529 ps
CPU time 655.61 seconds
Started Jul 22 06:14:18 PM PDT 24
Finished Jul 22 06:25:14 PM PDT 24
Peak memory 216888 kb
Host smart-69cd0083-c328-4491-addf-a9a89ecba648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616357051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1616357051
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2967561924
Short name T1009
Test name
Test status
Simulation time 6454336490 ps
CPU time 7.08 seconds
Started Jul 22 06:14:24 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 200064 kb
Host smart-82089878-60e8-4f8b-bf12-aca9535228ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967561924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2967561924
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3794892153
Short name T369
Test name
Test status
Simulation time 80377182323 ps
CPU time 110.03 seconds
Started Jul 22 06:14:16 PM PDT 24
Finished Jul 22 06:16:07 PM PDT 24
Peak memory 200236 kb
Host smart-50201d5e-8b03-4b0c-865e-fe7b70a503f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794892153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3794892153
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.81991392
Short name T478
Test name
Test status
Simulation time 39246585 ps
CPU time 0.55 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:14:55 PM PDT 24
Peak memory 195904 kb
Host smart-5a7c8c27-5385-423e-b61a-574272e71376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81991392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.81991392
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2134099011
Short name T102
Test name
Test status
Simulation time 50061112688 ps
CPU time 77.29 seconds
Started Jul 22 06:14:28 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 200200 kb
Host smart-9bc97f69-9eac-4427-b518-8ad7c766d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134099011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2134099011
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.238555311
Short name T567
Test name
Test status
Simulation time 34278084791 ps
CPU time 54.87 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:15:24 PM PDT 24
Peak memory 200256 kb
Host smart-cbf8c850-4684-4aad-b4d1-68199fed273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238555311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.238555311
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3530986082
Short name T121
Test name
Test status
Simulation time 101960374784 ps
CPU time 165.15 seconds
Started Jul 22 06:14:27 PM PDT 24
Finished Jul 22 06:17:13 PM PDT 24
Peak memory 200284 kb
Host smart-5118087f-8e38-46d0-87d7-aa308c2b1a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530986082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3530986082
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.984412271
Short name T1057
Test name
Test status
Simulation time 241644098236 ps
CPU time 226.61 seconds
Started Jul 22 06:14:28 PM PDT 24
Finished Jul 22 06:18:15 PM PDT 24
Peak memory 200240 kb
Host smart-b9f260a8-fcf1-42d6-85b8-9044920d374d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984412271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.984412271
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1600046126
Short name T1071
Test name
Test status
Simulation time 62268367604 ps
CPU time 216.78 seconds
Started Jul 22 06:15:00 PM PDT 24
Finished Jul 22 06:18:37 PM PDT 24
Peak memory 200108 kb
Host smart-3e5e79a3-589b-4aab-a963-74cfe924158d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600046126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1600046126
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3780521590
Short name T990
Test name
Test status
Simulation time 1303273990 ps
CPU time 1.13 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:14:33 PM PDT 24
Peak memory 195912 kb
Host smart-a5987be3-1f6e-4654-a897-3f8e25bd33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780521590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3780521590
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.884251235
Short name T998
Test name
Test status
Simulation time 92116717069 ps
CPU time 82.83 seconds
Started Jul 22 06:14:30 PM PDT 24
Finished Jul 22 06:15:54 PM PDT 24
Peak memory 208328 kb
Host smart-a4213ac4-f773-4e82-b5ad-b72dc6d7d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884251235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.884251235
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.257896672
Short name T1121
Test name
Test status
Simulation time 13192553105 ps
CPU time 727.69 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:26:39 PM PDT 24
Peak memory 200232 kb
Host smart-353bb209-91b3-4b22-8348-2e88fe792fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257896672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.257896672
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1088381697
Short name T406
Test name
Test status
Simulation time 6851799506 ps
CPU time 15.31 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:45 PM PDT 24
Peak memory 198392 kb
Host smart-c6ad902a-9467-47b0-b19a-3ad24b49efa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088381697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1088381697
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3367543854
Short name T994
Test name
Test status
Simulation time 83510898129 ps
CPU time 88.98 seconds
Started Jul 22 06:14:25 PM PDT 24
Finished Jul 22 06:15:55 PM PDT 24
Peak memory 200476 kb
Host smart-45f25549-0ed9-40d2-bf58-7b56e4ee77ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367543854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3367543854
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3302792167
Short name T323
Test name
Test status
Simulation time 4348128792 ps
CPU time 2.43 seconds
Started Jul 22 06:14:27 PM PDT 24
Finished Jul 22 06:14:30 PM PDT 24
Peak memory 196756 kb
Host smart-9531a4bf-6aec-4a28-a761-6e18811dc8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302792167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3302792167
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1112941680
Short name T1050
Test name
Test status
Simulation time 896962576 ps
CPU time 2.88 seconds
Started Jul 22 06:15:35 PM PDT 24
Finished Jul 22 06:15:38 PM PDT 24
Peak memory 199124 kb
Host smart-86b0737a-aea9-49f4-a9aa-e47f9c922086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112941680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1112941680
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2185579250
Short name T489
Test name
Test status
Simulation time 137489734437 ps
CPU time 863.83 seconds
Started Jul 22 06:14:33 PM PDT 24
Finished Jul 22 06:28:57 PM PDT 24
Peak memory 200216 kb
Host smart-a5fb1390-16fb-4f93-a9b2-fe325f845a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185579250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2185579250
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2373007950
Short name T822
Test name
Test status
Simulation time 785609537850 ps
CPU time 642.67 seconds
Started Jul 22 06:14:38 PM PDT 24
Finished Jul 22 06:25:22 PM PDT 24
Peak memory 225032 kb
Host smart-a0e8fceb-1a3e-4025-9286-12e3fff9d571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373007950 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2373007950
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4104278997
Short name T501
Test name
Test status
Simulation time 6465487585 ps
CPU time 15.63 seconds
Started Jul 22 06:14:27 PM PDT 24
Finished Jul 22 06:14:44 PM PDT 24
Peak memory 200248 kb
Host smart-738c2213-d3e5-4c0e-9ffd-30b9ce193f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104278997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4104278997
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1831765433
Short name T1129
Test name
Test status
Simulation time 16853647146 ps
CPU time 12.18 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:14:53 PM PDT 24
Peak memory 198336 kb
Host smart-b5ef2791-b9b7-474a-b062-c54b18f0391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831765433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1831765433
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.767014875
Short name T778
Test name
Test status
Simulation time 11658945 ps
CPU time 0.56 seconds
Started Jul 22 06:14:30 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 195072 kb
Host smart-dde7108f-1fa9-40e9-82d4-3895b2eb5a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767014875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.767014875
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3459288430
Short name T382
Test name
Test status
Simulation time 178646233895 ps
CPU time 142.99 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:16:53 PM PDT 24
Peak memory 200252 kb
Host smart-3eab17a2-1fca-49fa-801c-67b79c21f0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459288430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3459288430
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2134641428
Short name T992
Test name
Test status
Simulation time 186215726403 ps
CPU time 99.79 seconds
Started Jul 22 06:14:30 PM PDT 24
Finished Jul 22 06:16:11 PM PDT 24
Peak memory 200236 kb
Host smart-53b37112-7e75-44ca-809a-89d8b7be4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134641428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2134641428
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1052473361
Short name T591
Test name
Test status
Simulation time 30622371567 ps
CPU time 59.62 seconds
Started Jul 22 06:14:43 PM PDT 24
Finished Jul 22 06:15:43 PM PDT 24
Peak memory 200252 kb
Host smart-5d7eb4dd-d2cf-4751-9251-2de2a16c0838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052473361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1052473361
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2557763800
Short name T876
Test name
Test status
Simulation time 3981840843 ps
CPU time 2.68 seconds
Started Jul 22 06:15:00 PM PDT 24
Finished Jul 22 06:15:03 PM PDT 24
Peak memory 200172 kb
Host smart-4e821bca-ca79-4ede-b582-51d8c7e1ac4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557763800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2557763800
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4132328731
Short name T522
Test name
Test status
Simulation time 178715676632 ps
CPU time 111.25 seconds
Started Jul 22 06:15:09 PM PDT 24
Finished Jul 22 06:17:00 PM PDT 24
Peak memory 200244 kb
Host smart-3cf73041-efae-4538-8d55-d52bc604bf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132328731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4132328731
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1506701997
Short name T570
Test name
Test status
Simulation time 2514866211 ps
CPU time 5.05 seconds
Started Jul 22 06:14:28 PM PDT 24
Finished Jul 22 06:14:34 PM PDT 24
Peak memory 198816 kb
Host smart-f2da6114-eecf-4998-ba88-6d47a3851557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506701997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1506701997
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.4242861907
Short name T624
Test name
Test status
Simulation time 77424031115 ps
CPU time 121.76 seconds
Started Jul 22 06:14:34 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 208480 kb
Host smart-d402ef6e-84cf-4890-8a7a-b430a97319d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242861907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4242861907
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1696294261
Short name T771
Test name
Test status
Simulation time 20122131344 ps
CPU time 218.33 seconds
Started Jul 22 06:14:34 PM PDT 24
Finished Jul 22 06:18:12 PM PDT 24
Peak memory 200236 kb
Host smart-76896cf5-89e9-45e7-bab8-81929872b611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696294261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1696294261
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1302640804
Short name T37
Test name
Test status
Simulation time 5197455284 ps
CPU time 3.71 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:34 PM PDT 24
Peak memory 198560 kb
Host smart-c91abe40-9f0e-4f5f-937a-b57a1f778fd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302640804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1302640804
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1641271854
Short name T695
Test name
Test status
Simulation time 14676538249 ps
CPU time 36.27 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200256 kb
Host smart-279c0091-9186-40cc-8a67-ef0c6ba97dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641271854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1641271854
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.756836827
Short name T334
Test name
Test status
Simulation time 2196705100 ps
CPU time 1.34 seconds
Started Jul 22 06:14:45 PM PDT 24
Finished Jul 22 06:14:46 PM PDT 24
Peak memory 195944 kb
Host smart-f4f27f1b-7182-409b-961f-2a45f310e303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756836827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.756836827
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2511674320
Short name T340
Test name
Test status
Simulation time 302277482 ps
CPU time 1.07 seconds
Started Jul 22 06:14:36 PM PDT 24
Finished Jul 22 06:14:38 PM PDT 24
Peak memory 199260 kb
Host smart-a667b943-39c2-4dca-ad1c-c3607dab081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511674320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2511674320
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.62863065
Short name T590
Test name
Test status
Simulation time 235340350788 ps
CPU time 146.18 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:16:56 PM PDT 24
Peak memory 200172 kb
Host smart-645d4d03-56d8-4e48-90cf-c5038beb0e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62863065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.62863065
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1935659147
Short name T584
Test name
Test status
Simulation time 411028454290 ps
CPU time 677.38 seconds
Started Jul 22 06:14:30 PM PDT 24
Finished Jul 22 06:25:49 PM PDT 24
Peak memory 215376 kb
Host smart-44d08469-0ef6-4fab-924a-d565a9ae5177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935659147 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1935659147
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1381033470
Short name T589
Test name
Test status
Simulation time 1236235767 ps
CPU time 2.57 seconds
Started Jul 22 06:14:32 PM PDT 24
Finished Jul 22 06:14:35 PM PDT 24
Peak memory 200120 kb
Host smart-abcd4273-0d16-4323-abf2-a372dfba64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381033470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1381033470
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4040181805
Short name T1165
Test name
Test status
Simulation time 96419952175 ps
CPU time 69.35 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:15:50 PM PDT 24
Peak memory 200248 kb
Host smart-45303eff-a2e7-4b6c-b62d-b57c7e45cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040181805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4040181805
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2643798662
Short name T1100
Test name
Test status
Simulation time 11686563 ps
CPU time 0.55 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:14:50 PM PDT 24
Peak memory 195876 kb
Host smart-efc0c973-0894-4c39-9fb5-fff48ef291c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643798662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2643798662
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2926259018
Short name T152
Test name
Test status
Simulation time 28125509383 ps
CPU time 25.3 seconds
Started Jul 22 06:14:27 PM PDT 24
Finished Jul 22 06:14:53 PM PDT 24
Peak memory 200192 kb
Host smart-2bf37502-be90-4a60-a6be-6b28d37fd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926259018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2926259018
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1941492655
Short name T810
Test name
Test status
Simulation time 247539532593 ps
CPU time 119.14 seconds
Started Jul 22 06:14:32 PM PDT 24
Finished Jul 22 06:16:32 PM PDT 24
Peak memory 200204 kb
Host smart-f1070fa1-ffcd-4453-8782-05dfc771ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941492655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1941492655
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.577242541
Short name T573
Test name
Test status
Simulation time 10000532594 ps
CPU time 17.33 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:48 PM PDT 24
Peak memory 200168 kb
Host smart-9a6eb353-9648-4ab4-bb4a-ea0dab67b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577242541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.577242541
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2555835848
Short name T986
Test name
Test status
Simulation time 1938080372 ps
CPU time 1.42 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 195780 kb
Host smart-af4b9f27-7837-4d03-be94-342e71b2c922
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555835848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2555835848
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1205094287
Short name T894
Test name
Test status
Simulation time 26573460806 ps
CPU time 198.62 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 200244 kb
Host smart-ce7e38f1-5a63-40c5-aa44-12b4761ab36f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1205094287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1205094287
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.901056792
Short name T1092
Test name
Test status
Simulation time 5843056705 ps
CPU time 5.98 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:14:48 PM PDT 24
Peak memory 199048 kb
Host smart-b38243ee-a490-4861-9e06-f80dfa993068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901056792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.901056792
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.782721616
Short name T1111
Test name
Test status
Simulation time 67351516492 ps
CPU time 30.22 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:15:11 PM PDT 24
Peak memory 200312 kb
Host smart-c8e49eb2-1e06-44d9-9649-016930aae22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782721616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.782721616
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2208318581
Short name T595
Test name
Test status
Simulation time 4521770213 ps
CPU time 222.24 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:18:37 PM PDT 24
Peak memory 200172 kb
Host smart-ee23a4b3-2602-40a6-b669-f40d9fa20d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208318581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2208318581
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3584905089
Short name T604
Test name
Test status
Simulation time 1400446131 ps
CPU time 1.08 seconds
Started Jul 22 06:14:29 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 195916 kb
Host smart-b5f836cb-e623-424f-accc-45fc31791f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584905089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3584905089
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1145161351
Short name T954
Test name
Test status
Simulation time 160140307810 ps
CPU time 110.87 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:16:32 PM PDT 24
Peak memory 200196 kb
Host smart-7c8db907-558e-4318-801f-7496d52a0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145161351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1145161351
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2374450510
Short name T1150
Test name
Test status
Simulation time 48682499195 ps
CPU time 53.33 seconds
Started Jul 22 06:14:27 PM PDT 24
Finished Jul 22 06:15:21 PM PDT 24
Peak memory 196416 kb
Host smart-9d35551d-e101-4295-856f-ece09df0f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374450510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2374450510
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.977682000
Short name T1015
Test name
Test status
Simulation time 6285788146 ps
CPU time 10.6 seconds
Started Jul 22 06:15:26 PM PDT 24
Finished Jul 22 06:15:37 PM PDT 24
Peak memory 200228 kb
Host smart-565fb727-c812-47d6-be9c-8ef22155f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977682000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.977682000
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1102043682
Short name T159
Test name
Test status
Simulation time 152887336110 ps
CPU time 124.99 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 208436 kb
Host smart-c76fbe87-3934-4d6a-ae48-7c3a2006a64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102043682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1102043682
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.399832268
Short name T67
Test name
Test status
Simulation time 473609574928 ps
CPU time 344.66 seconds
Started Jul 22 06:15:34 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 225064 kb
Host smart-52afaa7a-b304-4a94-9291-491f55ccb50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399832268 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.399832268
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3300160463
Short name T434
Test name
Test status
Simulation time 7039879714 ps
CPU time 7.91 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:14:49 PM PDT 24
Peak memory 200180 kb
Host smart-0de26798-a143-4cb3-bf4e-ca9f9fbc3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300160463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3300160463
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2523941219
Short name T1080
Test name
Test status
Simulation time 51124236819 ps
CPU time 59.71 seconds
Started Jul 22 06:14:31 PM PDT 24
Finished Jul 22 06:15:32 PM PDT 24
Peak memory 200272 kb
Host smart-f1028cf9-2dd5-4713-9df9-3639be5ba57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523941219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2523941219
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2623924944
Short name T1017
Test name
Test status
Simulation time 40580808 ps
CPU time 0.55 seconds
Started Jul 22 06:14:39 PM PDT 24
Finished Jul 22 06:14:40 PM PDT 24
Peak memory 195612 kb
Host smart-e33f4685-9b60-4034-97a1-3883d21baa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623924944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2623924944
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4105424015
Short name T868
Test name
Test status
Simulation time 185377784774 ps
CPU time 307.57 seconds
Started Jul 22 06:14:43 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 200192 kb
Host smart-e0392e3f-5073-4ce6-b3b6-fbda45d917c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105424015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4105424015
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2553934572
Short name T164
Test name
Test status
Simulation time 158506038206 ps
CPU time 121.6 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:16:43 PM PDT 24
Peak memory 200196 kb
Host smart-b33e5383-42b4-4284-8e6b-bb1c97efe053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553934572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2553934572
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2585459049
Short name T673
Test name
Test status
Simulation time 79434217651 ps
CPU time 171.44 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:17:33 PM PDT 24
Peak memory 200184 kb
Host smart-c8e06a72-772e-4975-8306-2c24dfb4522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585459049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2585459049
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1757914748
Short name T435
Test name
Test status
Simulation time 61978449418 ps
CPU time 26.07 seconds
Started Jul 22 06:14:43 PM PDT 24
Finished Jul 22 06:15:10 PM PDT 24
Peak memory 200004 kb
Host smart-5aca1937-8c9a-47ef-b8de-957187b3dfbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757914748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1757914748
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.408735429
Short name T483
Test name
Test status
Simulation time 52799376027 ps
CPU time 231.56 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:18:35 PM PDT 24
Peak memory 200220 kb
Host smart-a9776152-034d-440f-81d5-0171f849dd95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408735429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.408735429
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1558138081
Short name T565
Test name
Test status
Simulation time 1770371583 ps
CPU time 3.59 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:14:46 PM PDT 24
Peak memory 195492 kb
Host smart-f6537896-1204-4c01-b6a5-702c9d1f5d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558138081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1558138081
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2754874012
Short name T505
Test name
Test status
Simulation time 132417344030 ps
CPU time 64.01 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:15:47 PM PDT 24
Peak memory 200064 kb
Host smart-a07405f8-1de8-4980-b3d0-bb1ea64cbdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754874012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2754874012
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.4079478895
Short name T278
Test name
Test status
Simulation time 10739228706 ps
CPU time 598.4 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:24:40 PM PDT 24
Peak memory 200144 kb
Host smart-da0915c3-31d5-4cee-bcbc-40dfdcc9717f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079478895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4079478895
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1715712685
Short name T1093
Test name
Test status
Simulation time 2642801092 ps
CPU time 5.16 seconds
Started Jul 22 06:14:44 PM PDT 24
Finished Jul 22 06:14:49 PM PDT 24
Peak memory 199128 kb
Host smart-71ba651e-4d4a-4ab9-af55-d005d4567a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715712685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1715712685
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.869126417
Short name T240
Test name
Test status
Simulation time 102025066323 ps
CPU time 34.91 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200264 kb
Host smart-7d57b442-71d6-479e-8905-00b532530c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869126417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.869126417
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3926779462
Short name T842
Test name
Test status
Simulation time 42606200961 ps
CPU time 16.11 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:14:58 PM PDT 24
Peak memory 196252 kb
Host smart-bbf00b96-0ae7-4419-8dbf-5b81ac6ac167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926779462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3926779462
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3106034200
Short name T279
Test name
Test status
Simulation time 309617964 ps
CPU time 1.06 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:14:43 PM PDT 24
Peak memory 198704 kb
Host smart-581297ef-586a-47ef-b232-b33c9f377f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106034200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3106034200
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3328885656
Short name T993
Test name
Test status
Simulation time 27378513171 ps
CPU time 8.1 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:14:51 PM PDT 24
Peak memory 200160 kb
Host smart-214141c4-10d6-4392-8dfb-9aa65d318563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328885656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3328885656
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1969179850
Short name T576
Test name
Test status
Simulation time 189093835684 ps
CPU time 758.93 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:27:20 PM PDT 24
Peak memory 225016 kb
Host smart-482ca61e-9738-4700-aced-b24cc21e094f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969179850 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1969179850
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3787345177
Short name T1167
Test name
Test status
Simulation time 8537726745 ps
CPU time 10.08 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:14:51 PM PDT 24
Peak memory 199556 kb
Host smart-b229b38a-6ec0-4df0-802e-8f10eb8ab51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787345177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3787345177
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1566420439
Short name T1065
Test name
Test status
Simulation time 109049897819 ps
CPU time 42.97 seconds
Started Jul 22 06:14:41 PM PDT 24
Finished Jul 22 06:15:24 PM PDT 24
Peak memory 200240 kb
Host smart-ce78542f-b997-49e4-bd9d-ed1a1181c302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566420439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1566420439
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2663691961
Short name T1124
Test name
Test status
Simulation time 63234448 ps
CPU time 0.56 seconds
Started Jul 22 06:11:35 PM PDT 24
Finished Jul 22 06:11:36 PM PDT 24
Peak memory 194584 kb
Host smart-89d54f54-9c59-413b-995a-cad6638700ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663691961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2663691961
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.154867334
Short name T150
Test name
Test status
Simulation time 82799582164 ps
CPU time 33.55 seconds
Started Jul 22 06:11:30 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 200256 kb
Host smart-3d1c6e30-d1c6-4fa4-9ae6-0d08bb818a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154867334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.154867334
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.608368206
Short name T466
Test name
Test status
Simulation time 66972294651 ps
CPU time 110.33 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 200136 kb
Host smart-6098fe46-6713-4f0f-b1c6-16126c37e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608368206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.608368206
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2822371196
Short name T200
Test name
Test status
Simulation time 126940863569 ps
CPU time 90.45 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:12:59 PM PDT 24
Peak memory 200176 kb
Host smart-579f6331-63ba-4dfa-bca2-d5b29caa1ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822371196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2822371196
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2278942434
Short name T1
Test name
Test status
Simulation time 292029590562 ps
CPU time 163.08 seconds
Started Jul 22 06:11:35 PM PDT 24
Finished Jul 22 06:14:19 PM PDT 24
Peak memory 200240 kb
Host smart-cf42984c-f9e2-4562-8828-4985ccca88a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278942434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2278942434
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3520210133
Short name T318
Test name
Test status
Simulation time 722651532 ps
CPU time 1.85 seconds
Started Jul 22 06:11:35 PM PDT 24
Finished Jul 22 06:11:38 PM PDT 24
Peak memory 195716 kb
Host smart-0e65fe10-cb77-46a3-929a-f3ddebd0ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520210133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3520210133
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3718871184
Short name T437
Test name
Test status
Simulation time 13144356355 ps
CPU time 22.94 seconds
Started Jul 22 06:11:24 PM PDT 24
Finished Jul 22 06:11:47 PM PDT 24
Peak memory 200392 kb
Host smart-df9d0fe0-bd48-4d49-a122-c27eaf5c8350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718871184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3718871184
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.220459544
Short name T635
Test name
Test status
Simulation time 16765786417 ps
CPU time 240.86 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:15:35 PM PDT 24
Peak memory 200232 kb
Host smart-65668126-3795-4374-a8c0-974571c88de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220459544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.220459544
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1843720390
Short name T1048
Test name
Test status
Simulation time 4587862074 ps
CPU time 16.56 seconds
Started Jul 22 06:11:27 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 199160 kb
Host smart-b89fdbfc-f1e5-431c-8252-4f88cb269a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843720390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1843720390
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.698833625
Short name T1036
Test name
Test status
Simulation time 139167712696 ps
CPU time 25.52 seconds
Started Jul 22 06:11:30 PM PDT 24
Finished Jul 22 06:11:56 PM PDT 24
Peak memory 200212 kb
Host smart-ae2c865a-fe57-4bc9-80b3-af061d7db620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698833625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.698833625
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2190249933
Short name T262
Test name
Test status
Simulation time 1667570437 ps
CPU time 2.61 seconds
Started Jul 22 06:11:25 PM PDT 24
Finished Jul 22 06:11:28 PM PDT 24
Peak memory 195708 kb
Host smart-05754957-e498-4d0a-9da2-429f10fc22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190249933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2190249933
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.842077096
Short name T351
Test name
Test status
Simulation time 705495816 ps
CPU time 2.04 seconds
Started Jul 22 06:13:51 PM PDT 24
Finished Jul 22 06:13:54 PM PDT 24
Peak memory 199008 kb
Host smart-8a67a6f1-78fd-4853-a18e-2d283c7b1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842077096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.842077096
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1076227295
Short name T786
Test name
Test status
Simulation time 728061353240 ps
CPU time 144.81 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:14:02 PM PDT 24
Peak memory 200372 kb
Host smart-98aafea9-a082-4bb3-9092-68cc54a8af88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076227295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1076227295
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.546433103
Short name T1012
Test name
Test status
Simulation time 85016588648 ps
CPU time 193.54 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:14:48 PM PDT 24
Peak memory 208576 kb
Host smart-7d7137f4-a4db-4237-a019-bfda8e9b019d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546433103 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.546433103
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1940215484
Short name T322
Test name
Test status
Simulation time 686050459 ps
CPU time 1.89 seconds
Started Jul 22 06:11:32 PM PDT 24
Finished Jul 22 06:11:34 PM PDT 24
Peak memory 198756 kb
Host smart-490c6535-790e-4b6c-804f-74c55069f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940215484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1940215484
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.770483392
Short name T1070
Test name
Test status
Simulation time 66540758569 ps
CPU time 54.64 seconds
Started Jul 22 06:11:28 PM PDT 24
Finished Jul 22 06:12:23 PM PDT 24
Peak memory 200228 kb
Host smart-9c768a58-d3ac-4b50-9751-6f27c8ed9e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770483392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.770483392
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.612450977
Short name T238
Test name
Test status
Simulation time 164364878421 ps
CPU time 50.01 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:15:30 PM PDT 24
Peak memory 200264 kb
Host smart-323e3764-4186-49fc-9884-15d08cf2c31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612450977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.612450977
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3699671409
Short name T1042
Test name
Test status
Simulation time 114458055255 ps
CPU time 885.76 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:29:26 PM PDT 24
Peak memory 225092 kb
Host smart-00859b59-00d0-44cd-a791-039d5602ec4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699671409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3699671409
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.596585798
Short name T884
Test name
Test status
Simulation time 75397728777 ps
CPU time 42.82 seconds
Started Jul 22 06:14:43 PM PDT 24
Finished Jul 22 06:15:26 PM PDT 24
Peak memory 200208 kb
Host smart-c560a9fd-a691-4941-b5dd-ef1dd19f05d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596585798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.596585798
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.621821457
Short name T64
Test name
Test status
Simulation time 16060394256 ps
CPU time 337.23 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:20:20 PM PDT 24
Peak memory 215732 kb
Host smart-feeb98d4-a664-4688-9915-94e836720189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621821457 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.621821457
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.874220716
Short name T475
Test name
Test status
Simulation time 47203660269 ps
CPU time 72.36 seconds
Started Jul 22 06:14:40 PM PDT 24
Finished Jul 22 06:15:52 PM PDT 24
Peak memory 200084 kb
Host smart-503d9250-56fb-47f4-8168-1f646fcd127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874220716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.874220716
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1231403742
Short name T552
Test name
Test status
Simulation time 91553142029 ps
CPU time 767.11 seconds
Started Jul 22 06:14:44 PM PDT 24
Finished Jul 22 06:27:32 PM PDT 24
Peak memory 224292 kb
Host smart-4d29c407-c93c-4982-8136-461bfd9cfa5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231403742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1231403742
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1066753237
Short name T566
Test name
Test status
Simulation time 162837064910 ps
CPU time 77.29 seconds
Started Jul 22 06:15:43 PM PDT 24
Finished Jul 22 06:17:01 PM PDT 24
Peak memory 200088 kb
Host smart-0d5bae09-292e-426f-89f3-c0ef7930ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066753237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1066753237
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3102711397
Short name T125
Test name
Test status
Simulation time 125482822879 ps
CPU time 193.39 seconds
Started Jul 22 06:14:38 PM PDT 24
Finished Jul 22 06:17:51 PM PDT 24
Peak memory 200212 kb
Host smart-4e235ebb-5560-4aae-adbc-efd8564c22cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102711397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3102711397
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3014062028
Short name T967
Test name
Test status
Simulation time 122265186737 ps
CPU time 49.49 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:15:39 PM PDT 24
Peak memory 200220 kb
Host smart-2e8b2e79-12ed-4901-b7d3-768f3f7d47a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014062028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3014062028
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4161968274
Short name T374
Test name
Test status
Simulation time 47954910849 ps
CPU time 20.91 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:15:04 PM PDT 24
Peak memory 198796 kb
Host smart-556c1ca5-36be-4390-b3d2-e7c9ed90d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161968274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4161968274
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3002242834
Short name T462
Test name
Test status
Simulation time 481613310411 ps
CPU time 758.06 seconds
Started Jul 22 06:14:44 PM PDT 24
Finished Jul 22 06:27:23 PM PDT 24
Peak memory 226200 kb
Host smart-ca294dbd-ad9b-4ebf-bd01-5fd0199acf0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002242834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3002242834
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3570119228
Short name T132
Test name
Test status
Simulation time 281091870066 ps
CPU time 116.77 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:16:46 PM PDT 24
Peak memory 200220 kb
Host smart-ec78a46e-f9a7-4d0a-8db4-82b10762659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570119228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3570119228
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1891537173
Short name T459
Test name
Test status
Simulation time 47155005513 ps
CPU time 116.08 seconds
Started Jul 22 06:14:42 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 212128 kb
Host smart-ff72f7d9-ee45-43cc-a437-f78adc09641b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891537173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1891537173
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3355522333
Short name T569
Test name
Test status
Simulation time 21214311407 ps
CPU time 33.93 seconds
Started Jul 22 06:14:38 PM PDT 24
Finished Jul 22 06:15:13 PM PDT 24
Peak memory 200224 kb
Host smart-9d928c8a-fc16-423a-9dcb-ebbb4bf6286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355522333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3355522333
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2476010890
Short name T399
Test name
Test status
Simulation time 48896703522 ps
CPU time 182.94 seconds
Started Jul 22 06:14:36 PM PDT 24
Finished Jul 22 06:17:39 PM PDT 24
Peak memory 200256 kb
Host smart-c8f2e78c-f8a0-409d-a212-7eef2b0f0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476010890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2476010890
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3054147462
Short name T96
Test name
Test status
Simulation time 68512758707 ps
CPU time 277.38 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 216720 kb
Host smart-23652684-2969-452d-847a-9c84522dd70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054147462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3054147462
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.619989248
Short name T22
Test name
Test status
Simulation time 13534878 ps
CPU time 0.56 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:11:35 PM PDT 24
Peak memory 195628 kb
Host smart-0572b756-2a22-4a6c-9d8e-557829d5a26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619989248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.619989248
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3267029476
Short name T795
Test name
Test status
Simulation time 19554264535 ps
CPU time 27.75 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:12:02 PM PDT 24
Peak memory 200256 kb
Host smart-de46c1af-b8fb-41c4-accc-2c24c24fa183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267029476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3267029476
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2950067413
Short name T560
Test name
Test status
Simulation time 28200043058 ps
CPU time 14.07 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:52 PM PDT 24
Peak memory 200224 kb
Host smart-1c8b86a2-574e-40ae-9f6a-3112df621ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950067413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2950067413
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1604198393
Short name T941
Test name
Test status
Simulation time 31691942419 ps
CPU time 15.97 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 200132 kb
Host smart-de31583b-db96-40e9-a704-0fccbf285e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604198393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1604198393
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3351125747
Short name T372
Test name
Test status
Simulation time 237070284375 ps
CPU time 117.31 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:13:39 PM PDT 24
Peak memory 200144 kb
Host smart-2227e700-a20f-4aa5-9db7-018a3ed01f38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351125747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3351125747
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.738708772
Short name T686
Test name
Test status
Simulation time 139484644097 ps
CPU time 1193.55 seconds
Started Jul 22 06:11:33 PM PDT 24
Finished Jul 22 06:31:27 PM PDT 24
Peak memory 200172 kb
Host smart-afd4092e-956f-4d9a-802e-7115b6bc1483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738708772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.738708772
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2984485481
Short name T414
Test name
Test status
Simulation time 9664297374 ps
CPU time 14.18 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:11:49 PM PDT 24
Peak memory 200248 kb
Host smart-595b3312-7fa1-41f2-a9d8-c0ea8cd0fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984485481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2984485481
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2023201610
Short name T274
Test name
Test status
Simulation time 250584017384 ps
CPU time 64.5 seconds
Started Jul 22 06:11:35 PM PDT 24
Finished Jul 22 06:12:40 PM PDT 24
Peak memory 208208 kb
Host smart-d0514600-9f38-45b0-b51b-45714be772a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023201610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2023201610
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2439653161
Short name T972
Test name
Test status
Simulation time 33068312839 ps
CPU time 409.88 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:18:31 PM PDT 24
Peak memory 200200 kb
Host smart-2ef7db95-bea2-42bb-856e-e8ca8abec7df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439653161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2439653161
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2861510551
Short name T14
Test name
Test status
Simulation time 4074101259 ps
CPU time 2.81 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:11:37 PM PDT 24
Peak memory 198560 kb
Host smart-5875a5b6-2f14-443a-896b-0421831d42dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861510551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2861510551
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2692067921
Short name T763
Test name
Test status
Simulation time 2492921854 ps
CPU time 2.44 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:41 PM PDT 24
Peak memory 196752 kb
Host smart-d558765d-4f8c-4c44-ae17-0ebf30a86846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692067921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2692067921
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4118992581
Short name T989
Test name
Test status
Simulation time 6254830842 ps
CPU time 9.96 seconds
Started Jul 22 06:12:43 PM PDT 24
Finished Jul 22 06:12:53 PM PDT 24
Peak memory 200088 kb
Host smart-fec525cf-4288-4017-a56e-5470abf37e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118992581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4118992581
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2323758756
Short name T143
Test name
Test status
Simulation time 528684905195 ps
CPU time 321.78 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:17:01 PM PDT 24
Peak memory 208604 kb
Host smart-bcbbdf90-741d-46d8-9bc1-7b789de0672b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323758756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2323758756
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.945535400
Short name T1060
Test name
Test status
Simulation time 59433938129 ps
CPU time 167.24 seconds
Started Jul 22 06:11:33 PM PDT 24
Finished Jul 22 06:14:21 PM PDT 24
Peak memory 216732 kb
Host smart-1b2c50cf-705e-4052-8d30-752bf70b5eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945535400 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.945535400
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3811834222
Short name T905
Test name
Test status
Simulation time 649842644 ps
CPU time 2.41 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 199844 kb
Host smart-af257550-b977-46e2-bb1b-0f211cfad3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811834222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3811834222
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2591258481
Short name T818
Test name
Test status
Simulation time 34496036472 ps
CPU time 20.5 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:58 PM PDT 24
Peak memory 200196 kb
Host smart-3c1616b0-89f8-4960-a174-867ebedd96d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591258481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2591258481
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3377634397
Short name T139
Test name
Test status
Simulation time 215278954306 ps
CPU time 25.48 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:15:16 PM PDT 24
Peak memory 200016 kb
Host smart-67cee520-b031-4be4-a0ef-422ff3f3e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377634397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3377634397
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1274743886
Short name T1086
Test name
Test status
Simulation time 84396261029 ps
CPU time 612.41 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:25:02 PM PDT 24
Peak memory 216736 kb
Host smart-c076bb11-1876-4fdc-b142-b2b2f9d8eb73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274743886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1274743886
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2653490439
Short name T561
Test name
Test status
Simulation time 36616244260 ps
CPU time 56.54 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:15:47 PM PDT 24
Peak memory 200168 kb
Host smart-841ba04b-6389-4b90-ab11-71d2c090854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653490439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2653490439
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.346696034
Short name T417
Test name
Test status
Simulation time 40839746911 ps
CPU time 354.54 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 215684 kb
Host smart-b891b81d-2ce2-46f4-a4a2-0ce744b788ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346696034 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.346696034
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.62123441
Short name T197
Test name
Test status
Simulation time 11170923762 ps
CPU time 15.48 seconds
Started Jul 22 06:14:47 PM PDT 24
Finished Jul 22 06:15:02 PM PDT 24
Peak memory 199836 kb
Host smart-9d598e5a-fb9b-4c69-a3de-9a67dd486f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62123441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.62123441
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3537684772
Short name T513
Test name
Test status
Simulation time 56104694199 ps
CPU time 482.54 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 216680 kb
Host smart-aa3c896b-9096-46fa-8b1e-dd8ef945cebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537684772 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3537684772
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2225278996
Short name T863
Test name
Test status
Simulation time 38691557161 ps
CPU time 15.25 seconds
Started Jul 22 06:14:47 PM PDT 24
Finished Jul 22 06:15:03 PM PDT 24
Peak memory 200136 kb
Host smart-a2b9eff7-f8b9-45af-95f1-f1a6cfd328f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225278996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2225278996
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2325862649
Short name T891
Test name
Test status
Simulation time 241345664197 ps
CPU time 772.4 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:27:42 PM PDT 24
Peak memory 216888 kb
Host smart-b09891c0-a61b-4118-97d5-8ae3ea283d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325862649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2325862649
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2450166398
Short name T594
Test name
Test status
Simulation time 97594469817 ps
CPU time 98.7 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:16:27 PM PDT 24
Peak memory 200104 kb
Host smart-2a9a7ee3-0792-4cee-878e-bc8a40be3420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450166398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2450166398
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.325887356
Short name T789
Test name
Test status
Simulation time 51724372049 ps
CPU time 491.33 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:23:02 PM PDT 24
Peak memory 216828 kb
Host smart-3571812e-35bb-4d09-a764-cf43a84dc1ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325887356 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.325887356
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2179987673
Short name T768
Test name
Test status
Simulation time 333757459453 ps
CPU time 89.88 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:16:20 PM PDT 24
Peak memory 200172 kb
Host smart-bcba78e8-d85d-4a89-a1d5-a825eac6fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179987673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2179987673
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3390752862
Short name T756
Test name
Test status
Simulation time 67656800887 ps
CPU time 670.96 seconds
Started Jul 22 06:15:24 PM PDT 24
Finished Jul 22 06:26:36 PM PDT 24
Peak memory 216896 kb
Host smart-8a3735e1-6aea-48de-adf9-f623d39633e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390752862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3390752862
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2707381470
Short name T204
Test name
Test status
Simulation time 19998569630 ps
CPU time 16.98 seconds
Started Jul 22 06:14:51 PM PDT 24
Finished Jul 22 06:15:08 PM PDT 24
Peak memory 200236 kb
Host smart-c9d82e02-f8a8-460d-8237-c944d410418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707381470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2707381470
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3861772262
Short name T177
Test name
Test status
Simulation time 113482082591 ps
CPU time 160.6 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:17:29 PM PDT 24
Peak memory 200196 kb
Host smart-ad653182-39a8-4e29-9d39-6450158b9c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861772262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3861772262
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.493717138
Short name T295
Test name
Test status
Simulation time 13435501154 ps
CPU time 135.5 seconds
Started Jul 22 06:14:47 PM PDT 24
Finished Jul 22 06:17:02 PM PDT 24
Peak memory 209844 kb
Host smart-9d229576-223e-4231-8376-c88d4269aa49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493717138 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.493717138
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2472347830
Short name T859
Test name
Test status
Simulation time 117229599372 ps
CPU time 217.66 seconds
Started Jul 22 06:15:10 PM PDT 24
Finished Jul 22 06:18:48 PM PDT 24
Peak memory 200196 kb
Host smart-ce404c9c-c737-41c4-b2bb-a312964f1f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472347830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2472347830
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.526971708
Short name T942
Test name
Test status
Simulation time 471829728957 ps
CPU time 1429.34 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:38:39 PM PDT 24
Peak memory 216792 kb
Host smart-46506460-f673-4933-bad7-c6922793d86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526971708 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.526971708
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4099340638
Short name T1006
Test name
Test status
Simulation time 62887082221 ps
CPU time 24.99 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:15:14 PM PDT 24
Peak memory 200200 kb
Host smart-e2d00581-2005-4430-a684-6de5f30499ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099340638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4099340638
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2958337109
Short name T621
Test name
Test status
Simulation time 58624787988 ps
CPU time 101.63 seconds
Started Jul 22 06:14:54 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 215800 kb
Host smart-8addf55f-eb1f-4beb-87eb-29cbd9657187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958337109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2958337109
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2217707069
Short name T987
Test name
Test status
Simulation time 14431996 ps
CPU time 0.55 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:39 PM PDT 24
Peak memory 195580 kb
Host smart-0e553e1f-62db-4e19-b50a-e61beb32128b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217707069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2217707069
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.282277715
Short name T490
Test name
Test status
Simulation time 25709047970 ps
CPU time 39.55 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:12:14 PM PDT 24
Peak memory 200156 kb
Host smart-79b3c2ad-cbdb-44b2-9895-975839e7c493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282277715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.282277715
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2143274805
Short name T1135
Test name
Test status
Simulation time 55004986735 ps
CPU time 43.95 seconds
Started Jul 22 06:11:33 PM PDT 24
Finished Jul 22 06:12:18 PM PDT 24
Peak memory 200172 kb
Host smart-a7909170-2426-4403-9802-d0c5b25f6b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143274805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2143274805
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1020489604
Short name T460
Test name
Test status
Simulation time 42923679773 ps
CPU time 5.55 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 200064 kb
Host smart-824c0437-69f5-426f-b3b9-565cbbb36883
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020489604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1020489604
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3729495181
Short name T1122
Test name
Test status
Simulation time 114491152997 ps
CPU time 543.94 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:20:43 PM PDT 24
Peak memory 200172 kb
Host smart-06a69e58-eb5d-4bc4-aec3-035549460291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729495181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3729495181
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2608381754
Short name T920
Test name
Test status
Simulation time 8090797675 ps
CPU time 15.97 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:11:51 PM PDT 24
Peak memory 200064 kb
Host smart-2d1a674e-39b2-4494-a24a-6d3c1b0ed68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608381754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2608381754
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2752078030
Short name T514
Test name
Test status
Simulation time 211528635969 ps
CPU time 100.3 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:13:19 PM PDT 24
Peak memory 200332 kb
Host smart-e494a55e-1d38-40f6-8029-43e2db7335a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752078030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2752078030
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1615024906
Short name T976
Test name
Test status
Simulation time 5003899827 ps
CPU time 75.98 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 200144 kb
Host smart-9627611a-ea5c-4265-ac2e-484652cfbc2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615024906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1615024906
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1091301914
Short name T429
Test name
Test status
Simulation time 4728640908 ps
CPU time 11.31 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:11:50 PM PDT 24
Peak memory 198392 kb
Host smart-659f34ee-284a-4d91-b88a-58aaa2b663f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091301914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1091301914
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.339998121
Short name T1096
Test name
Test status
Simulation time 69905752912 ps
CPU time 28.91 seconds
Started Jul 22 06:11:34 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 200232 kb
Host smart-fa3ec802-087b-4cd7-af97-33f497b8bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339998121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.339998121
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.403678382
Short name T1175
Test name
Test status
Simulation time 1955652110 ps
CPU time 1.4 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:39 PM PDT 24
Peak memory 195652 kb
Host smart-3e11c8fb-f8ec-456f-8d96-4936dd71f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403678382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.403678382
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1852764991
Short name T785
Test name
Test status
Simulation time 127131127 ps
CPU time 0.93 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:40 PM PDT 24
Peak memory 197984 kb
Host smart-e1cfbbd5-fd16-4d16-a7a9-e62ba03b6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852764991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1852764991
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3594486402
Short name T264
Test name
Test status
Simulation time 240351888043 ps
CPU time 296.79 seconds
Started Jul 22 06:11:33 PM PDT 24
Finished Jul 22 06:16:31 PM PDT 24
Peak memory 200180 kb
Host smart-1a1ffea1-4000-4c71-9e13-bba93b4156c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594486402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3594486402
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.745557029
Short name T746
Test name
Test status
Simulation time 96872964799 ps
CPU time 1279.86 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:32:58 PM PDT 24
Peak memory 220176 kb
Host smart-7b02b8f6-b4ff-431b-b0f9-aa10f29ee323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745557029 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.745557029
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.694062245
Short name T649
Test name
Test status
Simulation time 6741916521 ps
CPU time 9.97 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:47 PM PDT 24
Peak memory 199976 kb
Host smart-574eeffc-22ba-4cad-a0b9-43b47940e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694062245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.694062245
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3519429925
Short name T1170
Test name
Test status
Simulation time 42824447462 ps
CPU time 30.53 seconds
Started Jul 22 06:11:29 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 200288 kb
Host smart-f147f714-35a5-49e1-9b36-54444eef5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519429925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3519429925
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3558255105
Short name T482
Test name
Test status
Simulation time 70965443402 ps
CPU time 115.92 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:16:44 PM PDT 24
Peak memory 200216 kb
Host smart-60883cab-ac69-4396-9fa4-dd444b59f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558255105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3558255105
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3252695957
Short name T294
Test name
Test status
Simulation time 407152572980 ps
CPU time 1102.34 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:33:12 PM PDT 24
Peak memory 227648 kb
Host smart-f948591d-4dd3-48c9-a74d-e86912fbb6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252695957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3252695957
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.119162245
Short name T390
Test name
Test status
Simulation time 28287439128 ps
CPU time 28.47 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:15:19 PM PDT 24
Peak memory 199960 kb
Host smart-e2988f11-9071-4ce7-9572-85577b02f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119162245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.119162245
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.494230976
Short name T745
Test name
Test status
Simulation time 85374942022 ps
CPU time 180.92 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 216028 kb
Host smart-0b00b284-710d-4334-a6bb-c4c09e499b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494230976 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.494230976
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.966802823
Short name T472
Test name
Test status
Simulation time 139546917468 ps
CPU time 86.67 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:16:16 PM PDT 24
Peak memory 200124 kb
Host smart-a19b1be5-d402-4aed-a3f1-66007e482251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966802823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.966802823
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.372249327
Short name T386
Test name
Test status
Simulation time 22008613855 ps
CPU time 560.08 seconds
Started Jul 22 06:14:51 PM PDT 24
Finished Jul 22 06:24:11 PM PDT 24
Peak memory 208596 kb
Host smart-b4355141-16a4-4632-9593-27e26086227f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372249327 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.372249327
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1907427873
Short name T734
Test name
Test status
Simulation time 105995740570 ps
CPU time 104.17 seconds
Started Jul 22 06:14:55 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 200176 kb
Host smart-91c4e536-ad79-479d-9bd0-884dd785fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907427873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1907427873
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3151318267
Short name T577
Test name
Test status
Simulation time 58991026264 ps
CPU time 77.28 seconds
Started Jul 22 06:14:49 PM PDT 24
Finished Jul 22 06:16:07 PM PDT 24
Peak memory 200044 kb
Host smart-37a9af38-6acf-4a9f-8479-995ba5b8dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151318267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3151318267
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2941617494
Short name T29
Test name
Test status
Simulation time 7317310794 ps
CPU time 79.54 seconds
Started Jul 22 06:14:48 PM PDT 24
Finished Jul 22 06:16:08 PM PDT 24
Peak memory 216360 kb
Host smart-ab4198f6-52c7-407b-ad9e-fdb43ffcc34c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941617494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2941617494
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.326839879
Short name T939
Test name
Test status
Simulation time 48022471901 ps
CPU time 137.21 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:17:08 PM PDT 24
Peak memory 200244 kb
Host smart-b7988a75-aa50-488b-98c1-297f8910dbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326839879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.326839879
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1421069272
Short name T101
Test name
Test status
Simulation time 509116302964 ps
CPU time 959.32 seconds
Started Jul 22 06:14:50 PM PDT 24
Finished Jul 22 06:30:50 PM PDT 24
Peak memory 225068 kb
Host smart-b8790ae9-cb4e-4fc1-a031-a25b68c968db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421069272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1421069272
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1802574246
Short name T49
Test name
Test status
Simulation time 449630440823 ps
CPU time 558.87 seconds
Started Jul 22 06:14:58 PM PDT 24
Finished Jul 22 06:24:17 PM PDT 24
Peak memory 216728 kb
Host smart-b4e50ee2-8828-4c59-9a2c-e791fb2bdbca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802574246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1802574246
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1734428183
Short name T212
Test name
Test status
Simulation time 12659591356 ps
CPU time 18.59 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:15:18 PM PDT 24
Peak memory 200160 kb
Host smart-63728045-5cd4-44ea-aa2c-e832b99ab52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734428183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1734428183
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2225258652
Short name T917
Test name
Test status
Simulation time 130795729552 ps
CPU time 602.49 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:24:59 PM PDT 24
Peak memory 216936 kb
Host smart-17d32ac4-7452-42a8-a8e4-6b1d42326cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225258652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2225258652
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1694382371
Short name T724
Test name
Test status
Simulation time 249028067933 ps
CPU time 324.26 seconds
Started Jul 22 06:15:02 PM PDT 24
Finished Jul 22 06:20:27 PM PDT 24
Peak memory 200008 kb
Host smart-78d9fcf4-b37e-45c4-9743-82b6c690e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694382371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1694382371
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4096520337
Short name T50
Test name
Test status
Simulation time 81187085417 ps
CPU time 855.74 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:29:19 PM PDT 24
Peak memory 224912 kb
Host smart-c2c9ffa5-e475-4398-aa9e-c20d208588ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096520337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4096520337
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3002348968
Short name T1024
Test name
Test status
Simulation time 48458801432 ps
CPU time 41.07 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:15:37 PM PDT 24
Peak memory 200192 kb
Host smart-582f9d33-9285-44f1-a4e1-2c5373312875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002348968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3002348968
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.905014822
Short name T316
Test name
Test status
Simulation time 12836710 ps
CPU time 0.56 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:37 PM PDT 24
Peak memory 195928 kb
Host smart-1dc63147-62b5-45aa-a0a0-6b27db325200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905014822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.905014822
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3083790953
Short name T446
Test name
Test status
Simulation time 59918660811 ps
CPU time 32.24 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:12:12 PM PDT 24
Peak memory 200244 kb
Host smart-d26b52ef-c6d6-4928-bb7a-e567acaa1a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083790953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3083790953
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3385815438
Short name T181
Test name
Test status
Simulation time 18263573031 ps
CPU time 28.86 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:12:11 PM PDT 24
Peak memory 200124 kb
Host smart-407e1dba-cfc8-491a-909c-23aee59f0e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385815438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3385815438
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2973221420
Short name T393
Test name
Test status
Simulation time 42527596113 ps
CPU time 16.79 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 199328 kb
Host smart-076ff1e9-2d0d-4132-978e-78d8d1ee65b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973221420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2973221420
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1397649715
Short name T1067
Test name
Test status
Simulation time 50424332537 ps
CPU time 131.67 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:13:54 PM PDT 24
Peak memory 200228 kb
Host smart-8e5e4951-f6dc-4a4f-a068-cec9bcd33c88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397649715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1397649715
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4199795854
Short name T309
Test name
Test status
Simulation time 9379172486 ps
CPU time 10.35 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:53 PM PDT 24
Peak memory 199940 kb
Host smart-758c550d-4303-4f6f-afb4-64a3bdbdf26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199795854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4199795854
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2208514389
Short name T611
Test name
Test status
Simulation time 106898752969 ps
CPU time 93.06 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:13:13 PM PDT 24
Peak memory 200296 kb
Host smart-a135b0b5-280c-4ca1-b143-2fb20b48cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208514389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2208514389
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2247163123
Short name T424
Test name
Test status
Simulation time 24014599915 ps
CPU time 544.23 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:20:45 PM PDT 24
Peak memory 200216 kb
Host smart-b9012d9c-3de2-4a58-85f2-5ca27517d7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247163123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2247163123
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3080542273
Short name T347
Test name
Test status
Simulation time 6748964910 ps
CPU time 24.4 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 199420 kb
Host smart-e45aeb53-4de0-47f7-aa80-908901c4aec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080542273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3080542273
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1942748711
Short name T656
Test name
Test status
Simulation time 77302774358 ps
CPU time 116.75 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:13:39 PM PDT 24
Peak memory 200224 kb
Host smart-43e1be08-b8b6-4247-ab2a-b1fbbc4aa861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942748711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1942748711
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1322332373
Short name T1045
Test name
Test status
Simulation time 4217394013 ps
CPU time 1.61 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 196252 kb
Host smart-e7b1bfb5-4e2f-4a9f-821d-afd4a278af8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322332373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1322332373
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1310823722
Short name T805
Test name
Test status
Simulation time 94693234 ps
CPU time 0.76 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:38 PM PDT 24
Peak memory 197320 kb
Host smart-976b00dc-37c5-4d60-8de4-3dc07025c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310823722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1310823722
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3834063847
Short name T163
Test name
Test status
Simulation time 196381874759 ps
CPU time 107.62 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:13:28 PM PDT 24
Peak memory 200232 kb
Host smart-038c9df6-47d2-4fdc-a92b-004954e3c1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834063847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3834063847
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2902997214
Short name T762
Test name
Test status
Simulation time 33691211808 ps
CPU time 699.14 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:23:20 PM PDT 24
Peak memory 214928 kb
Host smart-19e1d34b-7770-40ea-b79c-ac9a3212274e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902997214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2902997214
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1574859155
Short name T685
Test name
Test status
Simulation time 2479875189 ps
CPU time 1.5 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:11:38 PM PDT 24
Peak memory 199052 kb
Host smart-9099bf79-9a45-4883-93eb-fbb5bc34b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574859155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1574859155
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.4095195460
Short name T547
Test name
Test status
Simulation time 103355228375 ps
CPU time 15.85 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 200128 kb
Host smart-70399169-270c-4a85-bfdd-6f1c0383f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095195460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4095195460
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4125719144
Short name T218
Test name
Test status
Simulation time 35969624314 ps
CPU time 17.63 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200208 kb
Host smart-34d8721c-e915-4a2a-ad90-613b3ad8c93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125719144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4125719144
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2400923244
Short name T1082
Test name
Test status
Simulation time 39679556687 ps
CPU time 277.36 seconds
Started Jul 22 06:14:58 PM PDT 24
Finished Jul 22 06:19:36 PM PDT 24
Peak memory 216900 kb
Host smart-d845b213-eef4-4319-8652-a1e5f0f27946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400923244 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2400923244
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.26561374
Short name T797
Test name
Test status
Simulation time 33047196931 ps
CPU time 4.48 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:15:03 PM PDT 24
Peak memory 200112 kb
Host smart-06aa3c83-23dc-45a7-9c66-7892b5ca24e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26561374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.26561374
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2874982139
Short name T833
Test name
Test status
Simulation time 39332643159 ps
CPU time 606.5 seconds
Started Jul 22 06:15:02 PM PDT 24
Finished Jul 22 06:25:09 PM PDT 24
Peak memory 226176 kb
Host smart-e30920cc-6817-4843-b143-ee1d747dd4f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874982139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2874982139
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3447950682
Short name T227
Test name
Test status
Simulation time 92075076634 ps
CPU time 36.83 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:15:44 PM PDT 24
Peak memory 200164 kb
Host smart-f175048d-f8fe-4228-8b7c-2b2f8644fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447950682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3447950682
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3573015302
Short name T1126
Test name
Test status
Simulation time 516459410756 ps
CPU time 915.77 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:30:13 PM PDT 24
Peak memory 225116 kb
Host smart-c7c44c41-c432-4ea8-a185-28f1236b468a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573015302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3573015302
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.698313573
Short name T231
Test name
Test status
Simulation time 73714268795 ps
CPU time 19.92 seconds
Started Jul 22 06:15:00 PM PDT 24
Finished Jul 22 06:15:20 PM PDT 24
Peak memory 200048 kb
Host smart-d189f735-1c63-4d78-9620-0d925a44ed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698313573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.698313573
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3024391646
Short name T846
Test name
Test status
Simulation time 122138408709 ps
CPU time 360.01 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:21:00 PM PDT 24
Peak memory 216720 kb
Host smart-eabb52e5-eccd-410e-a6b7-372efffeb2bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024391646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3024391646
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1314519662
Short name T1078
Test name
Test status
Simulation time 54097017661 ps
CPU time 83.89 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:16:22 PM PDT 24
Peak memory 200408 kb
Host smart-1767b01b-6fcd-4ddd-bef9-c70e3d9aac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314519662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1314519662
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.785336217
Short name T798
Test name
Test status
Simulation time 42443099342 ps
CPU time 377.07 seconds
Started Jul 22 06:15:17 PM PDT 24
Finished Jul 22 06:21:35 PM PDT 24
Peak memory 216900 kb
Host smart-996769b8-8dda-4687-8f33-5526eb884dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785336217 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.785336217
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.952158401
Short name T171
Test name
Test status
Simulation time 50106895638 ps
CPU time 40.13 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:15:43 PM PDT 24
Peak memory 199944 kb
Host smart-cea26737-8d43-45ce-a32f-1060803f84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952158401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.952158401
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2604570444
Short name T1115
Test name
Test status
Simulation time 12096856963 ps
CPU time 114.52 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:16:51 PM PDT 24
Peak memory 216764 kb
Host smart-9ce90fb6-25ed-48ab-ba62-8b9d721dcaff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604570444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2604570444
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1003110317
Short name T208
Test name
Test status
Simulation time 137901649746 ps
CPU time 50.08 seconds
Started Jul 22 06:14:59 PM PDT 24
Finished Jul 22 06:15:49 PM PDT 24
Peak memory 199948 kb
Host smart-c4e94df0-6e01-4b3f-b57a-7f8f80b0e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003110317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1003110317
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1740443171
Short name T711
Test name
Test status
Simulation time 33157159864 ps
CPU time 52.91 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:15:56 PM PDT 24
Peak memory 200084 kb
Host smart-872fb3bc-6143-4cd5-a903-04ecda7579ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740443171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1740443171
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1670039434
Short name T27
Test name
Test status
Simulation time 31994070256 ps
CPU time 256.51 seconds
Started Jul 22 06:14:56 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 212804 kb
Host smart-3d94f54d-6ac1-4ee9-a1fb-1e5153b009c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670039434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1670039434
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3064588616
Short name T633
Test name
Test status
Simulation time 71860400093 ps
CPU time 101.54 seconds
Started Jul 22 06:14:58 PM PDT 24
Finished Jul 22 06:16:40 PM PDT 24
Peak memory 200236 kb
Host smart-7e3c0545-d76e-49a7-93b7-ba6313352620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064588616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3064588616
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1281034983
Short name T299
Test name
Test status
Simulation time 160989558987 ps
CPU time 1676.45 seconds
Started Jul 22 06:15:01 PM PDT 24
Finished Jul 22 06:42:58 PM PDT 24
Peak memory 232932 kb
Host smart-18223fbd-05dd-421c-a00f-68435f77926b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281034983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1281034983
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.511644089
Short name T1064
Test name
Test status
Simulation time 121220104320 ps
CPU time 234.35 seconds
Started Jul 22 06:14:58 PM PDT 24
Finished Jul 22 06:18:52 PM PDT 24
Peak memory 200240 kb
Host smart-b2f4108a-82a9-448a-852d-29e3c494ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511644089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.511644089
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2977252129
Short name T856
Test name
Test status
Simulation time 26399375 ps
CPU time 0.54 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 195740 kb
Host smart-2670aa56-c340-4678-bea5-377bff06c7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977252129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2977252129
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2641499910
Short name T575
Test name
Test status
Simulation time 228801321673 ps
CPU time 427.98 seconds
Started Jul 22 06:11:42 PM PDT 24
Finished Jul 22 06:18:52 PM PDT 24
Peak memory 200260 kb
Host smart-db7d8d39-d698-41e3-8e9e-36d9817c83ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641499910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2641499910
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.742157608
Short name T63
Test name
Test status
Simulation time 96898750196 ps
CPU time 91.14 seconds
Started Jul 22 06:12:34 PM PDT 24
Finished Jul 22 06:14:05 PM PDT 24
Peak memory 200108 kb
Host smart-f1bcf943-a6b1-452d-90b0-4f379bc06109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742157608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.742157608
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1512728245
Short name T752
Test name
Test status
Simulation time 18964672370 ps
CPU time 12.63 seconds
Started Jul 22 06:11:43 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 200196 kb
Host smart-a7f52401-d439-4e03-bef1-6d4ffd6f0ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512728245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1512728245
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3633189368
Short name T933
Test name
Test status
Simulation time 27469726588 ps
CPU time 10.1 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:53 PM PDT 24
Peak memory 200028 kb
Host smart-779232b2-bef1-4587-91b7-474da78b6a0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633189368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3633189368
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1008179136
Short name T1162
Test name
Test status
Simulation time 103095036210 ps
CPU time 373.28 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:17:54 PM PDT 24
Peak memory 200064 kb
Host smart-1ed9b3b8-a242-4851-9654-b81d73b429db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008179136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1008179136
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2698035894
Short name T525
Test name
Test status
Simulation time 3174170332 ps
CPU time 2.24 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:11:43 PM PDT 24
Peak memory 199928 kb
Host smart-d77227ee-1b2e-448e-b425-ba27d75a3ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698035894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2698035894
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3122563045
Short name T865
Test name
Test status
Simulation time 189752788731 ps
CPU time 84.64 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:13:08 PM PDT 24
Peak memory 208596 kb
Host smart-aa88bc4a-cc0f-4f1f-9d3a-a8cc7dc7c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122563045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3122563045
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.409987541
Short name T341
Test name
Test status
Simulation time 16122537598 ps
CPU time 203.29 seconds
Started Jul 22 06:11:36 PM PDT 24
Finished Jul 22 06:15:01 PM PDT 24
Peak memory 200268 kb
Host smart-ecc024a7-b422-4312-a5da-4ec84df9202d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409987541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.409987541
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3649510533
Short name T872
Test name
Test status
Simulation time 5462333349 ps
CPU time 44.59 seconds
Started Jul 22 06:11:40 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 199348 kb
Host smart-03f64294-0d06-417b-8166-d1ae1948e33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649510533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3649510533
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.665226421
Short name T796
Test name
Test status
Simulation time 57558252096 ps
CPU time 21.12 seconds
Started Jul 22 06:11:39 PM PDT 24
Finished Jul 22 06:12:02 PM PDT 24
Peak memory 199968 kb
Host smart-c0153833-eaf4-4f8b-94ec-05adc97272c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665226421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.665226421
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.289786109
Short name T558
Test name
Test status
Simulation time 3179896391 ps
CPU time 1.46 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:11:40 PM PDT 24
Peak memory 196556 kb
Host smart-8f934dee-901f-47b0-b7dd-92a022667f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289786109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.289786109
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.209447488
Short name T650
Test name
Test status
Simulation time 304640164 ps
CPU time 1.12 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 198632 kb
Host smart-9f8ea1e2-abf5-4022-b43e-44eaa2731b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209447488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.209447488
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4058463209
Short name T142
Test name
Test status
Simulation time 151583930297 ps
CPU time 1734.4 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:40:33 PM PDT 24
Peak memory 200092 kb
Host smart-4cee745d-785a-48a3-b525-ec9532725c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058463209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4058463209
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2336338000
Short name T98
Test name
Test status
Simulation time 219135719747 ps
CPU time 411.67 seconds
Started Jul 22 06:11:37 PM PDT 24
Finished Jul 22 06:18:30 PM PDT 24
Peak memory 216720 kb
Host smart-7dfe3b98-c467-472c-a159-1f6f9ac81d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336338000 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2336338000
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1265374215
Short name T607
Test name
Test status
Simulation time 8517895616 ps
CPU time 6.85 seconds
Started Jul 22 06:11:38 PM PDT 24
Finished Jul 22 06:11:47 PM PDT 24
Peak memory 199412 kb
Host smart-8c6ad4a0-fb15-431c-a2d5-6e7a4859e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265374215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1265374215
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2623720535
Short name T614
Test name
Test status
Simulation time 69299617618 ps
CPU time 209 seconds
Started Jul 22 06:11:41 PM PDT 24
Finished Jul 22 06:15:11 PM PDT 24
Peak memory 200136 kb
Host smart-96f88104-c262-41bc-9d61-74a3534bb362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623720535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2623720535
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2559745568
Short name T1085
Test name
Test status
Simulation time 141397176189 ps
CPU time 56.51 seconds
Started Jul 22 06:15:01 PM PDT 24
Finished Jul 22 06:15:58 PM PDT 24
Peak memory 200248 kb
Host smart-4cc908d5-80b7-4fb0-900d-797d4853d2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559745568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2559745568
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3058716120
Short name T707
Test name
Test status
Simulation time 38493473860 ps
CPU time 307.28 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:20:05 PM PDT 24
Peak memory 216864 kb
Host smart-a1cb2a0e-0760-49fd-bc37-41efee5821d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058716120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3058716120
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.4068226712
Short name T148
Test name
Test status
Simulation time 66319910943 ps
CPU time 32.07 seconds
Started Jul 22 06:14:57 PM PDT 24
Finished Jul 22 06:15:30 PM PDT 24
Peak memory 200116 kb
Host smart-4ce3752a-11ec-4517-b80e-859b1bb49ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068226712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4068226712
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.346409093
Short name T1131
Test name
Test status
Simulation time 122406376327 ps
CPU time 233.96 seconds
Started Jul 22 06:15:00 PM PDT 24
Finished Jul 22 06:18:54 PM PDT 24
Peak memory 216752 kb
Host smart-c12176ce-6616-430d-9a00-16ff263fa9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346409093 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.346409093
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3934373846
Short name T722
Test name
Test status
Simulation time 92617582424 ps
CPU time 36.51 seconds
Started Jul 22 06:14:58 PM PDT 24
Finished Jul 22 06:15:35 PM PDT 24
Peak memory 200236 kb
Host smart-9362da4d-56a7-4c4a-8af8-5a936b1acddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934373846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3934373846
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2675407026
Short name T219
Test name
Test status
Simulation time 208656281386 ps
CPU time 882.22 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:29:48 PM PDT 24
Peak memory 216900 kb
Host smart-c7f8475b-2dc7-4f93-bd21-03d24132dc0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675407026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2675407026
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2107535185
Short name T583
Test name
Test status
Simulation time 165287097770 ps
CPU time 254.68 seconds
Started Jul 22 06:15:07 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 200260 kb
Host smart-d118b220-73ca-4dee-ae7f-1aeba5197d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107535185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2107535185
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3244589820
Short name T806
Test name
Test status
Simulation time 9541156851 ps
CPU time 86.88 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:16:33 PM PDT 24
Peak memory 215984 kb
Host smart-9c7edfc3-5846-40b5-89a4-a0854ae32503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244589820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3244589820
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.957019286
Short name T729
Test name
Test status
Simulation time 108642522319 ps
CPU time 149.91 seconds
Started Jul 22 06:15:18 PM PDT 24
Finished Jul 22 06:17:48 PM PDT 24
Peak memory 200124 kb
Host smart-e5c302a9-2477-48a3-895f-12c82630fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957019286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.957019286
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2596866939
Short name T293
Test name
Test status
Simulation time 40814721198 ps
CPU time 740.78 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:27:27 PM PDT 24
Peak memory 216880 kb
Host smart-e64f8888-f559-4a4e-a9ca-3317bc326d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596866939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2596866939
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3068705882
Short name T265
Test name
Test status
Simulation time 14740502780 ps
CPU time 13.14 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:15:17 PM PDT 24
Peak memory 200256 kb
Host smart-ff10b3cc-dee6-46a5-a665-61bddee2bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068705882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3068705882
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1661783171
Short name T938
Test name
Test status
Simulation time 46434851358 ps
CPU time 223.45 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:18:50 PM PDT 24
Peak memory 208568 kb
Host smart-7d5b7a2f-5467-4a2e-b0a1-a76ddb509de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661783171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1661783171
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3928234348
Short name T1166
Test name
Test status
Simulation time 283947588778 ps
CPU time 134.66 seconds
Started Jul 22 06:15:04 PM PDT 24
Finished Jul 22 06:17:19 PM PDT 24
Peak memory 200192 kb
Host smart-0c8c4b03-d55a-4439-ac91-4e8b9db8dab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928234348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3928234348
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1008279534
Short name T99
Test name
Test status
Simulation time 42916400624 ps
CPU time 106.93 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:16:53 PM PDT 24
Peak memory 216372 kb
Host smart-d82e08ef-6745-4e08-b9dd-00d5cbd737d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008279534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1008279534
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1236268299
Short name T643
Test name
Test status
Simulation time 52067121175 ps
CPU time 46.44 seconds
Started Jul 22 06:15:06 PM PDT 24
Finished Jul 22 06:15:53 PM PDT 24
Peak memory 200240 kb
Host smart-7c1c06a5-9474-43d7-8278-8e0d324215e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236268299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1236268299
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.749824756
Short name T52
Test name
Test status
Simulation time 44151502636 ps
CPU time 391.21 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:21:37 PM PDT 24
Peak memory 208540 kb
Host smart-c61a564c-b4dc-4e0d-819b-f247035bb6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749824756 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.749824756
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3931979065
Short name T175
Test name
Test status
Simulation time 223637413596 ps
CPU time 34.34 seconds
Started Jul 22 06:15:05 PM PDT 24
Finished Jul 22 06:15:40 PM PDT 24
Peak memory 200264 kb
Host smart-d467d3d4-35b1-4032-b66a-b81d25b97e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931979065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3931979065
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3024581437
Short name T1016
Test name
Test status
Simulation time 15918250653 ps
CPU time 183.87 seconds
Started Jul 22 06:15:03 PM PDT 24
Finished Jul 22 06:18:08 PM PDT 24
Peak memory 215924 kb
Host smart-1d6f7444-8323-4830-b6bc-1e840268db7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024581437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3024581437
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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