Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115754	1			T1	11		T2	2		T3	3
all_values[1]	115754	1			T1	11		T2	2		T3	3
all_values[2]	115754	1			T1	11		T2	2		T3	3
all_values[3]	115754	1			T1	11		T2	2		T3	3
all_values[4]	115754	1			T1	11		T2	2		T3	3
all_values[5]	115754	1			T1	11		T2	2		T3	3
all_values[6]	115754	1			T1	11		T2	2		T3	3
all_values[7]	115754	1			T1	11		T2	2		T3	3
all_values[8]	115754	1			T1	11		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527272

1

T1

34

T2

18

T3

15

auto[1]

514514

1

T1

65

T3

12

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951167

1

T1

79

T2

13

T3

22

auto[1]

90619

1

T1

20

T2

5

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34171	1			T5	1		T6	5		T11	1
all_values[0]	auto[0]	auto[1]	22675	1			T2	2		T4	1		T5	6
all_values[0]	auto[1]	auto[0]	36596	1			T1	2		T3	1		T6	15
all_values[0]	auto[1]	auto[1]	22312	1			T1	9		T3	2		T5	2
all_values[1]	auto[0]	auto[0]	60594	1			T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	1554	1			T5	6		T6	2		T12	4
all_values[1]	auto[1]	auto[0]	51882	1			T1	8		T3	1		T6	64
all_values[1]	auto[1]	auto[1]	1724	1			T6	2		T11	1		T12	11
all_values[2]	auto[0]	auto[0]	52495	1			T2	1		T5	5		T6	75
all_values[2]	auto[0]	auto[1]	2617	1			T2	1		T5	3		T7	1
all_values[2]	auto[1]	auto[0]	58057	1			T1	6		T3	2		T4	1
all_values[2]	auto[1]	auto[1]	2585	1			T1	5		T3	1		T5	1
all_values[3]	auto[0]	auto[0]	59662	1			T2	2		T5	6		T6	98
all_values[3]	auto[0]	auto[1]	330	1			T6	1		T12	1		T40	6
all_values[3]	auto[1]	auto[0]	55447	1			T1	11		T3	3		T4	1
all_values[3]	auto[1]	auto[1]	315	1			T12	1		T13	1		T17	3
all_values[4]	auto[0]	auto[0]	58554	1			T1	8		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	436	1			T6	8		T20	3		T21	2
all_values[4]	auto[1]	auto[0]	56184	1			T1	3		T4	1		T5	3
all_values[4]	auto[1]	auto[1]	580	1			T12	10		T14	4		T17	12
all_values[5]	auto[0]	auto[0]	52584	1			T1	8		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	188	1			T14	1		T20	2		T98	2
all_values[5]	auto[1]	auto[0]	62782	1			T1	3		T4	1		T5	8
all_values[5]	auto[1]	auto[1]	200	1			T20	2		T21	1		T145	3
all_values[6]	auto[0]	auto[0]	59800	1			T1	7		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	171	1			T20	1		T98	1		T30	1
all_values[6]	auto[1]	auto[0]	55582	1			T1	4		T3	2		T5	3
all_values[6]	auto[1]	auto[1]	201	1			T14	2		T20	3		T98	1
all_values[7]	auto[0]	auto[0]	63540	1			T1	7		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	378	1			T11	1		T12	5		T14	1
all_values[7]	auto[1]	auto[0]	51409	1			T1	4		T5	1		T6	109
all_values[7]	auto[1]	auto[1]	427	1			T11	1		T12	6		T17	1
all_values[8]	auto[0]	auto[0]	40326	1			T1	1		T3	1		T6	26
all_values[8]	auto[0]	auto[1]	17197	1			T2	2		T3	2		T4	1
all_values[8]	auto[1]	auto[0]	41502	1			T1	4		T5	1		T6	8
all_values[8]	auto[1]	auto[1]	16729	1			T1	6		T5	2		T6	25