Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2257	1			T1	3		T2	1		T4	15
auto[BaudRate115200]	1981	1			T1	1		T3	1		T6	2
auto[BaudRate230400]	1967	1			T1	3		T5	3		T6	2
auto[BaudRate128Kbps]	2057	1			T2	1		T5	2		T10	1
auto[BaudRate256Kbps]	2162	1			T1	2		T3	3		T5	1
auto[BaudRate1Mbps]	1934	1			T5	4		T7	1		T8	1
auto[BaudRate1p5Mbps]	1425	1			T7	2		T9	1		T10	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1420	1			T35	8		T14	21		T40	10
freqs[25]	1462	1			T5	10		T7	7		T154	10
freqs[48]	748	1			T137	9		T138	9		T360	9
freqs[50]	622	1			T6	4		T10	11		T37	6
freqs[100]	1107	1			T9	2		T41	19		T280	20

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	187	1			T35	1		T14	2		T40	1
auto[BaudRate9600]	freqs[25]	283	1			T7	2		T154	1		T157	2
auto[BaudRate9600]	freqs[48]	122	1			T360	9		T186	1		T205	3
auto[BaudRate9600]	freqs[50]	72	1			T10	1		T37	1		T278	1
auto[BaudRate9600]	freqs[100]	199	1			T41	19		T134	1		T124	1
auto[BaudRate115200]	freqs[24]	197	1			T14	2		T40	1		T152	1
auto[BaudRate115200]	freqs[25]	191	1			T7	1		T154	2		T157	1
auto[BaudRate115200]	freqs[48]	102	1			T138	1		T186	1		T176	1
auto[BaudRate115200]	freqs[50]	94	1			T6	2		T10	3		T37	2
auto[BaudRate115200]	freqs[100]	162	1			T280	5		T155	1		T361	1
auto[BaudRate230400]	freqs[24]	209	1			T35	1		T14	3		T40	3
auto[BaudRate230400]	freqs[25]	207	1			T5	3		T154	2		T157	1
auto[BaudRate230400]	freqs[48]	108	1			T138	2		T186	2		T205	3
auto[BaudRate230400]	freqs[50]	94	1			T6	2		T37	1		T19	9
auto[BaudRate230400]	freqs[100]	130	1			T280	3		T355	1		T134	2
auto[BaudRate128Kbps]	freqs[24]	228	1			T35	2		T14	2		T40	2
auto[BaudRate128Kbps]	freqs[25]	194	1			T5	2		T154	4		T157	1
auto[BaudRate128Kbps]	freqs[48]	100	1			T138	1		T176	1		T42	1
auto[BaudRate128Kbps]	freqs[50]	88	1			T10	1		T278	1		T130	2
auto[BaudRate128Kbps]	freqs[100]	157	1			T280	2		T155	1		T134	2
auto[BaudRate256Kbps]	freqs[24]	227	1			T35	1		T14	1		T152	3
auto[BaudRate256Kbps]	freqs[25]	224	1			T5	1		T7	1		T157	3
auto[BaudRate256Kbps]	freqs[48]	101	1			T137	5		T138	1		T281	5
auto[BaudRate256Kbps]	freqs[50]	82	1			T10	4		T19	9		T278	1
auto[BaudRate256Kbps]	freqs[100]	150	1			T9	1		T280	3		T155	2
auto[BaudRate1Mbps]	freqs[24]	232	1			T35	1		T14	6		T40	2
auto[BaudRate1Mbps]	freqs[25]	254	1			T5	4		T7	1		T154	1
auto[BaudRate1Mbps]	freqs[48]	94	1			T137	2		T138	3		T281	3
auto[BaudRate1Mbps]	freqs[50]	102	1			T37	1		T19	3		T278	1
auto[BaudRate1Mbps]	freqs[100]	154	1			T280	2		T134	1		T135	1
auto[BaudRate1p5Mbps]	freqs[25]	109	1			T7	2		T157	1		T296	1
auto[BaudRate1p5Mbps]	freqs[48]	121	1			T137	2		T138	1		T281	2
auto[BaudRate1p5Mbps]	freqs[50]	90	1			T10	2		T37	1		T19	3
auto[BaudRate1p5Mbps]	freqs[100]	155	1			T9	1		T280	5		T155	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded