Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32600833	1			T1	101		T3	134		T4	1
all_levels[1]	207782	1			T1	1		T3	11		T10	17
all_levels[2]	2676	1			T3	2		T10	7		T11	2
all_levels[3]	1176	1			T3	2		T11	1		T35	1
all_levels[4]	807	1			T1	2		T5	1		T10	1
all_levels[5]	557	1			T7	1		T14	4		T152	5
all_levels[6]	483	1			T5	1		T10	1		T11	2
all_levels[7]	351	1			T5	1		T12	1		T14	2
all_levels[8]	331	1			T12	1		T35	1		T14	1
all_levels[9]	291	1			T1	1		T7	2		T11	1
all_levels[10]	226	1			T1	1		T12	1		T13	1
all_levels[11]	194	1			T12	1		T36	1		T13	4
all_levels[12]	172	1			T1	1		T13	1		T153	1
all_levels[13]	152	1			T12	1		T154	1		T155	1
all_levels[14]	154	1			T5	1		T7	1		T13	1
all_levels[15]	160	1			T12	1		T13	2		T155	1
all_levels[16]	116	1			T5	1		T154	1		T156	4
all_levels[17]	113	1			T7	1		T157	1		T156	1
all_levels[18]	96	1			T5	2		T13	1		T156	1
all_levels[19]	94	1			T11	1		T98	1		T138	1
all_levels[20]	92	1			T154	1		T135	1		T158	1
all_levels[21]	75	1			T36	1		T13	1		T124	1
all_levels[22]	67	1			T159	2		T153	1		T147	1
all_levels[23]	75	1			T11	1		T154	1		T160	1
all_levels[24]	60	1			T36	2		T13	1		T40	1
all_levels[25]	61	1			T98	2		T135	1		T124	1
all_levels[26]	54	1			T40	1		T98	2		T134	2
all_levels[27]	57	1			T8	1		T11	1		T13	1
all_levels[28]	50	1			T98	2		T161	2		T162	1
all_levels[29]	39	1			T98	2		T124	1		T163	1
all_levels[30]	29	1			T98	1		T125	1		T147	2
all_levels[31]	36	1			T143	1		T164	1		T165	1
all_levels[32]	36	1			T162	1		T165	1		T52	1
all_levels[33]	26	1			T166	1		T167	1		T168	1
all_levels[34]	28	1			T5	1		T124	1		T160	1
all_levels[35]	26	1			T98	1		T124	1		T169	1
all_levels[36]	31	1			T162	1		T170	1		T171	2
all_levels[37]	29	1			T130	1		T162	1		T172	1
all_levels[38]	13	1			T173	1		T161	2		T174	1
all_levels[39]	24	1			T98	1		T167	1		T175	1
all_levels[40]	25	1			T40	1		T142	1		T98	1
all_levels[41]	20	1			T36	1		T98	1		T176	1
all_levels[42]	21	1			T36	1		T98	1		T174	1
all_levels[43]	18	1			T139	2		T177	1		T178	1
all_levels[44]	13	1			T179	1		T180	1		T181	1
all_levels[45]	17	1			T5	1		T36	1		T30	1
all_levels[46]	14	1			T142	2		T130	1		T30	1
all_levels[47]	11	1			T182	3		T183	1		T184	1
all_levels[48]	13	1			T11	1		T139	1		T185	1
all_levels[49]	10	1			T7	1		T12	1		T40	1
all_levels[50]	14	1			T11	2		T40	1		T155	2
all_levels[51]	19	1			T186	1		T178	1		T187	2
all_levels[52]	4	1			T164	1		T170	1		T174	1
all_levels[53]	13	1			T5	1		T186	1		T177	1
all_levels[54]	12	1			T188	1		T56	1		T189	2
all_levels[55]	4	1			T55	1		T190	1		T191	1
all_levels[56]	6	1			T192	1		T193	1		T194	2
all_levels[57]	3	1			T174	1		T195	2		-	-
all_levels[58]	12	1			T196	1		T170	1		T42	1
all_levels[59]	14	1			T5	1		T7	1		T36	4
all_levels[60]	2	1			T197	1		T198	1		-	-
all_levels[61]	2	1			T199	1		T62	1		-	-
all_levels[62]	3	1			T164	1		T200	1		T201	1
all_levels[63]	7	1			T202	1		T203	3		T204	2
all_levels[64]	109	1			T40	6		T143	1		T164	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32813049

1

T1

107

T3

149

T5

43

auto[1]

5009

1

T4

1

T6

38

T7

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32596306	1			T1	101		T3	134		T5	32
all_levels[0]	auto[1]	4527	1			T4	1		T6	38		T7	4
all_levels[1]	auto[0]	207726	1			T1	1		T3	11		T10	17
all_levels[1]	auto[1]	56	1			T142	1		T159	2		T170	1
all_levels[2]	auto[0]	2640	1			T3	2		T10	7		T11	2
all_levels[2]	auto[1]	36	1			T156	1		T163	1		T205	1
all_levels[3]	auto[0]	1148	1			T3	2		T11	1		T35	1
all_levels[3]	auto[1]	28	1			T164	2		T206	1		T207	1
all_levels[4]	auto[0]	783	1			T1	2		T5	1		T10	1
all_levels[4]	auto[1]	24	1			T163	1		T206	1		T208	1
all_levels[5]	auto[0]	531	1			T7	1		T14	4		T152	5
all_levels[5]	auto[1]	26	1			T154	1		T165	1		T209	3
all_levels[6]	auto[0]	467	1			T5	1		T10	1		T11	2
all_levels[6]	auto[1]	16	1			T210	1		T211	1		T212	1
all_levels[7]	auto[0]	334	1			T5	1		T12	1		T14	2
all_levels[7]	auto[1]	17	1			T206	1		T208	4		T189	1
all_levels[8]	auto[0]	313	1			T12	1		T35	1		T14	1
all_levels[8]	auto[1]	18	1			T139	4		T213	1		T214	1
all_levels[9]	auto[0]	264	1			T1	1		T7	2		T11	1
all_levels[9]	auto[1]	27	1			T142	1		T166	3		T215	3
all_levels[10]	auto[0]	217	1			T1	1		T12	1		T13	1
all_levels[10]	auto[1]	9	1			T153	1		T216	1		T217	1
all_levels[11]	auto[0]	187	1			T12	1		T36	1		T13	4
all_levels[11]	auto[1]	7	1			T218	1		T219	1		T120	1
all_levels[12]	auto[0]	157	1			T1	1		T13	1		T153	1
all_levels[12]	auto[1]	15	1			T220	1		T218	2		T221	2
all_levels[13]	auto[0]	144	1			T12	1		T154	1		T155	1
all_levels[13]	auto[1]	8	1			T161	1		T222	1		T223	1
all_levels[14]	auto[0]	145	1			T5	1		T7	1		T13	1
all_levels[14]	auto[1]	9	1			T187	1		T224	1		T215	2
all_levels[15]	auto[0]	133	1			T12	1		T13	2		T155	1
all_levels[15]	auto[1]	27	1			T225	2		T216	1		T226	1
all_levels[16]	auto[0]	102	1			T5	1		T154	1		T156	1
all_levels[16]	auto[1]	14	1			T156	3		T135	1		T227	1
all_levels[17]	auto[0]	106	1			T7	1		T157	1		T156	1
all_levels[17]	auto[1]	7	1			T228	2		T229	2		T230	1
all_levels[18]	auto[0]	84	1			T5	2		T13	1		T156	1
all_levels[18]	auto[1]	12	1			T138	3		T167	1		T225	2
all_levels[19]	auto[0]	89	1			T11	1		T98	1		T138	1
all_levels[19]	auto[1]	5	1			T231	1		T232	2		T233	1
all_levels[20]	auto[0]	89	1			T154	1		T135	1		T158	1
all_levels[20]	auto[1]	3	1			T223	2		T234	1		-	-
all_levels[21]	auto[0]	71	1			T36	1		T13	1		T124	1
all_levels[21]	auto[1]	4	1			T235	1		T236	2		T237	1
all_levels[22]	auto[0]	65	1			T159	2		T153	1		T147	1
all_levels[22]	auto[1]	2	1			T238	1		T239	1		-	-
all_levels[23]	auto[0]	66	1			T11	1		T154	1		T160	1
all_levels[23]	auto[1]	9	1			T86	3		T207	1		T228	2
all_levels[24]	auto[0]	50	1			T36	1		T13	1		T40	1
all_levels[24]	auto[1]	10	1			T36	1		T175	5		T240	1
all_levels[25]	auto[0]	59	1			T98	2		T135	1		T124	1
all_levels[25]	auto[1]	2	1			T241	1		T242	1		-	-
all_levels[26]	auto[0]	50	1			T40	1		T98	2		T134	2
all_levels[26]	auto[1]	4	1			T243	1		T244	3		-	-
all_levels[27]	auto[0]	52	1			T8	1		T11	1		T13	1
all_levels[27]	auto[1]	5	1			T245	1		T246	1		T247	1
all_levels[28]	auto[0]	46	1			T98	2		T161	1		T162	1
all_levels[28]	auto[1]	4	1			T161	1		T172	1		T248	1
all_levels[29]	auto[0]	32	1			T98	2		T124	1		T163	1
all_levels[29]	auto[1]	7	1			T210	1		T249	2		T250	2
all_levels[30]	auto[0]	27	1			T98	1		T125	1		T147	2
all_levels[30]	auto[1]	2	1			T251	2		-	-		-	-
all_levels[31]	auto[0]	35	1			T143	1		T164	1		T165	1
all_levels[31]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[32]	auto[0]	33	1			T162	1		T165	1		T52	1
all_levels[32]	auto[1]	3	1			T78	1		T232	2		-	-
all_levels[33]	auto[0]	22	1			T166	1		T167	1		T168	1
all_levels[33]	auto[1]	4	1			T215	1		T55	2		T253	1
all_levels[34]	auto[0]	27	1			T5	1		T124	1		T160	1
all_levels[34]	auto[1]	1	1			T211	1		-	-		-	-
all_levels[35]	auto[0]	25	1			T98	1		T124	1		T169	1
all_levels[35]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[36]	auto[0]	27	1			T162	1		T170	1		T171	1
all_levels[36]	auto[1]	4	1			T171	1		T255	1		T256	1
all_levels[37]	auto[0]	25	1			T130	1		T162	1		T172	1
all_levels[37]	auto[1]	4	1			T257	1		T258	1		T259	2
all_levels[38]	auto[0]	12	1			T173	1		T161	1		T174	1
all_levels[38]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[39]	auto[0]	22	1			T98	1		T167	1		T175	1
all_levels[39]	auto[1]	2	1			T260	2		-	-		-	-
all_levels[40]	auto[0]	23	1			T40	1		T142	1		T98	1
all_levels[40]	auto[1]	2	1			T261	1		T262	1		-	-
all_levels[41]	auto[0]	20	1			T36	1		T98	1		T176	1
all_levels[42]	auto[0]	19	1			T36	1		T98	1		T174	1
all_levels[42]	auto[1]	2	1			T263	1		T192	1		-	-
all_levels[43]	auto[0]	17	1			T139	1		T177	1		T178	1
all_levels[43]	auto[1]	1	1			T139	1		-	-		-	-
all_levels[44]	auto[0]	13	1			T179	1		T180	1		T181	1
all_levels[45]	auto[0]	14	1			T5	1		T36	1		T30	1
all_levels[45]	auto[1]	3	1			T47	1		T264	2		-	-
all_levels[46]	auto[0]	13	1			T142	2		T130	1		T30	1
all_levels[46]	auto[1]	1	1			T265	1		-	-		-	-
all_levels[47]	auto[0]	9	1			T182	1		T183	1		T184	1
all_levels[47]	auto[1]	2	1			T182	2		-	-		-	-
all_levels[48]	auto[0]	13	1			T11	1		T139	1		T185	1
all_levels[49]	auto[0]	10	1			T7	1		T12	1		T40	1
all_levels[50]	auto[0]	12	1			T11	2		T40	1		T155	1
all_levels[50]	auto[1]	2	1			T155	1		T201	1		-	-
all_levels[51]	auto[0]	16	1			T186	1		T178	1		T187	2
all_levels[51]	auto[1]	3	1			T266	3		-	-		-	-
all_levels[52]	auto[0]	4	1			T164	1		T170	1		T174	1
all_levels[53]	auto[0]	11	1			T5	1		T186	1		T177	1
all_levels[53]	auto[1]	2	1			T267	2		-	-		-	-
all_levels[54]	auto[0]	12	1			T188	1		T56	1		T189	2
all_levels[55]	auto[0]	4	1			T55	1		T190	1		T191	1
all_levels[56]	auto[0]	5	1			T192	1		T193	1		T194	1
all_levels[56]	auto[1]	1	1			T194	1		-	-		-	-
all_levels[57]	auto[0]	2	1			T174	1		T195	1		-	-
all_levels[57]	auto[1]	1	1			T195	1		-	-		-	-
all_levels[58]	auto[0]	10	1			T196	1		T170	1		T42	1
all_levels[58]	auto[1]	2	1			T268	1		T195	1		-	-
all_levels[59]	auto[0]	10	1			T5	1		T7	1		T36	2
all_levels[59]	auto[1]	4	1			T36	2		T269	2		-	-
all_levels[60]	auto[0]	2	1			T197	1		T198	1		-	-
all_levels[61]	auto[0]	2	1			T199	1		T62	1		-	-
all_levels[62]	auto[0]	3	1			T164	1		T200	1		T201	1
all_levels[63]	auto[0]	5	1			T202	1		T203	1		T204	2
all_levels[63]	auto[1]	2	1			T203	2		-	-		-	-
all_levels[64]	auto[0]	89	1			T40	6		T143	1		T164	1
all_levels[64]	auto[1]	20	1			T164	6		T208	1		T238	2