Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115754	1			T1	11		T2	2		T3	3
all_pins[1]	115754	1			T1	11		T2	2		T3	3
all_pins[2]	115754	1			T1	11		T2	2		T3	3
all_pins[3]	115754	1			T1	11		T2	2		T3	3
all_pins[4]	115754	1			T1	11		T2	2		T3	3
all_pins[5]	115754	1			T1	11		T2	2		T3	3
all_pins[6]	115754	1			T1	11		T2	2		T3	3
all_pins[7]	115754	1			T1	11		T2	2		T3	3
all_pins[8]	115754	1			T1	11		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	995800	1			T1	79		T2	18		T3	24
values[0x1]	45986	1			T1	20		T3	3		T5	6
transitions[0x0=>0x1]	36297	1			T1	16		T3	3		T5	5
transitions[0x1=>0x0]	36097	1			T1	16		T3	2		T5	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93361	1			T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	22393	1			T1	9		T3	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	21840	1			T1	9		T3	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	1167	1			T11	1		T40	12		T15	1
all_pins[1]	values[0x0]	114034	1			T1	11		T2	2		T3	3
all_pins[1]	values[0x1]	1720	1			T6	2		T11	1		T12	11
all_pins[1]	transitions[0x0=>0x1]	1583	1			T6	2		T12	11		T40	12
all_pins[1]	transitions[0x1=>0x0]	2503	1			T1	5		T3	1		T5	1
all_pins[2]	values[0x0]	113114	1			T1	6		T2	2		T3	2
all_pins[2]	values[0x1]	2640	1			T1	5		T3	1		T5	1
all_pins[2]	transitions[0x0=>0x1]	2569	1			T1	5		T3	1		T5	1
all_pins[2]	transitions[0x1=>0x0]	244	1			T12	1		T17	3		T40	1
all_pins[3]	values[0x0]	115439	1			T1	11		T2	2		T3	3
all_pins[3]	values[0x1]	315	1			T12	1		T13	1		T17	3
all_pins[3]	transitions[0x0=>0x1]	276	1			T12	1		T13	1		T17	3
all_pins[3]	transitions[0x1=>0x0]	541	1			T12	10		T14	4		T17	12
all_pins[4]	values[0x0]	115174	1			T1	11		T2	2		T3	3
all_pins[4]	values[0x1]	580	1			T12	10		T14	4		T17	12
all_pins[4]	transitions[0x0=>0x1]	471	1			T12	9		T14	4		T17	10
all_pins[4]	transitions[0x1=>0x0]	156	1			T6	1		T20	2		T145	1
all_pins[5]	values[0x0]	115489	1			T1	11		T2	2		T3	3
all_pins[5]	values[0x1]	265	1			T6	1		T12	1		T17	2
all_pins[5]	transitions[0x0=>0x1]	211	1			T6	1		T12	1		T17	2
all_pins[5]	transitions[0x1=>0x0]	781	1			T5	1		T36	2		T14	2
all_pins[6]	values[0x0]	114919	1			T1	11		T2	2		T3	3
all_pins[6]	values[0x1]	835	1			T5	1		T36	2		T14	2
all_pins[6]	transitions[0x0=>0x1]	763	1			T5	1		T36	2		T14	2
all_pins[6]	transitions[0x1=>0x0]	354	1			T11	1		T12	6		T17	1
all_pins[7]	values[0x0]	115328	1			T1	11		T2	2		T3	3
all_pins[7]	values[0x1]	426	1			T11	1		T12	6		T17	1
all_pins[7]	transitions[0x0=>0x1]	225	1			T11	1		T17	1		T98	1
all_pins[7]	transitions[0x1=>0x0]	16611	1			T1	6		T5	2		T6	27
all_pins[8]	values[0x0]	98942	1			T1	5		T2	2		T3	3
all_pins[8]	values[0x1]	16812	1			T1	6		T5	2		T6	27
all_pins[8]	transitions[0x0=>0x1]	8359	1			T1	2		T5	1		T6	5
all_pins[8]	transitions[0x1=>0x0]	13740	1			T1	5		T3	1		T6	31