Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7370961	1			T1	34		T3	93		T5	24
all_levels[1]	1838432	1			T3	1		T6	8186		T7	15
all_levels[2]	505448	1			T1	1		T3	2		T5	1
all_levels[3]	242323	1			T1	4		T10	6		T12	7
all_levels[4]	371953	1			T5	2		T10	18		T12	3
all_levels[5]	345691	1			T1	1		T5	3		T10	4
all_levels[6]	273845	1			T12	1		T14	2		T38	208
all_levels[7]	225800	1			T1	7		T6	5		T10	2
all_levels[8]	285506	1			T6	985		T7	4		T10	2
all_levels[9]	532460	1			T7	7		T10	8		T12	1
all_levels[10]	237885	1			T8	3		T10	1		T11	5
all_levels[11]	310440	1			T1	2		T10	1		T12	2
all_levels[12]	262433	1			T1	1		T5	1		T12	2
all_levels[13]	366201	1			T3	49		T10	2		T14	8
all_levels[14]	714331	1			T3	5		T10	6		T14	1
all_levels[15]	299510	1			T10	1		T12	16		T35	136
all_levels[16]	542632	1			T5	3		T10	37		T11	2
all_levels[17]	567548	1			T1	1		T10	1		T11	1
all_levels[18]	260620	1			T7	2		T10	2		T12	1
all_levels[19]	199627	1			T1	5		T38	191		T15	51
all_levels[20]	195051	1			T1	2		T10	1		T11	1
all_levels[21]	508989	1			T5	2		T12	21		T38	208
all_levels[22]	231055	1			T12	6		T38	194		T15	53
all_levels[23]	232576	1			T1	2		T11	1		T12	9
all_levels[24]	203408	1			T11	2		T12	3		T38	202
all_levels[25]	259518	1			T12	13		T38	201		T15	53
all_levels[26]	260058	1			T12	5		T38	179		T15	47
all_levels[27]	316808	1			T1	1		T12	3		T38	203
all_levels[28]	170276	1			T12	10		T38	201		T15	43
all_levels[29]	197784	1			T12	4		T38	202		T15	52
all_levels[30]	316569	1			T11	1		T12	8		T36	7
all_levels[31]	583256	1			T11	2		T35	2		T38	4008
all_levels[32]	13588688	1			T1	46		T5	8		T7	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32813049

1

T1

107

T3

149

T5

43

auto[1]

4633

1

T3

1

T5

1

T6

36

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7368458	1			T1	34		T3	93		T5	23
all_levels[0]	auto[1]	2503	1			T5	1		T6	27		T7	3
all_levels[1]	auto[0]	1838114	1			T3	1		T6	8181		T7	14
all_levels[1]	auto[1]	318	1			T6	5		T7	1		T11	1
all_levels[2]	auto[0]	505405	1			T1	1		T3	2		T5	1
all_levels[2]	auto[1]	43	1			T155	1		T159	1		T21	1
all_levels[3]	auto[0]	242213	1			T1	4		T10	6		T12	7
all_levels[3]	auto[1]	110	1			T15	1		T127	1		T186	1
all_levels[4]	auto[0]	371926	1			T5	2		T10	18		T12	3
all_levels[4]	auto[1]	27	1			T155	1		T173	2		T170	2
all_levels[5]	auto[0]	345653	1			T1	1		T5	3		T10	4
all_levels[5]	auto[1]	38	1			T165	1		T362	1		T199	1
all_levels[6]	auto[0]	273807	1			T12	1		T14	2		T38	208
all_levels[6]	auto[1]	38	1			T300	1		T225	2		T363	2
all_levels[7]	auto[0]	225595	1			T1	7		T6	1		T10	2
all_levels[7]	auto[1]	205	1			T6	4		T12	16		T37	2
all_levels[8]	auto[0]	285484	1			T6	985		T7	4		T10	2
all_levels[8]	auto[1]	22	1			T37	1		T40	1		T139	1
all_levels[9]	auto[0]	532429	1			T7	7		T10	8		T12	1
all_levels[9]	auto[1]	31	1			T135	1		T225	2		T289	1
all_levels[10]	auto[0]	237856	1			T8	2		T10	1		T11	5
all_levels[10]	auto[1]	29	1			T8	1		T36	1		T363	1
all_levels[11]	auto[0]	310417	1			T1	2		T10	1		T12	2
all_levels[11]	auto[1]	23	1			T13	2		T155	1		T186	2
all_levels[12]	auto[0]	262415	1			T1	1		T5	1		T12	2
all_levels[12]	auto[1]	18	1			T355	1		T160	2		T284	1
all_levels[13]	auto[0]	366173	1			T3	49		T10	2		T14	8
all_levels[13]	auto[1]	28	1			T301	1		T216	1		T364	1
all_levels[14]	auto[0]	714312	1			T3	4		T10	6		T14	1
all_levels[14]	auto[1]	19	1			T3	1		T216	2		T365	1
all_levels[15]	auto[0]	299270	1			T10	1		T12	6		T35	136
all_levels[15]	auto[1]	240	1			T12	10		T17	3		T287	7
all_levels[16]	auto[0]	542610	1			T5	3		T10	37		T11	2
all_levels[16]	auto[1]	22	1			T142	1		T223	1		T216	1
all_levels[17]	auto[0]	567530	1			T1	1		T10	1		T11	1
all_levels[17]	auto[1]	18	1			T206	2		T120	2		T366	2
all_levels[18]	auto[0]	260605	1			T7	2		T10	2		T12	1
all_levels[18]	auto[1]	15	1			T130	1		T308	2		T123	1
all_levels[19]	auto[0]	199609	1			T1	5		T38	191		T15	51
all_levels[19]	auto[1]	18	1			T158	1		T205	1		T222	1
all_levels[20]	auto[0]	195033	1			T1	2		T10	1		T11	1
all_levels[20]	auto[1]	18	1			T138	4		T120	1		T367	1
all_levels[21]	auto[0]	508975	1			T5	2		T12	21		T38	208
all_levels[21]	auto[1]	14	1			T363	1		T291	1		T368	1
all_levels[22]	auto[0]	231042	1			T12	6		T38	194		T15	53
all_levels[22]	auto[1]	13	1			T301	1		T187	1		T369	1
all_levels[23]	auto[0]	232552	1			T1	2		T11	1		T12	9
all_levels[23]	auto[1]	24	1			T154	2		T363	1		T213	1
all_levels[24]	auto[0]	203369	1			T11	2		T12	3		T38	202
all_levels[24]	auto[1]	39	1			T209	3		T121	2		T86	2
all_levels[25]	auto[0]	259492	1			T12	13		T38	201		T15	53
all_levels[25]	auto[1]	26	1			T142	1		T218	1		T370	1
all_levels[26]	auto[0]	260033	1			T12	5		T38	179		T15	47
all_levels[26]	auto[1]	25	1			T167	1		T275	1		T301	2
all_levels[27]	auto[0]	316785	1			T1	1		T12	3		T38	203
all_levels[27]	auto[1]	23	1			T216	1		T371	1		T372	1
all_levels[28]	auto[0]	170249	1			T12	10		T38	201		T15	43
all_levels[28]	auto[1]	27	1			T330	1		T47	1		T209	2
all_levels[29]	auto[0]	197752	1			T12	4		T38	202		T15	52
all_levels[29]	auto[1]	32	1			T139	2		T163	1		T160	2
all_levels[30]	auto[0]	316544	1			T11	1		T12	8		T36	5
all_levels[30]	auto[1]	25	1			T36	2		T223	3		T373	2
all_levels[31]	auto[0]	583246	1			T11	2		T35	2		T38	4008
all_levels[31]	auto[1]	10	1			T155	1		T44	2		T374	1
all_levels[32]	auto[0]	13588096	1			T1	46		T5	8		T7	2
all_levels[32]	auto[1]	592	1			T7	2		T12	2		T37	1