Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	803	1			T14	4		T20	7		T98	4
all_values[1]	803	1			T14	4		T20	7		T98	4
all_values[2]	803	1			T14	4		T20	7		T98	4
all_values[3]	803	1			T14	4		T20	7		T98	4
all_values[4]	803	1			T14	4		T20	7		T98	4
all_values[5]	803	1			T14	4		T20	7		T98	4
all_values[6]	803	1			T14	4		T20	7		T98	4
all_values[7]	803	1			T14	4		T20	7		T98	4
all_values[8]	803	1			T14	4		T20	7		T98	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3931

1

T14

18

T20

30

T98

15

auto[1]

3296

1

T14

18

T20

33

T98

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2348

1

T14

15

T20

21

T98

17

auto[1]

4879

1

T14

21

T20

42

T98

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4252

1

T14

24

T20

35

T98

24

auto[1]

2975

1

T14

12

T20

28

T98

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	258	1			T14	1		T20	4		T98	1
all_values[0]	auto[0]	auto[1]	auto[1]	219	1			T14	1		T21	1		T28	1
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T14	1		T20	1		T98	3
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T14	1		T20	2		T21	1
all_values[1]	auto[0]	auto[0]	auto[0]	248	1			T14	4		T20	2		T21	3
all_values[1]	auto[0]	auto[1]	auto[0]	230	1			T20	3		T98	3		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T20	1		T21	1		T145	1
all_values[1]	auto[1]	auto[1]	auto[1]	123	1			T20	1		T98	1		T21	2
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T20	4		T98	1		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T33	1		T146	1
all_values[2]	auto[0]	auto[1]	auto[0]	139	1			T20	1		T98	3		T21	1
all_values[2]	auto[0]	auto[1]	auto[1]	87	1			T14	1		T21	1		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T14	1		T20	1		T21	4
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T14	1		T20	1		T21	1
all_values[3]	auto[0]	auto[0]	auto[0]	190	1			T14	4		T21	1		T145	1
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T20	1		T28	1		T145	1
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T20	1		T98	2		T21	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T20	1		T98	1		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T20	2		T21	2		T28	1
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T20	2		T98	1		T21	1
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T98	1		T21	1		T28	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T20	1		T21	1		T28	1
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T20	1		T98	2		T30	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T14	1		T20	1		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T20	3		T98	1		T21	2
all_values[4]	auto[1]	auto[1]	auto[1]	129	1			T14	3		T20	1		T21	2
all_values[5]	auto[0]	auto[0]	auto[0]	149	1			T20	1		T21	3		T28	2
all_values[5]	auto[0]	auto[0]	auto[1]	89	1			T20	1		T98	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	152	1			T14	3		T20	2		T98	1
all_values[5]	auto[0]	auto[1]	auto[1]	81	1			T145	1		T33	2		T147	3
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T20	1		T98	1		T145	1
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T14	1		T20	2		T98	1
all_values[6]	auto[0]	auto[0]	auto[0]	186	1			T20	1		T98	1		T21	5
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T30	1		T33	2		T147	4
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T14	2		T20	1		T98	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T14	1		T20	2		T145	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T20	2		T30	1		T33	6
all_values[6]	auto[1]	auto[1]	auto[1]	148	1			T14	1		T20	1		T98	2
all_values[7]	auto[0]	auto[0]	auto[0]	162	1			T14	2		T20	1		T98	1
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T98	1		T21	1		T30	1
all_values[7]	auto[0]	auto[1]	auto[0]	110	1			T20	3		T98	1		T21	1
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T20	1		T145	2		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T14	2		T20	1		T98	1
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T20	1		T28	1		T30	1
all_values[8]	auto[0]	auto[0]	auto[1]	248	1			T14	2		T98	2		T21	2
all_values[8]	auto[0]	auto[1]	auto[1]	206	1			T14	1		T20	2		T98	1
all_values[8]	auto[1]	auto[0]	auto[1]	186	1			T20	2		T21	2		T32	2
all_values[8]	auto[1]	auto[1]	auto[1]	163	1			T14	1		T20	3		T98	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal