Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1318
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T1259 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1132890724 Jul 23 07:23:36 PM PDT 24 Jul 23 07:23:39 PM PDT 24 36403354 ps
T1260 /workspace/coverage/cover_reg_top/26.uart_intr_test.2593769658 Jul 23 07:23:50 PM PDT 24 Jul 23 07:23:52 PM PDT 24 22322748 ps
T1261 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1267819900 Jul 23 07:23:17 PM PDT 24 Jul 23 07:23:18 PM PDT 24 53947330 ps
T1262 /workspace/coverage/cover_reg_top/3.uart_intr_test.2292911979 Jul 23 07:22:45 PM PDT 24 Jul 23 07:22:46 PM PDT 24 10509299 ps
T1263 /workspace/coverage/cover_reg_top/7.uart_intr_test.1702521725 Jul 23 07:23:08 PM PDT 24 Jul 23 07:23:09 PM PDT 24 16195248 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_intr_test.123748475 Jul 23 07:22:50 PM PDT 24 Jul 23 07:22:52 PM PDT 24 22961303 ps
T1265 /workspace/coverage/cover_reg_top/19.uart_tl_errors.4150865850 Jul 23 07:23:43 PM PDT 24 Jul 23 07:23:46 PM PDT 24 42989500 ps
T1266 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.217865668 Jul 23 07:22:49 PM PDT 24 Jul 23 07:22:51 PM PDT 24 70282119 ps
T1267 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1941735387 Jul 23 07:23:41 PM PDT 24 Jul 23 07:23:43 PM PDT 24 25674484 ps
T1268 /workspace/coverage/cover_reg_top/25.uart_intr_test.2432051654 Jul 23 07:23:51 PM PDT 24 Jul 23 07:23:53 PM PDT 24 26413788 ps
T1269 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2426354145 Jul 23 07:22:35 PM PDT 24 Jul 23 07:22:37 PM PDT 24 32647320 ps
T1270 /workspace/coverage/cover_reg_top/30.uart_intr_test.507605596 Jul 23 07:23:50 PM PDT 24 Jul 23 07:23:52 PM PDT 24 24963350 ps
T103 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2891761482 Jul 23 07:23:28 PM PDT 24 Jul 23 07:23:31 PM PDT 24 97223639 ps
T1271 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2486548221 Jul 23 07:23:09 PM PDT 24 Jul 23 07:23:11 PM PDT 24 95289980 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4284309906 Jul 23 07:22:42 PM PDT 24 Jul 23 07:22:44 PM PDT 24 101739645 ps
T1273 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2120377315 Jul 23 07:22:42 PM PDT 24 Jul 23 07:22:44 PM PDT 24 157397027 ps
T1274 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1839369397 Jul 23 07:23:34 PM PDT 24 Jul 23 07:23:36 PM PDT 24 103563237 ps
T1275 /workspace/coverage/cover_reg_top/32.uart_intr_test.2136881531 Jul 23 07:23:58 PM PDT 24 Jul 23 07:24:00 PM PDT 24 12966523 ps
T1276 /workspace/coverage/cover_reg_top/2.uart_tl_errors.765469724 Jul 23 07:22:38 PM PDT 24 Jul 23 07:22:39 PM PDT 24 95709525 ps
T1277 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2593943134 Jul 23 07:22:58 PM PDT 24 Jul 23 07:23:01 PM PDT 24 137862612 ps
T1278 /workspace/coverage/cover_reg_top/6.uart_intr_test.1489030880 Jul 23 07:22:59 PM PDT 24 Jul 23 07:23:01 PM PDT 24 35860446 ps
T104 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1238740508 Jul 23 07:23:18 PM PDT 24 Jul 23 07:23:21 PM PDT 24 4438896175 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2824756637 Jul 23 07:23:31 PM PDT 24 Jul 23 07:23:33 PM PDT 24 50729900 ps
T1280 /workspace/coverage/cover_reg_top/31.uart_intr_test.3840769757 Jul 23 07:23:49 PM PDT 24 Jul 23 07:23:51 PM PDT 24 14258957 ps
T1281 /workspace/coverage/cover_reg_top/45.uart_intr_test.3545433809 Jul 23 07:23:49 PM PDT 24 Jul 23 07:23:51 PM PDT 24 11611279 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1838329181 Jul 23 07:22:41 PM PDT 24 Jul 23 07:22:42 PM PDT 24 37484090 ps
T65 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3787548788 Jul 23 07:22:34 PM PDT 24 Jul 23 07:22:38 PM PDT 24 59067586 ps
T1283 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.179071639 Jul 23 07:23:26 PM PDT 24 Jul 23 07:23:29 PM PDT 24 79645937 ps
T150 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.969721900 Jul 23 07:23:34 PM PDT 24 Jul 23 07:23:36 PM PDT 24 69644418 ps
T1284 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4259103537 Jul 23 07:23:27 PM PDT 24 Jul 23 07:23:30 PM PDT 24 98210375 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.293116067 Jul 23 07:22:28 PM PDT 24 Jul 23 07:22:30 PM PDT 24 173376289 ps
T1286 /workspace/coverage/cover_reg_top/24.uart_intr_test.1733589976 Jul 23 07:23:58 PM PDT 24 Jul 23 07:23:59 PM PDT 24 53681205 ps
T1287 /workspace/coverage/cover_reg_top/5.uart_csr_rw.14328024 Jul 23 07:22:59 PM PDT 24 Jul 23 07:23:01 PM PDT 24 17050182 ps
T1288 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3294755524 Jul 23 07:23:10 PM PDT 24 Jul 23 07:23:12 PM PDT 24 74107572 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_tl_errors.409890946 Jul 23 07:23:10 PM PDT 24 Jul 23 07:23:14 PM PDT 24 107458998 ps
T1290 /workspace/coverage/cover_reg_top/11.uart_csr_rw.255868228 Jul 23 07:23:19 PM PDT 24 Jul 23 07:23:20 PM PDT 24 12108454 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1718797097 Jul 23 07:22:22 PM PDT 24 Jul 23 07:22:23 PM PDT 24 38585779 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3430908124 Jul 23 07:23:08 PM PDT 24 Jul 23 07:23:10 PM PDT 24 26987762 ps
T1293 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1777158855 Jul 23 07:23:36 PM PDT 24 Jul 23 07:23:39 PM PDT 24 193009695 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2366114721 Jul 23 07:22:36 PM PDT 24 Jul 23 07:22:38 PM PDT 24 36248809 ps
T1295 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2651669037 Jul 23 07:22:21 PM PDT 24 Jul 23 07:22:22 PM PDT 24 60244390 ps
T1296 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3342419477 Jul 23 07:23:10 PM PDT 24 Jul 23 07:23:12 PM PDT 24 606697072 ps
T1297 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.741560824 Jul 23 07:22:51 PM PDT 24 Jul 23 07:22:53 PM PDT 24 45437826 ps
T1298 /workspace/coverage/cover_reg_top/37.uart_intr_test.308190493 Jul 23 07:23:49 PM PDT 24 Jul 23 07:23:51 PM PDT 24 28357893 ps
T1299 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2119564465 Jul 23 07:22:41 PM PDT 24 Jul 23 07:22:43 PM PDT 24 166201887 ps
T1300 /workspace/coverage/cover_reg_top/0.uart_tl_errors.135626976 Jul 23 07:22:23 PM PDT 24 Jul 23 07:22:25 PM PDT 24 72465019 ps
T1301 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2784896624 Jul 23 07:23:44 PM PDT 24 Jul 23 07:23:46 PM PDT 24 31493699 ps
T1302 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2696523720 Jul 23 07:23:41 PM PDT 24 Jul 23 07:23:43 PM PDT 24 105479966 ps
T1303 /workspace/coverage/cover_reg_top/5.uart_intr_test.539838707 Jul 23 07:23:00 PM PDT 24 Jul 23 07:23:02 PM PDT 24 13617838 ps
T1304 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3025437712 Jul 23 07:22:40 PM PDT 24 Jul 23 07:22:41 PM PDT 24 44247631 ps
T1305 /workspace/coverage/cover_reg_top/42.uart_intr_test.1802025550 Jul 23 07:23:48 PM PDT 24 Jul 23 07:23:50 PM PDT 24 12436990 ps
T1306 /workspace/coverage/cover_reg_top/0.uart_intr_test.3074053071 Jul 23 07:22:21 PM PDT 24 Jul 23 07:22:22 PM PDT 24 45492516 ps
T66 /workspace/coverage/cover_reg_top/9.uart_csr_rw.374796232 Jul 23 07:23:07 PM PDT 24 Jul 23 07:23:08 PM PDT 24 48421618 ps
T1307 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1740975357 Jul 23 07:23:00 PM PDT 24 Jul 23 07:23:02 PM PDT 24 72755125 ps
T1308 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1352920039 Jul 23 07:22:41 PM PDT 24 Jul 23 07:22:42 PM PDT 24 56584867 ps
T1309 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3629051086 Jul 23 07:23:20 PM PDT 24 Jul 23 07:23:23 PM PDT 24 135783781 ps
T1310 /workspace/coverage/cover_reg_top/4.uart_tl_errors.840868084 Jul 23 07:22:49 PM PDT 24 Jul 23 07:22:53 PM PDT 24 393833548 ps
T1311 /workspace/coverage/cover_reg_top/16.uart_csr_rw.4211823335 Jul 23 07:23:41 PM PDT 24 Jul 23 07:23:43 PM PDT 24 47071658 ps
T1312 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2121298163 Jul 23 07:23:10 PM PDT 24 Jul 23 07:23:12 PM PDT 24 96843550 ps
T1313 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4030032822 Jul 23 07:22:59 PM PDT 24 Jul 23 07:23:01 PM PDT 24 122975500 ps
T1314 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.557951366 Jul 23 07:22:50 PM PDT 24 Jul 23 07:22:52 PM PDT 24 21059413 ps
T1315 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3234445736 Jul 23 07:23:09 PM PDT 24 Jul 23 07:23:11 PM PDT 24 111620915 ps
T1316 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2723144438 Jul 23 07:22:58 PM PDT 24 Jul 23 07:23:00 PM PDT 24 187841631 ps
T67 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3290132199 Jul 23 07:22:29 PM PDT 24 Jul 23 07:22:30 PM PDT 24 144179940 ps
T1317 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3635527362 Jul 23 07:23:26 PM PDT 24 Jul 23 07:23:29 PM PDT 24 69470145 ps
T1318 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1191977343 Jul 23 07:22:29 PM PDT 24 Jul 23 07:22:31 PM PDT 24 512484008 ps
T68 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.944091000 Jul 23 07:22:48 PM PDT 24 Jul 23 07:22:49 PM PDT 24 55876840 ps
T69 /workspace/coverage/cover_reg_top/0.uart_csr_rw.832823227 Jul 23 07:22:22 PM PDT 24 Jul 23 07:22:24 PM PDT 24 14221777 ps

Test location /workspace/coverage/default/43.uart_fifo_full.2581080611
Short name T5
Test name
Test status
Simulation time 64209604199 ps
CPU time 25.05 seconds
Started Jul 23 06:53:26 PM PDT 24
Finished Jul 23 06:53:51 PM PDT 24
Peak memory 200176 kb
Host smart-cd3fec6f-7293-4fa1-8601-d8ea34756e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581080611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2581080611
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.4270186557
Short name T12
Test name
Test status
Simulation time 238084443502 ps
CPU time 1009.65 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 216644 kb
Host smart-f584a278-5747-4fec-81d3-79f2cce3a3d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270186557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4270186557
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.1109609079
Short name T98
Test name
Test status
Simulation time 110854263073 ps
CPU time 187.45 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:54:32 PM PDT 24
Peak memory 199756 kb
Host smart-07d0ef6a-1ed5-44bc-a243-c8ee290e5626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109609079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1109609079
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4252628424
Short name T29
Test name
Test status
Simulation time 191449363789 ps
CPU time 1062.22 seconds
Started Jul 23 06:57:29 PM PDT 24
Finished Jul 23 07:15:12 PM PDT 24
Peak memory 216720 kb
Host smart-8e8acd54-72ce-43b3-abea-905ce82a43d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252628424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4252628424
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.4289977215
Short name T28
Test name
Test status
Simulation time 165194472474 ps
CPU time 1272.57 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:19:01 PM PDT 24
Peak memory 225072 kb
Host smart-40497c26-ddb9-47a5-8ead-13aaa7060c8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289977215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.4289977215
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.358912908
Short name T147
Test name
Test status
Simulation time 323227778871 ps
CPU time 1365.17 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:20:33 PM PDT 24
Peak memory 224976 kb
Host smart-305a62fa-6c5a-4171-b732-9c1edd1ce856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358912908 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.358912908
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1126220419
Short name T53
Test name
Test status
Simulation time 274855881525 ps
CPU time 678.49 seconds
Started Jul 23 06:53:01 PM PDT 24
Finished Jul 23 07:04:21 PM PDT 24
Peak memory 224992 kb
Host smart-1f4b0e0a-5ad5-4ed1-bee9-dd4d98436d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126220419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1126220419
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2427440731
Short name T281
Test name
Test status
Simulation time 170750839607 ps
CPU time 925.33 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 07:09:09 PM PDT 24
Peak memory 200224 kb
Host smart-e2e5c7ea-1eee-4ca4-be67-ee4abab8a8de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427440731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2427440731
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1642772584
Short name T172
Test name
Test status
Simulation time 144253987445 ps
CPU time 189.16 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:56:55 PM PDT 24
Peak memory 200232 kb
Host smart-786d7d63-0cf3-4a17-96d2-410cc553f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642772584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1642772584
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.1521317282
Short name T15
Test name
Test status
Simulation time 222045965603 ps
CPU time 430.3 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:58:25 PM PDT 24
Peak memory 200184 kb
Host smart-4e2a4aaf-056b-4fd9-8661-2b7c562a0a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521317282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1521317282
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1449669500
Short name T109
Test name
Test status
Simulation time 132757839 ps
CPU time 0.92 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:57 PM PDT 24
Peak memory 218716 kb
Host smart-c0a6aba3-a2a6-4215-b620-6d653edc72dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449669500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1449669500
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/12.uart_alert_test.1479473715
Short name T23
Test name
Test status
Simulation time 10880070 ps
CPU time 0.55 seconds
Started Jul 23 06:51:27 PM PDT 24
Finished Jul 23 06:51:30 PM PDT 24
Peak memory 194716 kb
Host smart-5136b6e9-4105-43bd-b159-88225d7c05d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479473715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1479473715
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3875753545
Short name T135
Test name
Test status
Simulation time 26707894326 ps
CPU time 50.79 seconds
Started Jul 23 06:58:46 PM PDT 24
Finished Jul 23 06:59:39 PM PDT 24
Peak memory 200168 kb
Host smart-10bd67ea-770f-465e-9c86-3b185049b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875753545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3875753545
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2192856033
Short name T297
Test name
Test status
Simulation time 94372891548 ps
CPU time 69.55 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:52:33 PM PDT 24
Peak memory 200108 kb
Host smart-41c5b0ce-1f94-429d-8956-c25c21df0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192856033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2192856033
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3942963171
Short name T304
Test name
Test status
Simulation time 272195179390 ps
CPU time 94.32 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 200260 kb
Host smart-a158546f-0d2b-4897-b17a-3d364accfb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942963171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3942963171
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.491899950
Short name T337
Test name
Test status
Simulation time 100533772483 ps
CPU time 683.94 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 07:02:43 PM PDT 24
Peak memory 200184 kb
Host smart-21872106-6371-4c26-a2f0-ca8c4c0b0b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491899950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.491899950
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1125709188
Short name T54
Test name
Test status
Simulation time 590595145754 ps
CPU time 816.62 seconds
Started Jul 23 06:53:53 PM PDT 24
Finished Jul 23 07:07:31 PM PDT 24
Peak memory 225012 kb
Host smart-f2d52fea-ac74-4768-a633-09f588bd0b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125709188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1125709188
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1553568946
Short name T278
Test name
Test status
Simulation time 66843467898 ps
CPU time 55.33 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:52:20 PM PDT 24
Peak memory 200272 kb
Host smart-63459f9d-69ae-4250-b2c1-918bd08cbb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553568946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1553568946
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.580663657
Short name T102
Test name
Test status
Simulation time 315086714 ps
CPU time 1.48 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:22 PM PDT 24
Peak memory 200208 kb
Host smart-9e3cf967-b1b0-454e-8ffb-69043bbd4f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580663657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.580663657
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3602745167
Short name T40
Test name
Test status
Simulation time 71719184328 ps
CPU time 94.17 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:53:06 PM PDT 24
Peak memory 200176 kb
Host smart-4e07c99a-6b38-4d0a-a341-28d37d8cdfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602745167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3602745167
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2434522199
Short name T143
Test name
Test status
Simulation time 394890228372 ps
CPU time 61.47 seconds
Started Jul 23 06:53:41 PM PDT 24
Finished Jul 23 06:54:43 PM PDT 24
Peak memory 200224 kb
Host smart-a7e2e396-7857-4bef-8f34-16aaef818882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434522199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2434522199
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2913140378
Short name T301
Test name
Test status
Simulation time 119888535654 ps
CPU time 107.09 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 07:00:03 PM PDT 24
Peak memory 200192 kb
Host smart-5402ac92-486a-471d-ae5a-aa26d8dee0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913140378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2913140378
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2047289873
Short name T55
Test name
Test status
Simulation time 483805063632 ps
CPU time 1166.07 seconds
Started Jul 23 06:57:41 PM PDT 24
Finished Jul 23 07:17:08 PM PDT 24
Peak memory 226648 kb
Host smart-5248c1d3-bb8a-40cb-a0a9-026fbc781492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047289873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2047289873
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2508596677
Short name T173
Test name
Test status
Simulation time 98382245188 ps
CPU time 45.09 seconds
Started Jul 23 06:58:39 PM PDT 24
Finished Jul 23 06:59:24 PM PDT 24
Peak memory 200104 kb
Host smart-de7964e8-89b8-4fe5-87d2-099c24d64ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508596677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2508596677
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.2267133054
Short name T466
Test name
Test status
Simulation time 252754865284 ps
CPU time 223.16 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:56:00 PM PDT 24
Peak memory 200244 kb
Host smart-1cf53947-fbd4-423a-8a42-e4105df986a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267133054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2267133054
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2163216117
Short name T335
Test name
Test status
Simulation time 65458849274 ps
CPU time 369.17 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:58:26 PM PDT 24
Peak memory 200220 kb
Host smart-827b7323-528d-4756-ae5e-7b7d65a7a781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163216117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2163216117
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.911279340
Short name T139
Test name
Test status
Simulation time 58661924312 ps
CPU time 22.24 seconds
Started Jul 23 06:53:54 PM PDT 24
Finished Jul 23 06:54:17 PM PDT 24
Peak memory 200244 kb
Host smart-5bcedd3c-aff2-446e-a55d-b56ac5089a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911279340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.911279340
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3115694303
Short name T205
Test name
Test status
Simulation time 229332702945 ps
CPU time 228.94 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:57:06 PM PDT 24
Peak memory 200040 kb
Host smart-22c4072d-0bc3-48cd-b143-f510858045e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115694303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3115694303
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_noise_filter.818871464
Short name T300
Test name
Test status
Simulation time 81419867338 ps
CPU time 152.64 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:54:00 PM PDT 24
Peak memory 199044 kb
Host smart-8e3c019d-dd70-4625-a98b-dcc5e5f77d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818871464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.818871464
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4229100597
Short name T164
Test name
Test status
Simulation time 181325976407 ps
CPU time 70.71 seconds
Started Jul 23 06:58:42 PM PDT 24
Finished Jul 23 06:59:53 PM PDT 24
Peak memory 200268 kb
Host smart-8ce4a3e2-32ba-4526-8a10-c8ded9e980d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229100597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4229100597
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4044477991
Short name T63
Test name
Test status
Simulation time 486811597 ps
CPU time 2.51 seconds
Started Jul 23 07:22:21 PM PDT 24
Finished Jul 23 07:22:24 PM PDT 24
Peak memory 198940 kb
Host smart-caaaca68-6e75-4aed-b22d-4ad3f1d32bff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044477991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4044477991
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3894737781
Short name T97
Test name
Test status
Simulation time 16308031 ps
CPU time 0.64 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:20 PM PDT 24
Peak memory 196688 kb
Host smart-85731606-6efe-4c4b-8214-3522774e370f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894737781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3894737781
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2617523848
Short name T208
Test name
Test status
Simulation time 856206928912 ps
CPU time 704.6 seconds
Started Jul 23 06:57:57 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 225068 kb
Host smart-212acf9f-b755-4280-ab2c-757830f7eee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617523848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2617523848
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.4078861902
Short name T121
Test name
Test status
Simulation time 123760057825 ps
CPU time 173.6 seconds
Started Jul 23 06:51:32 PM PDT 24
Finished Jul 23 06:54:28 PM PDT 24
Peak memory 208744 kb
Host smart-c2881198-1fc8-49ae-af41-822b7b05d1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078861902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4078861902
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.28996901
Short name T218
Test name
Test status
Simulation time 77525006311 ps
CPU time 112.59 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 07:00:30 PM PDT 24
Peak memory 200188 kb
Host smart-fa224ae3-e7fb-449c-a476-ea882abf0977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28996901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.28996901
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3937989487
Short name T52
Test name
Test status
Simulation time 152734927560 ps
CPU time 986.19 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:14:14 PM PDT 24
Peak memory 216764 kb
Host smart-c66f9d9e-adb7-4ada-b371-5b99af8ebd5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937989487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3937989487
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3890714729
Short name T223
Test name
Test status
Simulation time 112759405229 ps
CPU time 24.8 seconds
Started Jul 23 06:58:04 PM PDT 24
Finished Jul 23 06:58:30 PM PDT 24
Peak memory 200148 kb
Host smart-15731f46-2800-42e5-a624-7895a410faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890714729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3890714729
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3770528938
Short name T170
Test name
Test status
Simulation time 38850472419 ps
CPU time 22.69 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:06 PM PDT 24
Peak memory 200196 kb
Host smart-dbb9161d-dc34-4866-b363-36e35e7d5160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770528938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3770528938
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3258828034
Short name T7
Test name
Test status
Simulation time 96783679183 ps
CPU time 99.38 seconds
Started Jul 23 06:53:58 PM PDT 24
Finished Jul 23 06:55:39 PM PDT 24
Peak memory 200244 kb
Host smart-77cd5ff7-53ea-4b24-b62f-69d739f69db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258828034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3258828034
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3095109266
Short name T194
Test name
Test status
Simulation time 501697767671 ps
CPU time 955.13 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 07:13:53 PM PDT 24
Peak memory 225196 kb
Host smart-36d9a1b6-604c-4ad3-9d09-0ee72e92c26f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095109266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3095109266
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3124790488
Short name T215
Test name
Test status
Simulation time 294013318309 ps
CPU time 336.05 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:56:57 PM PDT 24
Peak memory 200248 kb
Host smart-9481cd19-75b8-4c01-9ad8-18620671a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124790488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3124790488
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1632153200
Short name T263
Test name
Test status
Simulation time 50056487728 ps
CPU time 78.81 seconds
Started Jul 23 06:51:42 PM PDT 24
Finished Jul 23 06:53:03 PM PDT 24
Peak memory 200144 kb
Host smart-0ecc8045-b9ab-49d0-8d30-f086daf93448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632153200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1632153200
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.342714450
Short name T195
Test name
Test status
Simulation time 157371667626 ps
CPU time 669.31 seconds
Started Jul 23 06:51:34 PM PDT 24
Finished Jul 23 07:02:45 PM PDT 24
Peak memory 216720 kb
Host smart-82240b4f-d1b5-4b89-860b-5cbe37db0652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342714450 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.342714450
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_full.58736506
Short name T180
Test name
Test status
Simulation time 203007080097 ps
CPU time 358.14 seconds
Started Jul 23 06:51:47 PM PDT 24
Finished Jul 23 06:57:46 PM PDT 24
Peak memory 200268 kb
Host smart-b7164e17-4d58-47dc-a390-dacbf272efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58736506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.58736506
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3708310951
Short name T232
Test name
Test status
Simulation time 61324132733 ps
CPU time 44.94 seconds
Started Jul 23 06:59:09 PM PDT 24
Finished Jul 23 06:59:55 PM PDT 24
Peak memory 200208 kb
Host smart-d5eed202-e349-4a9b-980a-8d3d9cf6e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708310951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3708310951
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1109693919
Short name T110
Test name
Test status
Simulation time 24936547253 ps
CPU time 52.78 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:00:22 PM PDT 24
Peak memory 200180 kb
Host smart-c8fc5860-fe9c-45a2-80ab-14919a2ec7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109693919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1109693919
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2889807876
Short name T47
Test name
Test status
Simulation time 122172402218 ps
CPU time 91.5 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:52:41 PM PDT 24
Peak memory 200228 kb
Host smart-c1374782-6d7f-4daa-969d-6ecdd6709971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889807876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2889807876
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1617334547
Short name T203
Test name
Test status
Simulation time 264286374996 ps
CPU time 49.2 seconds
Started Jul 23 06:58:35 PM PDT 24
Finished Jul 23 06:59:24 PM PDT 24
Peak memory 199940 kb
Host smart-754e88fd-ab67-4c1a-9b87-e1e0e9b7ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617334547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1617334547
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3734570343
Short name T30
Test name
Test status
Simulation time 33107632214 ps
CPU time 470.96 seconds
Started Jul 23 06:51:49 PM PDT 24
Finished Jul 23 06:59:41 PM PDT 24
Peak memory 209760 kb
Host smart-c65103b0-17f1-485a-bfb1-a71c2cad3305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734570343 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3734570343
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2748091596
Short name T227
Test name
Test status
Simulation time 71026785040 ps
CPU time 71.39 seconds
Started Jul 23 06:58:53 PM PDT 24
Finished Jul 23 07:00:06 PM PDT 24
Peak memory 200184 kb
Host smart-f4539b35-01c8-4255-81ac-4636034f143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748091596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2748091596
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2835245316
Short name T291
Test name
Test status
Simulation time 151651866683 ps
CPU time 218.72 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:56:01 PM PDT 24
Peak memory 200272 kb
Host smart-13d8f22d-937a-4908-884c-bb8475decf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835245316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2835245316
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3126847707
Short name T931
Test name
Test status
Simulation time 21029413470 ps
CPU time 222.59 seconds
Started Jul 23 06:53:52 PM PDT 24
Finished Jul 23 06:57:37 PM PDT 24
Peak memory 216776 kb
Host smart-b02e8222-25ee-4c83-8d76-c31f0dbaa999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126847707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3126847707
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3248170663
Short name T149
Test name
Test status
Simulation time 140769534 ps
CPU time 0.97 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 199952 kb
Host smart-fed7fdc1-c59d-4d52-907d-df367bc6d13a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248170663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3248170663
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.763117221
Short name T211
Test name
Test status
Simulation time 61084105979 ps
CPU time 639.12 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 07:02:00 PM PDT 24
Peak memory 216696 kb
Host smart-d0ca51af-9d76-4d1e-a20c-72ff485b5c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763117221 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.763117221
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2919508302
Short name T260
Test name
Test status
Simulation time 82247825006 ps
CPU time 208.55 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 07:01:33 PM PDT 24
Peak memory 200232 kb
Host smart-dd7888fa-5c00-40ac-9c7c-52d91ae1964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919508302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2919508302
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3673958629
Short name T168
Test name
Test status
Simulation time 37841966717 ps
CPU time 31.28 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:56 PM PDT 24
Peak memory 200028 kb
Host smart-360a1cab-461e-446d-b85f-028a5fb84803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673958629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3673958629
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1476867324
Short name T188
Test name
Test status
Simulation time 14070969070 ps
CPU time 12.76 seconds
Started Jul 23 06:58:21 PM PDT 24
Finished Jul 23 06:58:34 PM PDT 24
Peak memory 200176 kb
Host smart-649d3d75-7393-4a69-9f2b-bb865ba4bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476867324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1476867324
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.808628433
Short name T197
Test name
Test status
Simulation time 43356313930 ps
CPU time 40.52 seconds
Started Jul 23 06:51:38 PM PDT 24
Finished Jul 23 06:52:20 PM PDT 24
Peak memory 200212 kb
Host smart-56f186c4-44f1-4ed5-be6d-27ce0e4abcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808628433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.808628433
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2026197726
Short name T199
Test name
Test status
Simulation time 16054417115 ps
CPU time 10.85 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:58:34 PM PDT 24
Peak memory 200236 kb
Host smart-2cb9216c-e5f5-48dc-81fe-ab20b41b78d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026197726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2026197726
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.877114569
Short name T161
Test name
Test status
Simulation time 57858426739 ps
CPU time 23.91 seconds
Started Jul 23 06:58:30 PM PDT 24
Finished Jul 23 06:58:55 PM PDT 24
Peak memory 200236 kb
Host smart-d779b9ac-3233-413d-a18c-e699b47e4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877114569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.877114569
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.29144112
Short name T36
Test name
Test status
Simulation time 33791977797 ps
CPU time 11.1 seconds
Started Jul 23 06:59:33 PM PDT 24
Finished Jul 23 06:59:46 PM PDT 24
Peak memory 200220 kb
Host smart-8574af59-50a6-49c2-8e69-623768d82858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29144112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.29144112
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1291768149
Short name T961
Test name
Test status
Simulation time 22225643034 ps
CPU time 31.44 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 06:59:57 PM PDT 24
Peak memory 200084 kb
Host smart-6616f0e9-5709-4c61-9625-cd85240d7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291768149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1291768149
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.659255323
Short name T138
Test name
Test status
Simulation time 19807317378 ps
CPU time 13.94 seconds
Started Jul 23 06:53:57 PM PDT 24
Finished Jul 23 06:54:12 PM PDT 24
Peak memory 200224 kb
Host smart-751b82a4-0997-46a5-b8c9-e0b1e395667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659255323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.659255323
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.985325735
Short name T572
Test name
Test status
Simulation time 78488574096 ps
CPU time 156.89 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:53:35 PM PDT 24
Peak memory 200316 kb
Host smart-8cd0ce49-1c6b-4122-b7b1-7a68d3744f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985325735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.985325735
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.891433926
Short name T504
Test name
Test status
Simulation time 18683955864 ps
CPU time 257.09 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:55:36 PM PDT 24
Peak memory 200176 kb
Host smart-4280cf74-94c2-441d-80d0-4bfb13738cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891433926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.891433926
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4293821824
Short name T255
Test name
Test status
Simulation time 37989293624 ps
CPU time 17.36 seconds
Started Jul 23 06:58:02 PM PDT 24
Finished Jul 23 06:58:21 PM PDT 24
Peak memory 200156 kb
Host smart-304416b5-c96d-4ef2-8656-466829b61085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293821824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4293821824
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.229657451
Short name T265
Test name
Test status
Simulation time 131135877045 ps
CPU time 104.15 seconds
Started Jul 23 06:58:12 PM PDT 24
Finished Jul 23 06:59:57 PM PDT 24
Peak memory 200168 kb
Host smart-a3fd8318-bdfe-4b75-9abe-bdee679c4a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229657451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.229657451
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3185635790
Short name T257
Test name
Test status
Simulation time 151817958982 ps
CPU time 717.09 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 07:03:23 PM PDT 24
Peak memory 213896 kb
Host smart-3ef89989-e19f-46ed-b768-1971f7e9a8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185635790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3185635790
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.427421349
Short name T241
Test name
Test status
Simulation time 15664424773 ps
CPU time 28.51 seconds
Started Jul 23 06:58:13 PM PDT 24
Finished Jul 23 06:58:43 PM PDT 24
Peak memory 200088 kb
Host smart-5696caa3-d81e-4ffa-9096-8abd361f4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427421349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.427421349
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.948722671
Short name T182
Test name
Test status
Simulation time 114178682041 ps
CPU time 160.19 seconds
Started Jul 23 06:58:23 PM PDT 24
Finished Jul 23 07:01:06 PM PDT 24
Peak memory 200148 kb
Host smart-dd5e6991-b2f3-4c89-8528-5fd11151d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948722671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.948722671
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1721880482
Short name T243
Test name
Test status
Simulation time 47357056567 ps
CPU time 21.88 seconds
Started Jul 23 06:58:36 PM PDT 24
Finished Jul 23 06:58:59 PM PDT 24
Peak memory 200260 kb
Host smart-9e35e166-ac4a-4205-b4a3-a0476932d8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721880482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1721880482
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3822994860
Short name T239
Test name
Test status
Simulation time 184525187607 ps
CPU time 36.55 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:23 PM PDT 24
Peak memory 200184 kb
Host smart-a28b1ed2-cc42-4fd8-a711-9644fa89da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822994860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3822994860
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2875169790
Short name T235
Test name
Test status
Simulation time 58413874008 ps
CPU time 24.1 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:59:13 PM PDT 24
Peak memory 200160 kb
Host smart-2f90f828-5a61-482f-a4c3-0068052f0ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875169790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2875169790
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1514632055
Short name T261
Test name
Test status
Simulation time 72843349962 ps
CPU time 44.39 seconds
Started Jul 23 06:51:58 PM PDT 24
Finished Jul 23 06:52:44 PM PDT 24
Peak memory 200256 kb
Host smart-c6843042-2a84-4617-83ea-13b12f591746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514632055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1514632055
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.114161073
Short name T254
Test name
Test status
Simulation time 8692951229 ps
CPU time 15.8 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:03 PM PDT 24
Peak memory 200268 kb
Host smart-bfcfda95-fb77-4645-9cc6-33dab81c2c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114161073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.114161073
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1911972536
Short name T252
Test name
Test status
Simulation time 86923889185 ps
CPU time 75.97 seconds
Started Jul 23 06:59:25 PM PDT 24
Finished Jul 23 07:00:43 PM PDT 24
Peak memory 200200 kb
Host smart-c3a3b952-90cd-4b22-9a0b-ebead6140edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911972536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1911972536
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.676732746
Short name T1075
Test name
Test status
Simulation time 61889025164 ps
CPU time 22.33 seconds
Started Jul 23 06:59:29 PM PDT 24
Finished Jul 23 06:59:54 PM PDT 24
Peak memory 199736 kb
Host smart-ef2b3ba8-38ad-4797-9d0e-267a0045f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676732746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.676732746
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1274154311
Short name T266
Test name
Test status
Simulation time 131452765913 ps
CPU time 75.32 seconds
Started Jul 23 06:59:29 PM PDT 24
Finished Jul 23 07:00:47 PM PDT 24
Peak memory 200100 kb
Host smart-e8fba8a0-9e55-44fd-a9c2-6176a3c17b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274154311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1274154311
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1436285588
Short name T251
Test name
Test status
Simulation time 417140609557 ps
CPU time 902.59 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 07:12:29 PM PDT 24
Peak memory 225072 kb
Host smart-3bf85e06-352e-426a-8fa9-45c7420e49ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436285588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1436285588
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3860783177
Short name T155
Test name
Test status
Simulation time 15771888669 ps
CPU time 28.76 seconds
Started Jul 23 06:57:44 PM PDT 24
Finished Jul 23 06:58:14 PM PDT 24
Peak memory 200244 kb
Host smart-126399f0-5eed-422d-8a3e-32f2fa33fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860783177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3860783177
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3725838437
Short name T267
Test name
Test status
Simulation time 72530886104 ps
CPU time 102.21 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 06:59:32 PM PDT 24
Peak memory 200224 kb
Host smart-4bce3c70-f2a4-4bb0-9fc8-e6218688acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725838437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3725838437
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2651669037
Short name T1295
Test name
Test status
Simulation time 60244390 ps
CPU time 0.75 seconds
Started Jul 23 07:22:21 PM PDT 24
Finished Jul 23 07:22:22 PM PDT 24
Peak memory 197756 kb
Host smart-2b2e6966-9533-4de3-b810-f674c7baca81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651669037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2651669037
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1610075350
Short name T1222
Test name
Test status
Simulation time 68725091 ps
CPU time 0.57 seconds
Started Jul 23 07:22:20 PM PDT 24
Finished Jul 23 07:22:22 PM PDT 24
Peak memory 196316 kb
Host smart-a6f03677-3ab0-4926-916a-9e6ea3b76812
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610075350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1610075350
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1022909934
Short name T1255
Test name
Test status
Simulation time 31561037 ps
CPU time 0.89 seconds
Started Jul 23 07:22:23 PM PDT 24
Finished Jul 23 07:22:24 PM PDT 24
Peak memory 200796 kb
Host smart-3e0ef909-89d1-4b96-b849-257429675fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022909934 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1022909934
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.832823227
Short name T69
Test name
Test status
Simulation time 14221777 ps
CPU time 0.58 seconds
Started Jul 23 07:22:22 PM PDT 24
Finished Jul 23 07:22:24 PM PDT 24
Peak memory 196332 kb
Host smart-e7f31c58-aaa4-4ad3-bd1e-aa2874a37d8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832823227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.832823227
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3074053071
Short name T1306
Test name
Test status
Simulation time 45492516 ps
CPU time 0.59 seconds
Started Jul 23 07:22:21 PM PDT 24
Finished Jul 23 07:22:22 PM PDT 24
Peak memory 195320 kb
Host smart-c965f21d-7f2c-4e0a-ad15-7e12bea31238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074053071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3074053071
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1718797097
Short name T1291
Test name
Test status
Simulation time 38585779 ps
CPU time 0.64 seconds
Started Jul 23 07:22:22 PM PDT 24
Finished Jul 23 07:22:23 PM PDT 24
Peak memory 196288 kb
Host smart-b20ed8d5-e315-44fb-9037-6b70c884a7da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718797097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1718797097
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.135626976
Short name T1300
Test name
Test status
Simulation time 72465019 ps
CPU time 1.88 seconds
Started Jul 23 07:22:23 PM PDT 24
Finished Jul 23 07:22:25 PM PDT 24
Peak memory 200968 kb
Host smart-66134795-a0a0-4663-8e5a-a363c9cb7dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135626976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.135626976
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3928299402
Short name T1234
Test name
Test status
Simulation time 72125182 ps
CPU time 1.21 seconds
Started Jul 23 07:22:21 PM PDT 24
Finished Jul 23 07:22:22 PM PDT 24
Peak memory 200436 kb
Host smart-14dd948a-5a5f-4153-9170-21426c7065af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928299402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3928299402
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2426354145
Short name T1269
Test name
Test status
Simulation time 32647320 ps
CPU time 0.78 seconds
Started Jul 23 07:22:35 PM PDT 24
Finished Jul 23 07:22:37 PM PDT 24
Peak memory 196964 kb
Host smart-2833d85b-ed61-4b06-a553-d77689dddc57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426354145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2426354145
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2685398120
Short name T1218
Test name
Test status
Simulation time 251152028 ps
CPU time 2.57 seconds
Started Jul 23 07:22:29 PM PDT 24
Finished Jul 23 07:22:32 PM PDT 24
Peak memory 198552 kb
Host smart-2b9ec4d4-9bee-44d7-ad2b-81c94979e615
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685398120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2685398120
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2895581918
Short name T1219
Test name
Test status
Simulation time 18853088 ps
CPU time 0.62 seconds
Started Jul 23 07:22:28 PM PDT 24
Finished Jul 23 07:22:30 PM PDT 24
Peak memory 196352 kb
Host smart-55ab7e03-5925-4efa-bbdd-a4f6aea764f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895581918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2895581918
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2528727488
Short name T1188
Test name
Test status
Simulation time 50247866 ps
CPU time 0.69 seconds
Started Jul 23 07:22:37 PM PDT 24
Finished Jul 23 07:22:39 PM PDT 24
Peak memory 198776 kb
Host smart-4abf21be-a5da-44cf-a830-a052c9263162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528727488 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2528727488
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3290132199
Short name T67
Test name
Test status
Simulation time 144179940 ps
CPU time 0.57 seconds
Started Jul 23 07:22:29 PM PDT 24
Finished Jul 23 07:22:30 PM PDT 24
Peak memory 196504 kb
Host smart-a528b8d2-776b-49d3-a4d6-e5f0458c8aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290132199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3290132199
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4255468583
Short name T1231
Test name
Test status
Simulation time 13968843 ps
CPU time 0.59 seconds
Started Jul 23 07:22:27 PM PDT 24
Finished Jul 23 07:22:28 PM PDT 24
Peak memory 195292 kb
Host smart-39d8cd98-96a9-435d-acb9-424eddb32189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255468583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4255468583
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2626277856
Short name T1223
Test name
Test status
Simulation time 181659646 ps
CPU time 0.79 seconds
Started Jul 23 07:22:36 PM PDT 24
Finished Jul 23 07:22:37 PM PDT 24
Peak memory 197864 kb
Host smart-4e09648f-9219-4c00-beac-cd775744d290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626277856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2626277856
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1191977343
Short name T1318
Test name
Test status
Simulation time 512484008 ps
CPU time 1.59 seconds
Started Jul 23 07:22:29 PM PDT 24
Finished Jul 23 07:22:31 PM PDT 24
Peak memory 200916 kb
Host smart-0ef06e81-b421-4560-a0b7-e522bf0dbbb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191977343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1191977343
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.293116067
Short name T1285
Test name
Test status
Simulation time 173376289 ps
CPU time 1.33 seconds
Started Jul 23 07:22:28 PM PDT 24
Finished Jul 23 07:22:30 PM PDT 24
Peak memory 200268 kb
Host smart-e6887060-57df-47cd-bb7a-4a9e807a8d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293116067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.293116067
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2341823482
Short name T1228
Test name
Test status
Simulation time 114719386 ps
CPU time 1.04 seconds
Started Jul 23 07:23:19 PM PDT 24
Finished Jul 23 07:23:21 PM PDT 24
Peak memory 201096 kb
Host smart-7a0c272c-fa84-490a-850a-5dc0525de81c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341823482 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2341823482
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2336457916
Short name T1256
Test name
Test status
Simulation time 23856007 ps
CPU time 0.58 seconds
Started Jul 23 07:23:21 PM PDT 24
Finished Jul 23 07:23:22 PM PDT 24
Peak memory 195332 kb
Host smart-37f7de36-a74d-4206-a5d2-d68f8dafc970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336457916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2336457916
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1267819900
Short name T1261
Test name
Test status
Simulation time 53947330 ps
CPU time 0.72 seconds
Started Jul 23 07:23:17 PM PDT 24
Finished Jul 23 07:23:18 PM PDT 24
Peak memory 197996 kb
Host smart-70741025-a708-4d32-a25b-74c8b7a90312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267819900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1267819900
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.867324778
Short name T1189
Test name
Test status
Simulation time 97811745 ps
CPU time 1.93 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:23 PM PDT 24
Peak memory 200988 kb
Host smart-f98b6d63-e5c1-4077-b287-76f1d4bac7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867324778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.867324778
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1238740508
Short name T104
Test name
Test status
Simulation time 4438896175 ps
CPU time 1.51 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:21 PM PDT 24
Peak memory 200808 kb
Host smart-122e9b0f-5ddd-402c-8057-bad4743f19ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238740508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1238740508
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3455733812
Short name T1230
Test name
Test status
Simulation time 97089403 ps
CPU time 0.8 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:19 PM PDT 24
Peak memory 200384 kb
Host smart-6d341f34-2f8c-45ec-9119-8cebfe6aa9f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455733812 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3455733812
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.255868228
Short name T1290
Test name
Test status
Simulation time 12108454 ps
CPU time 0.67 seconds
Started Jul 23 07:23:19 PM PDT 24
Finished Jul 23 07:23:20 PM PDT 24
Peak memory 196340 kb
Host smart-e012153b-d768-4e8e-832b-3179476759bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255868228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.255868228
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1807301625
Short name T1252
Test name
Test status
Simulation time 67511716 ps
CPU time 0.57 seconds
Started Jul 23 07:23:19 PM PDT 24
Finished Jul 23 07:23:20 PM PDT 24
Peak memory 194640 kb
Host smart-5c00995a-af20-4234-a48c-ecc6ce3643ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807301625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1807301625
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1702811461
Short name T95
Test name
Test status
Simulation time 92804244 ps
CPU time 0.65 seconds
Started Jul 23 07:23:19 PM PDT 24
Finished Jul 23 07:23:20 PM PDT 24
Peak memory 196168 kb
Host smart-cab5469b-a700-4344-a39c-7ea909b76835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702811461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1702811461
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2949571399
Short name T1205
Test name
Test status
Simulation time 169795629 ps
CPU time 1.1 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:20 PM PDT 24
Peak memory 200932 kb
Host smart-06e8a246-e377-4e9e-8818-1ccf90e8bd2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949571399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2949571399
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.954866878
Short name T100
Test name
Test status
Simulation time 155602228 ps
CPU time 1.28 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:22 PM PDT 24
Peak memory 200944 kb
Host smart-1c919423-d45d-47e1-9ebe-5f8680d576a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954866878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.954866878
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4259103537
Short name T1284
Test name
Test status
Simulation time 98210375 ps
CPU time 1.12 seconds
Started Jul 23 07:23:27 PM PDT 24
Finished Jul 23 07:23:30 PM PDT 24
Peak memory 200904 kb
Host smart-3b19e9b5-b8f6-4518-98c8-af3a67da733b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259103537 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4259103537
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.175070348
Short name T1214
Test name
Test status
Simulation time 59480815 ps
CPU time 0.58 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:19 PM PDT 24
Peak memory 196328 kb
Host smart-9fa45bdd-76ee-40e6-99a2-cc5890ffacc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175070348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.175070348
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1650290422
Short name T1201
Test name
Test status
Simulation time 14477602 ps
CPU time 0.57 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:22 PM PDT 24
Peak memory 195252 kb
Host smart-13122e5b-a31a-46e2-a967-f0c6e7a1a531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650290422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1650290422
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2824756637
Short name T1279
Test name
Test status
Simulation time 50729900 ps
CPU time 0.65 seconds
Started Jul 23 07:23:31 PM PDT 24
Finished Jul 23 07:23:33 PM PDT 24
Peak memory 196608 kb
Host smart-9a3c91b7-7d51-4766-ad6b-f6cdbacf93ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824756637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2824756637
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3629051086
Short name T1309
Test name
Test status
Simulation time 135783781 ps
CPU time 1.91 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:23 PM PDT 24
Peak memory 200892 kb
Host smart-59e37a59-465b-4234-afae-4d4c73ac02de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629051086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3629051086
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2655218365
Short name T1248
Test name
Test status
Simulation time 27439781 ps
CPU time 1.18 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 200976 kb
Host smart-6d720c86-8e16-4594-8f55-b1c29487b434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655218365 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2655218365
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2041404601
Short name T94
Test name
Test status
Simulation time 14550524 ps
CPU time 0.59 seconds
Started Jul 23 07:23:27 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 196360 kb
Host smart-4b2c2ecf-372e-413e-ba0b-6b443ef532f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041404601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2041404601
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.585775920
Short name T1221
Test name
Test status
Simulation time 69323012 ps
CPU time 0.55 seconds
Started Jul 23 07:23:27 PM PDT 24
Finished Jul 23 07:23:30 PM PDT 24
Peak memory 195244 kb
Host smart-ce3b7ac7-aac6-42d6-9d2b-f369cd00138d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585775920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.585775920
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.179071639
Short name T1283
Test name
Test status
Simulation time 79645937 ps
CPU time 0.71 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 197784 kb
Host smart-dafcf79a-7d93-4518-8823-07ddda10ac59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179071639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.179071639
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.590776034
Short name T1235
Test name
Test status
Simulation time 23715777 ps
CPU time 1.05 seconds
Started Jul 23 07:23:31 PM PDT 24
Finished Jul 23 07:23:33 PM PDT 24
Peak memory 200748 kb
Host smart-6e8bc845-b2df-4246-946f-72b79952acd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590776034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.590776034
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3495043688
Short name T1204
Test name
Test status
Simulation time 37750172 ps
CPU time 0.98 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 200696 kb
Host smart-0525c649-f010-4a93-885e-b3d39c3e8677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495043688 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3495043688
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2046461863
Short name T1246
Test name
Test status
Simulation time 13198061 ps
CPU time 0.62 seconds
Started Jul 23 07:23:27 PM PDT 24
Finished Jul 23 07:23:30 PM PDT 24
Peak memory 196332 kb
Host smart-4f2aef7b-87d6-4fc4-ab7f-b37797391410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046461863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2046461863
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2864873573
Short name T1196
Test name
Test status
Simulation time 17909400 ps
CPU time 0.56 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 195300 kb
Host smart-7baad800-aae7-4f81-88cb-6432afade7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864873573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2864873573
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4204728914
Short name T1217
Test name
Test status
Simulation time 52764336 ps
CPU time 0.62 seconds
Started Jul 23 07:23:29 PM PDT 24
Finished Jul 23 07:23:31 PM PDT 24
Peak memory 196536 kb
Host smart-7ad673ec-5725-45a0-92db-48ce472257ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204728914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4204728914
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1706882655
Short name T1202
Test name
Test status
Simulation time 93487440 ps
CPU time 2.05 seconds
Started Jul 23 07:23:29 PM PDT 24
Finished Jul 23 07:23:32 PM PDT 24
Peak memory 200912 kb
Host smart-e6e3567c-dbde-4c4c-b3a0-5c9e1254ad34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706882655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1706882655
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2891761482
Short name T103
Test name
Test status
Simulation time 97223639 ps
CPU time 1.38 seconds
Started Jul 23 07:23:28 PM PDT 24
Finished Jul 23 07:23:31 PM PDT 24
Peak memory 200108 kb
Host smart-ab9d5f2c-2bdf-462b-9188-735777574129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891761482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2891761482
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1941735387
Short name T1267
Test name
Test status
Simulation time 25674484 ps
CPU time 0.89 seconds
Started Jul 23 07:23:41 PM PDT 24
Finished Jul 23 07:23:43 PM PDT 24
Peak memory 200688 kb
Host smart-05c5ee60-872d-4dd3-bafc-edf726dac53b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941735387 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1941735387
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2603332950
Short name T1215
Test name
Test status
Simulation time 13445162 ps
CPU time 0.6 seconds
Started Jul 23 07:23:36 PM PDT 24
Finished Jul 23 07:23:37 PM PDT 24
Peak memory 196348 kb
Host smart-42d4a659-4b9a-403b-97db-707ff3a5c578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603332950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2603332950
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4265640929
Short name T1236
Test name
Test status
Simulation time 42824881 ps
CPU time 0.66 seconds
Started Jul 23 07:23:37 PM PDT 24
Finished Jul 23 07:23:38 PM PDT 24
Peak memory 195332 kb
Host smart-9fd029df-33e9-40c4-a677-3cf3864b9bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265640929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4265640929
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1558214138
Short name T96
Test name
Test status
Simulation time 51206399 ps
CPU time 0.67 seconds
Started Jul 23 07:23:33 PM PDT 24
Finished Jul 23 07:23:34 PM PDT 24
Peak memory 196596 kb
Host smart-86eb8a13-cd08-4ddf-ba1c-bb00bc71816d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558214138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1558214138
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3635527362
Short name T1317
Test name
Test status
Simulation time 69470145 ps
CPU time 1.06 seconds
Started Jul 23 07:23:26 PM PDT 24
Finished Jul 23 07:23:29 PM PDT 24
Peak memory 200800 kb
Host smart-a36e8a03-c643-4f7a-bb0d-89c350cc72e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635527362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3635527362
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.639865069
Short name T101
Test name
Test status
Simulation time 149574990 ps
CPU time 1.26 seconds
Started Jul 23 07:23:27 PM PDT 24
Finished Jul 23 07:23:31 PM PDT 24
Peak memory 200136 kb
Host smart-25f7aafa-3de0-45f2-960f-d8e34db521da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639865069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.639865069
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2696523720
Short name T1302
Test name
Test status
Simulation time 105479966 ps
CPU time 0.74 seconds
Started Jul 23 07:23:41 PM PDT 24
Finished Jul 23 07:23:43 PM PDT 24
Peak memory 198940 kb
Host smart-1bb45414-9979-4f88-9723-8900473edc25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696523720 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2696523720
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4211823335
Short name T1311
Test name
Test status
Simulation time 47071658 ps
CPU time 0.67 seconds
Started Jul 23 07:23:41 PM PDT 24
Finished Jul 23 07:23:43 PM PDT 24
Peak memory 196624 kb
Host smart-7d749bb8-d227-4f6a-9213-d33c4b6f1964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211823335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4211823335
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4051963387
Short name T1206
Test name
Test status
Simulation time 18519956 ps
CPU time 0.58 seconds
Started Jul 23 07:23:35 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 195336 kb
Host smart-36b636c8-f465-452f-b308-6666994e89d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051963387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4051963387
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2999281979
Short name T90
Test name
Test status
Simulation time 21578441 ps
CPU time 0.67 seconds
Started Jul 23 07:23:35 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 196644 kb
Host smart-54436d81-693f-4868-9be9-f127b7530281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999281979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2999281979
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1777158855
Short name T1293
Test name
Test status
Simulation time 193009695 ps
CPU time 2.05 seconds
Started Jul 23 07:23:36 PM PDT 24
Finished Jul 23 07:23:39 PM PDT 24
Peak memory 200940 kb
Host smart-ba994bf9-fe80-4f9c-b136-9ced9988679b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777158855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1777158855
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.969721900
Short name T150
Test name
Test status
Simulation time 69644418 ps
CPU time 1.29 seconds
Started Jul 23 07:23:34 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 200348 kb
Host smart-4b771394-5bc1-4c71-9837-6b9b8f3a52a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969721900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.969721900
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1839369397
Short name T1274
Test name
Test status
Simulation time 103563237 ps
CPU time 1.02 seconds
Started Jul 23 07:23:34 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 200720 kb
Host smart-521f6e91-cc12-4bf8-a5f3-c61f7feacd4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839369397 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1839369397
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.560961337
Short name T1243
Test name
Test status
Simulation time 23343763 ps
CPU time 0.59 seconds
Started Jul 23 07:23:35 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 196320 kb
Host smart-5103ad04-8695-42ba-a4c6-75de2a8a0b22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560961337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.560961337
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.110030974
Short name T1197
Test name
Test status
Simulation time 14811279 ps
CPU time 0.56 seconds
Started Jul 23 07:23:33 PM PDT 24
Finished Jul 23 07:23:34 PM PDT 24
Peak memory 195280 kb
Host smart-166e2491-ad60-4b62-b544-2ac0aa5114f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110030974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.110030974
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2688260579
Short name T1226
Test name
Test status
Simulation time 31065568 ps
CPU time 0.76 seconds
Started Jul 23 07:23:36 PM PDT 24
Finished Jul 23 07:23:37 PM PDT 24
Peak memory 197964 kb
Host smart-1941b3e6-1636-4457-82ee-25d6cbb67a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688260579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2688260579
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1132890724
Short name T1259
Test name
Test status
Simulation time 36403354 ps
CPU time 1.84 seconds
Started Jul 23 07:23:36 PM PDT 24
Finished Jul 23 07:23:39 PM PDT 24
Peak memory 200976 kb
Host smart-9b12ab3c-32eb-4277-b0a7-9a9d4b4c9ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132890724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1132890724
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1335569738
Short name T105
Test name
Test status
Simulation time 615319034 ps
CPU time 1.56 seconds
Started Jul 23 07:23:36 PM PDT 24
Finished Jul 23 07:23:38 PM PDT 24
Peak memory 200288 kb
Host smart-010a0bdb-b140-48e9-be37-bd4a02340812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335569738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1335569738
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.517464139
Short name T1199
Test name
Test status
Simulation time 108016981 ps
CPU time 0.82 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 200708 kb
Host smart-e0de776d-3f5e-4d89-84b3-3569f8a6544f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517464139 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.517464139
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3429930293
Short name T1227
Test name
Test status
Simulation time 53020912 ps
CPU time 0.6 seconds
Started Jul 23 07:23:37 PM PDT 24
Finished Jul 23 07:23:39 PM PDT 24
Peak memory 196416 kb
Host smart-95e6782c-ad53-4764-88b6-11842c95ae27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429930293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3429930293
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3793839855
Short name T1254
Test name
Test status
Simulation time 46094555 ps
CPU time 0.59 seconds
Started Jul 23 07:23:35 PM PDT 24
Finished Jul 23 07:23:37 PM PDT 24
Peak memory 195236 kb
Host smart-ebb47537-1bc7-4e0b-bc83-aef53bacb998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793839855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3793839855
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1065548725
Short name T1225
Test name
Test status
Simulation time 64853335 ps
CPU time 0.73 seconds
Started Jul 23 07:23:37 PM PDT 24
Finished Jul 23 07:23:39 PM PDT 24
Peak memory 197916 kb
Host smart-907c3c2a-13f2-4178-a004-cce69c21785b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065548725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1065548725
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.400366293
Short name T1193
Test name
Test status
Simulation time 110731620 ps
CPU time 2.19 seconds
Started Jul 23 07:23:35 PM PDT 24
Finished Jul 23 07:23:37 PM PDT 24
Peak memory 200872 kb
Host smart-9fce2d57-3481-4e0a-b410-e090cd27afb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400366293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.400366293
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2343083269
Short name T1249
Test name
Test status
Simulation time 365077829 ps
CPU time 0.97 seconds
Started Jul 23 07:23:33 PM PDT 24
Finished Jul 23 07:23:35 PM PDT 24
Peak memory 200100 kb
Host smart-fad6cbd8-42e7-4093-90d9-10677eaa7847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343083269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2343083269
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2784896624
Short name T1301
Test name
Test status
Simulation time 31493699 ps
CPU time 0.67 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 198028 kb
Host smart-ebd43e67-6886-42c3-ac3a-a688ddfe5119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784896624 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2784896624
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.885562534
Short name T1209
Test name
Test status
Simulation time 22550423 ps
CPU time 0.59 seconds
Started Jul 23 07:23:45 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 196288 kb
Host smart-f745c839-c18b-4de7-9eb8-97459f299d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885562534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.885562534
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.920176098
Short name T1250
Test name
Test status
Simulation time 12614271 ps
CPU time 0.56 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:45 PM PDT 24
Peak memory 195352 kb
Host smart-94744f59-0096-410b-bd31-aeabf875b0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920176098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.920176098
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3334690076
Short name T1242
Test name
Test status
Simulation time 23422075 ps
CPU time 0.71 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:45 PM PDT 24
Peak memory 197952 kb
Host smart-9d1affa0-acc7-47a2-b079-1ff595308f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334690076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3334690076
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.4150865850
Short name T1265
Test name
Test status
Simulation time 42989500 ps
CPU time 2.16 seconds
Started Jul 23 07:23:43 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 200984 kb
Host smart-0cd45877-afba-4e3d-bfe9-5879c2a0ca63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150865850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.4150865850
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1231710580
Short name T106
Test name
Test status
Simulation time 86738091 ps
CPU time 1.28 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 200252 kb
Host smart-af8cd348-f7d0-477e-b373-df5961eea8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231710580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1231710580
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2120377315
Short name T1273
Test name
Test status
Simulation time 157397027 ps
CPU time 0.65 seconds
Started Jul 23 07:22:42 PM PDT 24
Finished Jul 23 07:22:44 PM PDT 24
Peak memory 196324 kb
Host smart-3ea954ed-5a16-433d-b720-a8dc0ffcd974
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120377315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2120377315
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3787548788
Short name T65
Test name
Test status
Simulation time 59067586 ps
CPU time 2.21 seconds
Started Jul 23 07:22:34 PM PDT 24
Finished Jul 23 07:22:38 PM PDT 24
Peak memory 198176 kb
Host smart-0d213c2c-01cf-4dbf-b29e-a4d7ec342090
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787548788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3787548788
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3203153536
Short name T1251
Test name
Test status
Simulation time 76941677 ps
CPU time 0.61 seconds
Started Jul 23 07:22:36 PM PDT 24
Finished Jul 23 07:22:37 PM PDT 24
Peak memory 196308 kb
Host smart-b049833d-93e5-4c00-9bae-402b05be976b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203153536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3203153536
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1838329181
Short name T1282
Test name
Test status
Simulation time 37484090 ps
CPU time 0.92 seconds
Started Jul 23 07:22:41 PM PDT 24
Finished Jul 23 07:22:42 PM PDT 24
Peak memory 200736 kb
Host smart-066bce27-e502-4037-9ad3-97eb684aa534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838329181 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1838329181
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2366114721
Short name T1294
Test name
Test status
Simulation time 36248809 ps
CPU time 0.57 seconds
Started Jul 23 07:22:36 PM PDT 24
Finished Jul 23 07:22:38 PM PDT 24
Peak memory 196268 kb
Host smart-57ccfa30-ef2d-493c-beb6-b99708025922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366114721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2366114721
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1738810144
Short name T1239
Test name
Test status
Simulation time 18874188 ps
CPU time 0.58 seconds
Started Jul 23 07:22:34 PM PDT 24
Finished Jul 23 07:22:36 PM PDT 24
Peak memory 195292 kb
Host smart-8f4fc0cc-2c82-4865-a9a0-9cf4f6f8dcc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738810144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1738810144
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4284309906
Short name T1272
Test name
Test status
Simulation time 101739645 ps
CPU time 0.62 seconds
Started Jul 23 07:22:42 PM PDT 24
Finished Jul 23 07:22:44 PM PDT 24
Peak memory 195708 kb
Host smart-29ddd141-74a6-4949-8741-e46ea8ce4407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284309906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.4284309906
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.765469724
Short name T1276
Test name
Test status
Simulation time 95709525 ps
CPU time 0.86 seconds
Started Jul 23 07:22:38 PM PDT 24
Finished Jul 23 07:22:39 PM PDT 24
Peak memory 200552 kb
Host smart-9ffc8e92-b0d3-4e15-908a-0ac9fa2798d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765469724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.765469724
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2257419231
Short name T148
Test name
Test status
Simulation time 110964410 ps
CPU time 0.95 seconds
Started Jul 23 07:22:35 PM PDT 24
Finished Jul 23 07:22:37 PM PDT 24
Peak memory 200076 kb
Host smart-09e311e2-766c-4ed0-9e4d-19ce6298240e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257419231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2257419231
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3557657895
Short name T1244
Test name
Test status
Simulation time 15574786 ps
CPU time 0.61 seconds
Started Jul 23 07:23:43 PM PDT 24
Finished Jul 23 07:23:44 PM PDT 24
Peak memory 195212 kb
Host smart-7cfbe876-46f9-47dc-a7eb-725aec8605c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557657895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3557657895
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2968409742
Short name T1194
Test name
Test status
Simulation time 18679452 ps
CPU time 0.57 seconds
Started Jul 23 07:23:44 PM PDT 24
Finished Jul 23 07:23:46 PM PDT 24
Peak memory 195264 kb
Host smart-84755148-8165-49e8-a495-03cfc6d62b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968409742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2968409742
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.465272915
Short name T1203
Test name
Test status
Simulation time 29630632 ps
CPU time 0.57 seconds
Started Jul 23 07:23:43 PM PDT 24
Finished Jul 23 07:23:45 PM PDT 24
Peak memory 195204 kb
Host smart-98ecedbc-44f5-4f78-b01c-9e22176191a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465272915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.465272915
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3272187263
Short name T1195
Test name
Test status
Simulation time 17510244 ps
CPU time 0.57 seconds
Started Jul 23 07:23:43 PM PDT 24
Finished Jul 23 07:23:45 PM PDT 24
Peak memory 195316 kb
Host smart-6b9bcf6f-e2dd-466f-adc2-fe3fcf86788d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272187263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3272187263
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1733589976
Short name T1286
Test name
Test status
Simulation time 53681205 ps
CPU time 0.56 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 195308 kb
Host smart-e540ff75-03fd-4e58-9db5-eed2673fd109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733589976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1733589976
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2432051654
Short name T1268
Test name
Test status
Simulation time 26413788 ps
CPU time 0.59 seconds
Started Jul 23 07:23:51 PM PDT 24
Finished Jul 23 07:23:53 PM PDT 24
Peak memory 195236 kb
Host smart-31507833-832b-4a08-a5e4-c413cabccbcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432051654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2432051654
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2593769658
Short name T1260
Test name
Test status
Simulation time 22322748 ps
CPU time 0.57 seconds
Started Jul 23 07:23:50 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195300 kb
Host smart-583abcb0-cc08-4361-a91f-3ea38d555379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593769658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2593769658
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1913220733
Short name T1186
Test name
Test status
Simulation time 43776124 ps
CPU time 0.56 seconds
Started Jul 23 07:23:48 PM PDT 24
Finished Jul 23 07:23:50 PM PDT 24
Peak memory 195324 kb
Host smart-2822e7f2-e825-430c-ac13-e60809b54777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913220733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1913220733
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2993407064
Short name T1210
Test name
Test status
Simulation time 28408989 ps
CPU time 0.56 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195224 kb
Host smart-f8c9b0e8-9983-4853-b822-a27712088860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993407064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2993407064
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.20411140
Short name T1211
Test name
Test status
Simulation time 39072693 ps
CPU time 0.57 seconds
Started Jul 23 07:23:50 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195324 kb
Host smart-de796527-1c7a-47d1-96d4-d77531c35dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.20411140
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3025783329
Short name T1245
Test name
Test status
Simulation time 59100009 ps
CPU time 0.74 seconds
Started Jul 23 07:22:44 PM PDT 24
Finished Jul 23 07:22:45 PM PDT 24
Peak memory 197124 kb
Host smart-90d48ef7-99ea-4bd6-be8f-315c7bd5056b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025783329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3025783329
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2119564465
Short name T1299
Test name
Test status
Simulation time 166201887 ps
CPU time 1.48 seconds
Started Jul 23 07:22:41 PM PDT 24
Finished Jul 23 07:22:43 PM PDT 24
Peak memory 198540 kb
Host smart-4e62fd0f-8eb6-47b0-9f6f-4c5dce5c0a80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119564465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2119564465
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3025437712
Short name T1304
Test name
Test status
Simulation time 44247631 ps
CPU time 0.57 seconds
Started Jul 23 07:22:40 PM PDT 24
Finished Jul 23 07:22:41 PM PDT 24
Peak memory 196332 kb
Host smart-faffd055-9d33-4dd9-988d-395d860d5e7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025437712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3025437712
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.217865668
Short name T1266
Test name
Test status
Simulation time 70282119 ps
CPU time 0.65 seconds
Started Jul 23 07:22:49 PM PDT 24
Finished Jul 23 07:22:51 PM PDT 24
Peak memory 198488 kb
Host smart-2daddc2d-7b2c-4857-b830-8df6dc090b54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217865668 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.217865668
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2355268218
Short name T64
Test name
Test status
Simulation time 14489804 ps
CPU time 0.6 seconds
Started Jul 23 07:22:44 PM PDT 24
Finished Jul 23 07:22:45 PM PDT 24
Peak memory 196344 kb
Host smart-5dc38fb8-b2e3-4d5f-8255-9f000e95b99c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355268218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2355268218
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2292911979
Short name T1262
Test name
Test status
Simulation time 10509299 ps
CPU time 0.6 seconds
Started Jul 23 07:22:45 PM PDT 24
Finished Jul 23 07:22:46 PM PDT 24
Peak memory 195324 kb
Host smart-80119029-4cf6-4b8a-b63f-8a1f95a8b4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292911979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2292911979
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1505130860
Short name T89
Test name
Test status
Simulation time 27783397 ps
CPU time 0.79 seconds
Started Jul 23 07:22:49 PM PDT 24
Finished Jul 23 07:22:52 PM PDT 24
Peak memory 197988 kb
Host smart-4784527a-6c48-496b-97c4-e9ba883e3220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505130860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1505130860
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3113515048
Short name T1190
Test name
Test status
Simulation time 270422526 ps
CPU time 2.37 seconds
Started Jul 23 07:22:41 PM PDT 24
Finished Jul 23 07:22:44 PM PDT 24
Peak memory 200940 kb
Host smart-98bd1e04-f930-445a-94a3-bb2f8f03357d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113515048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3113515048
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1352920039
Short name T1308
Test name
Test status
Simulation time 56584867 ps
CPU time 0.99 seconds
Started Jul 23 07:22:41 PM PDT 24
Finished Jul 23 07:22:42 PM PDT 24
Peak memory 200040 kb
Host smart-b715a2d0-00eb-4d90-988f-8c3123310500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352920039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1352920039
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.507605596
Short name T1270
Test name
Test status
Simulation time 24963350 ps
CPU time 0.57 seconds
Started Jul 23 07:23:50 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195288 kb
Host smart-02484e9f-5663-42b2-8b72-a2341668b42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507605596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.507605596
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3840769757
Short name T1280
Test name
Test status
Simulation time 14258957 ps
CPU time 0.56 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195332 kb
Host smart-5dead570-59da-4774-bce1-5d62fcb7ee2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840769757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3840769757
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2136881531
Short name T1275
Test name
Test status
Simulation time 12966523 ps
CPU time 0.56 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:24:00 PM PDT 24
Peak memory 195236 kb
Host smart-cdaa3850-0fa8-4a28-8f5d-380a9d083168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136881531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2136881531
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1736736368
Short name T1213
Test name
Test status
Simulation time 15449039 ps
CPU time 0.59 seconds
Started Jul 23 07:23:50 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195228 kb
Host smart-8d81fdb0-4b98-4fd5-b16f-e2c35143a0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736736368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1736736368
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.628297212
Short name T1216
Test name
Test status
Simulation time 12898720 ps
CPU time 0.57 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195404 kb
Host smart-c4d90c44-fe4c-42c0-ae4d-a0f38689b71f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628297212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.628297212
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4016536690
Short name T1200
Test name
Test status
Simulation time 15223773 ps
CPU time 0.6 seconds
Started Jul 23 07:23:50 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195292 kb
Host smart-73a8b58b-56b1-42f1-9b96-34038334eaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016536690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4016536690
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2694244992
Short name T1187
Test name
Test status
Simulation time 21816720 ps
CPU time 0.59 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195324 kb
Host smart-7a4f3cb3-e53b-437f-a598-b9d955468e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694244992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2694244992
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.308190493
Short name T1298
Test name
Test status
Simulation time 28357893 ps
CPU time 0.56 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195312 kb
Host smart-f384159e-6a0b-46ac-97ef-58dbcf4730e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308190493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.308190493
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.669756335
Short name T1208
Test name
Test status
Simulation time 11664787 ps
CPU time 0.58 seconds
Started Jul 23 07:23:48 PM PDT 24
Finished Jul 23 07:23:49 PM PDT 24
Peak memory 195288 kb
Host smart-e0e30c7d-7ec8-446f-b04a-711412fa4bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669756335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.669756335
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4092121468
Short name T1198
Test name
Test status
Simulation time 23516093 ps
CPU time 0.56 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 195300 kb
Host smart-9bf5c57b-e107-416c-b52e-25535666d083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092121468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4092121468
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.557951366
Short name T1314
Test name
Test status
Simulation time 21059413 ps
CPU time 0.68 seconds
Started Jul 23 07:22:50 PM PDT 24
Finished Jul 23 07:22:52 PM PDT 24
Peak memory 196324 kb
Host smart-731c74fc-ab0e-4817-a039-9183042eda67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557951366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.557951366
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1758035949
Short name T1233
Test name
Test status
Simulation time 263620244 ps
CPU time 2.42 seconds
Started Jul 23 07:22:48 PM PDT 24
Finished Jul 23 07:22:51 PM PDT 24
Peak memory 198876 kb
Host smart-058c13f9-fb18-4869-ae22-53f473d14933
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758035949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1758035949
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.944091000
Short name T68
Test name
Test status
Simulation time 55876840 ps
CPU time 0.6 seconds
Started Jul 23 07:22:48 PM PDT 24
Finished Jul 23 07:22:49 PM PDT 24
Peak memory 196316 kb
Host smart-225624db-0f74-4abe-9e7f-00ada3508c1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944091000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.944091000
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2593943134
Short name T1277
Test name
Test status
Simulation time 137862612 ps
CPU time 1.08 seconds
Started Jul 23 07:22:58 PM PDT 24
Finished Jul 23 07:23:01 PM PDT 24
Peak memory 200692 kb
Host smart-7eb15f59-0997-4a72-992b-e6b7de332b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593943134 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2593943134
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3536694703
Short name T88
Test name
Test status
Simulation time 12799995 ps
CPU time 0.61 seconds
Started Jul 23 07:22:51 PM PDT 24
Finished Jul 23 07:22:52 PM PDT 24
Peak memory 196344 kb
Host smart-10d728a0-1738-40e0-998c-fc4433a0d1b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536694703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3536694703
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.123748475
Short name T1264
Test name
Test status
Simulation time 22961303 ps
CPU time 0.56 seconds
Started Jul 23 07:22:50 PM PDT 24
Finished Jul 23 07:22:52 PM PDT 24
Peak memory 195264 kb
Host smart-a3cdbf52-fb43-4605-89cc-e9f4ef244351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123748475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.123748475
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4009101732
Short name T92
Test name
Test status
Simulation time 51491762 ps
CPU time 0.73 seconds
Started Jul 23 07:22:57 PM PDT 24
Finished Jul 23 07:22:59 PM PDT 24
Peak memory 197852 kb
Host smart-70da9eb6-2fca-4e4b-91e1-c61a1b10b5d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009101732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4009101732
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.840868084
Short name T1310
Test name
Test status
Simulation time 393833548 ps
CPU time 2.2 seconds
Started Jul 23 07:22:49 PM PDT 24
Finished Jul 23 07:22:53 PM PDT 24
Peak memory 200988 kb
Host smart-3b89626b-bed3-4e98-a09a-7f70eef6ded7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840868084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.840868084
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.741560824
Short name T1297
Test name
Test status
Simulation time 45437826 ps
CPU time 0.94 seconds
Started Jul 23 07:22:51 PM PDT 24
Finished Jul 23 07:22:53 PM PDT 24
Peak memory 199836 kb
Host smart-2f91aed4-c90b-4b26-be9b-1f9f28999bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741560824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.741560824
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.546269495
Short name T1192
Test name
Test status
Simulation time 14175602 ps
CPU time 0.57 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195248 kb
Host smart-9c6a3c66-b9a5-4c34-88e6-1cbd93746204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546269495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.546269495
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3458284934
Short name T1185
Test name
Test status
Simulation time 17108568 ps
CPU time 0.56 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:23:59 PM PDT 24
Peak memory 195236 kb
Host smart-fcbf22f3-281f-4e54-b002-ca88e81058ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458284934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3458284934
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1802025550
Short name T1305
Test name
Test status
Simulation time 12436990 ps
CPU time 0.56 seconds
Started Jul 23 07:23:48 PM PDT 24
Finished Jul 23 07:23:50 PM PDT 24
Peak memory 195164 kb
Host smart-b360ab40-c8d3-42c1-b793-236c2d52fd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802025550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1802025550
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3315255054
Short name T1191
Test name
Test status
Simulation time 23556650 ps
CPU time 0.59 seconds
Started Jul 23 07:23:51 PM PDT 24
Finished Jul 23 07:23:52 PM PDT 24
Peak memory 195220 kb
Host smart-f7d30783-7fc4-4fe3-a943-0822b989df76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315255054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3315255054
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1377096411
Short name T1241
Test name
Test status
Simulation time 13106786 ps
CPU time 0.56 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195312 kb
Host smart-21ad13e4-5bdc-4104-bebe-431d763f5460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377096411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1377096411
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3545433809
Short name T1281
Test name
Test status
Simulation time 11611279 ps
CPU time 0.58 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195484 kb
Host smart-faa7bdc7-5013-431b-add1-851dc556466f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545433809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3545433809
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.617478068
Short name T1247
Test name
Test status
Simulation time 28917058 ps
CPU time 0.55 seconds
Started Jul 23 07:23:58 PM PDT 24
Finished Jul 23 07:24:00 PM PDT 24
Peak memory 195316 kb
Host smart-8da0fa22-c6c5-4c3f-bf9a-c87514fa5fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617478068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.617478068
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.869707298
Short name T1207
Test name
Test status
Simulation time 121658726 ps
CPU time 0.59 seconds
Started Jul 23 07:23:49 PM PDT 24
Finished Jul 23 07:23:51 PM PDT 24
Peak memory 195264 kb
Host smart-463d718d-1a62-42c6-a14c-c638f7ebc75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869707298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.869707298
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2266841680
Short name T1183
Test name
Test status
Simulation time 14174777 ps
CPU time 0.57 seconds
Started Jul 23 07:23:55 PM PDT 24
Finished Jul 23 07:23:56 PM PDT 24
Peak memory 195292 kb
Host smart-af11e7dc-a300-46d2-bd88-31c737340544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266841680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2266841680
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1034560126
Short name T1232
Test name
Test status
Simulation time 29189397 ps
CPU time 0.56 seconds
Started Jul 23 07:23:56 PM PDT 24
Finished Jul 23 07:23:57 PM PDT 24
Peak memory 195276 kb
Host smart-36e3794d-6a57-47c4-98a6-28cc0053338b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034560126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1034560126
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1740975357
Short name T1307
Test name
Test status
Simulation time 72755125 ps
CPU time 0.66 seconds
Started Jul 23 07:23:00 PM PDT 24
Finished Jul 23 07:23:02 PM PDT 24
Peak memory 198464 kb
Host smart-882d055b-52ff-4086-b73c-a70fde0673ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740975357 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1740975357
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.14328024
Short name T1287
Test name
Test status
Simulation time 17050182 ps
CPU time 0.56 seconds
Started Jul 23 07:22:59 PM PDT 24
Finished Jul 23 07:23:01 PM PDT 24
Peak memory 196296 kb
Host smart-724da728-0313-4441-8803-269b317393b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14328024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.14328024
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.539838707
Short name T1303
Test name
Test status
Simulation time 13617838 ps
CPU time 0.56 seconds
Started Jul 23 07:23:00 PM PDT 24
Finished Jul 23 07:23:02 PM PDT 24
Peak memory 195208 kb
Host smart-7203365e-1e31-4cb5-93d9-96fcfbd2739a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539838707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.539838707
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4030032822
Short name T1313
Test name
Test status
Simulation time 122975500 ps
CPU time 0.66 seconds
Started Jul 23 07:22:59 PM PDT 24
Finished Jul 23 07:23:01 PM PDT 24
Peak memory 196420 kb
Host smart-56907f25-2333-41ce-aa08-3df2fd67296b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030032822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4030032822
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3683931330
Short name T1220
Test name
Test status
Simulation time 451544878 ps
CPU time 2.26 seconds
Started Jul 23 07:22:58 PM PDT 24
Finished Jul 23 07:23:01 PM PDT 24
Peak memory 200960 kb
Host smart-e8a69347-0b1d-40bd-85b5-ce6cfacaa777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683931330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3683931330
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1541489067
Short name T1238
Test name
Test status
Simulation time 72669971 ps
CPU time 1.43 seconds
Started Jul 23 07:23:00 PM PDT 24
Finished Jul 23 07:23:02 PM PDT 24
Peak memory 200444 kb
Host smart-7f5d545d-2fb0-48f2-9bba-42fe114e505f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541489067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1541489067
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2486548221
Short name T1271
Test name
Test status
Simulation time 95289980 ps
CPU time 0.81 seconds
Started Jul 23 07:23:09 PM PDT 24
Finished Jul 23 07:23:11 PM PDT 24
Peak memory 200744 kb
Host smart-d3f30743-8174-4f43-9897-51f2103bc141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486548221 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2486548221
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3234161617
Short name T93
Test name
Test status
Simulation time 25721668 ps
CPU time 0.61 seconds
Started Jul 23 07:22:59 PM PDT 24
Finished Jul 23 07:23:00 PM PDT 24
Peak memory 196592 kb
Host smart-5ae8d8d3-a14a-498a-ab5c-0496762bcea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234161617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3234161617
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1489030880
Short name T1278
Test name
Test status
Simulation time 35860446 ps
CPU time 0.61 seconds
Started Jul 23 07:22:59 PM PDT 24
Finished Jul 23 07:23:01 PM PDT 24
Peak memory 195224 kb
Host smart-59d38ea5-b995-471b-b7ae-73ed9ab90bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489030880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1489030880
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.993229814
Short name T1237
Test name
Test status
Simulation time 23834848 ps
CPU time 0.66 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 195564 kb
Host smart-14263766-e37b-456b-ad54-857962c5ee7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993229814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.993229814
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2723144438
Short name T1316
Test name
Test status
Simulation time 187841631 ps
CPU time 1.06 seconds
Started Jul 23 07:22:58 PM PDT 24
Finished Jul 23 07:23:00 PM PDT 24
Peak memory 200840 kb
Host smart-a40e15c1-cf0d-4776-8118-12f3a2f1a594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723144438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2723144438
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2845868783
Short name T99
Test name
Test status
Simulation time 291906957 ps
CPU time 1.3 seconds
Started Jul 23 07:22:58 PM PDT 24
Finished Jul 23 07:23:00 PM PDT 24
Peak memory 200180 kb
Host smart-f0cc2c2b-5aab-49c0-bca4-b2fc89d801c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845868783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2845868783
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3551120856
Short name T1212
Test name
Test status
Simulation time 24703876 ps
CPU time 0.75 seconds
Started Jul 23 07:23:09 PM PDT 24
Finished Jul 23 07:23:10 PM PDT 24
Peak memory 199644 kb
Host smart-846942a5-c15d-4f01-a05e-9ebcf4c067b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551120856 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3551120856
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1353250062
Short name T1253
Test name
Test status
Simulation time 18793372 ps
CPU time 0.57 seconds
Started Jul 23 07:23:11 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 196344 kb
Host smart-82042d4a-91ad-41ff-a690-342e1984c114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353250062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1353250062
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1702521725
Short name T1263
Test name
Test status
Simulation time 16195248 ps
CPU time 0.56 seconds
Started Jul 23 07:23:08 PM PDT 24
Finished Jul 23 07:23:09 PM PDT 24
Peak memory 195340 kb
Host smart-69844f34-5ee6-436d-a1b2-bdd918ec09df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702521725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1702521725
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3430908124
Short name T1292
Test name
Test status
Simulation time 26987762 ps
CPU time 0.7 seconds
Started Jul 23 07:23:08 PM PDT 24
Finished Jul 23 07:23:10 PM PDT 24
Peak memory 197880 kb
Host smart-6787afcf-46bb-4b8f-b3eb-dbda905958ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430908124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3430908124
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2510605781
Short name T1240
Test name
Test status
Simulation time 96748682 ps
CPU time 1.33 seconds
Started Jul 23 07:23:08 PM PDT 24
Finished Jul 23 07:23:11 PM PDT 24
Peak memory 200968 kb
Host smart-1834b1df-7c17-4a04-b557-23a41b7dc1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510605781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2510605781
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3294755524
Short name T1288
Test name
Test status
Simulation time 74107572 ps
CPU time 1.24 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 200352 kb
Host smart-5833ca65-7b1a-4587-b389-e2f3d755cbe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294755524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3294755524
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2121298163
Short name T1312
Test name
Test status
Simulation time 96843550 ps
CPU time 1.4 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 200976 kb
Host smart-6fb3a7e1-137c-41f2-b063-83eb99e020f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121298163 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2121298163
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.4282187850
Short name T1258
Test name
Test status
Simulation time 35407410 ps
CPU time 0.61 seconds
Started Jul 23 07:23:09 PM PDT 24
Finished Jul 23 07:23:10 PM PDT 24
Peak memory 196300 kb
Host smart-198e349a-2c53-409d-b97b-1009c92eb5d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282187850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4282187850
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.218575700
Short name T1229
Test name
Test status
Simulation time 40828254 ps
CPU time 0.56 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 195332 kb
Host smart-eb623e92-fac3-429e-ab00-0157e26967e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218575700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.218575700
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3691862425
Short name T91
Test name
Test status
Simulation time 43433287 ps
CPU time 0.64 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 196484 kb
Host smart-e9a1965d-2c77-4de1-82e5-0af9a0eb86a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691862425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3691862425
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.409890946
Short name T1289
Test name
Test status
Simulation time 107458998 ps
CPU time 2.34 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:14 PM PDT 24
Peak memory 201092 kb
Host smart-42feabc9-fa54-496c-9067-1609ff05a63e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409890946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.409890946
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3118927285
Short name T151
Test name
Test status
Simulation time 320777397 ps
CPU time 1.24 seconds
Started Jul 23 07:23:09 PM PDT 24
Finished Jul 23 07:23:11 PM PDT 24
Peak memory 200212 kb
Host smart-a84945cf-96e3-4322-bd7f-cd8763e782ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118927285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3118927285
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1107388315
Short name T1224
Test name
Test status
Simulation time 42974478 ps
CPU time 1.14 seconds
Started Jul 23 07:23:20 PM PDT 24
Finished Jul 23 07:23:22 PM PDT 24
Peak memory 200912 kb
Host smart-07665867-4a91-4b8d-810d-3a5a41206507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107388315 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1107388315
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.374796232
Short name T66
Test name
Test status
Simulation time 48421618 ps
CPU time 0.58 seconds
Started Jul 23 07:23:07 PM PDT 24
Finished Jul 23 07:23:08 PM PDT 24
Peak memory 196324 kb
Host smart-2e56944c-dead-4516-8f1d-ea6c223bc61f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374796232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.374796232
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2832661982
Short name T1184
Test name
Test status
Simulation time 20882143 ps
CPU time 0.56 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:11 PM PDT 24
Peak memory 195220 kb
Host smart-4b3f440f-acb4-4d44-8934-877059ab48ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832661982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2832661982
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.219286633
Short name T1257
Test name
Test status
Simulation time 24315835 ps
CPU time 0.68 seconds
Started Jul 23 07:23:18 PM PDT 24
Finished Jul 23 07:23:19 PM PDT 24
Peak memory 196888 kb
Host smart-dff85fa9-04c1-4843-bc81-717ac00ab616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219286633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.219286633
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3234445736
Short name T1315
Test name
Test status
Simulation time 111620915 ps
CPU time 1.49 seconds
Started Jul 23 07:23:09 PM PDT 24
Finished Jul 23 07:23:11 PM PDT 24
Peak memory 201144 kb
Host smart-72910032-818e-479e-a508-12e3370baf49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234445736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3234445736
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3342419477
Short name T1296
Test name
Test status
Simulation time 606697072 ps
CPU time 0.98 seconds
Started Jul 23 07:23:10 PM PDT 24
Finished Jul 23 07:23:12 PM PDT 24
Peak memory 199956 kb
Host smart-ac9200cd-23a6-457a-8c52-07f1c1c5994a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342419477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3342419477
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.419124487
Short name T891
Test name
Test status
Simulation time 13567795 ps
CPU time 0.58 seconds
Started Jul 23 06:50:51 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 195628 kb
Host smart-ec97e69a-ba02-4224-a7ee-538c2ab66069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419124487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.419124487
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3592472020
Short name T713
Test name
Test status
Simulation time 272019759729 ps
CPU time 589.02 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 07:00:48 PM PDT 24
Peak memory 200236 kb
Host smart-8bbf11dd-061c-4ef7-bb20-d6ebd3e2330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592472020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3592472020
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1834734486
Short name T1013
Test name
Test status
Simulation time 22943523973 ps
CPU time 36.32 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:34 PM PDT 24
Peak memory 200180 kb
Host smart-99e2c211-0a4e-4bff-b08f-3fb3e99c4e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834734486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1834734486
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3099608980
Short name T794
Test name
Test status
Simulation time 44223514451 ps
CPU time 32.9 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:30 PM PDT 24
Peak memory 200212 kb
Host smart-d0f5a14c-8a6f-42ee-ba8a-72d2f86f207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099608980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3099608980
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3854416098
Short name T535
Test name
Test status
Simulation time 31968019991 ps
CPU time 25.56 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 200080 kb
Host smart-d305281c-7430-407e-a643-eba6a13242e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854416098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3854416098
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2235398842
Short name T553
Test name
Test status
Simulation time 77381712837 ps
CPU time 132.29 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:53:12 PM PDT 24
Peak memory 200184 kb
Host smart-578652b4-6e50-4946-a2a8-adb15f9c2fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235398842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2235398842
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1146503970
Short name T132
Test name
Test status
Simulation time 3954047180 ps
CPU time 5.44 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:03 PM PDT 24
Peak memory 196448 kb
Host smart-c6811cf3-572c-4179-81a0-16da02453a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146503970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1146503970
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.1203722755
Short name T647
Test name
Test status
Simulation time 12782403832 ps
CPU time 400.76 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:57:39 PM PDT 24
Peak memory 200168 kb
Host smart-759b2cee-4968-4473-bc67-62d290993dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203722755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1203722755
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3289103186
Short name T871
Test name
Test status
Simulation time 3067098244 ps
CPU time 6.07 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:05 PM PDT 24
Peak memory 198840 kb
Host smart-90db9359-bb60-42bd-928e-93065bbe120c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289103186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3289103186
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.707085662
Short name T1104
Test name
Test status
Simulation time 69829708275 ps
CPU time 52.08 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:52 PM PDT 24
Peak memory 199816 kb
Host smart-c8ec02b3-2ccb-4675-abb0-9eaaa3b26144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707085662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.707085662
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2135521815
Short name T424
Test name
Test status
Simulation time 1444679099 ps
CPU time 3.07 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:59 PM PDT 24
Peak memory 195720 kb
Host smart-f901bdbe-dd58-4a47-944e-174afbe23482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135521815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2135521815
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3649804032
Short name T651
Test name
Test status
Simulation time 487814210 ps
CPU time 1.04 seconds
Started Jul 23 06:50:51 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 198700 kb
Host smart-b0ea1bc4-b6ed-4a4f-af27-d1319c92faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649804032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3649804032
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2602626943
Short name T923
Test name
Test status
Simulation time 334302692259 ps
CPU time 380.14 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:57:18 PM PDT 24
Peak memory 200144 kb
Host smart-6cdf3a2f-53a0-4d04-8b08-bc0b704e3a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602626943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2602626943
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.101587601
Short name T925
Test name
Test status
Simulation time 15021959580 ps
CPU time 173.12 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 216884 kb
Host smart-73233d1b-01de-4e4c-b9b0-a483859b3109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101587601 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.101587601
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2325919073
Short name T432
Test name
Test status
Simulation time 5482125538 ps
CPU time 1.87 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:01 PM PDT 24
Peak memory 200212 kb
Host smart-5b98426f-8100-472d-923a-08332496dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325919073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2325919073
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.62995892
Short name T1018
Test name
Test status
Simulation time 36860529502 ps
CPU time 50.48 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:49 PM PDT 24
Peak memory 200236 kb
Host smart-93b2f1c9-a0ea-4a25-bceb-095b61f37196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62995892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.62995892
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3807644859
Short name T981
Test name
Test status
Simulation time 121071651 ps
CPU time 0.55 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 195924 kb
Host smart-ce132dbf-d207-4c8f-b17e-3227ff628d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807644859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3807644859
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4115974893
Short name T402
Test name
Test status
Simulation time 49659982090 ps
CPU time 41.14 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:42 PM PDT 24
Peak memory 200252 kb
Host smart-684b649b-83d2-4694-80d5-12ef021172c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115974893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4115974893
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.116086191
Short name T179
Test name
Test status
Simulation time 75347812180 ps
CPU time 26.68 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 200148 kb
Host smart-e701092a-e1f1-45da-acd7-0d1dc1fc4e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116086191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.116086191
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2263137733
Short name T750
Test name
Test status
Simulation time 220795111646 ps
CPU time 142.06 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 200248 kb
Host smart-36e98d40-f7cf-408d-91c8-9369572216d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263137733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2263137733
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.728953724
Short name T1178
Test name
Test status
Simulation time 46679288767 ps
CPU time 89.33 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:52:30 PM PDT 24
Peak memory 200136 kb
Host smart-7a26edfc-439d-4e08-8d9b-2cac314d14bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728953724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.728953724
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2859166244
Short name T624
Test name
Test status
Simulation time 101377345405 ps
CPU time 337.18 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:56:37 PM PDT 24
Peak memory 200352 kb
Host smart-9678821e-7267-435d-9951-7dbd313af866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859166244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2859166244
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1702975483
Short name T638
Test name
Test status
Simulation time 7566804180 ps
CPU time 14.71 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 200172 kb
Host smart-937b9193-9a6c-4aeb-9896-65450f1d54f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702975483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1702975483
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1874356891
Short name T48
Test name
Test status
Simulation time 62597958654 ps
CPU time 105.27 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:52:38 PM PDT 24
Peak memory 200184 kb
Host smart-82d7414e-03f6-417f-91b0-6b054f4f177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874356891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1874356891
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1306951728
Short name T943
Test name
Test status
Simulation time 5272693967 ps
CPU time 327.34 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:56:27 PM PDT 24
Peak memory 200440 kb
Host smart-67361f5d-fb6c-430f-a17e-39cf0cdb7126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306951728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1306951728
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.486703482
Short name T418
Test name
Test status
Simulation time 5949040953 ps
CPU time 6.79 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 198368 kb
Host smart-c7520bff-bf32-402e-b7f1-f5b50faffce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486703482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.486703482
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1501693820
Short name T595
Test name
Test status
Simulation time 34971060954 ps
CPU time 25.84 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 196092 kb
Host smart-a68d92f9-5d35-4174-b8c6-4c8181e7b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501693820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1501693820
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4091327874
Short name T27
Test name
Test status
Simulation time 151297846 ps
CPU time 0.76 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 218572 kb
Host smart-742abd4e-62be-4460-bb8f-d123d09cf8f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091327874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4091327874
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1581175056
Short name T696
Test name
Test status
Simulation time 470762049 ps
CPU time 1.5 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:58 PM PDT 24
Peak memory 198652 kb
Host smart-cc891ab8-2b0c-49f7-a0b7-9de5ef5991fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581175056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1581175056
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2606368109
Short name T1002
Test name
Test status
Simulation time 76205173814 ps
CPU time 121.33 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:53:05 PM PDT 24
Peak memory 208556 kb
Host smart-e894a068-4f5c-4773-90c8-7a07b3d98d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606368109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2606368109
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3842371616
Short name T841
Test name
Test status
Simulation time 35069243181 ps
CPU time 296.32 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:56:00 PM PDT 24
Peak memory 212948 kb
Host smart-b496647c-9a19-4094-b8f8-c1db668c4dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842371616 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3842371616
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1587567946
Short name T956
Test name
Test status
Simulation time 1208632913 ps
CPU time 1.18 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:50:59 PM PDT 24
Peak memory 197192 kb
Host smart-a741f4eb-3d12-4d27-9049-333a53e5bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587567946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1587567946
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1717934402
Short name T575
Test name
Test status
Simulation time 23343240151 ps
CPU time 10.32 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 200040 kb
Host smart-be1ae850-e0db-45a0-b697-d980b7e96ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717934402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1717934402
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.200425819
Short name T1111
Test name
Test status
Simulation time 35638446 ps
CPU time 0.53 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:51:20 PM PDT 24
Peak memory 194604 kb
Host smart-cf4ad4d1-0d50-4f6c-984e-37938bc5593c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200425819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.200425819
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3150836335
Short name T134
Test name
Test status
Simulation time 13385454900 ps
CPU time 19.71 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:44 PM PDT 24
Peak memory 200196 kb
Host smart-9a672b88-dc73-45de-a835-3c8199d7126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150836335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3150836335
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1808757516
Short name T1128
Test name
Test status
Simulation time 120478188824 ps
CPU time 85.98 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 200252 kb
Host smart-269d23f3-b571-40ae-947e-03b5be8e4145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808757516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1808757516
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1298942901
Short name T996
Test name
Test status
Simulation time 19931835598 ps
CPU time 8.46 seconds
Started Jul 23 06:51:16 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 197184 kb
Host smart-c130f648-7a00-4451-ae14-d8b5a45c086a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298942901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1298942901
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3584760855
Short name T346
Test name
Test status
Simulation time 140235593470 ps
CPU time 395.72 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:57:56 PM PDT 24
Peak memory 200160 kb
Host smart-3dbe04fa-a10f-447b-a9a8-4ee73bcf7b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584760855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3584760855
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3658917657
Short name T411
Test name
Test status
Simulation time 5577481671 ps
CPU time 13.84 seconds
Started Jul 23 06:51:13 PM PDT 24
Finished Jul 23 06:51:29 PM PDT 24
Peak memory 199636 kb
Host smart-6fa7a669-afba-4bc1-a54f-a6ae59266294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658917657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3658917657
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2687195564
Short name T364
Test name
Test status
Simulation time 67298886584 ps
CPU time 53.19 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:52:16 PM PDT 24
Peak memory 200392 kb
Host smart-46ac6491-15ee-49fb-812c-2052fd823dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687195564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2687195564
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.955998884
Short name T461
Test name
Test status
Simulation time 20722689025 ps
CPU time 943.51 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 07:07:09 PM PDT 24
Peak memory 200236 kb
Host smart-03bd45b0-2802-4478-9adb-6d7d7d8c4b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955998884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.955998884
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2851885412
Short name T770
Test name
Test status
Simulation time 6001107862 ps
CPU time 20.47 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:45 PM PDT 24
Peak memory 198448 kb
Host smart-d55cd719-006a-417c-9fb2-03818eb046f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851885412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2851885412
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3057140752
Short name T796
Test name
Test status
Simulation time 39453395167 ps
CPU time 58.16 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:52:19 PM PDT 24
Peak memory 199884 kb
Host smart-fd30bae4-0aa7-438e-a953-bc9b45345955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057140752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3057140752
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.4220911593
Short name T747
Test name
Test status
Simulation time 3440551295 ps
CPU time 3.43 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:51:24 PM PDT 24
Peak memory 196388 kb
Host smart-7f6cb7a3-ee7a-4b21-8a52-9073d9023fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220911593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4220911593
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2578870276
Short name T748
Test name
Test status
Simulation time 453918902 ps
CPU time 1.86 seconds
Started Jul 23 06:51:16 PM PDT 24
Finished Jul 23 06:51:19 PM PDT 24
Peak memory 198956 kb
Host smart-ee96723a-837f-400d-8e74-03f2f2a0e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578870276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2578870276
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.815453524
Short name T880
Test name
Test status
Simulation time 278149950561 ps
CPU time 795.91 seconds
Started Jul 23 06:51:13 PM PDT 24
Finished Jul 23 07:04:31 PM PDT 24
Peak memory 200212 kb
Host smart-56c51346-4603-4235-b120-91502d21bc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815453524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.815453524
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2204886061
Short name T646
Test name
Test status
Simulation time 879046855 ps
CPU time 2.82 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:51:24 PM PDT 24
Peak memory 198820 kb
Host smart-b68dc749-6eae-4f99-a1b6-fcd7e16622b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204886061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2204886061
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2104525568
Short name T1095
Test name
Test status
Simulation time 19220641945 ps
CPU time 24.74 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:49 PM PDT 24
Peak memory 200136 kb
Host smart-18b0d0ad-fc31-47f0-b999-de760f023121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104525568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2104525568
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.320696059
Short name T231
Test name
Test status
Simulation time 17086722914 ps
CPU time 12.51 seconds
Started Jul 23 06:57:57 PM PDT 24
Finished Jul 23 06:58:11 PM PDT 24
Peak memory 200192 kb
Host smart-58fa0701-76d6-4812-ac50-cf1bd99277d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320696059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.320696059
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1552100790
Short name T212
Test name
Test status
Simulation time 18388751589 ps
CPU time 33.65 seconds
Started Jul 23 06:57:52 PM PDT 24
Finished Jul 23 06:58:27 PM PDT 24
Peak memory 200164 kb
Host smart-433cc77a-2393-45a6-9421-0f915badc0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552100790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1552100790
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2905307840
Short name T1159
Test name
Test status
Simulation time 11397415413 ps
CPU time 21.92 seconds
Started Jul 23 06:57:59 PM PDT 24
Finished Jul 23 06:58:23 PM PDT 24
Peak memory 200176 kb
Host smart-ed267f68-2e10-470c-8324-c68e03db3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905307840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2905307840
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.677544733
Short name T546
Test name
Test status
Simulation time 174430959134 ps
CPU time 78.24 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 06:59:16 PM PDT 24
Peak memory 200200 kb
Host smart-4c0448cb-32e8-45b7-8992-aa47e76d2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677544733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.677544733
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3260469519
Short name T345
Test name
Test status
Simulation time 16054567519 ps
CPU time 25.96 seconds
Started Jul 23 06:57:53 PM PDT 24
Finished Jul 23 06:58:19 PM PDT 24
Peak memory 199924 kb
Host smart-7c28e0dd-d175-4a6e-b1d8-347b5a6eeeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260469519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3260469519
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1027671092
Short name T1058
Test name
Test status
Simulation time 82861996715 ps
CPU time 139.7 seconds
Started Jul 23 06:57:57 PM PDT 24
Finished Jul 23 07:00:18 PM PDT 24
Peak memory 200260 kb
Host smart-704f6e1d-68d4-4621-8f79-596c170aa171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027671092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1027671092
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.5176481
Short name T268
Test name
Test status
Simulation time 62460332900 ps
CPU time 12.54 seconds
Started Jul 23 06:57:49 PM PDT 24
Finished Jul 23 06:58:03 PM PDT 24
Peak memory 200260 kb
Host smart-5b925c6b-7647-4e54-a677-35b73e7d5dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5176481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.5176481
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2575325087
Short name T776
Test name
Test status
Simulation time 49416049778 ps
CPU time 80.01 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 06:59:18 PM PDT 24
Peak memory 200216 kb
Host smart-0c83aedf-f66c-4e8b-99d6-58cb7583c33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575325087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2575325087
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.98280579
Short name T467
Test name
Test status
Simulation time 27502844699 ps
CPU time 20.84 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:58:25 PM PDT 24
Peak memory 200236 kb
Host smart-7fce8101-1f8c-47ba-bd4b-afce6942ccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98280579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.98280579
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1163140809
Short name T936
Test name
Test status
Simulation time 60169817650 ps
CPU time 129.2 seconds
Started Jul 23 06:58:00 PM PDT 24
Finished Jul 23 07:00:10 PM PDT 24
Peak memory 200256 kb
Host smart-24a7415b-fdc7-4c23-9dae-4bddbd1c72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163140809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1163140809
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.332946185
Short name T472
Test name
Test status
Simulation time 15308336 ps
CPU time 0.59 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 195880 kb
Host smart-44b35942-5214-4df1-acd9-890303aa0b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332946185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.332946185
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.628586719
Short name T810
Test name
Test status
Simulation time 167371528840 ps
CPU time 264.69 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:55:50 PM PDT 24
Peak memory 200220 kb
Host smart-4d4b628b-be3a-479d-960a-a39763b19ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628586719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.628586719
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2462333131
Short name T950
Test name
Test status
Simulation time 142470780868 ps
CPU time 214.85 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:55:00 PM PDT 24
Peak memory 200200 kb
Host smart-9d5d67d7-1e0c-40c2-9702-3903494d9b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462333131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2462333131
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2789176124
Short name T756
Test name
Test status
Simulation time 131813600695 ps
CPU time 47.67 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:52:06 PM PDT 24
Peak memory 200248 kb
Host smart-c9a7e120-247f-44ea-a9e3-913fe59ca9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789176124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2789176124
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.536299576
Short name T287
Test name
Test status
Simulation time 8394728758 ps
CPU time 12.45 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 200236 kb
Host smart-879141d8-9c8a-47da-8165-048751d133c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536299576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.536299576
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_loopback.2619343636
Short name T1123
Test name
Test status
Simulation time 940916996 ps
CPU time 2.12 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:51:22 PM PDT 24
Peak memory 195664 kb
Host smart-d38d2693-a949-4420-a6ce-20492d0aa424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619343636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2619343636
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1649802183
Short name T417
Test name
Test status
Simulation time 17016364505 ps
CPU time 14.06 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:51:28 PM PDT 24
Peak memory 200132 kb
Host smart-01bae03f-4da5-4fdf-b962-1284e056fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649802183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1649802183
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.673098891
Short name T1107
Test name
Test status
Simulation time 9699494828 ps
CPU time 289.16 seconds
Started Jul 23 06:51:14 PM PDT 24
Finished Jul 23 06:56:05 PM PDT 24
Peak memory 200236 kb
Host smart-16ef84ff-3c69-46a3-8d8d-3bea885c5bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673098891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.673098891
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.303690054
Short name T507
Test name
Test status
Simulation time 3532815114 ps
CPU time 3.76 seconds
Started Jul 23 06:51:14 PM PDT 24
Finished Jul 23 06:51:19 PM PDT 24
Peak memory 198132 kb
Host smart-283da74e-e2e3-4cda-8b0e-a2952a2c34ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303690054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.303690054
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2256556247
Short name T577
Test name
Test status
Simulation time 72764303274 ps
CPU time 31.57 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:56 PM PDT 24
Peak memory 200256 kb
Host smart-85e6f071-cad9-4eb3-b034-0148c788202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256556247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2256556247
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.791917580
Short name T1040
Test name
Test status
Simulation time 41125381095 ps
CPU time 54.61 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:52:17 PM PDT 24
Peak memory 196392 kb
Host smart-0a4f2cc1-47a4-4352-a4a8-cb57fa0f4e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791917580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.791917580
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1867026040
Short name T908
Test name
Test status
Simulation time 487997880 ps
CPU time 1.95 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:27 PM PDT 24
Peak memory 198488 kb
Host smart-d5db0123-73bb-4b6b-8a45-15ad8e8df095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867026040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1867026040
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2045928283
Short name T184
Test name
Test status
Simulation time 308857118078 ps
CPU time 305.87 seconds
Started Jul 23 06:51:16 PM PDT 24
Finished Jul 23 06:56:23 PM PDT 24
Peak memory 215948 kb
Host smart-226bcef4-f198-4b61-a64c-1b6b9d1bb0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045928283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2045928283
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3957215109
Short name T884
Test name
Test status
Simulation time 172430128475 ps
CPU time 342.94 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:57:08 PM PDT 24
Peak memory 209280 kb
Host smart-c838cd7a-a03b-47e2-b9e8-5c6c137a54ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957215109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3957215109
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.667805256
Short name T136
Test name
Test status
Simulation time 1016413923 ps
CPU time 3.2 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:51:18 PM PDT 24
Peak memory 198600 kb
Host smart-997d45e4-069c-4a08-b25f-7464eedc6c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667805256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.667805256
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2802768915
Short name T405
Test name
Test status
Simulation time 15980749733 ps
CPU time 12.12 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:38 PM PDT 24
Peak memory 197492 kb
Host smart-ad352e86-1e5c-4099-a725-382894b5d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802768915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2802768915
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2996359204
Short name T13
Test name
Test status
Simulation time 19704147261 ps
CPU time 24.38 seconds
Started Jul 23 06:58:04 PM PDT 24
Finished Jul 23 06:58:30 PM PDT 24
Peak memory 200208 kb
Host smart-2bca5459-05c2-400e-a718-bfc0a34a47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996359204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2996359204
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3885002068
Short name T1051
Test name
Test status
Simulation time 42067484240 ps
CPU time 73.6 seconds
Started Jul 23 06:57:59 PM PDT 24
Finished Jul 23 06:59:14 PM PDT 24
Peak memory 200184 kb
Host smart-95353214-c79d-4a5f-afde-fb5f71c68242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885002068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3885002068
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2853077766
Short name T246
Test name
Test status
Simulation time 92193503444 ps
CPU time 141.45 seconds
Started Jul 23 06:57:59 PM PDT 24
Finished Jul 23 07:00:21 PM PDT 24
Peak memory 200192 kb
Host smart-c0944bf6-8deb-427d-a891-a8438c2fd18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853077766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2853077766
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1557559039
Short name T350
Test name
Test status
Simulation time 30786378648 ps
CPU time 49.45 seconds
Started Jul 23 06:58:05 PM PDT 24
Finished Jul 23 06:58:56 PM PDT 24
Peak memory 200268 kb
Host smart-b296fc0a-1e60-4825-addc-cea0df1d16bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557559039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1557559039
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1897833377
Short name T1161
Test name
Test status
Simulation time 46510454264 ps
CPU time 210.45 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 07:01:35 PM PDT 24
Peak memory 200156 kb
Host smart-15b25912-ebc5-4177-8d4a-f681781cc652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897833377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1897833377
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2049411796
Short name T875
Test name
Test status
Simulation time 23846491177 ps
CPU time 38.35 seconds
Started Jul 23 06:58:02 PM PDT 24
Finished Jul 23 06:58:42 PM PDT 24
Peak memory 200160 kb
Host smart-22d9f7ed-f52d-452e-b2db-0842cde0f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049411796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2049411796
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2667843770
Short name T992
Test name
Test status
Simulation time 39524747483 ps
CPU time 60.12 seconds
Started Jul 23 06:58:04 PM PDT 24
Finished Jul 23 06:59:05 PM PDT 24
Peak memory 200252 kb
Host smart-17ef7cca-2d45-4c96-a845-53eac213e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667843770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2667843770
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3806550695
Short name T672
Test name
Test status
Simulation time 45289272310 ps
CPU time 52.38 seconds
Started Jul 23 06:58:00 PM PDT 24
Finished Jul 23 06:58:54 PM PDT 24
Peak memory 200256 kb
Host smart-e237281c-dec7-4ff4-a0a8-3e0ebaf13e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806550695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3806550695
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4111285078
Short name T86
Test name
Test status
Simulation time 11782228477 ps
CPU time 16.82 seconds
Started Jul 23 06:58:05 PM PDT 24
Finished Jul 23 06:58:23 PM PDT 24
Peak memory 200268 kb
Host smart-c3973331-e25f-496b-bf57-e837f1646c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111285078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4111285078
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2056501550
Short name T640
Test name
Test status
Simulation time 134199266937 ps
CPU time 104.96 seconds
Started Jul 23 06:58:02 PM PDT 24
Finished Jul 23 06:59:48 PM PDT 24
Peak memory 200192 kb
Host smart-3348562a-8e3c-4f5c-83d8-993f02e89f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056501550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2056501550
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2823720899
Short name T724
Test name
Test status
Simulation time 27024182652 ps
CPU time 42.25 seconds
Started Jul 23 06:51:16 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 200184 kb
Host smart-ae478c9d-a48d-48e2-bc60-38183110d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823720899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2823720899
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.725435158
Short name T587
Test name
Test status
Simulation time 90202983142 ps
CPU time 8.65 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:51:40 PM PDT 24
Peak memory 199020 kb
Host smart-8d3339f3-e017-4696-838f-e0f95030b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725435158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.725435158
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.732843182
Short name T980
Test name
Test status
Simulation time 14065029954 ps
CPU time 7.12 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 200212 kb
Host smart-d47f158a-b4f6-4e33-bc27-18059dff2375
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732843182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.732843182
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2237794697
Short name T934
Test name
Test status
Simulation time 101231600390 ps
CPU time 754.69 seconds
Started Jul 23 06:51:16 PM PDT 24
Finished Jul 23 07:03:52 PM PDT 24
Peak memory 200128 kb
Host smart-e4f7c8c9-055d-4932-b861-7efbea9a8dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237794697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2237794697
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3923733286
Short name T1007
Test name
Test status
Simulation time 13330213323 ps
CPU time 11.69 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:37 PM PDT 24
Peak memory 199808 kb
Host smart-6acbf79e-b346-4624-812c-bc71114f3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923733286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3923733286
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2852592679
Short name T458
Test name
Test status
Simulation time 64304834181 ps
CPU time 31.08 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 200124 kb
Host smart-3556a3df-dee5-415d-8f26-6e5f66f17afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852592679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2852592679
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2783064806
Short name T391
Test name
Test status
Simulation time 6478249120 ps
CPU time 15.2 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:40 PM PDT 24
Peak memory 198340 kb
Host smart-e34a8861-f16a-4990-b9c3-5f1be7032a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783064806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2783064806
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2717238604
Short name T740
Test name
Test status
Simulation time 6972038444 ps
CPU time 6.27 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 200020 kb
Host smart-2b5536fe-981f-4e27-9d57-d950f66c10fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717238604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2717238604
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2976299202
Short name T331
Test name
Test status
Simulation time 1434754844 ps
CPU time 1.24 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:26 PM PDT 24
Peak memory 195404 kb
Host smart-8173178a-f8f0-498b-9075-4916b17c31f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976299202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2976299202
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1493441897
Short name T1102
Test name
Test status
Simulation time 92224137 ps
CPU time 0.81 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 197360 kb
Host smart-82d37c2a-540a-41f7-9026-ad75e5b7da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493441897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1493441897
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1374276060
Short name T320
Test name
Test status
Simulation time 68932031323 ps
CPU time 1641.85 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 07:18:55 PM PDT 24
Peak memory 225780 kb
Host smart-81c894b5-01c8-454b-bc72-81f6dc2e109b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374276060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1374276060
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3598704690
Short name T687
Test name
Test status
Simulation time 1243595183 ps
CPU time 3.38 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:51:23 PM PDT 24
Peak memory 200100 kb
Host smart-e5d3ac92-954a-47ec-8c75-78941b8d7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598704690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3598704690
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3935563167
Short name T769
Test name
Test status
Simulation time 59220222786 ps
CPU time 32.28 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:54 PM PDT 24
Peak memory 200264 kb
Host smart-a5ea758b-1486-4591-8444-b09a5c2d1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935563167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3935563167
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.137072687
Short name T685
Test name
Test status
Simulation time 65846574986 ps
CPU time 47.81 seconds
Started Jul 23 06:58:00 PM PDT 24
Finished Jul 23 06:58:49 PM PDT 24
Peak memory 200192 kb
Host smart-9e52ffb0-37b4-48f8-a3f9-cc2d5ef355a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137072687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.137072687
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2649079013
Short name T307
Test name
Test status
Simulation time 13466673883 ps
CPU time 19.9 seconds
Started Jul 23 06:57:58 PM PDT 24
Finished Jul 23 06:58:18 PM PDT 24
Peak memory 200208 kb
Host smart-0bbbb31e-7fc9-46e7-babc-16ba1adf5c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649079013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2649079013
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2571437296
Short name T1167
Test name
Test status
Simulation time 75662519952 ps
CPU time 27.64 seconds
Started Jul 23 06:58:04 PM PDT 24
Finished Jul 23 06:58:33 PM PDT 24
Peak memory 199944 kb
Host smart-c2e6fe9d-ceea-4cb7-8f24-a913ac52798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571437296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2571437296
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1736677113
Short name T818
Test name
Test status
Simulation time 49630892444 ps
CPU time 74.72 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:59:19 PM PDT 24
Peak memory 200192 kb
Host smart-0f3f25b8-a688-4356-a95c-6256db7e5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736677113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1736677113
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.202378558
Short name T488
Test name
Test status
Simulation time 11940480281 ps
CPU time 9.27 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:58:14 PM PDT 24
Peak memory 200100 kb
Host smart-c6618bee-4ac1-49dc-9355-42f028ec79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202378558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.202378558
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.211673047
Short name T610
Test name
Test status
Simulation time 67691578512 ps
CPU time 30.34 seconds
Started Jul 23 06:57:59 PM PDT 24
Finished Jul 23 06:58:30 PM PDT 24
Peak memory 200268 kb
Host smart-bda7a118-a6c0-4870-a43b-713d4a5bd8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211673047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.211673047
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1114928527
Short name T802
Test name
Test status
Simulation time 52770033998 ps
CPU time 72.45 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:59:17 PM PDT 24
Peak memory 200188 kb
Host smart-4bead36f-fd12-4df3-ab33-bc380e477fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114928527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1114928527
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1210806368
Short name T84
Test name
Test status
Simulation time 15517031768 ps
CPU time 29.4 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:58:34 PM PDT 24
Peak memory 200168 kb
Host smart-50ebf7df-e335-4cba-af5f-83fdbadcbb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210806368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1210806368
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1380293642
Short name T399
Test name
Test status
Simulation time 12133386 ps
CPU time 0.56 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:24 PM PDT 24
Peak memory 195576 kb
Host smart-2cea14df-ed04-45fe-92f4-125d8ae13fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380293642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1380293642
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.878535301
Short name T842
Test name
Test status
Simulation time 181155552145 ps
CPU time 1192.71 seconds
Started Jul 23 06:51:25 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 200132 kb
Host smart-e8c17c5a-0a1c-40cf-b383-30bbfbd98c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878535301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.878535301
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.570059901
Short name T870
Test name
Test status
Simulation time 77020853377 ps
CPU time 34.15 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 200224 kb
Host smart-53893277-3dd9-4a94-a39c-61a09baa7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570059901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.570059901
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.960069348
Short name T1131
Test name
Test status
Simulation time 44221497437 ps
CPU time 20.23 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:51:53 PM PDT 24
Peak memory 200024 kb
Host smart-52e738ee-cfb5-4891-8145-601a88418500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960069348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.960069348
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1628946239
Short name T585
Test name
Test status
Simulation time 252317249465 ps
CPU time 376.67 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:57:44 PM PDT 24
Peak memory 197976 kb
Host smart-0cbc0561-61ba-4c61-ae29-241cbd2a9a56
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628946239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1628946239
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2805421209
Short name T514
Test name
Test status
Simulation time 189155711298 ps
CPU time 2193.97 seconds
Started Jul 23 06:51:35 PM PDT 24
Finished Jul 23 07:28:10 PM PDT 24
Peak memory 200064 kb
Host smart-f229e860-03ed-4b4a-93e3-808a2b66c867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805421209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2805421209
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.58667624
Short name T619
Test name
Test status
Simulation time 7691275898 ps
CPU time 14.22 seconds
Started Jul 23 06:51:17 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 198632 kb
Host smart-413a4808-14ae-443e-b8ad-ac797fd8a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58667624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.58667624
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3132563295
Short name T631
Test name
Test status
Simulation time 16141160664 ps
CPU time 25 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:51 PM PDT 24
Peak memory 197304 kb
Host smart-8456807e-e962-471c-a367-622d7f04cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132563295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3132563295
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2884614373
Short name T396
Test name
Test status
Simulation time 24862459654 ps
CPU time 278.72 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:56:08 PM PDT 24
Peak memory 200208 kb
Host smart-f028f08a-a6b3-4266-8f3a-9f9116cddb0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884614373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2884614373
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2174938178
Short name T534
Test name
Test status
Simulation time 7399323400 ps
CPU time 45 seconds
Started Jul 23 06:51:27 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 198396 kb
Host smart-7bbca1b8-bf35-43d1-9559-1deab9313830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174938178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2174938178
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3107939455
Short name T999
Test name
Test status
Simulation time 52206948923 ps
CPU time 71.01 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:52:40 PM PDT 24
Peak memory 200192 kb
Host smart-7f440565-2d8d-4118-bd3b-e923bb0152f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107939455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3107939455
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.113941701
Short name T416
Test name
Test status
Simulation time 3211534186 ps
CPU time 1.21 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:51:31 PM PDT 24
Peak memory 196796 kb
Host smart-39eb4696-d3b6-42ff-9c74-4333cf6f73f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113941701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.113941701
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1756691149
Short name T436
Test name
Test status
Simulation time 5476600091 ps
CPU time 7.92 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 199956 kb
Host smart-61574bd2-8686-46d5-9694-6d8b49471a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756691149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1756691149
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3707400121
Short name T849
Test name
Test status
Simulation time 46941319924 ps
CPU time 24.85 seconds
Started Jul 23 06:51:33 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 200016 kb
Host smart-5e29a76a-929d-431d-af57-dcca2de8c77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707400121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3707400121
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3497505532
Short name T1011
Test name
Test status
Simulation time 363381381767 ps
CPU time 838.1 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 07:05:18 PM PDT 24
Peak memory 225048 kb
Host smart-fec677d9-a2f5-49e9-9e56-af0d216532b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497505532 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3497505532
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2076905988
Short name T774
Test name
Test status
Simulation time 13054760119 ps
CPU time 17.98 seconds
Started Jul 23 06:51:27 PM PDT 24
Finished Jul 23 06:51:48 PM PDT 24
Peak memory 200200 kb
Host smart-c9d9e890-1a06-40dd-a769-0001f961eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076905988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2076905988
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3311077755
Short name T699
Test name
Test status
Simulation time 61413263590 ps
CPU time 29.53 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:51:54 PM PDT 24
Peak memory 199876 kb
Host smart-6b98ed75-e802-407e-b1c5-4a6c9f3023f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311077755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3311077755
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.745037329
Short name T694
Test name
Test status
Simulation time 59490398048 ps
CPU time 63.24 seconds
Started Jul 23 06:57:58 PM PDT 24
Finished Jul 23 06:59:02 PM PDT 24
Peak memory 200024 kb
Host smart-58552743-3618-405f-9fd8-dc886c0c85ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745037329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.745037329
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1305489352
Short name T591
Test name
Test status
Simulation time 114125794284 ps
CPU time 106.59 seconds
Started Jul 23 06:58:05 PM PDT 24
Finished Jul 23 06:59:53 PM PDT 24
Peak memory 200176 kb
Host smart-5dfab3fc-58ef-4a59-84af-f59b39ea82b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305489352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1305489352
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.661783617
Short name T858
Test name
Test status
Simulation time 67331692929 ps
CPU time 117.25 seconds
Started Jul 23 06:58:02 PM PDT 24
Finished Jul 23 07:00:01 PM PDT 24
Peak memory 200192 kb
Host smart-0d536af7-2e2b-45a6-8ea6-3bdf87c55d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661783617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.661783617
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2291673555
Short name T742
Test name
Test status
Simulation time 37972469310 ps
CPU time 19.14 seconds
Started Jul 23 06:58:03 PM PDT 24
Finished Jul 23 06:58:23 PM PDT 24
Peak memory 200036 kb
Host smart-479c916f-0a01-4e2f-b9de-0534f6e77490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291673555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2291673555
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2732905637
Short name T332
Test name
Test status
Simulation time 11586202847 ps
CPU time 19.53 seconds
Started Jul 23 06:58:05 PM PDT 24
Finished Jul 23 06:58:26 PM PDT 24
Peak memory 200244 kb
Host smart-8d795dd9-23ff-4e8a-95bc-b3cf2adbe00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732905637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2732905637
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.12250667
Short name T492
Test name
Test status
Simulation time 149971499457 ps
CPU time 250.12 seconds
Started Jul 23 06:58:12 PM PDT 24
Finished Jul 23 07:02:23 PM PDT 24
Peak memory 200196 kb
Host smart-de6c2654-d5e7-4e28-b594-cbb50d97180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12250667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.12250667
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2235477906
Short name T158
Test name
Test status
Simulation time 157709683376 ps
CPU time 141.94 seconds
Started Jul 23 06:58:13 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 199984 kb
Host smart-32f34639-3301-4599-9cab-a98213825f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235477906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2235477906
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1132622428
Short name T717
Test name
Test status
Simulation time 60222981841 ps
CPU time 23.72 seconds
Started Jul 23 06:58:08 PM PDT 24
Finished Jul 23 06:58:33 PM PDT 24
Peak memory 200260 kb
Host smart-291e33ca-9d93-49bc-bb03-bfbb15a0aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132622428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1132622428
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3496586941
Short name T703
Test name
Test status
Simulation time 69511109 ps
CPU time 0.56 seconds
Started Jul 23 06:51:31 PM PDT 24
Finished Jul 23 06:51:34 PM PDT 24
Peak memory 195624 kb
Host smart-f3f41741-6b93-42a5-9c6e-cb505874ffa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496586941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3496586941
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.624894002
Short name T816
Test name
Test status
Simulation time 45840313946 ps
CPU time 63.67 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 200132 kb
Host smart-0319c19f-c23e-4ecc-a92e-910e613c0a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624894002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.624894002
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1663076262
Short name T917
Test name
Test status
Simulation time 89176731102 ps
CPU time 126.31 seconds
Started Jul 23 06:51:25 PM PDT 24
Finished Jul 23 06:53:34 PM PDT 24
Peak memory 200248 kb
Host smart-77a3383f-fdcd-4918-a0ab-26e3108331a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663076262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1663076262
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1755673061
Short name T855
Test name
Test status
Simulation time 15069493976 ps
CPU time 6.49 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 197260 kb
Host smart-82777bc2-966e-4bfd-952c-3e2a91cfc26c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755673061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1755673061
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2184495718
Short name T474
Test name
Test status
Simulation time 122752296549 ps
CPU time 396.79 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:58:06 PM PDT 24
Peak memory 200212 kb
Host smart-02b3005f-a4e3-4112-8203-559db21f1000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184495718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2184495718
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2940035128
Short name T859
Test name
Test status
Simulation time 3570837598 ps
CPU time 10.28 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:34 PM PDT 24
Peak memory 199524 kb
Host smart-5e76dd29-279f-4f16-963f-e31374280e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940035128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2940035128
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.2329080192
Short name T988
Test name
Test status
Simulation time 12758305161 ps
CPU time 646.2 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 07:02:08 PM PDT 24
Peak memory 200208 kb
Host smart-0658a8e8-358e-4223-ab08-f374771283a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329080192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2329080192
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1327434588
Short name T645
Test name
Test status
Simulation time 2406805536 ps
CPU time 4.08 seconds
Started Jul 23 06:51:28 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 198632 kb
Host smart-f811bcf1-8428-4301-be19-f20dbf1d5fc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327434588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1327434588
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3496086240
Short name T639
Test name
Test status
Simulation time 124742046585 ps
CPU time 215.39 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:55:03 PM PDT 24
Peak memory 200068 kb
Host smart-39700ea1-844d-48f5-9783-c20ec13eee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496086240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3496086240
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3304490278
Short name T1059
Test name
Test status
Simulation time 4878461845 ps
CPU time 2.37 seconds
Started Jul 23 06:51:28 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 196708 kb
Host smart-a98ff046-9026-4da5-bbf1-e7a6276c5509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304490278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3304490278
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1361250909
Short name T383
Test name
Test status
Simulation time 110303826 ps
CPU time 0.8 seconds
Started Jul 23 06:51:28 PM PDT 24
Finished Jul 23 06:51:31 PM PDT 24
Peak memory 197148 kb
Host smart-2d6cf3b0-da08-4feb-aa35-84b009fbf48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361250909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1361250909
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1423916774
Short name T1020
Test name
Test status
Simulation time 895464242 ps
CPU time 1.83 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 198588 kb
Host smart-ba3da5d7-656b-4ead-aad4-f05fb70adde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423916774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1423916774
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3996307070
Short name T157
Test name
Test status
Simulation time 38496002211 ps
CPU time 17.78 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:51:47 PM PDT 24
Peak memory 200228 kb
Host smart-6aa90198-c469-4dd5-8e8c-245efdb02991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996307070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3996307070
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.530660744
Short name T542
Test name
Test status
Simulation time 77679074078 ps
CPU time 54.75 seconds
Started Jul 23 06:58:12 PM PDT 24
Finished Jul 23 06:59:08 PM PDT 24
Peak memory 200256 kb
Host smart-9fceb589-badb-4af9-b011-40ac7b7dce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530660744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.530660744
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.4270232281
Short name T187
Test name
Test status
Simulation time 15960549542 ps
CPU time 15.27 seconds
Started Jul 23 06:58:12 PM PDT 24
Finished Jul 23 06:58:28 PM PDT 24
Peak memory 200220 kb
Host smart-72ec5824-7914-4f4e-a68d-bb544ff0f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270232281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.4270232281
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.518421821
Short name T511
Test name
Test status
Simulation time 77003250223 ps
CPU time 75.82 seconds
Started Jul 23 06:58:13 PM PDT 24
Finished Jul 23 06:59:30 PM PDT 24
Peak memory 200000 kb
Host smart-e9759562-9f65-4635-a01c-66c1a0d7c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518421821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.518421821
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3265136723
Short name T526
Test name
Test status
Simulation time 171178715669 ps
CPU time 85.86 seconds
Started Jul 23 06:58:13 PM PDT 24
Finished Jul 23 06:59:40 PM PDT 24
Peak memory 200088 kb
Host smart-002b5955-e893-4389-abef-b4c2f4e68138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265136723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3265136723
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1280170128
Short name T71
Test name
Test status
Simulation time 218150937172 ps
CPU time 141.88 seconds
Started Jul 23 06:58:13 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 200072 kb
Host smart-da48033e-c575-4369-9f39-1c89e5126aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280170128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1280170128
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.638018842
Short name T221
Test name
Test status
Simulation time 26450017278 ps
CPU time 9.99 seconds
Started Jul 23 06:58:23 PM PDT 24
Finished Jul 23 06:58:35 PM PDT 24
Peak memory 199912 kb
Host smart-aa1e6fb8-2817-4beb-8dba-050f7040ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638018842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.638018842
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1329328674
Short name T868
Test name
Test status
Simulation time 175167673031 ps
CPU time 99.19 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 06:59:56 PM PDT 24
Peak memory 200172 kb
Host smart-2bc581f4-0f1b-432f-a80d-24d89b385fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329328674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1329328674
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1965151978
Short name T1121
Test name
Test status
Simulation time 121860640286 ps
CPU time 207.1 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 07:01:43 PM PDT 24
Peak memory 200228 kb
Host smart-e23cd921-c6b4-4768-b0f7-f6c6219f3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965151978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1965151978
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2279801908
Short name T209
Test name
Test status
Simulation time 56104758676 ps
CPU time 49.99 seconds
Started Jul 23 06:58:21 PM PDT 24
Finished Jul 23 06:59:12 PM PDT 24
Peak memory 200200 kb
Host smart-091eee57-f751-4665-a36d-b2fd9e2edfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279801908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2279801908
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4031270677
Short name T797
Test name
Test status
Simulation time 16078833 ps
CPU time 0.56 seconds
Started Jul 23 06:51:38 PM PDT 24
Finished Jul 23 06:51:40 PM PDT 24
Peak memory 195624 kb
Host smart-94148b33-e4bb-4906-b52f-5402c1b51725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031270677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4031270677
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2951348260
Short name T449
Test name
Test status
Simulation time 323609169975 ps
CPU time 40.18 seconds
Started Jul 23 06:51:42 PM PDT 24
Finished Jul 23 06:52:24 PM PDT 24
Peak memory 200244 kb
Host smart-6cfb69a4-3ce8-40bb-8dc9-1475258565e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951348260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2951348260
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4260811867
Short name T1180
Test name
Test status
Simulation time 156621323410 ps
CPU time 111.84 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:53:25 PM PDT 24
Peak memory 200224 kb
Host smart-b9a29dcc-7095-4e37-a40c-2afc0d5b6d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260811867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4260811867
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.3095756141
Short name T306
Test name
Test status
Simulation time 61926386625 ps
CPU time 55.14 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 200232 kb
Host smart-61691588-8d58-43f8-b462-29776dbb46e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095756141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3095756141
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.511305657
Short name T1141
Test name
Test status
Simulation time 115667639510 ps
CPU time 829.45 seconds
Started Jul 23 06:51:31 PM PDT 24
Finished Jul 23 07:05:23 PM PDT 24
Peak memory 200212 kb
Host smart-24a114f6-a41a-48b7-9ac2-3f733592738d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511305657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.511305657
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2885358038
Short name T452
Test name
Test status
Simulation time 4197859814 ps
CPU time 4.88 seconds
Started Jul 23 06:51:31 PM PDT 24
Finished Jul 23 06:51:38 PM PDT 24
Peak memory 200124 kb
Host smart-b1c4fe73-ad2c-4113-a44f-8317d94cecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885358038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2885358038
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3155130149
Short name T289
Test name
Test status
Simulation time 151183813138 ps
CPU time 168.95 seconds
Started Jul 23 06:51:31 PM PDT 24
Finished Jul 23 06:54:22 PM PDT 24
Peak memory 200384 kb
Host smart-155a0df7-fe8c-4b29-b4c4-eec7efd2a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155130149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3155130149
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1902040800
Short name T767
Test name
Test status
Simulation time 13016097132 ps
CPU time 185.4 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:54:46 PM PDT 24
Peak memory 200444 kb
Host smart-287b037b-c6d3-4096-8013-2271b3c003b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902040800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1902040800
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1449318580
Short name T378
Test name
Test status
Simulation time 3112580266 ps
CPU time 2.27 seconds
Started Jul 23 06:51:37 PM PDT 24
Finished Jul 23 06:51:41 PM PDT 24
Peak memory 198244 kb
Host smart-d7262e83-cd6c-4650-b841-3863d3724638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449318580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1449318580
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1253189897
Short name T918
Test name
Test status
Simulation time 190539090464 ps
CPU time 86.2 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:52:59 PM PDT 24
Peak memory 200252 kb
Host smart-2c84c4e6-9fe9-4ccb-bbf4-644dd0009550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253189897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1253189897
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1102503336
Short name T342
Test name
Test status
Simulation time 42906320514 ps
CPU time 17.49 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 196292 kb
Host smart-62fdd8d2-8bbf-43b1-a41f-52b9259e3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102503336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1102503336
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3460567170
Short name T414
Test name
Test status
Simulation time 612112319 ps
CPU time 1.93 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:52:10 PM PDT 24
Peak memory 198508 kb
Host smart-ba63904a-8e61-4762-924b-6b5b8aa32255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460567170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3460567170
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1155094815
Short name T171
Test name
Test status
Simulation time 72399556250 ps
CPU time 120.14 seconds
Started Jul 23 06:51:34 PM PDT 24
Finished Jul 23 06:53:36 PM PDT 24
Peak memory 200220 kb
Host smart-728002c2-593e-426b-b408-b464952e9724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155094815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1155094815
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3069431520
Short name T771
Test name
Test status
Simulation time 932746168 ps
CPU time 3.06 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:51:36 PM PDT 24
Peak memory 200084 kb
Host smart-86095445-8344-41f4-b7e6-f8979f2fd99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069431520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3069431520
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3610535349
Short name T565
Test name
Test status
Simulation time 23246397026 ps
CPU time 5.86 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 198068 kb
Host smart-0a1b3e91-c9bb-4236-9ac4-2506c5b04d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610535349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3610535349
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3998850405
Short name T874
Test name
Test status
Simulation time 260851645403 ps
CPU time 338.53 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 07:04:01 PM PDT 24
Peak memory 200236 kb
Host smart-fa8737d2-573c-4a42-98ac-46f1c00ad6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998850405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3998850405
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2636809977
Short name T1062
Test name
Test status
Simulation time 50535946010 ps
CPU time 47.33 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 06:59:02 PM PDT 24
Peak memory 200208 kb
Host smart-7ec4cc38-afc3-4f32-a817-0c85ee374ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636809977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2636809977
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.702405986
Short name T861
Test name
Test status
Simulation time 42833360259 ps
CPU time 20.06 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:58:42 PM PDT 24
Peak memory 200256 kb
Host smart-7bda34bf-0f05-43d0-9f09-843c69799278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702405986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.702405986
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1230376831
Short name T831
Test name
Test status
Simulation time 225146453524 ps
CPU time 93.04 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:59:58 PM PDT 24
Peak memory 199964 kb
Host smart-43d04a06-a9d2-4b2b-b24e-f5ecd2456040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230376831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1230376831
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2574695340
Short name T154
Test name
Test status
Simulation time 102551727113 ps
CPU time 47.09 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:59:12 PM PDT 24
Peak memory 200260 kb
Host smart-d682cc91-7d17-4bee-9e4b-b3329443e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574695340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2574695340
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3060403464
Short name T156
Test name
Test status
Simulation time 40826113858 ps
CPU time 11.84 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:58:36 PM PDT 24
Peak memory 200216 kb
Host smart-717e492a-4447-40fd-8cfd-d816d9beff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060403464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3060403464
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.369068935
Short name T733
Test name
Test status
Simulation time 124269036760 ps
CPU time 55.13 seconds
Started Jul 23 06:58:23 PM PDT 24
Finished Jul 23 06:59:21 PM PDT 24
Peak memory 200208 kb
Host smart-2e948f51-b2b7-42cb-961f-45e036073370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369068935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.369068935
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3858093578
Short name T37
Test name
Test status
Simulation time 86047908278 ps
CPU time 59.31 seconds
Started Jul 23 06:58:24 PM PDT 24
Finished Jul 23 06:59:25 PM PDT 24
Peak memory 200208 kb
Host smart-044eac42-5b18-416e-beed-4d35984bb317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858093578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3858093578
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.324117419
Short name T530
Test name
Test status
Simulation time 40025993 ps
CPU time 0.55 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:47 PM PDT 24
Peak memory 195868 kb
Host smart-8cfade1e-0bd8-42ed-bedf-05a9bc0e8172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324117419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.324117419
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3653173445
Short name T1
Test name
Test status
Simulation time 293144815467 ps
CPU time 56.33 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:52:29 PM PDT 24
Peak memory 200232 kb
Host smart-1ef2c686-535c-4beb-82ed-29b5536b3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653173445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3653173445
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1227777539
Short name T363
Test name
Test status
Simulation time 57509988311 ps
CPU time 43.46 seconds
Started Jul 23 06:51:28 PM PDT 24
Finished Jul 23 06:52:14 PM PDT 24
Peak memory 200180 kb
Host smart-015b9a9f-ddc5-40f7-b68e-737047c43b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227777539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1227777539
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3756335653
Short name T807
Test name
Test status
Simulation time 192774058420 ps
CPU time 97.07 seconds
Started Jul 23 06:51:28 PM PDT 24
Finished Jul 23 06:53:08 PM PDT 24
Peak memory 200164 kb
Host smart-c41cd4c2-e691-4c73-8192-395e36227b17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756335653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3756335653
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3225117588
Short name T573
Test name
Test status
Simulation time 67033765616 ps
CPU time 126.28 seconds
Started Jul 23 06:51:36 PM PDT 24
Finished Jul 23 06:53:43 PM PDT 24
Peak memory 200180 kb
Host smart-0e3404eb-21f5-40ab-a9ec-2efb606d039e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225117588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3225117588
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3174207953
Short name T644
Test name
Test status
Simulation time 11202662597 ps
CPU time 18.86 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:51:52 PM PDT 24
Peak memory 199920 kb
Host smart-944a84ec-bb3f-4059-a048-516aa5fa4a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174207953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3174207953
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.597766478
Short name T141
Test name
Test status
Simulation time 71887054159 ps
CPU time 63.84 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:52:31 PM PDT 24
Peak memory 200388 kb
Host smart-e9357244-d62f-42c4-a79e-7538d6150243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597766478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.597766478
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2977798369
Short name T919
Test name
Test status
Simulation time 16409514626 ps
CPU time 105.59 seconds
Started Jul 23 06:51:33 PM PDT 24
Finished Jul 23 06:53:21 PM PDT 24
Peak memory 200216 kb
Host smart-c2af82ab-95cd-42bf-8d72-e8b32c8658f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977798369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2977798369
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.219281465
Short name T435
Test name
Test status
Simulation time 2935369769 ps
CPU time 16.92 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:51:44 PM PDT 24
Peak memory 199148 kb
Host smart-372dad52-8b32-46a7-8078-ebca46f1c349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219281465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.219281465
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.876287588
Short name T554
Test name
Test status
Simulation time 131089798523 ps
CPU time 65.34 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:52:37 PM PDT 24
Peak memory 199872 kb
Host smart-3ce75d75-0269-432e-880d-04c0587562f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876287588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.876287588
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3828083299
Short name T1154
Test name
Test status
Simulation time 2175621785 ps
CPU time 1.57 seconds
Started Jul 23 06:51:42 PM PDT 24
Finished Jul 23 06:51:46 PM PDT 24
Peak memory 195696 kb
Host smart-863a786f-d83f-41fe-812e-a13342cbee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828083299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3828083299
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4054209326
Short name T1078
Test name
Test status
Simulation time 5981498516 ps
CPU time 32.23 seconds
Started Jul 23 06:51:38 PM PDT 24
Finished Jul 23 06:52:12 PM PDT 24
Peak memory 200000 kb
Host smart-1aa694a7-21dd-4c42-8202-efe678b0a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054209326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4054209326
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1194188978
Short name T893
Test name
Test status
Simulation time 47747182250 ps
CPU time 275.96 seconds
Started Jul 23 06:51:33 PM PDT 24
Finished Jul 23 06:56:11 PM PDT 24
Peak memory 200192 kb
Host smart-09aca992-0818-4c81-946a-6ba5ca4ed285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194188978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1194188978
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.363309213
Short name T648
Test name
Test status
Simulation time 3561502207 ps
CPU time 2.44 seconds
Started Jul 23 06:51:43 PM PDT 24
Finished Jul 23 06:51:47 PM PDT 24
Peak memory 200116 kb
Host smart-6d7b3c29-b519-4a0e-aeeb-39b03cf4ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363309213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.363309213
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.809054803
Short name T131
Test name
Test status
Simulation time 94378266585 ps
CPU time 48.27 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:30 PM PDT 24
Peak memory 200220 kb
Host smart-95538ea6-3aaf-42a6-8aa5-215b3be807be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809054803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.809054803
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1919332120
Short name T423
Test name
Test status
Simulation time 18309735388 ps
CPU time 16.47 seconds
Started Jul 23 06:58:23 PM PDT 24
Finished Jul 23 06:58:42 PM PDT 24
Peak memory 200208 kb
Host smart-e67539c9-abb8-4234-ba2e-eb2386a525db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919332120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1919332120
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3975911200
Short name T520
Test name
Test status
Simulation time 109233460140 ps
CPU time 51.12 seconds
Started Jul 23 06:58:24 PM PDT 24
Finished Jul 23 06:59:17 PM PDT 24
Peak memory 200208 kb
Host smart-15e749b0-3bb6-40ca-bc5f-e5d2c6759f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975911200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3975911200
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.478925266
Short name T1163
Test name
Test status
Simulation time 25664670971 ps
CPU time 45.98 seconds
Started Jul 23 06:58:19 PM PDT 24
Finished Jul 23 06:59:06 PM PDT 24
Peak memory 200176 kb
Host smart-0508686c-ca2b-45fd-8ae5-2fd25b4967a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478925266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.478925266
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.628607092
Short name T642
Test name
Test status
Simulation time 157134890374 ps
CPU time 119.14 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 07:00:24 PM PDT 24
Peak memory 200280 kb
Host smart-f3c66ae2-6ed7-4b4d-a4dc-49e9575b96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628607092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.628607092
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3453633517
Short name T73
Test name
Test status
Simulation time 32062776199 ps
CPU time 51.26 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 06:59:08 PM PDT 24
Peak memory 200196 kb
Host smart-8bbc52e7-d130-4889-ac48-fdefc69a221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453633517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3453633517
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3345234642
Short name T531
Test name
Test status
Simulation time 33196249900 ps
CPU time 11.94 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:58:36 PM PDT 24
Peak memory 200260 kb
Host smart-b72e2ceb-f7c3-4c96-b734-f9c30b139260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345234642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3345234642
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3676773517
Short name T216
Test name
Test status
Simulation time 90597817215 ps
CPU time 192.84 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 07:01:36 PM PDT 24
Peak memory 200260 kb
Host smart-7166a6a6-d773-4134-a1e8-ad1af50bd5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676773517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3676773517
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1996976583
Short name T270
Test name
Test status
Simulation time 97944253333 ps
CPU time 156.15 seconds
Started Jul 23 06:58:15 PM PDT 24
Finished Jul 23 07:00:52 PM PDT 24
Peak memory 200164 kb
Host smart-4927a6d3-b2c4-4440-abd3-e447f28a3119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996976583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1996976583
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.137317540
Short name T1147
Test name
Test status
Simulation time 269041780121 ps
CPU time 20.41 seconds
Started Jul 23 06:58:22 PM PDT 24
Finished Jul 23 06:58:44 PM PDT 24
Peak memory 200140 kb
Host smart-c91ae9e2-2494-4eb6-9479-5f27d7bf4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137317540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.137317540
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2896231098
Short name T512
Test name
Test status
Simulation time 44187468 ps
CPU time 0.55 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:51:41 PM PDT 24
Peak memory 195644 kb
Host smart-e8a4d622-e645-4e97-8f1f-81954deeeb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896231098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2896231098
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1008301389
Short name T951
Test name
Test status
Simulation time 54659427380 ps
CPU time 91.4 seconds
Started Jul 23 06:51:33 PM PDT 24
Finished Jul 23 06:53:06 PM PDT 24
Peak memory 200256 kb
Host smart-6c1a2d83-ec5c-48d8-bed2-d6c82523e891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008301389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1008301389
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1601172783
Short name T1046
Test name
Test status
Simulation time 28060853224 ps
CPU time 20.81 seconds
Started Jul 23 06:51:35 PM PDT 24
Finished Jul 23 06:51:57 PM PDT 24
Peak memory 200256 kb
Host smart-5b421d14-c909-4b52-bcf6-19c4b56e3167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601172783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1601172783
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1243017011
Short name T1152
Test name
Test status
Simulation time 23229458591 ps
CPU time 43.9 seconds
Started Jul 23 06:51:33 PM PDT 24
Finished Jul 23 06:52:19 PM PDT 24
Peak memory 200272 kb
Host smart-65c6a16f-2af6-4f18-90d2-c8291aeedbf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243017011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1243017011
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3227492330
Short name T443
Test name
Test status
Simulation time 159772286417 ps
CPU time 568.99 seconds
Started Jul 23 06:51:43 PM PDT 24
Finished Jul 23 07:01:14 PM PDT 24
Peak memory 200140 kb
Host smart-a8a61f2f-327a-41ab-9660-35bb396f7233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227492330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3227492330
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2666529780
Short name T946
Test name
Test status
Simulation time 122036778 ps
CPU time 0.75 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:51:42 PM PDT 24
Peak memory 195696 kb
Host smart-e094dfc6-22fd-4eb9-b13a-77cc165175ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666529780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2666529780
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.323230930
Short name T701
Test name
Test status
Simulation time 19120164904 ps
CPU time 17.95 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 199252 kb
Host smart-f93b11e1-8af3-4146-a444-ab5328972d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323230930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.323230930
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2211959637
Short name T1094
Test name
Test status
Simulation time 26329462336 ps
CPU time 1400.54 seconds
Started Jul 23 06:51:44 PM PDT 24
Finished Jul 23 07:15:06 PM PDT 24
Peak memory 199924 kb
Host smart-dbe95d3a-912f-4b17-9b57-dd154e72605f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211959637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2211959637
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.705570490
Short name T878
Test name
Test status
Simulation time 2317158583 ps
CPU time 4.11 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:51:36 PM PDT 24
Peak memory 199284 kb
Host smart-5fb804cc-6394-4da9-a4c9-93d4563e947e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705570490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.705570490
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3328778807
Short name T181
Test name
Test status
Simulation time 72462667232 ps
CPU time 30.21 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:12 PM PDT 24
Peak memory 200184 kb
Host smart-e0871703-a964-414e-8492-28c513b95dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328778807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3328778807
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2931750489
Short name T1030
Test name
Test status
Simulation time 49890620257 ps
CPU time 35.2 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:18 PM PDT 24
Peak memory 195984 kb
Host smart-69656396-ebfd-4a8e-93ae-b233b84a648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931750489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2931750489
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2623377299
Short name T1026
Test name
Test status
Simulation time 296823396 ps
CPU time 1.6 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:48 PM PDT 24
Peak memory 199124 kb
Host smart-dbde2a8a-097e-4dd1-bd7b-4732c0715588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623377299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2623377299
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1625006879
Short name T574
Test name
Test status
Simulation time 32456864176 ps
CPU time 615.17 seconds
Started Jul 23 06:51:34 PM PDT 24
Finished Jul 23 07:01:50 PM PDT 24
Peak memory 200188 kb
Host smart-093e99ef-bcd0-4257-b4bd-fbed9cee39d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625006879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1625006879
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1074073991
Short name T693
Test name
Test status
Simulation time 90247602398 ps
CPU time 320.92 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:57:04 PM PDT 24
Peak memory 209776 kb
Host smart-c5007259-ea4a-4dd3-ae84-642c96cde720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074073991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1074073991
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3515089251
Short name T896
Test name
Test status
Simulation time 11847549778 ps
CPU time 36.83 seconds
Started Jul 23 06:51:44 PM PDT 24
Finished Jul 23 06:52:23 PM PDT 24
Peak memory 199648 kb
Host smart-cf75f238-a1a3-4e04-9655-fcbe452afb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515089251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3515089251
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4110428275
Short name T662
Test name
Test status
Simulation time 303289465531 ps
CPU time 73.98 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:52:54 PM PDT 24
Peak memory 200244 kb
Host smart-2d43c229-38a2-4648-8e38-06eb152ccf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110428275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4110428275
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.110487366
Short name T186
Test name
Test status
Simulation time 82767425081 ps
CPU time 69.89 seconds
Started Jul 23 06:58:23 PM PDT 24
Finished Jul 23 06:59:35 PM PDT 24
Peak memory 200144 kb
Host smart-03d1fe11-6b80-40c7-8b79-5ac5833a4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110487366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.110487366
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2949710850
Short name T832
Test name
Test status
Simulation time 378884887102 ps
CPU time 54.01 seconds
Started Jul 23 06:58:36 PM PDT 24
Finished Jul 23 06:59:31 PM PDT 24
Peak memory 200240 kb
Host smart-b12904d1-462f-446d-8c5d-9bdd34dd281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949710850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2949710850
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.314031133
Short name T986
Test name
Test status
Simulation time 16529265222 ps
CPU time 27.91 seconds
Started Jul 23 06:58:30 PM PDT 24
Finished Jul 23 06:58:59 PM PDT 24
Peak memory 200444 kb
Host smart-c29fcc18-d63b-4981-9309-04f1761b691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314031133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.314031133
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3089889260
Short name T1130
Test name
Test status
Simulation time 26931220578 ps
CPU time 12.95 seconds
Started Jul 23 06:58:32 PM PDT 24
Finished Jul 23 06:58:46 PM PDT 24
Peak memory 200212 kb
Host smart-21b6fad9-bbb3-4f66-a442-194dcb644bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089889260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3089889260
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1485641900
Short name T860
Test name
Test status
Simulation time 162989762969 ps
CPU time 446.12 seconds
Started Jul 23 06:58:39 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 200268 kb
Host smart-06bc25f2-f7ea-4f1d-9cf7-dc2593c65855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485641900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1485641900
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2919187077
Short name T1063
Test name
Test status
Simulation time 18481661508 ps
CPU time 8.62 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:58:47 PM PDT 24
Peak memory 199928 kb
Host smart-5bee52e0-039f-4c88-ba47-66d7048ef6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919187077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2919187077
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3316664287
Short name T974
Test name
Test status
Simulation time 25396537164 ps
CPU time 12.83 seconds
Started Jul 23 06:58:29 PM PDT 24
Finished Jul 23 06:58:43 PM PDT 24
Peak memory 200132 kb
Host smart-b961d362-64ea-451b-bf9d-7a9447838c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316664287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3316664287
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.231178840
Short name T527
Test name
Test status
Simulation time 36741828365 ps
CPU time 26.97 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:59:05 PM PDT 24
Peak memory 200020 kb
Host smart-e20ea39e-a761-40cb-b2fb-a10147e583f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231178840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.231178840
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2322321775
Short name T634
Test name
Test status
Simulation time 10659546 ps
CPU time 0.53 seconds
Started Jul 23 06:51:44 PM PDT 24
Finished Jul 23 06:51:46 PM PDT 24
Peak memory 194588 kb
Host smart-2fc8dca9-9e3b-4b4a-a78f-f643d8d06ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322321775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2322321775
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.594125081
Short name T456
Test name
Test status
Simulation time 58790301934 ps
CPU time 51.38 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 200160 kb
Host smart-12eb506d-d511-4748-97ad-9f617e828863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594125081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.594125081
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3309739711
Short name T1092
Test name
Test status
Simulation time 72054903140 ps
CPU time 32.28 seconds
Started Jul 23 06:51:38 PM PDT 24
Finished Jul 23 06:52:11 PM PDT 24
Peak memory 200252 kb
Host smart-f13b0d06-09a7-46be-a610-651c82a3a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309739711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3309739711
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2692325559
Short name T712
Test name
Test status
Simulation time 3388735068 ps
CPU time 6.32 seconds
Started Jul 23 06:51:37 PM PDT 24
Finished Jul 23 06:51:44 PM PDT 24
Peak memory 200260 kb
Host smart-33d9d589-2341-4184-8a01-fb3427101f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692325559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2692325559
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1275233556
Short name T6
Test name
Test status
Simulation time 45628042068 ps
CPU time 60.11 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:43 PM PDT 24
Peak memory 200200 kb
Host smart-6401f1b7-f3b7-4505-8da6-9998f6b7eaa6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275233556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1275233556
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.617888127
Short name T656
Test name
Test status
Simulation time 92862129940 ps
CPU time 633.6 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 07:02:14 PM PDT 24
Peak memory 200136 kb
Host smart-2dd95c28-7b96-4dd5-8d31-e996dade9e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617888127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.617888127
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1574504410
Short name T911
Test name
Test status
Simulation time 1596164801 ps
CPU time 2.48 seconds
Started Jul 23 06:51:37 PM PDT 24
Finished Jul 23 06:51:41 PM PDT 24
Peak memory 198524 kb
Host smart-e6475421-1b66-4d5b-a777-4f2a031f3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574504410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1574504410
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3650539420
Short name T606
Test name
Test status
Simulation time 46501979820 ps
CPU time 39.79 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:52:23 PM PDT 24
Peak memory 199072 kb
Host smart-aae0decb-c130-4251-a027-aeaf2b275414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650539420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3650539420
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.742090486
Short name T762
Test name
Test status
Simulation time 16631610535 ps
CPU time 217.11 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:55:21 PM PDT 24
Peak memory 200172 kb
Host smart-e54a1c2c-3af5-4595-87c3-363f4ede6e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742090486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.742090486
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3611243014
Short name T578
Test name
Test status
Simulation time 5476530113 ps
CPU time 23.6 seconds
Started Jul 23 06:51:43 PM PDT 24
Finished Jul 23 06:52:08 PM PDT 24
Peak memory 199396 kb
Host smart-8ae5361e-0ec5-40dd-8c1c-7edb5c767133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611243014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3611243014
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1366496895
Short name T1120
Test name
Test status
Simulation time 179502033498 ps
CPU time 231.3 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:55:35 PM PDT 24
Peak memory 200204 kb
Host smart-a37e45ef-b2b9-48f0-9360-1595c8b02dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366496895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1366496895
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2783685931
Short name T607
Test name
Test status
Simulation time 4224122296 ps
CPU time 1.05 seconds
Started Jul 23 06:51:37 PM PDT 24
Finished Jul 23 06:51:39 PM PDT 24
Peak memory 197084 kb
Host smart-d3a2f8a9-8a3e-4cb6-b7c5-caec024dcf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783685931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2783685931
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2084771974
Short name T50
Test name
Test status
Simulation time 567452218 ps
CPU time 1.44 seconds
Started Jul 23 06:51:37 PM PDT 24
Finished Jul 23 06:51:39 PM PDT 24
Peak memory 200184 kb
Host smart-b08266a0-060e-452c-8106-721974ece6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084771974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2084771974
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3637584974
Short name T551
Test name
Test status
Simulation time 345159449305 ps
CPU time 1665.69 seconds
Started Jul 23 06:51:43 PM PDT 24
Finished Jul 23 07:19:31 PM PDT 24
Peak memory 200192 kb
Host smart-aed489a1-3cbe-43bd-94d5-5b646203b3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637584974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3637584974
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2358127857
Short name T120
Test name
Test status
Simulation time 44309546217 ps
CPU time 484.69 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:59:51 PM PDT 24
Peak memory 216880 kb
Host smart-7ba96237-5f87-4a5d-8e29-850f05ba350e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358127857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2358127857
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.431926161
Short name T343
Test name
Test status
Simulation time 7465527799 ps
CPU time 10.93 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:51:54 PM PDT 24
Peak memory 200200 kb
Host smart-f997ca6a-c88d-483d-821a-c0f575b84368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431926161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.431926161
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3384178188
Short name T314
Test name
Test status
Simulation time 46985845619 ps
CPU time 73.27 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:52:57 PM PDT 24
Peak memory 200256 kb
Host smart-84630356-ad2a-4116-9017-34a889c98d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384178188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3384178188
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3712014177
Short name T277
Test name
Test status
Simulation time 11757153290 ps
CPU time 17.18 seconds
Started Jul 23 06:58:39 PM PDT 24
Finished Jul 23 06:58:57 PM PDT 24
Peak memory 200168 kb
Host smart-e616a508-3829-484b-a71a-0b1e6c3ab644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712014177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3712014177
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3766604271
Short name T365
Test name
Test status
Simulation time 54402601801 ps
CPU time 22.98 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:59:01 PM PDT 24
Peak memory 200272 kb
Host smart-5428154a-8185-4e35-b73d-a8c93e184186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766604271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3766604271
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3156746160
Short name T1029
Test name
Test status
Simulation time 28226794537 ps
CPU time 16.93 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:58:55 PM PDT 24
Peak memory 199976 kb
Host smart-eadf6e21-db93-4915-83d3-527d66ed99a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156746160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3156746160
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.974570803
Short name T308
Test name
Test status
Simulation time 64890543847 ps
CPU time 47.2 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:59:25 PM PDT 24
Peak memory 200212 kb
Host smart-b3feb9b4-f439-4b93-a669-1c9892d37da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974570803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.974570803
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2233213149
Short name T965
Test name
Test status
Simulation time 101090216097 ps
CPU time 80.67 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:59:58 PM PDT 24
Peak memory 200244 kb
Host smart-a8d2e2af-1103-4151-b3a6-3c552b6368c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233213149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2233213149
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4269311328
Short name T674
Test name
Test status
Simulation time 83090751946 ps
CPU time 65.07 seconds
Started Jul 23 06:58:37 PM PDT 24
Finished Jul 23 06:59:43 PM PDT 24
Peak memory 200208 kb
Host smart-fa518868-ac10-4c59-8838-5ca08184f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269311328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4269311328
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2899680313
Short name T952
Test name
Test status
Simulation time 166531667238 ps
CPU time 245.72 seconds
Started Jul 23 06:58:36 PM PDT 24
Finished Jul 23 07:02:43 PM PDT 24
Peak memory 200192 kb
Host smart-f15e4170-7e26-4b4f-83cd-219c71ca7601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899680313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2899680313
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3841636104
Short name T978
Test name
Test status
Simulation time 36183448 ps
CPU time 0.56 seconds
Started Jul 23 06:51:49 PM PDT 24
Finished Jul 23 06:51:51 PM PDT 24
Peak memory 194428 kb
Host smart-2b515548-0239-46d1-9bf1-11cdeecfdb8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841636104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3841636104
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1177830923
Short name T550
Test name
Test status
Simulation time 22674302718 ps
CPU time 37.62 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 06:52:21 PM PDT 24
Peak memory 200252 kb
Host smart-e420ba4f-73e7-4999-8605-b4daec510719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177830923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1177830923
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.165119932
Short name T77
Test name
Test status
Simulation time 110853526318 ps
CPU time 158.28 seconds
Started Jul 23 06:51:42 PM PDT 24
Finished Jul 23 06:54:23 PM PDT 24
Peak memory 200276 kb
Host smart-44d04488-9e64-4955-bf23-89cffb65b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165119932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.165119932
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3055187037
Short name T1081
Test name
Test status
Simulation time 12555019000 ps
CPU time 21.18 seconds
Started Jul 23 06:51:39 PM PDT 24
Finished Jul 23 06:52:02 PM PDT 24
Peak memory 200084 kb
Host smart-bf56f547-5c7e-4f74-a3b0-40d77502e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055187037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3055187037
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3268085874
Short name T702
Test name
Test status
Simulation time 13776593689 ps
CPU time 25.11 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:08 PM PDT 24
Peak memory 200232 kb
Host smart-03ce7074-0401-4e3b-9861-77391e1b598d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268085874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3268085874
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.287569483
Short name T81
Test name
Test status
Simulation time 104011223807 ps
CPU time 115.38 seconds
Started Jul 23 06:51:42 PM PDT 24
Finished Jul 23 06:53:40 PM PDT 24
Peak memory 200240 kb
Host smart-00082082-71e0-4644-a5ec-d4c500bc2316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287569483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.287569483
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.30727903
Short name T410
Test name
Test status
Simulation time 10281478608 ps
CPU time 23.93 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:07 PM PDT 24
Peak memory 198860 kb
Host smart-edb6199a-6fa9-44a4-970b-91dc0cef3811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30727903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.30727903
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2447513720
Short name T487
Test name
Test status
Simulation time 71372065329 ps
CPU time 26.17 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:52:09 PM PDT 24
Peak memory 208240 kb
Host smart-8466c83d-82b6-46e7-9319-d3de065ac27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447513720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2447513720
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1383857853
Short name T515
Test name
Test status
Simulation time 12884623284 ps
CPU time 377.8 seconds
Started Jul 23 06:51:46 PM PDT 24
Finished Jul 23 06:58:05 PM PDT 24
Peak memory 200148 kb
Host smart-945c72bd-df03-4d1c-b1e4-f6568462bf24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383857853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1383857853
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3135551840
Short name T430
Test name
Test status
Simulation time 7264393549 ps
CPU time 3.92 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:51:46 PM PDT 24
Peak memory 198916 kb
Host smart-550f5986-3f6c-416a-a873-8c22504bcfb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135551840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3135551840
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3237973455
Short name T496
Test name
Test status
Simulation time 17658279246 ps
CPU time 45.88 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:52:33 PM PDT 24
Peak memory 200240 kb
Host smart-3556ced0-04d3-4111-9f9b-ebe0a4238850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237973455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3237973455
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2463978213
Short name T319
Test name
Test status
Simulation time 31161239978 ps
CPU time 5.26 seconds
Started Jul 23 06:51:49 PM PDT 24
Finished Jul 23 06:51:56 PM PDT 24
Peak memory 196208 kb
Host smart-679a1c34-1027-4b51-b653-8e8fb8cdb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463978213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2463978213
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2499830182
Short name T1067
Test name
Test status
Simulation time 651240662 ps
CPU time 1.65 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:49 PM PDT 24
Peak memory 200176 kb
Host smart-cf5f5a80-30b0-4a09-9f2f-21171aa42c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499830182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2499830182
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2027626701
Short name T710
Test name
Test status
Simulation time 235959693555 ps
CPU time 331.59 seconds
Started Jul 23 06:51:40 PM PDT 24
Finished Jul 23 06:57:15 PM PDT 24
Peak memory 200252 kb
Host smart-8f85e7d7-21cc-4f7d-88b6-8c46562f2977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027626701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2027626701
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2681453802
Short name T56
Test name
Test status
Simulation time 497747271522 ps
CPU time 1514.18 seconds
Started Jul 23 06:51:41 PM PDT 24
Finished Jul 23 07:16:57 PM PDT 24
Peak memory 230680 kb
Host smart-9ae5428d-4fca-4a5c-bd48-2eb38520840a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681453802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2681453802
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4276932630
Short name T1133
Test name
Test status
Simulation time 1141025202 ps
CPU time 2.29 seconds
Started Jul 23 06:51:49 PM PDT 24
Finished Jul 23 06:51:52 PM PDT 24
Peak memory 198968 kb
Host smart-ec925c63-8cff-403e-8fb5-86bb6d577474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276932630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4276932630
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1614219223
Short name T330
Test name
Test status
Simulation time 25016475899 ps
CPU time 10.79 seconds
Started Jul 23 06:51:44 PM PDT 24
Finished Jul 23 06:51:56 PM PDT 24
Peak memory 200164 kb
Host smart-3de7bda3-360b-4468-84f9-d4375c5ea472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614219223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1614219223
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.833081887
Short name T248
Test name
Test status
Simulation time 136536590084 ps
CPU time 85.29 seconds
Started Jul 23 06:58:41 PM PDT 24
Finished Jul 23 07:00:08 PM PDT 24
Peak memory 200184 kb
Host smart-ccd53da9-9c22-44f8-9f86-bc9f56fb8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833081887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.833081887
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3022958566
Short name T1016
Test name
Test status
Simulation time 116865550848 ps
CPU time 94.48 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 07:00:21 PM PDT 24
Peak memory 200076 kb
Host smart-da0b61a4-08b1-42d6-aa8b-b42e3db55f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022958566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3022958566
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1331973274
Short name T283
Test name
Test status
Simulation time 57627972209 ps
CPU time 9.81 seconds
Started Jul 23 06:58:39 PM PDT 24
Finished Jul 23 06:58:49 PM PDT 24
Peak memory 200260 kb
Host smart-c48d33aa-7a20-4961-8512-f572d1f728b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331973274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1331973274
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3155535607
Short name T253
Test name
Test status
Simulation time 77317072309 ps
CPU time 168.95 seconds
Started Jul 23 06:58:40 PM PDT 24
Finished Jul 23 07:01:30 PM PDT 24
Peak memory 200188 kb
Host smart-54c51ac4-d1a4-4575-9ac4-e7fdec7f0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155535607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3155535607
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3685115141
Short name T1027
Test name
Test status
Simulation time 82744851586 ps
CPU time 234.21 seconds
Started Jul 23 06:58:35 PM PDT 24
Finished Jul 23 07:02:30 PM PDT 24
Peak memory 200224 kb
Host smart-6417c4af-256f-4b20-ba73-fb2cd8ba6f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685115141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3685115141
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.4105997160
Short name T783
Test name
Test status
Simulation time 13488453960 ps
CPU time 7.62 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:58:53 PM PDT 24
Peak memory 200096 kb
Host smart-2165273d-2d90-4abc-9fce-4cac223f47ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105997160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.4105997160
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3247314696
Short name T1015
Test name
Test status
Simulation time 33391704423 ps
CPU time 48.51 seconds
Started Jul 23 06:58:41 PM PDT 24
Finished Jul 23 06:59:30 PM PDT 24
Peak memory 200104 kb
Host smart-bfb828b0-c424-47fd-b086-5c2d283fa9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247314696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3247314696
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4092724108
Short name T1042
Test name
Test status
Simulation time 94036033800 ps
CPU time 29.65 seconds
Started Jul 23 06:58:41 PM PDT 24
Finished Jul 23 06:59:11 PM PDT 24
Peak memory 200256 kb
Host smart-f45e5bf8-556f-4dc1-8875-2f44a320af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092724108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4092724108
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2950778213
Short name T957
Test name
Test status
Simulation time 107924154598 ps
CPU time 48.5 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:59:33 PM PDT 24
Peak memory 200076 kb
Host smart-256f661e-7d2a-409e-a9c1-142d90332dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950778213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2950778213
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1799555434
Short name T1076
Test name
Test status
Simulation time 55719435552 ps
CPU time 140.59 seconds
Started Jul 23 06:58:40 PM PDT 24
Finished Jul 23 07:01:02 PM PDT 24
Peak memory 200248 kb
Host smart-bed9e271-ea03-48b6-a052-c967fea1534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799555434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1799555434
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2794949990
Short name T129
Test name
Test status
Simulation time 58981294 ps
CPU time 0.56 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 195856 kb
Host smart-255cf935-4f18-46c1-9f95-4d6cbd4c6b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794949990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2794949990
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3114046450
Short name T118
Test name
Test status
Simulation time 155923228343 ps
CPU time 219.73 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 06:54:49 PM PDT 24
Peak memory 200264 kb
Host smart-6667fa24-791c-4988-a1ff-b162f7dcc88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114046450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3114046450
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.112482756
Short name T830
Test name
Test status
Simulation time 10331534027 ps
CPU time 15.7 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:19 PM PDT 24
Peak memory 200196 kb
Host smart-b76bde2e-7059-493e-a6b5-5df6f912196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112482756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.112482756
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2234291801
Short name T977
Test name
Test status
Simulation time 43661931977 ps
CPU time 30.36 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:34 PM PDT 24
Peak memory 200232 kb
Host smart-2d91388a-aa7a-4ff4-ae14-2383b7571b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234291801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2234291801
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1271791285
Short name T635
Test name
Test status
Simulation time 277296217333 ps
CPU time 130.1 seconds
Started Jul 23 06:51:03 PM PDT 24
Finished Jul 23 06:53:16 PM PDT 24
Peak memory 199460 kb
Host smart-619cacd1-86a9-4f39-853a-7dc5661251b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271791285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1271791285
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.355088618
Short name T442
Test name
Test status
Simulation time 62654283434 ps
CPU time 363.9 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 06:57:13 PM PDT 24
Peak memory 200228 kb
Host smart-3c31aa9e-e1e5-469b-b99b-bcc1ce6a0261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355088618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.355088618
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.646700877
Short name T558
Test name
Test status
Simulation time 4137114611 ps
CPU time 7.79 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:51:10 PM PDT 24
Peak memory 199984 kb
Host smart-d485d913-4deb-483b-857f-fd199a346042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646700877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.646700877
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2759217846
Short name T273
Test name
Test status
Simulation time 136103949305 ps
CPU time 48.27 seconds
Started Jul 23 06:51:04 PM PDT 24
Finished Jul 23 06:51:55 PM PDT 24
Peak memory 199324 kb
Host smart-221cfacc-d4e0-4561-a54d-17b04bf42079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759217846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2759217846
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1544865351
Short name T329
Test name
Test status
Simulation time 17148105979 ps
CPU time 136.19 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:53:19 PM PDT 24
Peak memory 200148 kb
Host smart-5798b488-9f52-448e-94d7-dad750be2a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544865351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1544865351
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1922019525
Short name T1109
Test name
Test status
Simulation time 5078859385 ps
CPU time 12.39 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 199480 kb
Host smart-a20c351b-f681-4300-b98e-4de0b481fe7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922019525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1922019525
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2737008727
Short name T652
Test name
Test status
Simulation time 159267365630 ps
CPU time 163.63 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 200248 kb
Host smart-6b87b403-0f1f-46d5-a3b8-e96400d4f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737008727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2737008727
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3528163222
Short name T338
Test name
Test status
Simulation time 36290843705 ps
CPU time 4.44 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 196520 kb
Host smart-2760b5f3-3550-4817-b192-2f9d4c023e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528163222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3528163222
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2948057217
Short name T26
Test name
Test status
Simulation time 77877536 ps
CPU time 0.89 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:51:06 PM PDT 24
Peak memory 218780 kb
Host smart-79d33cbd-293b-4d7b-ad99-d89f9b825b65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948057217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2948057217
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4203048828
Short name T837
Test name
Test status
Simulation time 270019198 ps
CPU time 1.66 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:51:06 PM PDT 24
Peak memory 198964 kb
Host smart-4e88ac6c-d749-4276-8b8d-32aeb2e1d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203048828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4203048828
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3758112056
Short name T772
Test name
Test status
Simulation time 229188940858 ps
CPU time 171.4 seconds
Started Jul 23 06:51:03 PM PDT 24
Finished Jul 23 06:54:03 PM PDT 24
Peak memory 208568 kb
Host smart-a908c2f3-8bac-4c42-b965-167934c038dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758112056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3758112056
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1050750641
Short name T200
Test name
Test status
Simulation time 52963817237 ps
CPU time 252.52 seconds
Started Jul 23 06:51:04 PM PDT 24
Finished Jul 23 06:55:19 PM PDT 24
Peak memory 215796 kb
Host smart-a103d1b3-ce20-48c7-a583-ad6a65d78980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050750641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1050750641
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3794365134
Short name T311
Test name
Test status
Simulation time 9903311639 ps
CPU time 7.71 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 200160 kb
Host smart-6009ff8e-3c6e-4fb7-906f-b373895d9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794365134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3794365134
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4145027306
Short name T960
Test name
Test status
Simulation time 47799804182 ps
CPU time 44.21 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:51:49 PM PDT 24
Peak memory 200220 kb
Host smart-4438c53c-ebba-410e-accc-785730b412d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145027306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4145027306
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1796406417
Short name T384
Test name
Test status
Simulation time 15465882 ps
CPU time 0.57 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:47 PM PDT 24
Peak memory 194604 kb
Host smart-7c85d9bf-d988-4cdd-81ce-5442cca17877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796406417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1796406417
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.499527142
Short name T447
Test name
Test status
Simulation time 47229857418 ps
CPU time 14.15 seconds
Started Jul 23 06:51:44 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 200256 kb
Host smart-66d27002-8e6a-463e-b6d2-e867199c063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499527142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.499527142
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2589215263
Short name T296
Test name
Test status
Simulation time 114974497457 ps
CPU time 156.61 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:54:24 PM PDT 24
Peak memory 200244 kb
Host smart-0d098aee-a71f-4797-b4dc-fea66c20fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589215263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2589215263
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4256071362
Short name T843
Test name
Test status
Simulation time 6701034698 ps
CPU time 10.92 seconds
Started Jul 23 06:51:53 PM PDT 24
Finished Jul 23 06:52:05 PM PDT 24
Peak memory 197568 kb
Host smart-82ea8acb-bdc8-4300-9a14-0617e15ca659
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256071362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4256071362
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4027166690
Short name T137
Test name
Test status
Simulation time 138240019122 ps
CPU time 413.1 seconds
Started Jul 23 06:51:46 PM PDT 24
Finished Jul 23 06:58:41 PM PDT 24
Peak memory 200384 kb
Host smart-56d4a909-e625-464b-9ef9-c9391c9d473f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027166690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4027166690
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2997312631
Short name T937
Test name
Test status
Simulation time 10111984281 ps
CPU time 6.68 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:53 PM PDT 24
Peak memory 200164 kb
Host smart-53e1ff38-63c7-4875-8da4-14765b1da043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997312631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2997312631
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3101866186
Short name T792
Test name
Test status
Simulation time 152755565134 ps
CPU time 38.25 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:52:25 PM PDT 24
Peak memory 200208 kb
Host smart-482e0750-87e9-43f1-9eee-2a6c459f7082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101866186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3101866186
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.90472173
Short name T323
Test name
Test status
Simulation time 16878804615 ps
CPU time 753.72 seconds
Started Jul 23 06:51:46 PM PDT 24
Finished Jul 23 07:04:21 PM PDT 24
Peak memory 200376 kb
Host smart-c628cb91-ca0c-40cc-a77d-a2bc8a1a7aba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90472173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.90472173
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2876145594
Short name T113
Test name
Test status
Simulation time 5300717467 ps
CPU time 44.6 seconds
Started Jul 23 06:51:46 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 200232 kb
Host smart-3d188afc-70bb-41e5-9993-b3e19374a6a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876145594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2876145594
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3311604246
Short name T1136
Test name
Test status
Simulation time 205996090163 ps
CPU time 172.78 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:54:44 PM PDT 24
Peak memory 200180 kb
Host smart-f64746b6-35d2-45e4-bd55-440c9d66ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311604246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3311604246
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.97593436
Short name T2
Test name
Test status
Simulation time 49831831278 ps
CPU time 17.83 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:52:05 PM PDT 24
Peak memory 196040 kb
Host smart-64b701dc-e6e9-43c4-bccc-1ff77d5dc733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97593436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.97593436
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3315527317
Short name T1083
Test name
Test status
Simulation time 476860825 ps
CPU time 1.18 seconds
Started Jul 23 06:51:49 PM PDT 24
Finished Jul 23 06:51:52 PM PDT 24
Peak memory 199072 kb
Host smart-c6675a5f-cc2a-4d9c-a2f9-2631808a8d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315527317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3315527317
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1544512872
Short name T1006
Test name
Test status
Simulation time 260104070704 ps
CPU time 252.98 seconds
Started Jul 23 06:51:53 PM PDT 24
Finished Jul 23 06:56:08 PM PDT 24
Peak memory 200148 kb
Host smart-e0fb0968-84a5-4810-8773-5b0e0fd0669b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544512872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1544512872
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.127421645
Short name T720
Test name
Test status
Simulation time 1075114301 ps
CPU time 1.3 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:48 PM PDT 24
Peak memory 198212 kb
Host smart-37ac7d84-c67c-4be1-8ec6-95d6fad19076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127421645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.127421645
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2963855068
Short name T601
Test name
Test status
Simulation time 76002246495 ps
CPU time 55.82 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 200280 kb
Host smart-cbcc43ae-4b4d-4028-8e8b-b66896b266d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963855068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2963855068
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1899010042
Short name T581
Test name
Test status
Simulation time 14171864764 ps
CPU time 19.52 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:59:05 PM PDT 24
Peak memory 200184 kb
Host smart-a7646847-f4a8-465b-8bcd-fa80a6a0f6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899010042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1899010042
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1704941649
Short name T993
Test name
Test status
Simulation time 68884362554 ps
CPU time 39.07 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:25 PM PDT 24
Peak memory 200136 kb
Host smart-5cb2df39-2891-463f-a8ff-532f1759fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704941649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1704941649
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2785541287
Short name T142
Test name
Test status
Simulation time 12717220559 ps
CPU time 21.52 seconds
Started Jul 23 06:58:46 PM PDT 24
Finished Jul 23 06:59:09 PM PDT 24
Peak memory 200064 kb
Host smart-0fb7e372-d76f-41cd-a077-275383654be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785541287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2785541287
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4014504398
Short name T431
Test name
Test status
Simulation time 91635187135 ps
CPU time 38.85 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:59:24 PM PDT 24
Peak memory 200136 kb
Host smart-5858b93c-143c-4537-adc3-a605a4e3b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014504398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4014504398
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2823307831
Short name T1086
Test name
Test status
Simulation time 42472688108 ps
CPU time 33.95 seconds
Started Jul 23 06:58:39 PM PDT 24
Finished Jul 23 06:59:14 PM PDT 24
Peak memory 200188 kb
Host smart-0d508e4b-cbe5-47c9-9e5d-68fe0f8de69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823307831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2823307831
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.338454599
Short name T240
Test name
Test status
Simulation time 26652705735 ps
CPU time 10.89 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:58:56 PM PDT 24
Peak memory 200132 kb
Host smart-2916db46-7405-4481-90d4-8f49df61d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338454599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.338454599
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.388754027
Short name T219
Test name
Test status
Simulation time 27724778199 ps
CPU time 15.08 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:02 PM PDT 24
Peak memory 199932 kb
Host smart-f550e58a-e541-415c-bab1-267608a30b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388754027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.388754027
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3213400030
Short name T189
Test name
Test status
Simulation time 183713935679 ps
CPU time 189.89 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 07:01:56 PM PDT 24
Peak memory 200140 kb
Host smart-379e7c07-0900-4bd8-a160-c689b9307633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213400030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3213400030
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.598351796
Short name T758
Test name
Test status
Simulation time 125584244554 ps
CPU time 84.9 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 07:00:11 PM PDT 24
Peak memory 200076 kb
Host smart-eb74501f-6612-43ad-ad03-b4faf35689df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598351796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.598351796
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1153578128
Short name T990
Test name
Test status
Simulation time 15931603 ps
CPU time 0.55 seconds
Started Jul 23 06:51:53 PM PDT 24
Finished Jul 23 06:51:55 PM PDT 24
Peak memory 195604 kb
Host smart-6c9eaa80-c22b-477b-b60a-d9a324675e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153578128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1153578128
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2671395620
Short name T969
Test name
Test status
Simulation time 115302097329 ps
CPU time 32.31 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:52:25 PM PDT 24
Peak memory 200172 kb
Host smart-841fb01f-6d4b-44a2-839a-41eeae15bffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671395620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2671395620
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3821996765
Short name T387
Test name
Test status
Simulation time 52922613936 ps
CPU time 12.02 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:52:06 PM PDT 24
Peak memory 198640 kb
Host smart-fe85ccea-6faf-414a-a5da-2b51e827d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821996765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3821996765
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1744504853
Short name T821
Test name
Test status
Simulation time 135929598767 ps
CPU time 299.75 seconds
Started Jul 23 06:51:53 PM PDT 24
Finished Jul 23 06:56:54 PM PDT 24
Peak memory 200228 kb
Host smart-32aaf09a-cd8e-4bba-8097-37ab737be317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744504853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1744504853
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4228184808
Short name T663
Test name
Test status
Simulation time 11900760966 ps
CPU time 5.23 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:51:56 PM PDT 24
Peak memory 197064 kb
Host smart-ebffd97e-8c2e-44c7-aab6-02c2a3177583
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228184808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4228184808
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.846685160
Short name T38
Test name
Test status
Simulation time 97320853517 ps
CPU time 889.4 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 200176 kb
Host smart-50cdc44e-1dee-4f8d-b95a-692cfff4244c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846685160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.846685160
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2386537848
Short name T1132
Test name
Test status
Simulation time 4324230235 ps
CPU time 11.01 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:52:08 PM PDT 24
Peak memory 200052 kb
Host smart-4e6441d3-6135-4bc7-9f7c-a50bb0257a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386537848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2386537848
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.332425566
Short name T495
Test name
Test status
Simulation time 73702009028 ps
CPU time 36.43 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 200368 kb
Host smart-bbb26ed3-ae06-41a6-a422-f4042319b421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332425566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.332425566
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2221485571
Short name T126
Test name
Test status
Simulation time 9721366755 ps
CPU time 556.46 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 07:01:13 PM PDT 24
Peak memory 200168 kb
Host smart-5dbe33ce-1454-4836-855c-84a58300c9fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221485571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2221485571
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.14684706
Short name T406
Test name
Test status
Simulation time 3704241021 ps
CPU time 23.57 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 198272 kb
Host smart-5dd0ae4c-66f1-4e96-b43e-3a0e3b4d6062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14684706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.14684706
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2837634991
Short name T777
Test name
Test status
Simulation time 67566444367 ps
CPU time 97.08 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:53:34 PM PDT 24
Peak memory 200128 kb
Host smart-f29b3f64-ded0-4f38-a57f-c74f2a0d9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837634991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2837634991
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1708400676
Short name T513
Test name
Test status
Simulation time 4056051452 ps
CPU time 5 seconds
Started Jul 23 06:51:54 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 196484 kb
Host smart-1775c746-3cdf-4b77-ac6e-3b1c4988f793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708400676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1708400676
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2920896754
Short name T737
Test name
Test status
Simulation time 5873434391 ps
CPU time 10.67 seconds
Started Jul 23 06:51:45 PM PDT 24
Finished Jul 23 06:51:58 PM PDT 24
Peak memory 200028 kb
Host smart-3a2d9892-3ef8-43b1-b4de-d67ca223f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920896754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2920896754
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2942542145
Short name T503
Test name
Test status
Simulation time 346849392362 ps
CPU time 460.38 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:59:34 PM PDT 24
Peak memory 200240 kb
Host smart-ede2a75e-2e49-49cf-a306-e353eb687ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942542145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2942542145
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3613323622
Short name T349
Test name
Test status
Simulation time 217476968736 ps
CPU time 516.14 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 07:00:30 PM PDT 24
Peak memory 216660 kb
Host smart-ad319245-13b3-430c-b1ec-6045863372d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613323622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3613323622
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.59463027
Short name T427
Test name
Test status
Simulation time 9238905570 ps
CPU time 1.8 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:51:54 PM PDT 24
Peak memory 199644 kb
Host smart-2d7d09bb-8f85-4da1-8039-6dba285f418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59463027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.59463027
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2436335776
Short name T127
Test name
Test status
Simulation time 95801272550 ps
CPU time 39.42 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:52:33 PM PDT 24
Peak memory 200164 kb
Host smart-a9f472ba-6d17-400f-848c-7b565b8ccf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436335776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2436335776
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1106664200
Short name T1041
Test name
Test status
Simulation time 26673042631 ps
CPU time 19.52 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:07 PM PDT 24
Peak memory 199840 kb
Host smart-d6de403c-664e-4895-879e-46acf805c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106664200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1106664200
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2052004536
Short name T894
Test name
Test status
Simulation time 99749971451 ps
CPU time 27.11 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 06:59:13 PM PDT 24
Peak memory 200080 kb
Host smart-18f34637-0ee4-4530-935d-1aa19a9425fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052004536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2052004536
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.268836532
Short name T207
Test name
Test status
Simulation time 104445204716 ps
CPU time 219.25 seconds
Started Jul 23 06:58:44 PM PDT 24
Finished Jul 23 07:02:25 PM PDT 24
Peak memory 200168 kb
Host smart-8dd71e14-384e-426b-880e-d12a719b4f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268836532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.268836532
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.719471203
Short name T373
Test name
Test status
Simulation time 9372666112 ps
CPU time 13.94 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:59:04 PM PDT 24
Peak memory 199952 kb
Host smart-5019492b-c770-4a23-b95a-396249ea744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719471203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.719471203
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.81084994
Short name T206
Test name
Test status
Simulation time 17655775440 ps
CPU time 27.02 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:13 PM PDT 24
Peak memory 200184 kb
Host smart-2fd6c9c5-9d3f-40b5-9d7a-13cc7be2425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81084994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.81084994
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2540627698
Short name T160
Test name
Test status
Simulation time 29673565033 ps
CPU time 54.84 seconds
Started Jul 23 06:58:46 PM PDT 24
Finished Jul 23 06:59:43 PM PDT 24
Peak memory 200256 kb
Host smart-d5ba9a3d-5c8a-43f5-9f08-0316055e4d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540627698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2540627698
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2116530827
Short name T528
Test name
Test status
Simulation time 18493108 ps
CPU time 0.57 seconds
Started Jul 23 06:51:58 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 194592 kb
Host smart-ff42a004-fb1e-44d2-947d-c3323d0eb0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116530827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2116530827
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1158734017
Short name T324
Test name
Test status
Simulation time 58179591655 ps
CPU time 76.57 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:53:07 PM PDT 24
Peak memory 200216 kb
Host smart-0755b5ed-fe17-4796-bfe1-d8b2f3626556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158734017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1158734017
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4246531103
Short name T935
Test name
Test status
Simulation time 73312728836 ps
CPU time 127.05 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:53:59 PM PDT 24
Peak memory 200284 kb
Host smart-f42afc93-6cac-4cf0-bc02-5eb3434a2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246531103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4246531103
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2996113400
Short name T1173
Test name
Test status
Simulation time 12816032558 ps
CPU time 11.21 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:52:04 PM PDT 24
Peak memory 200184 kb
Host smart-d1272b4f-9735-4c5b-ab24-af19d17de705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996113400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2996113400
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3134675264
Short name T954
Test name
Test status
Simulation time 18311521081 ps
CPU time 7.38 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:52:05 PM PDT 24
Peak memory 197252 kb
Host smart-a6d438c0-7b8f-434c-b4eb-9e00efa6f0a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134675264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3134675264
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3853280113
Short name T112
Test name
Test status
Simulation time 85658910873 ps
CPU time 322.55 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:57:16 PM PDT 24
Peak memory 200228 kb
Host smart-d2582275-b94d-48e4-9fa5-feb1cb4f07b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853280113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3853280113
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3258928515
Short name T1177
Test name
Test status
Simulation time 4162618474 ps
CPU time 8.07 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:52:02 PM PDT 24
Peak memory 198888 kb
Host smart-7540baa9-9e10-4a45-8b29-28d8f291da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258928515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3258928515
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1749925982
Short name T115
Test name
Test status
Simulation time 75021782185 ps
CPU time 24.18 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:52:17 PM PDT 24
Peak memory 199040 kb
Host smart-e20a5ecf-e401-4620-86a7-277204ee451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749925982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1749925982
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1885201745
Short name T356
Test name
Test status
Simulation time 13924570115 ps
CPU time 216.99 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:55:29 PM PDT 24
Peak memory 200252 kb
Host smart-2e3b4577-dbbf-4e62-b98c-2dfc117fde0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885201745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1885201745
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1794330329
Short name T382
Test name
Test status
Simulation time 3066159113 ps
CPU time 5.89 seconds
Started Jul 23 06:51:51 PM PDT 24
Finished Jul 23 06:51:58 PM PDT 24
Peak memory 198280 kb
Host smart-358bbd9c-3cf9-4d6e-bc0d-d6179c9eb52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794330329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1794330329
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2035652244
Short name T1140
Test name
Test status
Simulation time 88645226703 ps
CPU time 71.9 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:53:03 PM PDT 24
Peak memory 200208 kb
Host smart-2b485db9-1e05-4b8e-ab5a-febf92890ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035652244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2035652244
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3970513290
Short name T429
Test name
Test status
Simulation time 4765072806 ps
CPU time 1.25 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:51:53 PM PDT 24
Peak memory 196572 kb
Host smart-94f0165a-15de-463d-84bb-0eb3ce0d6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970513290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3970513290
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.107729060
Short name T901
Test name
Test status
Simulation time 116681207 ps
CPU time 0.99 seconds
Started Jul 23 06:51:50 PM PDT 24
Finished Jul 23 06:51:52 PM PDT 24
Peak memory 198408 kb
Host smart-11286d68-c376-44d0-9e0c-08d57ed501fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107729060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.107729060
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3986457521
Short name T1103
Test name
Test status
Simulation time 310748073171 ps
CPU time 539.46 seconds
Started Jul 23 06:51:58 PM PDT 24
Finished Jul 23 07:00:58 PM PDT 24
Peak memory 200164 kb
Host smart-9b688211-caf2-402b-ae31-c38f097aff4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986457521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3986457521
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3334857133
Short name T464
Test name
Test status
Simulation time 98709834307 ps
CPU time 570.16 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 07:01:23 PM PDT 24
Peak memory 216752 kb
Host smart-92e98db1-aa34-4c44-a3b2-783aea94824c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334857133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3334857133
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3203763227
Short name T927
Test name
Test status
Simulation time 790537871 ps
CPU time 3.15 seconds
Started Jul 23 06:51:53 PM PDT 24
Finished Jul 23 06:51:57 PM PDT 24
Peak memory 199812 kb
Host smart-81fa300b-052d-4b1f-a916-ea27d20647cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203763227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3203763227
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.870950439
Short name T913
Test name
Test status
Simulation time 36578519961 ps
CPU time 53.43 seconds
Started Jul 23 06:51:52 PM PDT 24
Finished Jul 23 06:52:47 PM PDT 24
Peak memory 200204 kb
Host smart-1ea5153c-bd83-4eae-8ab9-c0ee17a4a233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870950439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.870950439
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4294877268
Short name T677
Test name
Test status
Simulation time 121404418148 ps
CPU time 45.42 seconds
Started Jul 23 06:58:47 PM PDT 24
Finished Jul 23 06:59:34 PM PDT 24
Peak memory 200236 kb
Host smart-e572bc54-f243-41df-a52a-a0c1a81dfe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294877268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4294877268
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1965065758
Short name T817
Test name
Test status
Simulation time 160350024980 ps
CPU time 166.63 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 07:01:36 PM PDT 24
Peak memory 200184 kb
Host smart-d6d38b5a-9531-4f34-abee-eda02fc53e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965065758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1965065758
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3761521505
Short name T746
Test name
Test status
Simulation time 51084352453 ps
CPU time 81.16 seconds
Started Jul 23 06:58:53 PM PDT 24
Finished Jul 23 07:00:15 PM PDT 24
Peak memory 200200 kb
Host smart-9f814afc-18da-43ac-8126-6b53386fdba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761521505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3761521505
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1245817118
Short name T220
Test name
Test status
Simulation time 15521926579 ps
CPU time 18.95 seconds
Started Jul 23 06:58:53 PM PDT 24
Finished Jul 23 06:59:13 PM PDT 24
Peak memory 200244 kb
Host smart-232fac8f-dfb0-44a2-a4bd-3a81e193da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245817118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1245817118
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.345517935
Short name T800
Test name
Test status
Simulation time 36786362573 ps
CPU time 13.69 seconds
Started Jul 23 06:58:54 PM PDT 24
Finished Jul 23 06:59:08 PM PDT 24
Peak memory 200200 kb
Host smart-a61b99fb-f693-4416-9c68-95c09b8f6697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345517935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.345517935
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3027049632
Short name T711
Test name
Test status
Simulation time 88363096833 ps
CPU time 106.23 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 200168 kb
Host smart-9748b2a2-b87c-431e-a996-55eb94cfb9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027049632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3027049632
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.855848429
Short name T78
Test name
Test status
Simulation time 50724766563 ps
CPU time 21.12 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:59:12 PM PDT 24
Peak memory 200172 kb
Host smart-e9bdc1aa-09aa-4d2d-85fe-67b07c4b95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855848429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.855848429
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3257779738
Short name T697
Test name
Test status
Simulation time 146467901740 ps
CPU time 62.47 seconds
Started Jul 23 06:58:47 PM PDT 24
Finished Jul 23 06:59:51 PM PDT 24
Peak memory 200072 kb
Host smart-b4a060e6-7461-42ee-8493-97e8f83e6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257779738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3257779738
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3761276290
Short name T653
Test name
Test status
Simulation time 28345175042 ps
CPU time 41.32 seconds
Started Jul 23 06:58:54 PM PDT 24
Finished Jul 23 06:59:36 PM PDT 24
Peak memory 200200 kb
Host smart-2b03d235-a6e6-4d1a-aebe-4e1920fd08aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761276290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3761276290
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1188894106
Short name T444
Test name
Test status
Simulation time 24057847 ps
CPU time 0.57 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 195644 kb
Host smart-ccbeb037-8b69-4bd5-9e6b-8a00ba56af48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188894106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1188894106
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1295306899
Short name T353
Test name
Test status
Simulation time 208592773944 ps
CPU time 142.64 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:54:20 PM PDT 24
Peak memory 200256 kb
Host smart-143b2bb3-aad9-4aa7-b287-57e400dc921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295306899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1295306899
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3279428336
Short name T404
Test name
Test status
Simulation time 58893072989 ps
CPU time 33.51 seconds
Started Jul 23 06:51:57 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 200200 kb
Host smart-b4c35a66-fa05-4a26-9297-093e28e5a9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279428336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3279428336
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.1125934160
Short name T1108
Test name
Test status
Simulation time 30257972070 ps
CPU time 49.62 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 200184 kb
Host smart-e1da96d2-dfcd-4692-93b0-63e68c938893
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125934160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1125934160
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1212202841
Short name T963
Test name
Test status
Simulation time 111828236555 ps
CPU time 635.61 seconds
Started Jul 23 06:51:55 PM PDT 24
Finished Jul 23 07:02:32 PM PDT 24
Peak memory 200252 kb
Host smart-4368a598-0ffa-4cc5-acbd-5f861ca5f553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212202841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1212202841
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3340891436
Short name T1143
Test name
Test status
Simulation time 11048922860 ps
CPU time 11.12 seconds
Started Jul 23 06:51:55 PM PDT 24
Finished Jul 23 06:52:07 PM PDT 24
Peak memory 200120 kb
Host smart-2c2e55a0-ac90-4a71-a137-b9646e15feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340891436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3340891436
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3998300588
Short name T3
Test name
Test status
Simulation time 58213516707 ps
CPU time 15.67 seconds
Started Jul 23 06:51:57 PM PDT 24
Finished Jul 23 06:52:14 PM PDT 24
Peak memory 200012 kb
Host smart-da9f84be-a63e-4db0-8876-d6bc659b6ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998300588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3998300588
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1755632138
Short name T1139
Test name
Test status
Simulation time 10411754744 ps
CPU time 249.76 seconds
Started Jul 23 06:51:58 PM PDT 24
Finished Jul 23 06:56:09 PM PDT 24
Peak memory 200224 kb
Host smart-8a82a5e5-64c1-4d68-a0cd-72280b87ce69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755632138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1755632138
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1783677781
Short name T1182
Test name
Test status
Simulation time 5119579767 ps
CPU time 46.86 seconds
Started Jul 23 06:51:57 PM PDT 24
Finished Jul 23 06:52:45 PM PDT 24
Peak memory 198456 kb
Host smart-12ee5b60-086c-4939-a4a0-2d315c25befd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783677781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1783677781
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2059096933
Short name T615
Test name
Test status
Simulation time 98002882240 ps
CPU time 42.74 seconds
Started Jul 23 06:51:59 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 198676 kb
Host smart-a9b3e2b4-f73b-4cb3-8bd0-127a0d2c372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059096933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2059096933
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2285499197
Short name T567
Test name
Test status
Simulation time 4852178200 ps
CPU time 2.38 seconds
Started Jul 23 06:51:57 PM PDT 24
Finished Jul 23 06:52:01 PM PDT 24
Peak memory 196556 kb
Host smart-8a00d75b-4122-484c-8f4f-165c4706bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285499197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2285499197
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.275082134
Short name T453
Test name
Test status
Simulation time 843164952 ps
CPU time 3.46 seconds
Started Jul 23 06:51:57 PM PDT 24
Finished Jul 23 06:52:01 PM PDT 24
Peak memory 199224 kb
Host smart-88ca766b-3121-4100-a5be-4833b83a347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275082134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.275082134
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2643968600
Short name T1035
Test name
Test status
Simulation time 164133388274 ps
CPU time 652.92 seconds
Started Jul 23 06:52:00 PM PDT 24
Finished Jul 23 07:02:54 PM PDT 24
Peak memory 208520 kb
Host smart-74cd4144-c4f0-4e16-85c4-c5f03b3b3f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643968600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2643968600
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1126244302
Short name T32
Test name
Test status
Simulation time 92996097465 ps
CPU time 1004.78 seconds
Started Jul 23 06:51:55 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 226780 kb
Host smart-45e23785-5717-403d-bee0-119b1be3842f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126244302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1126244302
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1610664918
Short name T569
Test name
Test status
Simulation time 2153293437 ps
CPU time 1.95 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 198736 kb
Host smart-681f69f8-93b2-4155-a1b6-a83d3fa7920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610664918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1610664918
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1305664193
Short name T76
Test name
Test status
Simulation time 95134647429 ps
CPU time 50.04 seconds
Started Jul 23 06:51:56 PM PDT 24
Finished Jul 23 06:52:47 PM PDT 24
Peak memory 200204 kb
Host smart-7c981a52-4d9f-4376-a91f-325ad0fe8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305664193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1305664193
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2758198268
Short name T854
Test name
Test status
Simulation time 23396040698 ps
CPU time 46.69 seconds
Started Jul 23 06:58:47 PM PDT 24
Finished Jul 23 06:59:35 PM PDT 24
Peak memory 200168 kb
Host smart-d7a9685f-94e0-4c4d-8061-63cab529ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758198268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2758198268
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1713603624
Short name T1127
Test name
Test status
Simulation time 18331020722 ps
CPU time 28.63 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:59:19 PM PDT 24
Peak memory 199852 kb
Host smart-b645dd8a-2c9c-4c39-95ba-5699c79314f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713603624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1713603624
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4224190760
Short name T660
Test name
Test status
Simulation time 132582255906 ps
CPU time 22.47 seconds
Started Jul 23 06:58:54 PM PDT 24
Finished Jul 23 06:59:17 PM PDT 24
Peak memory 200244 kb
Host smart-2b7f08ca-883b-48c5-81fb-7029a2286f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224190760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4224190760
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1872906892
Short name T1158
Test name
Test status
Simulation time 4766802278 ps
CPU time 8.63 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:58:58 PM PDT 24
Peak memory 200112 kb
Host smart-106c0a58-120b-45fe-bae9-980ef071796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872906892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1872906892
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2055914365
Short name T153
Test name
Test status
Simulation time 30268842273 ps
CPU time 51.08 seconds
Started Jul 23 06:58:45 PM PDT 24
Finished Jul 23 06:59:37 PM PDT 24
Peak memory 200208 kb
Host smart-07712ad6-3091-41d6-beac-f49c95238328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055914365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2055914365
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4160104871
Short name T791
Test name
Test status
Simulation time 30723907688 ps
CPU time 13.16 seconds
Started Jul 23 06:58:46 PM PDT 24
Finished Jul 23 06:59:01 PM PDT 24
Peak memory 200168 kb
Host smart-9e8af275-4270-458a-b2e1-05f1cb22fd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160104871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4160104871
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2774154580
Short name T732
Test name
Test status
Simulation time 15325436002 ps
CPU time 24.63 seconds
Started Jul 23 06:58:48 PM PDT 24
Finished Jul 23 06:59:15 PM PDT 24
Peak memory 200200 kb
Host smart-3d405493-b097-4104-8887-21da5ddfee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774154580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2774154580
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3770167391
Short name T730
Test name
Test status
Simulation time 113629892185 ps
CPU time 188.52 seconds
Started Jul 23 06:59:00 PM PDT 24
Finished Jul 23 07:02:09 PM PDT 24
Peak memory 200256 kb
Host smart-e5efe0fa-3795-4d08-b739-31ee2c68082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770167391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3770167391
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.622711565
Short name T543
Test name
Test status
Simulation time 59370823726 ps
CPU time 102.19 seconds
Started Jul 23 06:59:00 PM PDT 24
Finished Jul 23 07:00:43 PM PDT 24
Peak memory 200228 kb
Host smart-9e83f10f-9c63-4a50-b10a-f99f7ad9686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622711565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.622711565
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3051073671
Short name T419
Test name
Test status
Simulation time 44828865 ps
CPU time 0.57 seconds
Started Jul 23 06:52:08 PM PDT 24
Finished Jul 23 06:52:10 PM PDT 24
Peak memory 195644 kb
Host smart-dfe7bd42-583c-4fb2-b183-47dca86f343c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051073671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3051073671
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2475885293
Short name T125
Test name
Test status
Simulation time 53192095953 ps
CPU time 77.57 seconds
Started Jul 23 06:52:01 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 200140 kb
Host smart-e5cff6f5-162b-42c0-af31-3ea15d40e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475885293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2475885293
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.97511720
Short name T836
Test name
Test status
Simulation time 179239923752 ps
CPU time 233.24 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:55:57 PM PDT 24
Peak memory 200168 kb
Host smart-72419d5a-c3b0-4984-8d14-0bda8fcc06fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97511720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.97511720
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2773947108
Short name T780
Test name
Test status
Simulation time 86758839926 ps
CPU time 138.87 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:54:21 PM PDT 24
Peak memory 200236 kb
Host smart-33b0ae4e-f625-4d54-b66d-321a43e66605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773947108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2773947108
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1413167526
Short name T421
Test name
Test status
Simulation time 469395575319 ps
CPU time 738.21 seconds
Started Jul 23 06:52:00 PM PDT 24
Finished Jul 23 07:04:19 PM PDT 24
Peak memory 199404 kb
Host smart-1d1c0501-81d0-4bc7-989a-d82a4d172779
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413167526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1413167526
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1783904481
Short name T942
Test name
Test status
Simulation time 292504678709 ps
CPU time 594.84 seconds
Started Jul 23 06:52:00 PM PDT 24
Finished Jul 23 07:01:56 PM PDT 24
Peak memory 200196 kb
Host smart-b516fb20-5397-42d4-9779-47e8818d1e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783904481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1783904481
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1810948483
Short name T1056
Test name
Test status
Simulation time 989156886 ps
CPU time 1.28 seconds
Started Jul 23 06:52:00 PM PDT 24
Finished Jul 23 06:52:02 PM PDT 24
Peak memory 196396 kb
Host smart-777be761-5e2c-4c0b-b5d1-31a64a3a33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810948483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1810948483
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3143450755
Short name T668
Test name
Test status
Simulation time 174618608317 ps
CPU time 80.73 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:53:24 PM PDT 24
Peak memory 208796 kb
Host smart-acc62454-d6f5-4b58-a302-f04c93632305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143450755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3143450755
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3870378638
Short name T650
Test name
Test status
Simulation time 14811584490 ps
CPU time 226.04 seconds
Started Jul 23 06:52:04 PM PDT 24
Finished Jul 23 06:55:50 PM PDT 24
Peak memory 200192 kb
Host smart-aee9fc7b-6bc2-4ac7-8c8d-9844fd5b26fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870378638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3870378638
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3618616092
Short name T1049
Test name
Test status
Simulation time 1376650377 ps
CPU time 2.53 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:52:06 PM PDT 24
Peak memory 197128 kb
Host smart-5b80fedb-18e1-4435-94cb-bcb357010be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618616092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3618616092
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.125771697
Short name T944
Test name
Test status
Simulation time 175721845538 ps
CPU time 20.81 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:52:24 PM PDT 24
Peak memory 200180 kb
Host smart-1672d347-46f1-4bb8-80ad-ae0d7d0227f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125771697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.125771697
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2736037724
Short name T958
Test name
Test status
Simulation time 1612520958 ps
CPU time 1.33 seconds
Started Jul 23 06:52:00 PM PDT 24
Finished Jul 23 06:52:02 PM PDT 24
Peak memory 195632 kb
Host smart-1a40de9d-850e-4a2d-9d2c-86ea4157e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736037724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2736037724
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.972777833
Short name T676
Test name
Test status
Simulation time 672300377 ps
CPU time 1.73 seconds
Started Jul 23 06:52:01 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 199956 kb
Host smart-8f2448e3-5e09-4d91-b21c-ff423e1104ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972777833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.972777833
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2868387694
Short name T834
Test name
Test status
Simulation time 216182722487 ps
CPU time 793.94 seconds
Started Jul 23 06:52:09 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 200012 kb
Host smart-5ea781d9-6b9b-46d6-8c77-cbc6f0331d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868387694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2868387694
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2894462486
Short name T995
Test name
Test status
Simulation time 146481001693 ps
CPU time 431.11 seconds
Started Jul 23 06:52:01 PM PDT 24
Finished Jul 23 06:59:13 PM PDT 24
Peak memory 226696 kb
Host smart-e66641a9-5af3-4cdd-8fa8-cae550850696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894462486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2894462486
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3679316072
Short name T409
Test name
Test status
Simulation time 575554111 ps
CPU time 1.84 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:52:04 PM PDT 24
Peak memory 199400 kb
Host smart-01481bcd-9eb9-4b58-ae49-8a386ac8f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679316072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3679316072
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3986093426
Short name T633
Test name
Test status
Simulation time 70692495366 ps
CPU time 32.23 seconds
Started Jul 23 06:52:02 PM PDT 24
Finished Jul 23 06:52:35 PM PDT 24
Peak memory 200208 kb
Host smart-54549ece-38e6-4717-b6f9-22af7aadcf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986093426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3986093426
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1349098899
Short name T1053
Test name
Test status
Simulation time 93174690674 ps
CPU time 34.86 seconds
Started Jul 23 06:59:01 PM PDT 24
Finished Jul 23 06:59:36 PM PDT 24
Peak memory 200268 kb
Host smart-6b91b435-6e26-4718-a431-ff4afb03e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349098899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1349098899
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3965327168
Short name T166
Test name
Test status
Simulation time 16050147856 ps
CPU time 21.25 seconds
Started Jul 23 06:59:00 PM PDT 24
Finished Jul 23 06:59:22 PM PDT 24
Peak memory 200244 kb
Host smart-4a2d5b11-55e1-4639-868c-edf8b03002c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965327168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3965327168
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2104834276
Short name T264
Test name
Test status
Simulation time 68099393685 ps
CPU time 32.66 seconds
Started Jul 23 06:59:00 PM PDT 24
Finished Jul 23 06:59:33 PM PDT 24
Peak memory 200196 kb
Host smart-68f42bd5-734a-4037-aa52-8f363c4ec8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104834276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2104834276
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.819621153
Short name T847
Test name
Test status
Simulation time 82889695374 ps
CPU time 157.63 seconds
Started Jul 23 06:59:03 PM PDT 24
Finished Jul 23 07:01:42 PM PDT 24
Peak memory 200156 kb
Host smart-de7cf62e-8d24-4a83-ada0-bc1007846213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819621153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.819621153
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4244034655
Short name T237
Test name
Test status
Simulation time 12249711132 ps
CPU time 11.42 seconds
Started Jul 23 06:58:59 PM PDT 24
Finished Jul 23 06:59:11 PM PDT 24
Peak memory 198564 kb
Host smart-7f43b947-b076-4e12-b3d9-8b5b0e738e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244034655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4244034655
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3406174200
Short name T714
Test name
Test status
Simulation time 117358554939 ps
CPU time 184.63 seconds
Started Jul 23 06:59:23 PM PDT 24
Finished Jul 23 07:02:29 PM PDT 24
Peak memory 200436 kb
Host smart-f88d6358-10de-4f4f-8913-d240a73f0a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406174200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3406174200
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1448376860
Short name T602
Test name
Test status
Simulation time 118721815964 ps
CPU time 182.37 seconds
Started Jul 23 06:59:23 PM PDT 24
Finished Jul 23 07:02:26 PM PDT 24
Peak memory 200208 kb
Host smart-4bbf6e9c-4f4a-492a-a170-655ecd458552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448376860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1448376860
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2865981541
Short name T592
Test name
Test status
Simulation time 95668604985 ps
CPU time 69.91 seconds
Started Jul 23 06:59:23 PM PDT 24
Finished Jul 23 07:00:33 PM PDT 24
Peak memory 200180 kb
Host smart-49cc58cc-ea97-4f54-b194-9a637aad75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865981541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2865981541
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.4031535917
Short name T236
Test name
Test status
Simulation time 17660265943 ps
CPU time 40.21 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 07:00:06 PM PDT 24
Peak memory 200196 kb
Host smart-508c63c3-bb69-4985-9a2f-569402724cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031535917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4031535917
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2366034903
Short name T979
Test name
Test status
Simulation time 13386237 ps
CPU time 0.55 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:09 PM PDT 24
Peak memory 195884 kb
Host smart-d43dfe94-c3c9-40a7-be5a-5391cc724387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366034903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2366034903
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1604237178
Short name T665
Test name
Test status
Simulation time 152459879624 ps
CPU time 326.11 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:57:35 PM PDT 24
Peak memory 200152 kb
Host smart-608428ee-ce00-47dc-a6ef-5fc4ebbdb56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604237178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1604237178
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.266324319
Short name T1172
Test name
Test status
Simulation time 160788345324 ps
CPU time 62.24 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:53:10 PM PDT 24
Peak memory 200168 kb
Host smart-14c58157-b301-4dbf-b843-2c27bccc66f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266324319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.266324319
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.194505389
Short name T191
Test name
Test status
Simulation time 48474997200 ps
CPU time 36.32 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:45 PM PDT 24
Peak memory 200256 kb
Host smart-239d268d-3f49-44cc-91e8-94313df8c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194505389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.194505389
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.943438023
Short name T1004
Test name
Test status
Simulation time 13045030892 ps
CPU time 7.35 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:16 PM PDT 24
Peak memory 197744 kb
Host smart-af3a8415-bc9b-4c58-8577-eb6f2b1d56cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943438023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.943438023
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.933888195
Short name T502
Test name
Test status
Simulation time 132007557647 ps
CPU time 257.01 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:56:25 PM PDT 24
Peak memory 200236 kb
Host smart-b8ab9544-106e-4815-94cf-e9f1196c75a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933888195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.933888195
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.86046810
Short name T953
Test name
Test status
Simulation time 2044340468 ps
CPU time 2.04 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:11 PM PDT 24
Peak memory 198796 kb
Host smart-61156c9a-1954-429c-97f7-12b3474b4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86046810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.86046810
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3475638451
Short name T814
Test name
Test status
Simulation time 131474601143 ps
CPU time 63.28 seconds
Started Jul 23 06:52:12 PM PDT 24
Finished Jul 23 06:53:16 PM PDT 24
Peak memory 200248 kb
Host smart-c95184f3-1161-4bbd-9091-023d865562be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475638451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3475638451
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3677731952
Short name T827
Test name
Test status
Simulation time 24572765359 ps
CPU time 246.51 seconds
Started Jul 23 06:52:09 PM PDT 24
Finished Jul 23 06:56:16 PM PDT 24
Peak memory 200164 kb
Host smart-a3cc9e21-8931-4683-8a0c-fa21fd138882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677731952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3677731952
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1207579606
Short name T390
Test name
Test status
Simulation time 3441153655 ps
CPU time 12.35 seconds
Started Jul 23 06:52:08 PM PDT 24
Finished Jul 23 06:52:22 PM PDT 24
Peak memory 199276 kb
Host smart-e1590139-0c62-44d3-a71b-918d862ed4bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207579606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1207579606
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1928651734
Short name T183
Test name
Test status
Simulation time 114433959369 ps
CPU time 153.91 seconds
Started Jul 23 06:52:12 PM PDT 24
Finished Jul 23 06:54:47 PM PDT 24
Peak memory 200048 kb
Host smart-6f9ce8e1-c846-439b-a960-dd28a89e0b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928651734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1928651734
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3475170575
Short name T341
Test name
Test status
Simulation time 6387317067 ps
CPU time 1.59 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:52:08 PM PDT 24
Peak memory 196728 kb
Host smart-a064e445-7a18-4aa7-9e9b-b89b8c2c241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475170575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3475170575
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.145798401
Short name T920
Test name
Test status
Simulation time 501397440 ps
CPU time 1.93 seconds
Started Jul 23 06:52:12 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 199652 kb
Host smart-b07597f7-e686-4f9e-a170-d6edeb2f70dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145798401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.145798401
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1835508472
Short name T145
Test name
Test status
Simulation time 500609335723 ps
CPU time 641.99 seconds
Started Jul 23 06:52:08 PM PDT 24
Finished Jul 23 07:02:51 PM PDT 24
Peak memory 200204 kb
Host smart-7e06789e-8728-45b6-8f07-f4e31c1d9796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835508472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1835508472
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.191982234
Short name T848
Test name
Test status
Simulation time 32640039819 ps
CPU time 709.75 seconds
Started Jul 23 06:52:09 PM PDT 24
Finished Jul 23 07:04:00 PM PDT 24
Peak memory 216604 kb
Host smart-6e8c9fa9-ec39-43a6-8dc4-2c783afd7571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191982234 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.191982234
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.637743385
Short name T1106
Test name
Test status
Simulation time 8462624518 ps
CPU time 10.91 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:52:19 PM PDT 24
Peak memory 199956 kb
Host smart-3c8e5f98-7c99-483b-b494-f2e9a251e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637743385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.637743385
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1936467908
Short name T862
Test name
Test status
Simulation time 33001542545 ps
CPU time 37.33 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:52:44 PM PDT 24
Peak memory 200188 kb
Host smart-8cabc542-2c51-49b8-8ada-6ae03dce230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936467908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1936467908
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4282609648
Short name T428
Test name
Test status
Simulation time 24508692459 ps
CPU time 38.84 seconds
Started Jul 23 06:59:30 PM PDT 24
Finished Jul 23 07:00:11 PM PDT 24
Peak memory 199960 kb
Host smart-60d5ff6f-74f2-4e1b-8fe3-822ae6f01272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282609648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4282609648
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3798541850
Short name T1037
Test name
Test status
Simulation time 48773927584 ps
CPU time 67.59 seconds
Started Jul 23 06:59:26 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 200164 kb
Host smart-f526789f-8142-4ab0-b5f6-a39a410ffb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798541850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3798541850
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1507329431
Short name T1155
Test name
Test status
Simulation time 176472313370 ps
CPU time 309.82 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:04:40 PM PDT 24
Peak memory 200144 kb
Host smart-7931fb98-ad13-4635-b83b-94794e21932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507329431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1507329431
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2410278938
Short name T895
Test name
Test status
Simulation time 129070038426 ps
CPU time 59.18 seconds
Started Jul 23 06:59:23 PM PDT 24
Finished Jul 23 07:00:24 PM PDT 24
Peak memory 200228 kb
Host smart-9ac91140-b2fe-489e-8ba4-7f8f26305818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410278938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2410278938
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2891947742
Short name T1031
Test name
Test status
Simulation time 14696906288 ps
CPU time 6.57 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 06:59:37 PM PDT 24
Peak memory 200156 kb
Host smart-6cc7282f-0341-4120-9d6c-730ddef94266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891947742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2891947742
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3969316501
Short name T589
Test name
Test status
Simulation time 58438118429 ps
CPU time 32.37 seconds
Started Jul 23 06:59:26 PM PDT 24
Finished Jul 23 07:00:01 PM PDT 24
Peak memory 200260 kb
Host smart-8ef10a16-37bc-4ed6-b739-91e3cffe66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969316501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3969316501
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1214109840
Short name T840
Test name
Test status
Simulation time 37317189630 ps
CPU time 16.83 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 06:59:42 PM PDT 24
Peak memory 200248 kb
Host smart-1467dd4d-b8bb-4937-a021-58d8e35e8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214109840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1214109840
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3885470388
Short name T269
Test name
Test status
Simulation time 163322979436 ps
CPU time 30.21 seconds
Started Jul 23 06:59:25 PM PDT 24
Finished Jul 23 06:59:57 PM PDT 24
Peak memory 200164 kb
Host smart-13a09fbd-e54e-4e2f-8e92-c020d1d09f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885470388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3885470388
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1729493663
Short name T1014
Test name
Test status
Simulation time 43420342177 ps
CPU time 79.04 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:00:49 PM PDT 24
Peak memory 200224 kb
Host smart-4fd30290-5ce8-4525-a820-24161463e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729493663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1729493663
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4107634564
Short name T128
Test name
Test status
Simulation time 39425075 ps
CPU time 0.55 seconds
Started Jul 23 06:52:15 PM PDT 24
Finished Jul 23 06:52:18 PM PDT 24
Peak memory 195616 kb
Host smart-9038d7f8-b4ee-4d73-a010-9206d3a2b5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107634564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4107634564
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2720134773
Short name T588
Test name
Test status
Simulation time 102359619605 ps
CPU time 160.87 seconds
Started Jul 23 06:52:06 PM PDT 24
Finished Jul 23 06:54:48 PM PDT 24
Peak memory 200232 kb
Host smart-f9ce4f5f-01bb-4cab-b8b2-e884955d4eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720134773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2720134773
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1081736279
Short name T778
Test name
Test status
Simulation time 63188664020 ps
CPU time 26.29 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 200256 kb
Host smart-dda8800e-ffa2-496b-ba65-2f7e895c8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081736279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1081736279
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3675047464
Short name T1117
Test name
Test status
Simulation time 92371272957 ps
CPU time 35.32 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:51 PM PDT 24
Peak memory 200252 kb
Host smart-7411c8d0-8731-4221-8887-73c3cd05dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675047464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3675047464
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1887176670
Short name T1066
Test name
Test status
Simulation time 47340057923 ps
CPU time 20.1 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 200092 kb
Host smart-23f86d25-4752-4a67-9fc7-fe0be0c35bf3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887176670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1887176670
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1951411653
Short name T781
Test name
Test status
Simulation time 53452743833 ps
CPU time 386.92 seconds
Started Jul 23 06:52:15 PM PDT 24
Finished Jul 23 06:58:45 PM PDT 24
Peak memory 200180 kb
Host smart-90061f57-c36c-491e-9b29-8ee64d2f73e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951411653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1951411653
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2598862132
Short name T133
Test name
Test status
Simulation time 1380631119 ps
CPU time 0.93 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 196352 kb
Host smart-70393698-be7d-42de-ba10-fb241f3e5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598862132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2598862132
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.23312731
Short name T782
Test name
Test status
Simulation time 8978336303 ps
CPU time 13.53 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:52:30 PM PDT 24
Peak memory 200156 kb
Host smart-6984e97a-c595-4e15-acbf-0b67a5b47c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23312731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.23312731
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2482006329
Short name T505
Test name
Test status
Simulation time 12429830356 ps
CPU time 342.21 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:57:59 PM PDT 24
Peak memory 200176 kb
Host smart-d7da66c6-76e6-4719-889a-20e81009029b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482006329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2482006329
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3183756884
Short name T540
Test name
Test status
Simulation time 1874132063 ps
CPU time 9 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:24 PM PDT 24
Peak memory 199136 kb
Host smart-55d1496c-a72e-445a-a64a-8da985bccc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183756884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3183756884
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.163824390
Short name T982
Test name
Test status
Simulation time 46205388375 ps
CPU time 15.61 seconds
Started Jul 23 06:52:11 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 200196 kb
Host smart-b9f818f9-032b-491a-ad57-9b836ac6435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163824390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.163824390
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1916573047
Short name T735
Test name
Test status
Simulation time 3208802645 ps
CPU time 1.61 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:18 PM PDT 24
Peak memory 195992 kb
Host smart-b36fbc23-7ce0-4595-a101-001df8a17cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916573047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1916573047
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1376831138
Short name T1149
Test name
Test status
Simulation time 5450346580 ps
CPU time 19.37 seconds
Started Jul 23 06:52:12 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 199280 kb
Host smart-964fbba7-6ce9-45bf-ba64-0f3c53d839ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376831138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1376831138
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.942335477
Short name T929
Test name
Test status
Simulation time 45411401044 ps
CPU time 388.71 seconds
Started Jul 23 06:52:17 PM PDT 24
Finished Jul 23 06:58:48 PM PDT 24
Peak memory 216828 kb
Host smart-1ddfcb52-9280-435e-80cf-41f6e2ea3de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942335477 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.942335477
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2400422647
Short name T1176
Test name
Test status
Simulation time 822758145 ps
CPU time 3.06 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:52:20 PM PDT 24
Peak memory 198716 kb
Host smart-107429e5-b980-4e60-9b1e-d9ad96b0039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400422647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2400422647
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.4276220578
Short name T541
Test name
Test status
Simulation time 87871992891 ps
CPU time 18.21 seconds
Started Jul 23 06:52:07 PM PDT 24
Finished Jul 23 06:52:26 PM PDT 24
Peak memory 200012 kb
Host smart-00ced40f-cd02-4161-a7b1-922a1a5839c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276220578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4276220578
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2092059860
Short name T1060
Test name
Test status
Simulation time 15337741991 ps
CPU time 7.85 seconds
Started Jul 23 06:59:25 PM PDT 24
Finished Jul 23 06:59:35 PM PDT 24
Peak memory 199956 kb
Host smart-a0214058-283d-4b09-b4a4-353b6044eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092059860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2092059860
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1061081349
Short name T940
Test name
Test status
Simulation time 167984693738 ps
CPU time 66.95 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 07:00:32 PM PDT 24
Peak memory 200224 kb
Host smart-02901e01-63d8-4175-9826-de921c7b6ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061081349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1061081349
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.775257498
Short name T169
Test name
Test status
Simulation time 62787123003 ps
CPU time 24.29 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 06:59:54 PM PDT 24
Peak memory 200156 kb
Host smart-25403b25-459e-4875-8596-ec2424c5e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775257498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.775257498
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2324609488
Short name T238
Test name
Test status
Simulation time 57641199263 ps
CPU time 29.02 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 06:59:59 PM PDT 24
Peak memory 200132 kb
Host smart-43782af2-788c-4680-9d03-a98f33eee8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324609488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2324609488
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.751598266
Short name T1169
Test name
Test status
Simulation time 94465074967 ps
CPU time 40.04 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:00:10 PM PDT 24
Peak memory 200156 kb
Host smart-52b521b6-747c-45e9-be27-bcc6fcdeb8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751598266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.751598266
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2430977378
Short name T916
Test name
Test status
Simulation time 15691580213 ps
CPU time 25.71 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 06:59:52 PM PDT 24
Peak memory 200212 kb
Host smart-808e0ed6-59fc-47e0-8280-00aa115591ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430977378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2430977378
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.714616620
Short name T366
Test name
Test status
Simulation time 16932423000 ps
CPU time 23.74 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 06:59:49 PM PDT 24
Peak memory 200276 kb
Host smart-5cdc9d4b-295e-4cf7-a48e-2a803989b42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714616620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.714616620
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2367683014
Short name T167
Test name
Test status
Simulation time 156165515593 ps
CPU time 76.36 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:00:46 PM PDT 24
Peak memory 200224 kb
Host smart-c6e35bd4-816f-4be9-a22e-88ba3c2f5906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367683014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2367683014
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4218453099
Short name T863
Test name
Test status
Simulation time 25398531270 ps
CPU time 44.83 seconds
Started Jul 23 06:59:25 PM PDT 24
Finished Jul 23 07:00:12 PM PDT 24
Peak memory 200192 kb
Host smart-667e2523-1baf-45fc-9016-0e0d72d5b3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218453099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4218453099
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2866083201
Short name T915
Test name
Test status
Simulation time 24872671 ps
CPU time 0.63 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:52:18 PM PDT 24
Peak memory 195644 kb
Host smart-5cc35640-3ab0-4b21-98c5-29e8802faaac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866083201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2866083201
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.310741926
Short name T903
Test name
Test status
Simulation time 39017502905 ps
CPU time 67.74 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:53:25 PM PDT 24
Peak memory 200192 kb
Host smart-49669428-4784-4d5e-a7d0-eaca10c39b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310741926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.310741926
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2824673058
Short name T789
Test name
Test status
Simulation time 29600758181 ps
CPU time 47.03 seconds
Started Jul 23 06:52:11 PM PDT 24
Finished Jul 23 06:53:00 PM PDT 24
Peak memory 200152 kb
Host smart-83c13f68-5f51-4169-bc4e-77721d829b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824673058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2824673058
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3891122186
Short name T1179
Test name
Test status
Simulation time 185460803082 ps
CPU time 60.49 seconds
Started Jul 23 06:52:17 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 200232 kb
Host smart-ff3f7453-c870-4770-8ac0-895ef3403b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891122186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3891122186
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3541708033
Short name T853
Test name
Test status
Simulation time 40388120470 ps
CPU time 18.02 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:52:35 PM PDT 24
Peak memory 200232 kb
Host smart-d4da8603-5cc5-4331-9833-97f185bf27c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541708033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3541708033
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_loopback.291857615
Short name T385
Test name
Test status
Simulation time 8701933833 ps
CPU time 16.41 seconds
Started Jul 23 06:52:15 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 199916 kb
Host smart-a962b644-a1b8-4460-9bae-ec5a83189296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291857615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.291857615
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.210297825
Short name T371
Test name
Test status
Simulation time 60003683893 ps
CPU time 26.88 seconds
Started Jul 23 06:52:12 PM PDT 24
Finished Jul 23 06:52:40 PM PDT 24
Peak memory 200008 kb
Host smart-42f765b7-3257-4c3c-b154-7ffb471d7387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210297825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.210297825
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3996756436
Short name T451
Test name
Test status
Simulation time 18074315354 ps
CPU time 169.09 seconds
Started Jul 23 06:52:16 PM PDT 24
Finished Jul 23 06:55:07 PM PDT 24
Peak memory 200236 kb
Host smart-8a0ab59a-605d-4832-b2b2-9da093de0d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996756436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3996756436
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.541175807
Short name T4
Test name
Test status
Simulation time 6177030348 ps
CPU time 48.16 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:53:05 PM PDT 24
Peak memory 198268 kb
Host smart-26c2b03b-b89d-463f-a299-6ed874167486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541175807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.541175807
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2825180784
Short name T499
Test name
Test status
Simulation time 47441908151 ps
CPU time 66.44 seconds
Started Jul 23 06:52:15 PM PDT 24
Finished Jul 23 06:53:24 PM PDT 24
Peak memory 200200 kb
Host smart-dc669e81-4ccc-413c-96bf-11d3b834c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825180784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2825180784
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1544339325
Short name T1005
Test name
Test status
Simulation time 5216904286 ps
CPU time 2.8 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:52:20 PM PDT 24
Peak memory 196384 kb
Host smart-face82fc-8a54-40b7-b214-ab6009922b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544339325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1544339325
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3467821929
Short name T434
Test name
Test status
Simulation time 702337641 ps
CPU time 1.91 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:17 PM PDT 24
Peak memory 198832 kb
Host smart-a422dee0-e677-40d6-8e7d-db3f47cf73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467821929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3467821929
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1915475520
Short name T85
Test name
Test status
Simulation time 180939334784 ps
CPU time 443.19 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:59:40 PM PDT 24
Peak memory 200064 kb
Host smart-097d86bd-7384-4a55-8814-38b4f521bb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915475520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1915475520
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4184347445
Short name T485
Test name
Test status
Simulation time 41396545770 ps
CPU time 188.1 seconds
Started Jul 23 06:52:14 PM PDT 24
Finished Jul 23 06:55:25 PM PDT 24
Peak memory 216076 kb
Host smart-52b614bb-d802-4c0b-9bc8-304cd0be9ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184347445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4184347445
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1253851557
Short name T876
Test name
Test status
Simulation time 1480144315 ps
CPU time 4.04 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:52:19 PM PDT 24
Peak memory 200056 kb
Host smart-89883d5d-dc87-4a5c-9c9c-ee93f9129674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253851557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1253851557
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1094777039
Short name T819
Test name
Test status
Simulation time 87685430663 ps
CPU time 157.52 seconds
Started Jul 23 06:52:13 PM PDT 24
Finished Jul 23 06:54:53 PM PDT 24
Peak memory 200204 kb
Host smart-b3d1346c-17c8-4082-a0e0-275c5107e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094777039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1094777039
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.191441035
Short name T460
Test name
Test status
Simulation time 66160473327 ps
CPU time 29.07 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 06:59:59 PM PDT 24
Peak memory 200280 kb
Host smart-7a06d554-14c9-4445-8bc0-4f0dbf91c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191441035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.191441035
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3281849585
Short name T1151
Test name
Test status
Simulation time 13256720628 ps
CPU time 24.49 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 06:59:50 PM PDT 24
Peak memory 200196 kb
Host smart-2d6c0853-3942-4277-bb91-f6df9be4aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281849585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3281849585
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2331238138
Short name T906
Test name
Test status
Simulation time 68602623321 ps
CPU time 110.35 seconds
Started Jul 23 06:59:33 PM PDT 24
Finished Jul 23 07:01:24 PM PDT 24
Peak memory 200192 kb
Host smart-21e46c2e-3996-4552-b504-c99b4ce0dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331238138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2331238138
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.441219825
Short name T8
Test name
Test status
Simulation time 44625862784 ps
CPU time 16.26 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 06:59:46 PM PDT 24
Peak memory 200176 kb
Host smart-c1711419-a1bf-4267-97cd-abfe8bdbc58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441219825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.441219825
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.147879571
Short name T217
Test name
Test status
Simulation time 22559436431 ps
CPU time 33.42 seconds
Started Jul 23 06:59:26 PM PDT 24
Finished Jul 23 07:00:01 PM PDT 24
Peak memory 199892 kb
Host smart-002840a3-29d5-483d-9653-3f9957cb79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147879571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.147879571
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.809525798
Short name T590
Test name
Test status
Simulation time 65907242240 ps
CPU time 111.78 seconds
Started Jul 23 06:59:23 PM PDT 24
Finished Jul 23 07:01:16 PM PDT 24
Peak memory 200104 kb
Host smart-5702a692-bc94-4f57-89fa-d32f9ddf5f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809525798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.809525798
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2445993983
Short name T247
Test name
Test status
Simulation time 188039266804 ps
CPU time 59.64 seconds
Started Jul 23 06:59:24 PM PDT 24
Finished Jul 23 07:00:25 PM PDT 24
Peak memory 200212 kb
Host smart-c81c2b94-a285-40df-8cb2-03c48cdeeca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445993983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2445993983
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.475717491
Short name T465
Test name
Test status
Simulation time 63981676043 ps
CPU time 26.04 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 06:59:56 PM PDT 24
Peak memory 200124 kb
Host smart-9734956b-153b-4b21-a816-0a662e145a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475717491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.475717491
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.298627334
Short name T722
Test name
Test status
Simulation time 34418124 ps
CPU time 0.55 seconds
Started Jul 23 06:52:21 PM PDT 24
Finished Jul 23 06:52:24 PM PDT 24
Peak memory 195616 kb
Host smart-cabcff34-24b4-4292-8e55-c7e91992078c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298627334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.298627334
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.386200233
Short name T174
Test name
Test status
Simulation time 168492276929 ps
CPU time 81.17 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:53:43 PM PDT 24
Peak memory 200164 kb
Host smart-b458fd09-97b3-4b65-89fa-0213c2271c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386200233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.386200233
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3901570167
Short name T949
Test name
Test status
Simulation time 22604983298 ps
CPU time 31.7 seconds
Started Jul 23 06:52:24 PM PDT 24
Finished Jul 23 06:52:57 PM PDT 24
Peak memory 200076 kb
Host smart-b71da440-42d1-4be0-95ae-8eb214e079c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901570167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3901570167
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.37681551
Short name T1017
Test name
Test status
Simulation time 130975334584 ps
CPU time 51.44 seconds
Started Jul 23 06:52:22 PM PDT 24
Finished Jul 23 06:53:15 PM PDT 24
Peak memory 200140 kb
Host smart-a717cf2a-5684-4cfe-a4e1-68cd99fff0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37681551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.37681551
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1477241994
Short name T728
Test name
Test status
Simulation time 50068682402 ps
CPU time 38.98 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:53:04 PM PDT 24
Peak memory 200140 kb
Host smart-616fa5a2-a776-42c6-beae-d3bb6b3748b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477241994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1477241994
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.671989576
Short name T856
Test name
Test status
Simulation time 96117982619 ps
CPU time 162.28 seconds
Started Jul 23 06:52:18 PM PDT 24
Finished Jul 23 06:55:03 PM PDT 24
Peak memory 200244 kb
Host smart-626f63df-11a6-4c24-bbb8-3183a147a16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671989576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.671989576
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2122941563
Short name T902
Test name
Test status
Simulation time 5927604450 ps
CPU time 11.66 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 199732 kb
Host smart-a700fe93-7440-4c9b-b9c9-80fb8eb86c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122941563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2122941563
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2528222004
Short name T501
Test name
Test status
Simulation time 20634723380 ps
CPU time 31.39 seconds
Started Jul 23 06:52:21 PM PDT 24
Finished Jul 23 06:52:55 PM PDT 24
Peak memory 199016 kb
Host smart-12c0fbeb-e37d-4ff4-9b8f-8dde4b4c1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528222004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2528222004
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1547591471
Short name T643
Test name
Test status
Simulation time 6721797614 ps
CPU time 174.51 seconds
Started Jul 23 06:52:21 PM PDT 24
Finished Jul 23 06:55:18 PM PDT 24
Peak memory 200208 kb
Host smart-b817c99c-5be1-46fe-8295-35896c6e1966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547591471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1547591471
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.499664620
Short name T395
Test name
Test status
Simulation time 5779085679 ps
CPU time 50.39 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:53:13 PM PDT 24
Peak memory 198360 kb
Host smart-124f4ba7-9d30-4a9a-a76b-258510c507e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499664620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.499664620
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1327457730
Short name T661
Test name
Test status
Simulation time 33665759028 ps
CPU time 79.06 seconds
Started Jul 23 06:52:18 PM PDT 24
Finished Jul 23 06:53:39 PM PDT 24
Peak memory 200148 kb
Host smart-05111792-bd30-49ca-8bfa-912694d30b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327457730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1327457730
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1473043507
Short name T970
Test name
Test status
Simulation time 75836154901 ps
CPU time 16.4 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:52:38 PM PDT 24
Peak memory 196068 kb
Host smart-0d259149-ad54-4d0b-b091-87472b4927e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473043507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1473043507
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2211363467
Short name T544
Test name
Test status
Simulation time 5897976115 ps
CPU time 7.44 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:52:29 PM PDT 24
Peak memory 200136 kb
Host smart-9e0daa83-c5d9-4cff-8f2d-a974a4dd1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211363467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2211363467
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.554163
Short name T1039
Test name
Test status
Simulation time 249728391576 ps
CPU time 1151.34 seconds
Started Jul 23 06:52:18 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 200208 kb
Host smart-fa22a6e9-1b06-4038-a2a8-b1384c0d6df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.554163
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2242725866
Short name T359
Test name
Test status
Simulation time 33067657049 ps
CPU time 301.19 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:57:23 PM PDT 24
Peak memory 215988 kb
Host smart-f89f3f63-c07b-4220-b3e3-6c0293c8b11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242725866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2242725866
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1690406708
Short name T904
Test name
Test status
Simulation time 9250925852 ps
CPU time 2.2 seconds
Started Jul 23 06:52:21 PM PDT 24
Finished Jul 23 06:52:25 PM PDT 24
Peak memory 199436 kb
Host smart-b201f8b6-b640-4363-b1d6-aeee6083cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690406708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1690406708
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2013123303
Short name T533
Test name
Test status
Simulation time 97332513422 ps
CPU time 28.11 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:52:50 PM PDT 24
Peak memory 200260 kb
Host smart-5043c39e-85da-4460-8dae-8c2e36712e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013123303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2013123303
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3255141909
Short name T486
Test name
Test status
Simulation time 38734116394 ps
CPU time 59.42 seconds
Started Jul 23 06:59:26 PM PDT 24
Finished Jul 23 07:00:27 PM PDT 24
Peak memory 200236 kb
Host smart-5be3278e-cbfc-4117-86f3-c13200a5d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255141909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3255141909
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2953247459
Short name T198
Test name
Test status
Simulation time 85312323143 ps
CPU time 127.47 seconds
Started Jul 23 06:59:30 PM PDT 24
Finished Jul 23 07:01:39 PM PDT 24
Peak memory 200260 kb
Host smart-cfef075d-2aee-4ed4-87c3-46bdf6830b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953247459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2953247459
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3603359803
Short name T407
Test name
Test status
Simulation time 81335276855 ps
CPU time 28.6 seconds
Started Jul 23 06:59:34 PM PDT 24
Finished Jul 23 07:00:04 PM PDT 24
Peak memory 199976 kb
Host smart-8190eb83-b3b7-48fe-81fe-2eb796390edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603359803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3603359803
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.710929336
Short name T989
Test name
Test status
Simulation time 253066973918 ps
CPU time 571.25 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 200260 kb
Host smart-a9affe2c-8280-4977-881c-bcc17299e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710929336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.710929336
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2032261687
Short name T159
Test name
Test status
Simulation time 16430239379 ps
CPU time 30.58 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:00:00 PM PDT 24
Peak memory 200252 kb
Host smart-43bac819-54c9-428e-b246-e065712ccf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032261687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2032261687
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1849891745
Short name T224
Test name
Test status
Simulation time 76987540068 ps
CPU time 94.4 seconds
Started Jul 23 06:59:29 PM PDT 24
Finished Jul 23 07:01:06 PM PDT 24
Peak memory 200260 kb
Host smart-e8857448-efaa-4c62-bc2f-0c01d28e4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849891745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1849891745
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.408556236
Short name T684
Test name
Test status
Simulation time 100120743759 ps
CPU time 129.46 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:01:40 PM PDT 24
Peak memory 200268 kb
Host smart-f9252450-d15b-4fec-a1a2-5c1581229822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408556236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.408556236
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1741371530
Short name T1116
Test name
Test status
Simulation time 58898969542 ps
CPU time 37.9 seconds
Started Jul 23 06:59:29 PM PDT 24
Finished Jul 23 07:00:09 PM PDT 24
Peak memory 199132 kb
Host smart-4bf86ac1-cd89-4519-95b8-ac934b5abda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741371530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1741371530
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2791198577
Short name T233
Test name
Test status
Simulation time 132015935211 ps
CPU time 214.18 seconds
Started Jul 23 06:59:27 PM PDT 24
Finished Jul 23 07:03:03 PM PDT 24
Peak memory 200256 kb
Host smart-9ef41f57-3df0-45c0-ae3d-7a56f5b76f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791198577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2791198577
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3031100247
Short name T441
Test name
Test status
Simulation time 16386647 ps
CPU time 0.57 seconds
Started Jul 23 06:52:26 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 195644 kb
Host smart-263d5c8e-5fe4-4b3e-bbbc-f42dfe932a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031100247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3031100247
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.49420307
Short name T1145
Test name
Test status
Simulation time 30608379202 ps
CPU time 47.26 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:53:09 PM PDT 24
Peak memory 199496 kb
Host smart-ca3c5075-35de-4af3-8b62-3ea74bf6c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49420307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.49420307
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.196958667
Short name T948
Test name
Test status
Simulation time 24455993547 ps
CPU time 22.83 seconds
Started Jul 23 06:52:17 PM PDT 24
Finished Jul 23 06:52:43 PM PDT 24
Peak memory 200156 kb
Host smart-1887e628-4216-47a1-874b-e677f2e9ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196958667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.196958667
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4281087090
Short name T477
Test name
Test status
Simulation time 53409702650 ps
CPU time 39.56 seconds
Started Jul 23 06:52:24 PM PDT 24
Finished Jul 23 06:53:05 PM PDT 24
Peak memory 199248 kb
Host smart-e3de3ec1-3712-409c-9648-94b9cc1e09c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281087090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4281087090
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2460222482
Short name T888
Test name
Test status
Simulation time 127694012869 ps
CPU time 989.83 seconds
Started Jul 23 06:52:25 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 200120 kb
Host smart-0b5e69c1-83da-4fc4-a552-1c9660e633cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460222482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2460222482
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.216002949
Short name T657
Test name
Test status
Simulation time 4698491973 ps
CPU time 3.76 seconds
Started Jul 23 06:52:22 PM PDT 24
Finished Jul 23 06:52:28 PM PDT 24
Peak memory 200252 kb
Host smart-74350d43-a295-4659-84c1-caa8ab991358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216002949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.216002949
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2506298739
Short name T1012
Test name
Test status
Simulation time 116800409001 ps
CPU time 56.44 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:53:19 PM PDT 24
Peak memory 200076 kb
Host smart-193f34d3-9abe-4f48-9fd8-2399b924aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506298739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2506298739
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.659641625
Short name T361
Test name
Test status
Simulation time 8371645984 ps
CPU time 496.67 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 07:00:42 PM PDT 24
Peak memory 200164 kb
Host smart-57c07b30-43f4-43c0-8c47-f5bf54a893ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659641625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.659641625
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3716369483
Short name T757
Test name
Test status
Simulation time 4659841439 ps
CPU time 40.02 seconds
Started Jul 23 06:52:22 PM PDT 24
Finished Jul 23 06:53:04 PM PDT 24
Peak memory 199300 kb
Host smart-79ed64d3-2ec7-4ce5-b175-fdf09e07f5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716369483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3716369483
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2071872222
Short name T839
Test name
Test status
Simulation time 27582047123 ps
CPU time 13.38 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:52:38 PM PDT 24
Peak memory 200436 kb
Host smart-9f4d0d67-6228-41df-b45e-cb77ac964f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071872222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2071872222
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2824284490
Short name T83
Test name
Test status
Simulation time 29036709660 ps
CPU time 47.39 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:53:10 PM PDT 24
Peak memory 196352 kb
Host smart-420bcf08-d9df-43db-b764-1d76929134aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824284490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2824284490
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1643075678
Short name T1034
Test name
Test status
Simulation time 803410525 ps
CPU time 3.65 seconds
Started Jul 23 06:52:20 PM PDT 24
Finished Jul 23 06:52:26 PM PDT 24
Peak memory 199500 kb
Host smart-60b8f25e-f885-4e8a-bbc1-6d52ae03d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643075678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1643075678
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3710243736
Short name T204
Test name
Test status
Simulation time 233068358371 ps
CPU time 108.72 seconds
Started Jul 23 06:52:24 PM PDT 24
Finished Jul 23 06:54:14 PM PDT 24
Peak memory 200132 kb
Host smart-ca0cb015-8393-410b-a076-13920866c203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710243736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3710243736
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.348032412
Short name T844
Test name
Test status
Simulation time 249130186174 ps
CPU time 797 seconds
Started Jul 23 06:52:24 PM PDT 24
Finished Jul 23 07:05:43 PM PDT 24
Peak memory 224992 kb
Host smart-e3ba4030-02e5-488b-9bfd-000d033f035f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348032412 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.348032412
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.54234226
Short name T637
Test name
Test status
Simulation time 799449419 ps
CPU time 2.3 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 198696 kb
Host smart-3624927c-7fd4-4beb-a21d-a5f61b9005b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54234226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.54234226
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.149464435
Short name T959
Test name
Test status
Simulation time 174303817541 ps
CPU time 338.25 seconds
Started Jul 23 06:52:19 PM PDT 24
Finished Jul 23 06:58:00 PM PDT 24
Peak memory 200212 kb
Host smart-487d4ff0-bcc4-4476-85c3-0eca31657dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149464435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.149464435
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4255458996
Short name T659
Test name
Test status
Simulation time 9253194569 ps
CPU time 14.73 seconds
Started Jul 23 06:59:29 PM PDT 24
Finished Jul 23 06:59:46 PM PDT 24
Peak memory 199688 kb
Host smart-5d098dac-5fd2-4314-b52c-0b3c6ee3a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255458996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4255458996
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3445137737
Short name T670
Test name
Test status
Simulation time 9831450308 ps
CPU time 15.65 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 06:59:46 PM PDT 24
Peak memory 199884 kb
Host smart-6db53110-6cbd-4fa2-ab8c-5a8ffda4a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445137737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3445137737
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.540052489
Short name T242
Test name
Test status
Simulation time 133689574154 ps
CPU time 66.69 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:00:37 PM PDT 24
Peak memory 200148 kb
Host smart-51c22415-2011-4b2a-875b-8626ae8c30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540052489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.540052489
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4136580614
Short name T163
Test name
Test status
Simulation time 40308286569 ps
CPU time 7.62 seconds
Started Jul 23 06:59:33 PM PDT 24
Finished Jul 23 06:59:42 PM PDT 24
Peak memory 200192 kb
Host smart-0970b055-bf71-4455-bf94-0355a9ee5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136580614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4136580614
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.897835822
Short name T765
Test name
Test status
Simulation time 206933718703 ps
CPU time 23.38 seconds
Started Jul 23 06:59:26 PM PDT 24
Finished Jul 23 06:59:51 PM PDT 24
Peak memory 200232 kb
Host smart-bb125000-9081-4960-8294-eaf203efee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897835822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.897835822
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1969807979
Short name T557
Test name
Test status
Simulation time 26666195907 ps
CPU time 53.25 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:00:24 PM PDT 24
Peak memory 200176 kb
Host smart-236f4dfa-cd4a-48fe-b8cc-10e952ad9a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969807979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1969807979
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2250325998
Short name T628
Test name
Test status
Simulation time 18956610856 ps
CPU time 43.71 seconds
Started Jul 23 06:59:28 PM PDT 24
Finished Jul 23 07:00:14 PM PDT 24
Peak memory 200208 kb
Host smart-ebdceea6-c59f-4611-9d1e-890a53726ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250325998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2250325998
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.994752439
Short name T165
Test name
Test status
Simulation time 16653814690 ps
CPU time 34.92 seconds
Started Jul 23 06:59:33 PM PDT 24
Finished Jul 23 07:00:10 PM PDT 24
Peak memory 200196 kb
Host smart-86925ecf-efd4-4ae9-995f-828ec0a480bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994752439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.994752439
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2040260987
Short name T245
Test name
Test status
Simulation time 76509761846 ps
CPU time 73.77 seconds
Started Jul 23 06:59:33 PM PDT 24
Finished Jul 23 07:00:48 PM PDT 24
Peak memory 200268 kb
Host smart-1ca61129-3ba1-4d75-90cd-7ad7b02fbf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040260987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2040260987
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1417015879
Short name T24
Test name
Test status
Simulation time 16218932 ps
CPU time 0.56 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 195928 kb
Host smart-8c42a28f-8a3d-47d4-a6fe-9348c85e6a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417015879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1417015879
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3014538448
Short name T682
Test name
Test status
Simulation time 123181181083 ps
CPU time 50.1 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 200192 kb
Host smart-3578dd7e-a3ae-4954-839d-a75116dd9033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014538448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3014538448
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.846532033
Short name T749
Test name
Test status
Simulation time 42283207887 ps
CPU time 71.46 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:52:14 PM PDT 24
Peak memory 200272 kb
Host smart-971d9ebb-2331-4e1d-bac7-57ae89b1e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846532033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.846532033
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2035135657
Short name T1077
Test name
Test status
Simulation time 29861126465 ps
CPU time 14.51 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:18 PM PDT 24
Peak memory 200192 kb
Host smart-8a70b3c6-ac92-4908-825b-b0e6843ff43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035135657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2035135657
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4261508535
Short name T605
Test name
Test status
Simulation time 50216176683 ps
CPU time 69.89 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:52:13 PM PDT 24
Peak memory 200224 kb
Host smart-838614fa-cc9d-4fac-b405-031d3384cd3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261508535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4261508535
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3445805053
Short name T593
Test name
Test status
Simulation time 80706851648 ps
CPU time 164.78 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:53:50 PM PDT 24
Peak memory 200268 kb
Host smart-1011aefe-b78c-4037-b093-13e12e2b1c0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445805053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3445805053
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.4211094486
Short name T1071
Test name
Test status
Simulation time 10242113965 ps
CPU time 10.01 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 200248 kb
Host smart-7302479a-c2e2-41b7-8956-e1b2db9b425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211094486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4211094486
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.691077124
Short name T484
Test name
Test status
Simulation time 63645860359 ps
CPU time 24.26 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 196940 kb
Host smart-ce6a4603-f80e-4efa-8358-a996710d83cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691077124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.691077124
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1740626825
Short name T690
Test name
Test status
Simulation time 27266229623 ps
CPU time 209.41 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:54:35 PM PDT 24
Peak memory 200148 kb
Host smart-98c65dbc-7b4e-4050-a966-551e09b6dbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740626825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1740626825
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3547935211
Short name T576
Test name
Test status
Simulation time 1614721758 ps
CPU time 1.78 seconds
Started Jul 23 06:51:02 PM PDT 24
Finished Jul 23 06:51:07 PM PDT 24
Peak memory 198188 kb
Host smart-76d9c36f-74ab-4dc8-b57a-50f64b0da8c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547935211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3547935211
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1760242841
Short name T274
Test name
Test status
Simulation time 21615440292 ps
CPU time 78.85 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 06:52:28 PM PDT 24
Peak memory 199888 kb
Host smart-30c4e92d-b024-46ff-bd4a-253d8c341b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760242841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1760242841
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2156523140
Short name T1098
Test name
Test status
Simulation time 73270322438 ps
CPU time 27.47 seconds
Started Jul 23 06:51:03 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 196100 kb
Host smart-2301022c-4979-46f2-810b-e97021e2255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156523140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2156523140
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2222467265
Short name T25
Test name
Test status
Simulation time 134101411 ps
CPU time 0.8 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 218592 kb
Host smart-7409b967-902a-4e51-9873-6671932b9558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222467265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2222467265
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.117185623
Short name T727
Test name
Test status
Simulation time 273387801 ps
CPU time 1.51 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 198512 kb
Host smart-1122cd79-389b-4741-9017-92cd47e02e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117185623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.117185623
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2481102209
Short name T679
Test name
Test status
Simulation time 191465978335 ps
CPU time 415.45 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:58:04 PM PDT 24
Peak memory 200180 kb
Host smart-5ccef467-97d7-4a95-b4ae-4e746571e679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481102209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2481102209
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1054233652
Short name T813
Test name
Test status
Simulation time 59182616848 ps
CPU time 782.86 seconds
Started Jul 23 06:51:03 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 216884 kb
Host smart-54382cf0-8c02-4ed8-a0cb-cd33f159630f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054233652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1054233652
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.145167820
Short name T1144
Test name
Test status
Simulation time 2265927340 ps
CPU time 1.99 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 198824 kb
Host smart-1a37aad7-8741-4be9-a5f5-c590f12bf88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145167820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.145167820
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3821858541
Short name T510
Test name
Test status
Simulation time 42022676715 ps
CPU time 61.7 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:52:06 PM PDT 24
Peak memory 200252 kb
Host smart-cb187006-dfc8-4add-a993-00c9534aa6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821858541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3821858541
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1308507570
Short name T708
Test name
Test status
Simulation time 19259379 ps
CPU time 0.56 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 195936 kb
Host smart-1036b29d-f802-4c7d-a6d0-879dfd584788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308507570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1308507570
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3393673105
Short name T715
Test name
Test status
Simulation time 27614379627 ps
CPU time 41.54 seconds
Started Jul 23 06:52:26 PM PDT 24
Finished Jul 23 06:53:08 PM PDT 24
Peak memory 200244 kb
Host smart-e2081ece-7f2d-4f85-b5f4-6958b776252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393673105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3393673105
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3759275664
Short name T823
Test name
Test status
Simulation time 176907423843 ps
CPU time 72.65 seconds
Started Jul 23 06:52:27 PM PDT 24
Finished Jul 23 06:53:41 PM PDT 24
Peak memory 200088 kb
Host smart-6a3a2dc3-8e40-43b5-9ea4-b6861d41b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759275664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3759275664
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2517533735
Short name T367
Test name
Test status
Simulation time 35373076327 ps
CPU time 64.82 seconds
Started Jul 23 06:52:25 PM PDT 24
Finished Jul 23 06:53:31 PM PDT 24
Peak memory 200200 kb
Host smart-918cf486-b5ff-496e-97fe-97ecc5995229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517533735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2517533735
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.644885940
Short name T930
Test name
Test status
Simulation time 21345291342 ps
CPU time 36.12 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:53:01 PM PDT 24
Peak memory 200248 kb
Host smart-ec2d0094-1f7b-453f-a876-1e0deb6fe241
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644885940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.644885940
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.395991295
Short name T1009
Test name
Test status
Simulation time 76747128644 ps
CPU time 466.78 seconds
Started Jul 23 06:52:38 PM PDT 24
Finished Jul 23 07:00:26 PM PDT 24
Peak memory 200192 kb
Host smart-d8712986-8729-43a3-b811-b120cb8e432e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395991295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.395991295
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1185299212
Short name T475
Test name
Test status
Simulation time 656517903 ps
CPU time 0.87 seconds
Started Jul 23 06:52:24 PM PDT 24
Finished Jul 23 06:52:26 PM PDT 24
Peak memory 196292 kb
Host smart-7c590802-84a8-4a8a-b858-93a21c60df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185299212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1185299212
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3970344266
Short name T666
Test name
Test status
Simulation time 68814886162 ps
CPU time 121.88 seconds
Started Jul 23 06:52:22 PM PDT 24
Finished Jul 23 06:54:26 PM PDT 24
Peak memory 200092 kb
Host smart-adb1c371-da98-486c-903a-354ce5c479a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970344266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3970344266
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.474304464
Short name T1100
Test name
Test status
Simulation time 20033517591 ps
CPU time 505.82 seconds
Started Jul 23 06:52:30 PM PDT 24
Finished Jul 23 07:00:57 PM PDT 24
Peak memory 200164 kb
Host smart-9a231523-c128-40f1-b727-d0eaf3b37c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474304464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.474304464
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3324352633
Short name T869
Test name
Test status
Simulation time 7049011849 ps
CPU time 15.25 seconds
Started Jul 23 06:52:25 PM PDT 24
Finished Jul 23 06:52:41 PM PDT 24
Peak memory 198212 kb
Host smart-a5ca4394-c42c-4199-a5e3-5b6f0a053830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324352633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3324352633
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1553682127
Short name T1129
Test name
Test status
Simulation time 20718763285 ps
CPU time 16.71 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 198144 kb
Host smart-4d00b93f-da67-43b3-a069-3e7975f5d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553682127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1553682127
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.418464112
Short name T140
Test name
Test status
Simulation time 3532831327 ps
CPU time 2.14 seconds
Started Jul 23 06:52:26 PM PDT 24
Finished Jul 23 06:52:29 PM PDT 24
Peak memory 196464 kb
Host smart-6b44f83f-7eaf-4c80-aa75-8cf177fdd763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418464112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.418464112
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.69464680
Short name T1036
Test name
Test status
Simulation time 5355039095 ps
CPU time 10.23 seconds
Started Jul 23 06:52:27 PM PDT 24
Finished Jul 23 06:52:38 PM PDT 24
Peak memory 200128 kb
Host smart-60b4f432-3c82-4dac-b220-f696c20e1af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69464680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.69464680
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3769058212
Short name T352
Test name
Test status
Simulation time 513776538037 ps
CPU time 541.75 seconds
Started Jul 23 06:52:32 PM PDT 24
Finished Jul 23 07:01:34 PM PDT 24
Peak memory 208568 kb
Host smart-f6d4401d-d1b1-4667-b4a5-51e782af28fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769058212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3769058212
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3146715821
Short name T347
Test name
Test status
Simulation time 17094832512 ps
CPU time 678.11 seconds
Started Jul 23 06:52:29 PM PDT 24
Finished Jul 23 07:03:48 PM PDT 24
Peak memory 208544 kb
Host smart-3715b6cc-2e86-4b21-b114-c35f34fd2cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146715821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3146715821
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3046788825
Short name T760
Test name
Test status
Simulation time 848070046 ps
CPU time 2.58 seconds
Started Jul 23 06:52:23 PM PDT 24
Finished Jul 23 06:52:27 PM PDT 24
Peak memory 199912 kb
Host smart-1cafd469-3ae6-47ab-a222-d9c13e1e5824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046788825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3046788825
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1868890268
Short name T326
Test name
Test status
Simulation time 200259649486 ps
CPU time 223.76 seconds
Started Jul 23 06:52:27 PM PDT 24
Finished Jul 23 06:56:12 PM PDT 24
Peak memory 200024 kb
Host smart-278a2850-1b67-47bc-9883-54d6ce2abb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868890268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1868890268
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3946963827
Short name T470
Test name
Test status
Simulation time 33209102 ps
CPU time 0.56 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:52:35 PM PDT 24
Peak memory 195604 kb
Host smart-e3838c7d-4561-4848-8c50-9ddd80125938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946963827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3946963827
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.665989250
Short name T1156
Test name
Test status
Simulation time 17364846686 ps
CPU time 12.63 seconds
Started Jul 23 06:52:31 PM PDT 24
Finished Jul 23 06:52:44 PM PDT 24
Peak memory 200216 kb
Host smart-929ab381-8a2d-4c5b-90f3-bd40643fa141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665989250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.665989250
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2555552732
Short name T892
Test name
Test status
Simulation time 128315914597 ps
CPU time 36.9 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:53:18 PM PDT 24
Peak memory 199876 kb
Host smart-cae0a413-a99d-46c0-9cdd-5b6b2d4eb2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555552732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2555552732
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3364263228
Short name T1099
Test name
Test status
Simulation time 38092850148 ps
CPU time 20.74 seconds
Started Jul 23 06:52:31 PM PDT 24
Finished Jul 23 06:52:53 PM PDT 24
Peak memory 200168 kb
Host smart-5ba3eb6f-d95b-48c6-9ef5-a66e233cc81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364263228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3364263228
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2545909581
Short name T1165
Test name
Test status
Simulation time 30780342648 ps
CPU time 13.7 seconds
Started Jul 23 06:52:33 PM PDT 24
Finished Jul 23 06:52:47 PM PDT 24
Peak memory 200252 kb
Host smart-c61e9d6f-c6d1-4e95-a591-f614ef4d4a9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545909581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2545909581
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.399029395
Short name T815
Test name
Test status
Simulation time 54851480567 ps
CPU time 280.23 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:57:22 PM PDT 24
Peak memory 200156 kb
Host smart-99259fb4-c4ee-4f03-9840-dd30b1cda2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399029395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.399029395
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.157937407
Short name T721
Test name
Test status
Simulation time 4939732627 ps
CPU time 12.84 seconds
Started Jul 23 06:52:30 PM PDT 24
Finished Jul 23 06:52:44 PM PDT 24
Peak memory 199792 kb
Host smart-96b64a42-12f0-4b1c-87a1-59b31e19ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157937407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.157937407
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.4286559529
Short name T763
Test name
Test status
Simulation time 114202064270 ps
CPU time 429.7 seconds
Started Jul 23 06:52:30 PM PDT 24
Finished Jul 23 06:59:40 PM PDT 24
Peak memory 199728 kb
Host smart-52deab21-3aae-40a9-9a53-b26fcf87fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286559529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4286559529
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3277001028
Short name T279
Test name
Test status
Simulation time 13831400991 ps
CPU time 540.66 seconds
Started Jul 23 06:52:31 PM PDT 24
Finished Jul 23 07:01:32 PM PDT 24
Peak memory 200120 kb
Host smart-2de38a41-abc6-47a5-9f19-cbe9f0426842
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277001028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3277001028
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1191980202
Short name T864
Test name
Test status
Simulation time 4123877264 ps
CPU time 29.21 seconds
Started Jul 23 06:52:30 PM PDT 24
Finished Jul 23 06:53:00 PM PDT 24
Peak memory 199472 kb
Host smart-184d9129-3d30-49b7-ae8a-25ca6b265174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191980202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1191980202
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3573115515
Short name T885
Test name
Test status
Simulation time 48312265352 ps
CPU time 45.32 seconds
Started Jul 23 06:52:29 PM PDT 24
Finished Jul 23 06:53:15 PM PDT 24
Peak memory 200232 kb
Host smart-b0dbac72-a756-4fe8-82c3-926442511f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573115515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3573115515
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3231578821
Short name T1153
Test name
Test status
Simulation time 4131680900 ps
CPU time 6.03 seconds
Started Jul 23 06:52:32 PM PDT 24
Finished Jul 23 06:52:38 PM PDT 24
Peak memory 197056 kb
Host smart-9c0387b2-1c13-4363-bcf1-621691f180a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231578821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3231578821
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3474876515
Short name T328
Test name
Test status
Simulation time 5556945138 ps
CPU time 18.64 seconds
Started Jul 23 06:52:31 PM PDT 24
Finished Jul 23 06:52:50 PM PDT 24
Peak memory 200172 kb
Host smart-b97f7b2e-b072-4a75-8a25-ad33709edcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474876515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3474876515
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2470897008
Short name T1160
Test name
Test status
Simulation time 506773928341 ps
CPU time 389.74 seconds
Started Jul 23 06:52:39 PM PDT 24
Finished Jul 23 06:59:10 PM PDT 24
Peak memory 200248 kb
Host smart-01973405-bffc-4d21-b78d-c8df75854e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470897008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2470897008
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1149854713
Short name T31
Test name
Test status
Simulation time 51874137401 ps
CPU time 416.19 seconds
Started Jul 23 06:52:29 PM PDT 24
Finished Jul 23 06:59:26 PM PDT 24
Peak memory 216948 kb
Host smart-60137c23-61ea-4dc2-9eca-ec3caa7d7006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149854713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1149854713
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.418000350
Short name T877
Test name
Test status
Simulation time 8595569354 ps
CPU time 1.43 seconds
Started Jul 23 06:52:30 PM PDT 24
Finished Jul 23 06:52:33 PM PDT 24
Peak memory 199184 kb
Host smart-95187c12-2c37-4c25-86a6-e3425f972c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418000350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.418000350
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.341158534
Short name T46
Test name
Test status
Simulation time 70165360380 ps
CPU time 122.6 seconds
Started Jul 23 06:52:29 PM PDT 24
Finished Jul 23 06:54:32 PM PDT 24
Peak memory 200208 kb
Host smart-bc968542-7518-4384-b425-7494d2555bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341158534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.341158534
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4032940513
Short name T933
Test name
Test status
Simulation time 11936927 ps
CPU time 0.53 seconds
Started Jul 23 06:52:35 PM PDT 24
Finished Jul 23 06:52:37 PM PDT 24
Peak memory 195100 kb
Host smart-9cb87582-14d7-4921-aff8-4cab67a19afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032940513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4032940513
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3533897080
Short name T751
Test name
Test status
Simulation time 193458312357 ps
CPU time 68.27 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:53:50 PM PDT 24
Peak memory 200252 kb
Host smart-d9a441c9-c7b8-4e41-b59e-6ed2b6ebdb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533897080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3533897080
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1816280709
Short name T483
Test name
Test status
Simulation time 16573056370 ps
CPU time 22.57 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:52:58 PM PDT 24
Peak memory 200000 kb
Host smart-0bfb63e8-781e-4583-9518-780f70319c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816280709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1816280709
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.893566350
Short name T571
Test name
Test status
Simulation time 81060074265 ps
CPU time 95.75 seconds
Started Jul 23 06:52:39 PM PDT 24
Finished Jul 23 06:54:15 PM PDT 24
Peak memory 200192 kb
Host smart-52cc12e8-1954-4e4e-9de4-5cf08bfd889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893566350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.893566350
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1424111065
Short name T983
Test name
Test status
Simulation time 67905627943 ps
CPU time 77.53 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 200264 kb
Host smart-ec11708a-62d5-4b78-ac5d-8f7d4e8fc51e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424111065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1424111065
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3494068339
Short name T994
Test name
Test status
Simulation time 63314880347 ps
CPU time 694.38 seconds
Started Jul 23 06:52:36 PM PDT 24
Finished Jul 23 07:04:11 PM PDT 24
Peak memory 200128 kb
Host smart-137534dc-63a0-4a5c-b8aa-68ed48c8b33a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494068339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3494068339
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1084609998
Short name T19
Test name
Test status
Simulation time 3360441532 ps
CPU time 3.86 seconds
Started Jul 23 06:52:35 PM PDT 24
Finished Jul 23 06:52:40 PM PDT 24
Peak memory 198932 kb
Host smart-a54d6ed1-b405-46c5-b2fd-ea1b2ea4857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084609998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1084609998
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3125755711
Short name T566
Test name
Test status
Simulation time 209048884252 ps
CPU time 140.49 seconds
Started Jul 23 06:52:35 PM PDT 24
Finished Jul 23 06:54:56 PM PDT 24
Peak memory 208504 kb
Host smart-61cc2e5a-d8e4-414e-9598-b73409f918dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125755711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3125755711
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1556171484
Short name T354
Test name
Test status
Simulation time 5059909411 ps
CPU time 285.19 seconds
Started Jul 23 06:52:33 PM PDT 24
Finished Jul 23 06:57:18 PM PDT 24
Peak memory 200180 kb
Host smart-32afb249-8d63-4d8c-b639-ce0915fd1d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556171484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1556171484
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3774868277
Short name T641
Test name
Test status
Simulation time 3918001648 ps
CPU time 31.27 seconds
Started Jul 23 06:52:36 PM PDT 24
Finished Jul 23 06:53:08 PM PDT 24
Peak memory 198300 kb
Host smart-04f9c936-c82a-499d-87cf-c74379a309fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774868277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3774868277
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1721316446
Short name T124
Test name
Test status
Simulation time 18606758400 ps
CPU time 39.08 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:53:14 PM PDT 24
Peak memory 200244 kb
Host smart-3751da8f-a1b4-4aea-bc03-5a0d8d69aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721316446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1721316446
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2627528034
Short name T1043
Test name
Test status
Simulation time 33681883446 ps
CPU time 13.92 seconds
Started Jul 23 06:52:38 PM PDT 24
Finished Jul 23 06:52:53 PM PDT 24
Peak memory 196264 kb
Host smart-e7fd4efd-13ca-4858-9b7e-03bc1fc09dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627528034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2627528034
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3771227184
Short name T734
Test name
Test status
Simulation time 312611208 ps
CPU time 1.08 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:52:36 PM PDT 24
Peak memory 198812 kb
Host smart-19de30d1-14c2-40a6-a532-67c014debdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771227184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3771227184
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3920688761
Short name T292
Test name
Test status
Simulation time 39374753384 ps
CPU time 23.23 seconds
Started Jul 23 06:52:39 PM PDT 24
Finished Jul 23 06:53:03 PM PDT 24
Peak memory 200188 kb
Host smart-49e632c1-3f42-4a7d-816b-c0f422790815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920688761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3920688761
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1922601655
Short name T58
Test name
Test status
Simulation time 132527372591 ps
CPU time 892.05 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 225352 kb
Host smart-b379a4e4-0e7f-44af-91b8-60e05f8a37bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922601655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1922601655
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1122740693
Short name T381
Test name
Test status
Simulation time 484902074 ps
CPU time 1.69 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:52:44 PM PDT 24
Peak memory 199404 kb
Host smart-b3f82110-9edb-440f-911b-c445ea090f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122740693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1122740693
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2839884670
Short name T922
Test name
Test status
Simulation time 94430536699 ps
CPU time 72.88 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:56 PM PDT 24
Peak memory 200260 kb
Host smart-5bae0d6f-fa30-4665-82ed-3514391476be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839884670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2839884670
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1338507782
Short name T379
Test name
Test status
Simulation time 37345161 ps
CPU time 0.55 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:52:41 PM PDT 24
Peak memory 195600 kb
Host smart-73f89527-a018-4e64-a20c-45f6cd9a6eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338507782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1338507782
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2817977960
Short name T480
Test name
Test status
Simulation time 38330424998 ps
CPU time 29.69 seconds
Started Jul 23 06:52:36 PM PDT 24
Finished Jul 23 06:53:06 PM PDT 24
Peak memory 199788 kb
Host smart-74253cad-737e-4161-a117-dc2b9a5bcaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817977960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2817977960
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3641433967
Short name T564
Test name
Test status
Simulation time 12138115553 ps
CPU time 18.16 seconds
Started Jul 23 06:52:35 PM PDT 24
Finished Jul 23 06:52:54 PM PDT 24
Peak memory 199012 kb
Host smart-fcbb9c03-4039-4aae-abad-4caf384ac28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641433967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3641433967
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1174977624
Short name T1146
Test name
Test status
Simulation time 15582355352 ps
CPU time 13.45 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:52:57 PM PDT 24
Peak memory 200028 kb
Host smart-5d90bb2f-4074-4474-a09f-a35d5fc97a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174977624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1174977624
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2763282901
Short name T984
Test name
Test status
Simulation time 16695079860 ps
CPU time 7.36 seconds
Started Jul 23 06:52:38 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 198100 kb
Host smart-8b13152c-928a-4812-9b01-ded3e63fe56a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763282901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2763282901
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2565284967
Short name T302
Test name
Test status
Simulation time 153593044035 ps
CPU time 96.59 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 06:54:21 PM PDT 24
Peak memory 200156 kb
Host smart-254d56a2-1c4d-4ae8-b7f5-51b71ad589f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565284967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2565284967
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2777915400
Short name T753
Test name
Test status
Simulation time 5012472857 ps
CPU time 1.73 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 196820 kb
Host smart-80109843-4b7a-4086-b137-4071a82823ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777915400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2777915400
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4145128856
Short name T1001
Test name
Test status
Simulation time 99131250035 ps
CPU time 107.57 seconds
Started Jul 23 06:52:39 PM PDT 24
Finished Jul 23 06:54:27 PM PDT 24
Peak memory 200344 kb
Host smart-e5b89f62-8d80-46f8-a783-5f372cc88d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145128856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4145128856
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3061782914
Short name T403
Test name
Test status
Simulation time 25687582055 ps
CPU time 374.89 seconds
Started Jul 23 06:52:42 PM PDT 24
Finished Jul 23 06:58:59 PM PDT 24
Peak memory 200144 kb
Host smart-afebe8a0-6fff-4255-b13e-92c74e58e0f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061782914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3061782914
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3227121784
Short name T812
Test name
Test status
Simulation time 2229675858 ps
CPU time 3.35 seconds
Started Jul 23 06:52:37 PM PDT 24
Finished Jul 23 06:52:41 PM PDT 24
Peak memory 198376 kb
Host smart-6c75a292-6955-4bc6-9e45-c1316293cde9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227121784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3227121784
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2365003237
Short name T664
Test name
Test status
Simulation time 32344673606 ps
CPU time 20.82 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:04 PM PDT 24
Peak memory 200244 kb
Host smart-cecd0685-aca1-49ae-a37f-dbc7e494966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365003237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2365003237
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.843198524
Short name T315
Test name
Test status
Simulation time 4686707691 ps
CPU time 2.44 seconds
Started Jul 23 06:52:42 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 196344 kb
Host smart-e2625a68-cb5c-4b0d-af47-e58d081f2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843198524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.843198524
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1159304799
Short name T117
Test name
Test status
Simulation time 462024731 ps
CPU time 1.72 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:52:43 PM PDT 24
Peak memory 198676 kb
Host smart-35829230-3dac-4bf3-9320-7f21414b0c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159304799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1159304799
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.431924383
Short name T368
Test name
Test status
Simulation time 294138656935 ps
CPU time 648.17 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 07:03:32 PM PDT 24
Peak memory 200224 kb
Host smart-201725c6-c050-4a81-bcc8-e97366cb7c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431924383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.431924383
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2225199706
Short name T752
Test name
Test status
Simulation time 48847049314 ps
CPU time 1349.05 seconds
Started Jul 23 06:52:38 PM PDT 24
Finished Jul 23 07:15:08 PM PDT 24
Peak memory 225076 kb
Host smart-a2970c3b-4a15-4ef0-ad50-49b6410d844b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225199706 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2225199706
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2710656070
Short name T1024
Test name
Test status
Simulation time 1276358545 ps
CPU time 4.44 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 06:52:49 PM PDT 24
Peak memory 199740 kb
Host smart-ab3d0990-025f-4b07-a829-3472a10e76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710656070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2710656070
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3358309335
Short name T327
Test name
Test status
Simulation time 68251820032 ps
CPU time 93.37 seconds
Started Jul 23 06:52:34 PM PDT 24
Finished Jul 23 06:54:09 PM PDT 24
Peak memory 200228 kb
Host smart-cd39023c-8453-4eb9-bee6-f444c0973072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358309335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3358309335
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1710977249
Short name T398
Test name
Test status
Simulation time 14880082 ps
CPU time 0.58 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 06:52:47 PM PDT 24
Peak memory 195928 kb
Host smart-8d0733bf-9d14-4620-ae4b-90f59a19e7da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710977249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1710977249
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.506590949
Short name T1022
Test name
Test status
Simulation time 45658214386 ps
CPU time 22.8 seconds
Started Jul 23 06:52:42 PM PDT 24
Finished Jul 23 06:53:07 PM PDT 24
Peak memory 200168 kb
Host smart-8091bacf-9f24-4bcf-ac97-1ed34df6f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506590949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.506590949
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.74621975
Short name T851
Test name
Test status
Simulation time 53460150689 ps
CPU time 42 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 06:53:26 PM PDT 24
Peak memory 200244 kb
Host smart-146acd54-f622-4755-adb6-a082e70fab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74621975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.74621975
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.3187092115
Short name T731
Test name
Test status
Simulation time 21979690661 ps
CPU time 15.47 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:52:58 PM PDT 24
Peak memory 197176 kb
Host smart-a1e7fd2a-85e8-44e5-b81f-40f2e23581f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187092115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3187092115
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3640573883
Short name T272
Test name
Test status
Simulation time 111249420333 ps
CPU time 300.66 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:57:44 PM PDT 24
Peak memory 200156 kb
Host smart-a9100df4-bd34-4014-bcdb-119949b42327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640573883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3640573883
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2736854774
Short name T680
Test name
Test status
Simulation time 8693490671 ps
CPU time 6.32 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:52:49 PM PDT 24
Peak memory 200108 kb
Host smart-22abb0f3-a1fe-429a-bd2b-42faf04c889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736854774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2736854774
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.778890064
Short name T35
Test name
Test status
Simulation time 73619785471 ps
CPU time 29.75 seconds
Started Jul 23 06:52:43 PM PDT 24
Finished Jul 23 06:53:14 PM PDT 24
Peak memory 199464 kb
Host smart-b5118f59-e0e0-4b54-a400-3833c802f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778890064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.778890064
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2373720989
Short name T312
Test name
Test status
Simulation time 30581853982 ps
CPU time 266.83 seconds
Started Jul 23 06:52:40 PM PDT 24
Finished Jul 23 06:57:09 PM PDT 24
Peak memory 200240 kb
Host smart-b00314e5-ca4d-4f08-b7c2-02d22e90967d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373720989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2373720989
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1758763310
Short name T408
Test name
Test status
Simulation time 3259683947 ps
CPU time 5.97 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 06:52:52 PM PDT 24
Peak memory 198280 kb
Host smart-d0e33ace-56df-4f25-8a7e-9266445af8d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758763310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1758763310
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3447329698
Short name T621
Test name
Test status
Simulation time 20837282256 ps
CPU time 25.15 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:08 PM PDT 24
Peak memory 200176 kb
Host smart-54fb3b89-505f-460d-adcc-46391924a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447329698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3447329698
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2193380946
Short name T1021
Test name
Test status
Simulation time 34872637213 ps
CPU time 27.61 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:11 PM PDT 24
Peak memory 196264 kb
Host smart-4edf11ad-98f2-40f4-9e28-c169812133a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193380946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2193380946
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2894494784
Short name T318
Test name
Test status
Simulation time 6043877848 ps
CPU time 6.9 seconds
Started Jul 23 06:52:42 PM PDT 24
Finished Jul 23 06:52:51 PM PDT 24
Peak memory 200008 kb
Host smart-ba40a1ef-0c47-4386-af49-8cb456d288a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894494784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2894494784
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.719189773
Short name T509
Test name
Test status
Simulation time 117003629600 ps
CPU time 1511.17 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 07:17:57 PM PDT 24
Peak memory 200164 kb
Host smart-82622d0d-76c2-46a9-9d09-d7d1a836f235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719189773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.719189773
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.891849708
Short name T79
Test name
Test status
Simulation time 68315914055 ps
CPU time 539.15 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 07:01:46 PM PDT 24
Peak memory 216916 kb
Host smart-00e9e084-bed3-43b8-aff6-a2bb0c925cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891849708 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.891849708
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3609357779
Short name T433
Test name
Test status
Simulation time 768200774 ps
CPU time 1.1 seconds
Started Jul 23 06:52:39 PM PDT 24
Finished Jul 23 06:52:41 PM PDT 24
Peak memory 197564 kb
Host smart-7a5f3142-2c21-41c7-8e60-461e7a6ac51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609357779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3609357779
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2692803250
Short name T370
Test name
Test status
Simulation time 72322298338 ps
CPU time 29.81 seconds
Started Jul 23 06:52:41 PM PDT 24
Finished Jul 23 06:53:12 PM PDT 24
Peak memory 200200 kb
Host smart-ca14245c-9fe7-43db-a160-4123ce0a6b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692803250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2692803250
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1252623711
Short name T1162
Test name
Test status
Simulation time 13733104 ps
CPU time 0.55 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 06:52:46 PM PDT 24
Peak memory 195628 kb
Host smart-32a188d1-93bf-4f32-b878-00aed07da85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252623711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1252623711
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.114990136
Short name T625
Test name
Test status
Simulation time 93968175742 ps
CPU time 103.01 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 06:54:29 PM PDT 24
Peak memory 200280 kb
Host smart-e426fdca-ce97-4267-bdfd-cf25611c7531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114990136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.114990136
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1642110166
Short name T809
Test name
Test status
Simulation time 195257886366 ps
CPU time 162.67 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 06:55:30 PM PDT 24
Peak memory 200204 kb
Host smart-4033a0d9-5468-47a7-8b11-09dfa03374c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642110166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1642110166
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.818224050
Short name T230
Test name
Test status
Simulation time 36982912464 ps
CPU time 57.9 seconds
Started Jul 23 06:52:49 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 200056 kb
Host smart-2983c3d9-7402-4b57-8af2-91c08ad376ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818224050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.818224050
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1361837360
Short name T51
Test name
Test status
Simulation time 39096351886 ps
CPU time 20.75 seconds
Started Jul 23 06:52:51 PM PDT 24
Finished Jul 23 06:53:13 PM PDT 24
Peak memory 200016 kb
Host smart-51ebe25d-27da-4d98-ba12-115c036786ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361837360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1361837360
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.37044018
Short name T282
Test name
Test status
Simulation time 138309950431 ps
CPU time 591.63 seconds
Started Jul 23 06:52:46 PM PDT 24
Finished Jul 23 07:02:39 PM PDT 24
Peak memory 200148 kb
Host smart-90c921bc-612c-4379-9fc2-7f80c87e3db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37044018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.37044018
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2602366834
Short name T766
Test name
Test status
Simulation time 13192202053 ps
CPU time 12.09 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 06:52:58 PM PDT 24
Peak memory 198700 kb
Host smart-dab8c78b-a168-4b74-925a-060eec26cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602366834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2602366834
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4036185158
Short name T303
Test name
Test status
Simulation time 252011893562 ps
CPU time 75.3 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 208544 kb
Host smart-3f51288b-bf42-4a48-9de1-0426b3fbd1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036185158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4036185158
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1080804966
Short name T440
Test name
Test status
Simulation time 15780977596 ps
CPU time 696.03 seconds
Started Jul 23 06:52:46 PM PDT 24
Finished Jul 23 07:04:24 PM PDT 24
Peak memory 200252 kb
Host smart-5ac90bb2-6777-4eaf-905a-3ca0be017701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080804966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1080804966
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3856213881
Short name T799
Test name
Test status
Simulation time 5093728642 ps
CPU time 12.9 seconds
Started Jul 23 06:52:46 PM PDT 24
Finished Jul 23 06:53:00 PM PDT 24
Peak memory 198388 kb
Host smart-d4eef5e1-763a-411a-a9ce-abe18fa4dc47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856213881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3856213881
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1812341452
Short name T941
Test name
Test status
Simulation time 55086909588 ps
CPU time 83.19 seconds
Started Jul 23 06:52:46 PM PDT 24
Finished Jul 23 06:54:11 PM PDT 24
Peak memory 200228 kb
Host smart-d594b7c9-3f5e-4bb3-8337-45ccc7543868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812341452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1812341452
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.160977962
Short name T392
Test name
Test status
Simulation time 2942848527 ps
CPU time 4.94 seconds
Started Jul 23 06:52:47 PM PDT 24
Finished Jul 23 06:52:53 PM PDT 24
Peak memory 196704 kb
Host smart-bec77e31-14f8-4760-aa9f-9a734a466087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160977962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.160977962
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2627801448
Short name T1070
Test name
Test status
Simulation time 269276366 ps
CPU time 1.11 seconds
Started Jul 23 06:52:49 PM PDT 24
Finished Jul 23 06:52:52 PM PDT 24
Peak memory 198620 kb
Host smart-0a042796-5ac0-4f7d-8043-a38a2122f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627801448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2627801448
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2049262918
Short name T773
Test name
Test status
Simulation time 302306106795 ps
CPU time 451.53 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 07:00:17 PM PDT 24
Peak memory 200236 kb
Host smart-cd86a116-39e9-4e3e-a596-d12772ade67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049262918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2049262918
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2534284738
Short name T59
Test name
Test status
Simulation time 190527237491 ps
CPU time 793.86 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 07:06:00 PM PDT 24
Peak memory 216704 kb
Host smart-97f3bc6a-93da-4fce-9635-e4d9505ebb8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534284738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2534284738
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2672326011
Short name T1157
Test name
Test status
Simulation time 522830420 ps
CPU time 2.12 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 06:52:56 PM PDT 24
Peak memory 199212 kb
Host smart-eaf515d5-d05e-4f53-a178-dc6b50bbba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672326011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2672326011
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3874537896
Short name T926
Test name
Test status
Simulation time 5517496805 ps
CPU time 9.14 seconds
Started Jul 23 06:52:44 PM PDT 24
Finished Jul 23 06:52:55 PM PDT 24
Peak memory 197200 kb
Host smart-18c20d7d-df15-4f5f-bf72-bea829e525aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874537896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3874537896
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.74192248
Short name T376
Test name
Test status
Simulation time 42347537 ps
CPU time 0.58 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:52:52 PM PDT 24
Peak memory 195928 kb
Host smart-ae8cc857-0fa7-4ecf-a74c-d32b7a8fceb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74192248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.74192248
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.863431698
Short name T688
Test name
Test status
Simulation time 112877039631 ps
CPU time 172.11 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 06:55:39 PM PDT 24
Peak memory 200108 kb
Host smart-9aaf2542-deee-4c15-8017-b416c0ec3912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863431698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.863431698
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.947849476
Short name T190
Test name
Test status
Simulation time 15390995764 ps
CPU time 7.34 seconds
Started Jul 23 06:52:49 PM PDT 24
Finished Jul 23 06:52:58 PM PDT 24
Peak memory 199680 kb
Host smart-37e53f41-5101-4f1a-aae9-9ab18bb232a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947849476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.947849476
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3981230788
Short name T177
Test name
Test status
Simulation time 181562441245 ps
CPU time 68.47 seconds
Started Jul 23 06:52:51 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 200124 kb
Host smart-d9b67c62-0426-4cda-a73c-79fde375b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981230788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3981230788
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2950091364
Short name T618
Test name
Test status
Simulation time 67229724308 ps
CPU time 85.04 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:54:16 PM PDT 24
Peak memory 200240 kb
Host smart-52a6e414-e7d1-469c-970d-eae597517e1f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950091364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2950091364
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1645496715
Short name T1110
Test name
Test status
Simulation time 28945638764 ps
CPU time 185.01 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 06:56:00 PM PDT 24
Peak memory 200192 kb
Host smart-40c1d03c-59bf-4438-b3a5-2ef364edff61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645496715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1645496715
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2469631422
Short name T500
Test name
Test status
Simulation time 4286470866 ps
CPU time 1.52 seconds
Started Jul 23 06:52:51 PM PDT 24
Finished Jul 23 06:52:54 PM PDT 24
Peak memory 198424 kb
Host smart-82ed6824-4621-4920-b7d7-bdd59cd12d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469631422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2469631422
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.2601758398
Short name T786
Test name
Test status
Simulation time 21056943551 ps
CPU time 1076.42 seconds
Started Jul 23 06:52:52 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 200152 kb
Host smart-19ad1545-c064-4dc9-9126-c381bcc3098f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601758398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2601758398
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1789292541
Short name T1082
Test name
Test status
Simulation time 5667231680 ps
CPU time 50.34 seconds
Started Jul 23 06:52:51 PM PDT 24
Finished Jul 23 06:53:42 PM PDT 24
Peak memory 199172 kb
Host smart-fadd44fa-1db9-44c1-aabb-78b7376b1a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789292541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1789292541
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1903401667
Short name T299
Test name
Test status
Simulation time 12951825439 ps
CPU time 13.96 seconds
Started Jul 23 06:52:52 PM PDT 24
Finished Jul 23 06:53:07 PM PDT 24
Peak memory 200164 kb
Host smart-2ec94cbf-78bd-4bd6-8c49-332ab98e0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903401667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1903401667
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2710464618
Short name T686
Test name
Test status
Simulation time 4391429569 ps
CPU time 3.69 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:52:55 PM PDT 24
Peak memory 196320 kb
Host smart-a393ac7e-b183-4c62-a4d8-7767d47d7b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710464618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2710464618
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1581613050
Short name T698
Test name
Test status
Simulation time 5718467643 ps
CPU time 21.05 seconds
Started Jul 23 06:52:45 PM PDT 24
Finished Jul 23 06:53:08 PM PDT 24
Peak memory 199892 kb
Host smart-0bd6c907-a3d7-4ff9-a96a-608ed984f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581613050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1581613050
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.329183404
Short name T968
Test name
Test status
Simulation time 62639260762 ps
CPU time 35.59 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:53:27 PM PDT 24
Peak memory 200232 kb
Host smart-128f7d91-f0fb-47e4-8dc0-fd048d5e9b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329183404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.329183404
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1454829327
Short name T34
Test name
Test status
Simulation time 104041460832 ps
CPU time 303.73 seconds
Started Jul 23 06:52:51 PM PDT 24
Finished Jul 23 06:57:56 PM PDT 24
Peak memory 216808 kb
Host smart-902dc613-6597-45b4-b9a0-9a17cc4356c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454829327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1454829327
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3055415092
Short name T805
Test name
Test status
Simulation time 1733453664 ps
CPU time 3.15 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:52:54 PM PDT 24
Peak memory 199028 kb
Host smart-0b0c37ae-26a2-4e94-b1e2-4ee118d4a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055415092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3055415092
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.126127925
Short name T481
Test name
Test status
Simulation time 33578890236 ps
CPU time 14.39 seconds
Started Jul 23 06:52:46 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 200148 kb
Host smart-8dcd7db9-abd2-4224-8130-c659e361870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126127925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.126127925
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3516058909
Short name T1148
Test name
Test status
Simulation time 15019902 ps
CPU time 0.56 seconds
Started Jul 23 06:52:55 PM PDT 24
Finished Jul 23 06:52:56 PM PDT 24
Peak memory 195616 kb
Host smart-fd2c5236-4d23-41fe-8eb6-67ecda8f994e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516058909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3516058909
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3428387289
Short name T162
Test name
Test status
Simulation time 44070881649 ps
CPU time 19.6 seconds
Started Jul 23 06:52:49 PM PDT 24
Finished Jul 23 06:53:09 PM PDT 24
Peak memory 200264 kb
Host smart-e446ac98-4982-40ac-b540-82829a92c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428387289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3428387289
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1543236603
Short name T803
Test name
Test status
Simulation time 185381595571 ps
CPU time 321.33 seconds
Started Jul 23 06:52:49 PM PDT 24
Finished Jul 23 06:58:12 PM PDT 24
Peak memory 200268 kb
Host smart-9baa0d61-5085-4be8-9aa4-bd7b5ff7f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543236603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1543236603
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3737388698
Short name T692
Test name
Test status
Simulation time 33980532239 ps
CPU time 17.36 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 06:53:12 PM PDT 24
Peak memory 200208 kb
Host smart-05fe69dc-6592-439d-886c-7759da9ac874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737388698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3737388698
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1765226611
Short name T394
Test name
Test status
Simulation time 40395245096 ps
CPU time 16.53 seconds
Started Jul 23 06:52:55 PM PDT 24
Finished Jul 23 06:53:13 PM PDT 24
Peak memory 199712 kb
Host smart-f7ede752-fe1d-4856-a512-0720a8fe9c76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765226611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1765226611
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2389690264
Short name T478
Test name
Test status
Simulation time 76616577422 ps
CPU time 608.58 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 07:03:02 PM PDT 24
Peak memory 200172 kb
Host smart-5bc07ac2-dc8f-47f4-973c-0a29f87fb6ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389690264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2389690264
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.390004897
Short name T945
Test name
Test status
Simulation time 9511812194 ps
CPU time 4.74 seconds
Started Jul 23 06:52:57 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 200144 kb
Host smart-daf62159-9f49-43d2-9e65-d79d7ba50235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390004897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.390004897
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1910372266
Short name T726
Test name
Test status
Simulation time 66236737262 ps
CPU time 111.63 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 06:54:47 PM PDT 24
Peak memory 200296 kb
Host smart-43821346-87e3-43f6-82ba-2e13a97619a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910372266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1910372266
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.976187055
Short name T806
Test name
Test status
Simulation time 22934004983 ps
CPU time 1309.05 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 07:14:44 PM PDT 24
Peak memory 200188 kb
Host smart-d8903228-5353-49d9-a5a0-5adb2bd66ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976187055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.976187055
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3847896053
Short name T1084
Test name
Test status
Simulation time 5410467365 ps
CPU time 15.56 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 06:53:11 PM PDT 24
Peak memory 199316 kb
Host smart-46b8407c-734c-45ca-af18-dd2c3f31c42a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847896053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3847896053
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.700969406
Short name T290
Test name
Test status
Simulation time 101289437367 ps
CPU time 89.47 seconds
Started Jul 23 06:52:55 PM PDT 24
Finished Jul 23 06:54:25 PM PDT 24
Peak memory 200256 kb
Host smart-5c2ffe7f-6d07-4971-99f2-39e0ea3753ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700969406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.700969406
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4033902190
Short name T998
Test name
Test status
Simulation time 2970734098 ps
CPU time 5.4 seconds
Started Jul 23 06:52:57 PM PDT 24
Finished Jul 23 06:53:03 PM PDT 24
Peak memory 196136 kb
Host smart-dcb11e04-378f-41a7-a6f1-268b847fed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033902190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4033902190
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2052373884
Short name T972
Test name
Test status
Simulation time 501303699 ps
CPU time 1.28 seconds
Started Jul 23 06:52:52 PM PDT 24
Finished Jul 23 06:52:54 PM PDT 24
Peak memory 199044 kb
Host smart-beec0d5b-78c1-4f68-b0a7-bfe732846d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052373884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2052373884
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3697722114
Short name T146
Test name
Test status
Simulation time 45644428375 ps
CPU time 140.83 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 06:55:16 PM PDT 24
Peak memory 200212 kb
Host smart-a5bda4ae-da5c-40d3-9cf4-f763f36cdedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697722114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3697722114
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4024882587
Short name T914
Test name
Test status
Simulation time 50279476304 ps
CPU time 158.41 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 06:55:33 PM PDT 24
Peak memory 208444 kb
Host smart-483c6663-3a91-47d2-91d7-13674d229391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024882587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4024882587
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4028264375
Short name T298
Test name
Test status
Simulation time 6403548380 ps
CPU time 17 seconds
Started Jul 23 06:52:55 PM PDT 24
Finished Jul 23 06:53:13 PM PDT 24
Peak memory 200156 kb
Host smart-63b4848d-2602-48f8-bd01-13696ee3722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028264375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4028264375
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1582063556
Short name T286
Test name
Test status
Simulation time 77440589907 ps
CPU time 108.51 seconds
Started Jul 23 06:52:50 PM PDT 24
Finished Jul 23 06:54:40 PM PDT 24
Peak memory 200264 kb
Host smart-035263dc-c512-46e8-b119-fd4be4cc8d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582063556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1582063556
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2814424852
Short name T22
Test name
Test status
Simulation time 25305735 ps
CPU time 0.56 seconds
Started Jul 23 06:53:01 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 195616 kb
Host smart-9267ce1e-716e-4b3b-9f66-354993da21b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814424852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2814424852
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1399349662
Short name T824
Test name
Test status
Simulation time 134269614778 ps
CPU time 442.84 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 07:00:18 PM PDT 24
Peak memory 200216 kb
Host smart-fd485e02-7e05-4e71-987f-400020b4e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399349662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1399349662
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2232591694
Short name T516
Test name
Test status
Simulation time 18895841825 ps
CPU time 13.09 seconds
Started Jul 23 06:52:56 PM PDT 24
Finished Jul 23 06:53:10 PM PDT 24
Peak memory 200200 kb
Host smart-a861626a-0250-44ef-b4d8-a11f18f2418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232591694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2232591694
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.679467845
Short name T459
Test name
Test status
Simulation time 77086753040 ps
CPU time 26.25 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 06:53:21 PM PDT 24
Peak memory 200240 kb
Host smart-e31b683a-9d84-4138-b011-eef71e0f4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679467845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.679467845
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.4251990999
Short name T17
Test name
Test status
Simulation time 43134189797 ps
CPU time 61.26 seconds
Started Jul 23 06:53:00 PM PDT 24
Finished Jul 23 06:54:02 PM PDT 24
Peak memory 199672 kb
Host smart-b0ee79dc-2c32-4b4b-a381-8e7c291f324c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251990999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4251990999
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.139436537
Short name T529
Test name
Test status
Simulation time 129389483322 ps
CPU time 257.83 seconds
Started Jul 23 06:53:04 PM PDT 24
Finished Jul 23 06:57:22 PM PDT 24
Peak memory 200112 kb
Host smart-9f02b581-c759-454c-a659-dbab6cd5ad14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139436537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.139436537
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2093329723
Short name T426
Test name
Test status
Simulation time 6625653448 ps
CPU time 12.7 seconds
Started Jul 23 06:52:58 PM PDT 24
Finished Jul 23 06:53:12 PM PDT 24
Peak memory 200184 kb
Host smart-0b7118a3-0edf-4e22-9b29-783de75c2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093329723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2093329723
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2811998565
Short name T939
Test name
Test status
Simulation time 248311532900 ps
CPU time 47.38 seconds
Started Jul 23 06:52:59 PM PDT 24
Finished Jul 23 06:53:47 PM PDT 24
Peak memory 200256 kb
Host smart-0cd92f2a-0993-4c7b-8c42-d1030eb44ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811998565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2811998565
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4282968285
Short name T397
Test name
Test status
Simulation time 8000723461 ps
CPU time 226.58 seconds
Started Jul 23 06:53:01 PM PDT 24
Finished Jul 23 06:56:48 PM PDT 24
Peak memory 200260 kb
Host smart-a9b75324-5198-4429-960a-14d8d6e589ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282968285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4282968285
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2835892915
Short name T468
Test name
Test status
Simulation time 2983404385 ps
CPU time 6.11 seconds
Started Jul 23 06:52:54 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 198308 kb
Host smart-ef25ce7d-c1ce-403a-9332-75eb98d35e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835892915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2835892915
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2278994118
Short name T506
Test name
Test status
Simulation time 52059557962 ps
CPU time 82.36 seconds
Started Jul 23 06:52:59 PM PDT 24
Finished Jul 23 06:54:22 PM PDT 24
Peak memory 200272 kb
Host smart-736e3c8d-152d-4911-ab52-b8112e3ad4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278994118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2278994118
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1420869194
Short name T997
Test name
Test status
Simulation time 2067255869 ps
CPU time 1.41 seconds
Started Jul 23 06:52:59 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 195700 kb
Host smart-57586c09-96e7-42a0-8e18-c6b8b6772016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420869194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1420869194
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4178884391
Short name T580
Test name
Test status
Simulation time 6079291713 ps
CPU time 6.03 seconds
Started Jul 23 06:52:55 PM PDT 24
Finished Jul 23 06:53:03 PM PDT 24
Peak memory 200252 kb
Host smart-a0fc5e7e-bfb2-4b79-9e07-2525c2809bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178884391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4178884391
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.4190187893
Short name T271
Test name
Test status
Simulation time 131807215905 ps
CPU time 232.11 seconds
Started Jul 23 06:53:00 PM PDT 24
Finished Jul 23 06:56:53 PM PDT 24
Peak memory 208504 kb
Host smart-28e711ef-797a-4b42-98f3-be7dfc1b13ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190187893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4190187893
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.7244601
Short name T738
Test name
Test status
Simulation time 8586437628 ps
CPU time 9.95 seconds
Started Jul 23 06:53:04 PM PDT 24
Finished Jul 23 06:53:15 PM PDT 24
Peak memory 199680 kb
Host smart-3e179a6c-3583-4536-a74e-3bdb4ecf5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7244601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.7244601
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.832194024
Short name T689
Test name
Test status
Simulation time 43964037903 ps
CPU time 15.21 seconds
Started Jul 23 06:52:53 PM PDT 24
Finished Jul 23 06:53:09 PM PDT 24
Peak memory 200248 kb
Host smart-b1c0a8b5-0b82-4ed7-87d9-6eb139648d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832194024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.832194024
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1687237494
Short name T654
Test name
Test status
Simulation time 38449665 ps
CPU time 0.6 seconds
Started Jul 23 06:53:08 PM PDT 24
Finished Jul 23 06:53:09 PM PDT 24
Peak memory 195936 kb
Host smart-80b71bfe-8dda-4064-bcdd-8ee9f5f2c5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687237494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1687237494
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.86782394
Short name T288
Test name
Test status
Simulation time 193729597163 ps
CPU time 16.48 seconds
Started Jul 23 06:53:04 PM PDT 24
Finished Jul 23 06:53:21 PM PDT 24
Peak memory 200108 kb
Host smart-f4b5eb3a-d3bd-45a8-975c-6751bd8ab751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86782394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.86782394
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.390237479
Short name T1093
Test name
Test status
Simulation time 36666364716 ps
CPU time 30.94 seconds
Started Jul 23 06:53:03 PM PDT 24
Finished Jul 23 06:53:35 PM PDT 24
Peak memory 200264 kb
Host smart-533afe01-b7cf-4bcd-9c82-809bc60a5f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390237479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.390237479
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3344252915
Short name T222
Test name
Test status
Simulation time 125327938579 ps
CPU time 25.37 seconds
Started Jul 23 06:53:00 PM PDT 24
Finished Jul 23 06:53:26 PM PDT 24
Peak memory 200244 kb
Host smart-8f645fc5-7344-426e-a405-e5b7e969b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344252915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3344252915
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1335848420
Short name T718
Test name
Test status
Simulation time 48519529230 ps
CPU time 22.85 seconds
Started Jul 23 06:52:58 PM PDT 24
Finished Jul 23 06:53:22 PM PDT 24
Peak memory 200000 kb
Host smart-e78608e4-34ad-4c8b-9c4b-49163ee95c6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335848420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1335848420
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3900200876
Short name T439
Test name
Test status
Simulation time 86290907373 ps
CPU time 519.85 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 07:01:47 PM PDT 24
Peak memory 200228 kb
Host smart-f17cfa07-ecf0-4cf1-a185-66aefff9bff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900200876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3900200876
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1797338208
Short name T1010
Test name
Test status
Simulation time 11141615106 ps
CPU time 4.76 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 06:53:12 PM PDT 24
Peak memory 199768 kb
Host smart-2b07534a-dfd3-4a77-a9d8-7e5f1e7afa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797338208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1797338208
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1874404600
Short name T881
Test name
Test status
Simulation time 67172527260 ps
CPU time 52.32 seconds
Started Jul 23 06:53:00 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 216128 kb
Host smart-ee283d1c-a094-4be8-8018-a9be92e269f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874404600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1874404600
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1435373409
Short name T828
Test name
Test status
Simulation time 16515259167 ps
CPU time 568.81 seconds
Started Jul 23 06:53:05 PM PDT 24
Finished Jul 23 07:02:35 PM PDT 24
Peak memory 200200 kb
Host smart-55a3029b-7083-4295-8392-a5e0605edc56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435373409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1435373409
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3449414405
Short name T41
Test name
Test status
Simulation time 6867476062 ps
CPU time 67.59 seconds
Started Jul 23 06:52:59 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 198596 kb
Host smart-b1040ede-ddac-4eaa-94a4-99b4af56d035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449414405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3449414405
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3242332573
Short name T178
Test name
Test status
Simulation time 16967381611 ps
CPU time 10.52 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 06:53:18 PM PDT 24
Peak memory 200260 kb
Host smart-5214604e-eae8-45e4-9e46-3a338b25a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242332573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3242332573
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1689834463
Short name T612
Test name
Test status
Simulation time 29115079887 ps
CPU time 11.94 seconds
Started Jul 23 06:53:05 PM PDT 24
Finished Jul 23 06:53:18 PM PDT 24
Peak memory 196240 kb
Host smart-5d6b7e6e-70cb-46e3-8f3a-e1773e5eeab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689834463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1689834463
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.605262692
Short name T623
Test name
Test status
Simulation time 147896881 ps
CPU time 0.8 seconds
Started Jul 23 06:53:00 PM PDT 24
Finished Jul 23 06:53:02 PM PDT 24
Peak memory 197528 kb
Host smart-be5ac50f-7496-4c71-837b-3cfc08ba2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605262692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.605262692
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2563659156
Short name T630
Test name
Test status
Simulation time 542993015786 ps
CPU time 994 seconds
Started Jul 23 06:53:07 PM PDT 24
Finished Jul 23 07:09:42 PM PDT 24
Peak memory 208568 kb
Host smart-5d31186b-a182-4605-a7a4-c75e90ca333a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563659156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2563659156
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.790504576
Short name T358
Test name
Test status
Simulation time 19521209658 ps
CPU time 272.98 seconds
Started Jul 23 06:53:05 PM PDT 24
Finished Jul 23 06:57:39 PM PDT 24
Peak memory 216236 kb
Host smart-cd5b737b-e1f6-47d5-9d1e-305e129ce398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790504576 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.790504576
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1364398008
Short name T725
Test name
Test status
Simulation time 849605021 ps
CPU time 2.11 seconds
Started Jul 23 06:53:07 PM PDT 24
Finished Jul 23 06:53:10 PM PDT 24
Peak memory 199156 kb
Host smart-d154364d-bede-49f3-9a87-7f7062fa63ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364398008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1364398008
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2976528839
Short name T1115
Test name
Test status
Simulation time 4364300611 ps
CPU time 5.21 seconds
Started Jul 23 06:53:01 PM PDT 24
Finished Jul 23 06:53:07 PM PDT 24
Peak memory 198048 kb
Host smart-f7e2a849-afd2-4555-9425-a33e5a164cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976528839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2976528839
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2310912853
Short name T377
Test name
Test status
Simulation time 12582282 ps
CPU time 0.59 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:09 PM PDT 24
Peak memory 195560 kb
Host smart-dbb34d17-69e5-4456-b3b4-942a317bf355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310912853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2310912853
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.846787374
Short name T316
Test name
Test status
Simulation time 116062156733 ps
CPU time 156.97 seconds
Started Jul 23 06:51:04 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 200244 kb
Host smart-805af62d-f7a4-4d39-8c60-ec8c495b5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846787374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.846787374
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1780134650
Short name T1048
Test name
Test status
Simulation time 50413630227 ps
CPU time 57.38 seconds
Started Jul 23 06:51:03 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 200000 kb
Host smart-f4548682-2048-4d4d-b958-e63812646486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780134650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1780134650
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3399991779
Short name T671
Test name
Test status
Simulation time 127596415880 ps
CPU time 143.02 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:53:27 PM PDT 24
Peak memory 200244 kb
Host smart-abcc7395-0b1d-4038-804d-f20d8b98ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399991779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3399991779
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3003134062
Short name T344
Test name
Test status
Simulation time 69412178284 ps
CPU time 47.49 seconds
Started Jul 23 06:50:58 PM PDT 24
Finished Jul 23 06:51:50 PM PDT 24
Peak memory 200220 kb
Host smart-856cfd3b-b1e0-4279-9101-d5fbb9e2a749
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003134062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3003134062
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1127141533
Short name T519
Test name
Test status
Simulation time 68554931382 ps
CPU time 558.97 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 07:00:48 PM PDT 24
Peak memory 200176 kb
Host smart-2e449470-e7d2-48af-8cf5-d3775422fb42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127141533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1127141533
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3265606355
Short name T389
Test name
Test status
Simulation time 9231599749 ps
CPU time 9.84 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:17 PM PDT 24
Peak memory 198932 kb
Host smart-1c1e00f1-2343-4d20-96f0-135bf63bfdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265606355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3265606355
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.217782092
Short name T372
Test name
Test status
Simulation time 175498956111 ps
CPU time 57.78 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:52:09 PM PDT 24
Peak memory 208536 kb
Host smart-e795c664-8942-4bd7-a84f-b2d77d3fa877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217782092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.217782092
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.807773550
Short name T446
Test name
Test status
Simulation time 12786449179 ps
CPU time 375.07 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:57:30 PM PDT 24
Peak memory 200160 kb
Host smart-9db2acb1-cd2e-45ac-b421-2586f08eac98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807773550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.807773550
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4034424736
Short name T829
Test name
Test status
Simulation time 3488813047 ps
CPU time 28.89 seconds
Started Jul 23 06:51:00 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 198364 kb
Host smart-e3bacbf1-4525-4ffc-bb92-c3622bf5a7df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034424736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4034424736
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4187472244
Short name T11
Test name
Test status
Simulation time 17921480389 ps
CPU time 29.19 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:37 PM PDT 24
Peak memory 199840 kb
Host smart-207cf481-d20f-4162-ad3c-34caaf9876a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187472244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4187472244
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3246102458
Short name T706
Test name
Test status
Simulation time 4869400546 ps
CPU time 2.4 seconds
Started Jul 23 06:51:01 PM PDT 24
Finished Jul 23 06:51:06 PM PDT 24
Peak memory 196328 kb
Host smart-a5f58ddd-be07-4f2d-9142-7527a22077e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246102458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3246102458
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2351100823
Short name T108
Test name
Test status
Simulation time 52869984 ps
CPU time 0.79 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 218460 kb
Host smart-c9b86850-02dd-4ec5-872c-44ebcbab464d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351100823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2351100823
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4112034780
Short name T294
Test name
Test status
Simulation time 286612482 ps
CPU time 1.01 seconds
Started Jul 23 06:50:59 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 198540 kb
Host smart-f843850a-eaf8-4265-8ccb-0a7547cd050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112034780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4112034780
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3243386881
Short name T336
Test name
Test status
Simulation time 306005884995 ps
CPU time 901.72 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 07:06:11 PM PDT 24
Peak memory 200252 kb
Host smart-24da425e-aae9-415f-896a-961cf99c16da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243386881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3243386881
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3906170000
Short name T924
Test name
Test status
Simulation time 19122176572 ps
CPU time 210.15 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:54:41 PM PDT 24
Peak memory 208600 kb
Host smart-856e7632-2441-4524-88e0-13bc6f6c45b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906170000 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3906170000
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2979303912
Short name T1054
Test name
Test status
Simulation time 1246321051 ps
CPU time 1.4 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:10 PM PDT 24
Peak memory 200148 kb
Host smart-b73345d3-c985-4cfd-a6bd-ff948bebcadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979303912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2979303912
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3764710506
Short name T284
Test name
Test status
Simulation time 110810893748 ps
CPU time 52.22 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 200244 kb
Host smart-f56ea937-5bbe-4714-9a5f-a4b15e1db15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764710506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3764710506
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3291498000
Short name T393
Test name
Test status
Simulation time 18765781 ps
CPU time 0.52 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:53:15 PM PDT 24
Peak memory 195648 kb
Host smart-418a10fc-ac8a-4d83-98f6-2b091b47b090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291498000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3291498000
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3417983064
Short name T691
Test name
Test status
Simulation time 52174586295 ps
CPU time 84.68 seconds
Started Jul 23 06:53:05 PM PDT 24
Finished Jul 23 06:54:30 PM PDT 24
Peak memory 200172 kb
Host smart-a5b54a59-f793-435e-a406-0617444833ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417983064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3417983064
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.980148836
Short name T1119
Test name
Test status
Simulation time 102973729418 ps
CPU time 45.49 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 06:53:52 PM PDT 24
Peak memory 200184 kb
Host smart-56339fae-b601-4ca2-ba8d-75a4de09e9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980148836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.980148836
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2558073917
Short name T522
Test name
Test status
Simulation time 54561997281 ps
CPU time 50.75 seconds
Started Jul 23 06:53:04 PM PDT 24
Finished Jul 23 06:53:55 PM PDT 24
Peak memory 200256 kb
Host smart-2798474a-62e2-4019-9720-8401cbbdc3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558073917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2558073917
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.4084745693
Short name T450
Test name
Test status
Simulation time 14413235347 ps
CPU time 20.54 seconds
Started Jul 23 06:53:07 PM PDT 24
Finished Jul 23 06:53:29 PM PDT 24
Peak memory 200188 kb
Host smart-e85237fb-e2c4-4a5e-8287-db0332e5d703
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084745693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4084745693
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1225455924
Short name T1088
Test name
Test status
Simulation time 80927384934 ps
CPU time 258.09 seconds
Started Jul 23 06:53:12 PM PDT 24
Finished Jul 23 06:57:31 PM PDT 24
Peak memory 200176 kb
Host smart-7a82f664-978e-4acc-b552-5e3c6f332696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225455924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1225455924
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.189835914
Short name T388
Test name
Test status
Simulation time 3616667074 ps
CPU time 1.65 seconds
Started Jul 23 06:53:15 PM PDT 24
Finished Jul 23 06:53:18 PM PDT 24
Peak memory 199500 kb
Host smart-0b909846-79f3-4d4b-8555-87b30aabe7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189835914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.189835914
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1197028306
Short name T111
Test name
Test status
Simulation time 22914044683 ps
CPU time 37.46 seconds
Started Jul 23 06:53:07 PM PDT 24
Finished Jul 23 06:53:45 PM PDT 24
Peak memory 200352 kb
Host smart-18840a87-f820-4647-b785-9ce276109060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197028306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1197028306
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1908945655
Short name T1003
Test name
Test status
Simulation time 15612842671 ps
CPU time 380.82 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:59:36 PM PDT 24
Peak memory 200172 kb
Host smart-e5c93487-1eae-4beb-a763-4f469cc5e9f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908945655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1908945655
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2791689614
Short name T617
Test name
Test status
Simulation time 6954613889 ps
CPU time 61.3 seconds
Started Jul 23 06:53:08 PM PDT 24
Finished Jul 23 06:54:10 PM PDT 24
Peak memory 199356 kb
Host smart-c99c551e-1a54-44f1-a43f-b6d58d58fc01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791689614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2791689614
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2281031173
Short name T1074
Test name
Test status
Simulation time 135764645034 ps
CPU time 269.83 seconds
Started Jul 23 06:53:08 PM PDT 24
Finished Jul 23 06:57:39 PM PDT 24
Peak memory 200268 kb
Host smart-8ffc586b-f436-4953-b0d3-b7b192e28c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281031173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2281031173
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.185003877
Short name T340
Test name
Test status
Simulation time 25550766123 ps
CPU time 41.6 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 196372 kb
Host smart-151771e8-122c-49fd-97f8-2b0d0dc0b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185003877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.185003877
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.484824154
Short name T1044
Test name
Test status
Simulation time 670412895 ps
CPU time 2.22 seconds
Started Jul 23 06:53:07 PM PDT 24
Finished Jul 23 06:53:10 PM PDT 24
Peak memory 200092 kb
Host smart-d735ec00-136d-45fe-8ff3-ed8e42381f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484824154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.484824154
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.4201418585
Short name T1073
Test name
Test status
Simulation time 42427307662 ps
CPU time 61.74 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:54:16 PM PDT 24
Peak memory 200212 kb
Host smart-3cbb684d-0df8-44ef-8f93-f5fe8899ace0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201418585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4201418585
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1756866224
Short name T57
Test name
Test status
Simulation time 20512736773 ps
CPU time 428.83 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 07:00:23 PM PDT 24
Peak memory 216904 kb
Host smart-1305bcc6-5069-4eb3-9911-f010af722677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756866224 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1756866224
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2337886578
Short name T775
Test name
Test status
Simulation time 7258164657 ps
CPU time 17.4 seconds
Started Jul 23 06:53:05 PM PDT 24
Finished Jul 23 06:53:23 PM PDT 24
Peak memory 200220 kb
Host smart-721c2af4-6080-4e49-8d52-6050d5ea440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337886578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2337886578
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.830326711
Short name T865
Test name
Test status
Simulation time 38175774094 ps
CPU time 17.21 seconds
Started Jul 23 06:53:06 PM PDT 24
Finished Jul 23 06:53:24 PM PDT 24
Peak memory 200236 kb
Host smart-471e9456-561c-4555-97c3-5c8a4a3935b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830326711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.830326711
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2326260432
Short name T785
Test name
Test status
Simulation time 26514157 ps
CPU time 0.54 seconds
Started Jul 23 06:53:15 PM PDT 24
Finished Jul 23 06:53:16 PM PDT 24
Peak memory 195628 kb
Host smart-008e7b19-ac8a-4a6b-9c6d-2eb9f80c6d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326260432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2326260432
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3159170894
Short name T476
Test name
Test status
Simulation time 40672483310 ps
CPU time 16.7 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:53:32 PM PDT 24
Peak memory 200260 kb
Host smart-f381687a-b57a-4a93-a4d0-e0f66071b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159170894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3159170894
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2467439316
Short name T736
Test name
Test status
Simulation time 20583116050 ps
CPU time 21.32 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:53:36 PM PDT 24
Peak memory 200184 kb
Host smart-c8787c1c-688d-4587-8fea-48bb0a6b3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467439316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2467439316
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3736441518
Short name T700
Test name
Test status
Simulation time 41669103995 ps
CPU time 57.13 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:54:14 PM PDT 24
Peak memory 200236 kb
Host smart-88e54755-6f1f-4723-8ae2-0c997cc0304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736441518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3736441518
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.789977556
Short name T808
Test name
Test status
Simulation time 7949416765 ps
CPU time 4.55 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 200180 kb
Host smart-d2898e0d-4c69-4515-aa15-8713765f080b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789977556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.789977556
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2841095888
Short name T987
Test name
Test status
Simulation time 68888149117 ps
CPU time 365.73 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:59:23 PM PDT 24
Peak memory 200244 kb
Host smart-4758d2db-cdfc-40e3-b10e-4a4bd316db0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841095888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2841095888
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3153803054
Short name T1008
Test name
Test status
Simulation time 11024300014 ps
CPU time 20.81 seconds
Started Jul 23 06:53:15 PM PDT 24
Finished Jul 23 06:53:37 PM PDT 24
Peak memory 200032 kb
Host smart-475ea59f-6856-42c7-bdfb-042db5882708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153803054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3153803054
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.437112819
Short name T1118
Test name
Test status
Simulation time 42259238635 ps
CPU time 146.96 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:55:44 PM PDT 24
Peak memory 199516 kb
Host smart-e55fe9f9-7dbe-4223-8731-5a36aeb2cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437112819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.437112819
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3784161393
Short name T469
Test name
Test status
Simulation time 12783421368 ps
CPU time 174 seconds
Started Jul 23 06:53:15 PM PDT 24
Finished Jul 23 06:56:10 PM PDT 24
Peak memory 200272 kb
Host smart-73c11f0a-e10e-4103-8e64-54b105b56bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784161393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3784161393
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2481191022
Short name T556
Test name
Test status
Simulation time 2580087428 ps
CPU time 14.64 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:53:30 PM PDT 24
Peak memory 199380 kb
Host smart-18468a4d-7fc9-42d2-b494-a53952aa562c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481191022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2481191022
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1033132847
Short name T627
Test name
Test status
Simulation time 170337226032 ps
CPU time 130.18 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:55:25 PM PDT 24
Peak memory 200240 kb
Host smart-f2b6f33f-8e0d-43b6-bf55-71a30b76e93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033132847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1033132847
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2492528165
Short name T1097
Test name
Test status
Simulation time 42922353291 ps
CPU time 33.32 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:53:47 PM PDT 24
Peak memory 196392 kb
Host smart-9b009fe6-ef44-4028-8316-1190df610231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492528165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2492528165
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2185711067
Short name T454
Test name
Test status
Simulation time 730749229 ps
CPU time 1.22 seconds
Started Jul 23 06:53:17 PM PDT 24
Finished Jul 23 06:53:19 PM PDT 24
Peak memory 198684 kb
Host smart-ce1dbd20-bf56-45e3-bb5f-25a717bb814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185711067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2185711067
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1203313717
Short name T825
Test name
Test status
Simulation time 236925106829 ps
CPU time 934.13 seconds
Started Jul 23 06:53:12 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 200148 kb
Host smart-30a9a309-a78d-42fc-b6df-c25f60ab9253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203313717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1203313717
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2144359274
Short name T62
Test name
Test status
Simulation time 501180980934 ps
CPU time 2322.59 seconds
Started Jul 23 06:53:12 PM PDT 24
Finished Jul 23 07:31:56 PM PDT 24
Peak memory 241548 kb
Host smart-d388e96f-9f3e-4a08-9ce0-60021625448c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144359274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2144359274
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1262900439
Short name T561
Test name
Test status
Simulation time 1372337069 ps
CPU time 3.5 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 199180 kb
Host smart-16185828-04ba-4c0d-8523-ef91776c8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262900439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1262900439
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1450889684
Short name T305
Test name
Test status
Simulation time 123556267802 ps
CPU time 44.44 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:54:00 PM PDT 24
Peak memory 200176 kb
Host smart-1889a5f8-e7c6-41d4-b89d-f5fe06c96a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450889684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1450889684
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4267542676
Short name T386
Test name
Test status
Simulation time 18677070 ps
CPU time 0.55 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:22 PM PDT 24
Peak memory 195616 kb
Host smart-d6a45241-1305-444b-92d3-813d755e3991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267542676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4267542676
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1828244056
Short name T1105
Test name
Test status
Simulation time 145508041715 ps
CPU time 127.84 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:55:23 PM PDT 24
Peak memory 200184 kb
Host smart-c1c26b1e-91cd-41b9-8245-ed2013fbdc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828244056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1828244056
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.75082720
Short name T1087
Test name
Test status
Simulation time 12266892628 ps
CPU time 9.23 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:53:24 PM PDT 24
Peak memory 200196 kb
Host smart-362a447e-1ff3-4a7b-8d06-08117158f3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75082720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.75082720
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.87836585
Short name T116
Test name
Test status
Simulation time 122483075644 ps
CPU time 165.8 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:56:01 PM PDT 24
Peak memory 199808 kb
Host smart-d554d7ab-bff9-4da2-826d-14c44f17818e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87836585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.87836585
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2481568151
Short name T910
Test name
Test status
Simulation time 53465309121 ps
CPU time 488.64 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 07:01:29 PM PDT 24
Peak memory 200228 kb
Host smart-7d869e45-9011-4c51-a547-a0b5f263c4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481568151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2481568151
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3769493676
Short name T1122
Test name
Test status
Simulation time 6893100880 ps
CPU time 12.13 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:34 PM PDT 24
Peak memory 199720 kb
Host smart-12292374-9967-4a86-885b-433bf7e13ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769493676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3769493676
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2360406079
Short name T704
Test name
Test status
Simulation time 38514998186 ps
CPU time 60.11 seconds
Started Jul 23 06:53:12 PM PDT 24
Finished Jul 23 06:54:13 PM PDT 24
Peak memory 199996 kb
Host smart-3d090a25-5ac8-4f64-8c49-9c61abdfa55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360406079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2360406079
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.584683989
Short name T804
Test name
Test status
Simulation time 8370886954 ps
CPU time 274.57 seconds
Started Jul 23 06:53:22 PM PDT 24
Finished Jul 23 06:57:57 PM PDT 24
Peak memory 200248 kb
Host smart-eb78c380-d379-4b8d-9d07-64a6b8dd38ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584683989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.584683989
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1969650344
Short name T39
Test name
Test status
Simulation time 5605604985 ps
CPU time 43.85 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 198208 kb
Host smart-b70d10f7-cdbe-4194-b97b-e799c656a6da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969650344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1969650344
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3067301462
Short name T745
Test name
Test status
Simulation time 87726572498 ps
CPU time 68.04 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:54:25 PM PDT 24
Peak memory 200104 kb
Host smart-72cbc703-aa02-463c-b6ae-4f73962829fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067301462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3067301462
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1453752233
Short name T667
Test name
Test status
Simulation time 4317758632 ps
CPU time 6.94 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:53:22 PM PDT 24
Peak memory 196556 kb
Host smart-40ad5bb7-0041-4666-bf08-752f3f4824bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453752233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1453752233
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.812343466
Short name T517
Test name
Test status
Simulation time 959500344 ps
CPU time 1.82 seconds
Started Jul 23 06:53:13 PM PDT 24
Finished Jul 23 06:53:15 PM PDT 24
Peak memory 199032 kb
Host smart-27221174-6156-4881-87e3-36621dfac9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812343466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.812343466
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1488329180
Short name T603
Test name
Test status
Simulation time 372847686204 ps
CPU time 148.92 seconds
Started Jul 23 06:53:22 PM PDT 24
Finished Jul 23 06:55:52 PM PDT 24
Peak memory 200168 kb
Host smart-1b60bc86-53ff-45fc-aa12-c91e081b3125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488329180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1488329180
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2384422395
Short name T1091
Test name
Test status
Simulation time 110801266794 ps
CPU time 988.99 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 224972 kb
Host smart-9ebde5a6-a3db-4bf0-80a5-243edbf11120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384422395 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2384422395
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.358435015
Short name T883
Test name
Test status
Simulation time 2478839943 ps
CPU time 2.14 seconds
Started Jul 23 06:53:16 PM PDT 24
Finished Jul 23 06:53:19 PM PDT 24
Peak memory 198664 kb
Host smart-307cf361-4210-4548-a11f-942feeea0b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358435015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.358435015
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.414200425
Short name T471
Test name
Test status
Simulation time 178077280853 ps
CPU time 73.18 seconds
Started Jul 23 06:53:14 PM PDT 24
Finished Jul 23 06:54:28 PM PDT 24
Peak memory 200144 kb
Host smart-f5f69297-62bc-4843-bdad-76d4bec84fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414200425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.414200425
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3474288711
Short name T1096
Test name
Test status
Simulation time 50816705 ps
CPU time 0.56 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 06:53:20 PM PDT 24
Peak memory 195932 kb
Host smart-d937831a-4b62-4e62-b70f-63fc215d8cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474288711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3474288711
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.367433622
Short name T185
Test name
Test status
Simulation time 54132566133 ps
CPU time 8.34 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 06:53:28 PM PDT 24
Peak memory 200260 kb
Host smart-f6fa4797-39cf-4302-bac9-cce52b53ff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367433622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.367433622
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2034384410
Short name T608
Test name
Test status
Simulation time 22282191668 ps
CPU time 16.99 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:39 PM PDT 24
Peak memory 199876 kb
Host smart-b04f3e15-5254-454e-9561-fcba7fdc3c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034384410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2034384410
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3810088149
Short name T779
Test name
Test status
Simulation time 7262161377 ps
CPU time 19.13 seconds
Started Jul 23 06:53:21 PM PDT 24
Finished Jul 23 06:53:42 PM PDT 24
Peak memory 200168 kb
Host smart-a1f4d0a8-f978-4786-a41e-2fabd648fdca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810088149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3810088149
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1965762978
Short name T985
Test name
Test status
Simulation time 283335460638 ps
CPU time 339.8 seconds
Started Jul 23 06:53:18 PM PDT 24
Finished Jul 23 06:58:59 PM PDT 24
Peak memory 200212 kb
Host smart-466a719b-3152-4297-939f-dea63571694c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965762978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1965762978
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1175989904
Short name T18
Test name
Test status
Simulation time 5896890925 ps
CPU time 3.36 seconds
Started Jul 23 06:53:22 PM PDT 24
Finished Jul 23 06:53:26 PM PDT 24
Peak memory 199044 kb
Host smart-16b74d03-bd27-4fb0-a1e2-d9014e38b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175989904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1175989904
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.96089808
Short name T275
Test name
Test status
Simulation time 21360430741 ps
CPU time 41.64 seconds
Started Jul 23 06:53:18 PM PDT 24
Finished Jul 23 06:54:00 PM PDT 24
Peak memory 199896 kb
Host smart-a067616c-d421-45a6-9197-14dfb6ece753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96089808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.96089808
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.803152245
Short name T313
Test name
Test status
Simulation time 19565997874 ps
CPU time 272.68 seconds
Started Jul 23 06:53:18 PM PDT 24
Finished Jul 23 06:57:52 PM PDT 24
Peak memory 200048 kb
Host smart-c39d67d1-1a73-450d-941d-47b9199128eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803152245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.803152245
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4292702763
Short name T518
Test name
Test status
Simulation time 4419888278 ps
CPU time 20.93 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:43 PM PDT 24
Peak memory 199532 kb
Host smart-de77c548-b0d9-469b-a750-e4a7c5bc3b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292702763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4292702763
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2753256875
Short name T611
Test name
Test status
Simulation time 18702775553 ps
CPU time 26.3 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:48 PM PDT 24
Peak memory 200236 kb
Host smart-ce8c997e-7470-4d5d-9de0-8e3eb448186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753256875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2753256875
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2638576802
Short name T899
Test name
Test status
Simulation time 4400911404 ps
CPU time 2.17 seconds
Started Jul 23 06:53:26 PM PDT 24
Finished Jul 23 06:53:29 PM PDT 24
Peak memory 196500 kb
Host smart-f622d3c6-b34f-43d4-b81f-54cfd428f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638576802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2638576802
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1842240836
Short name T321
Test name
Test status
Simulation time 6072581007 ps
CPU time 30.01 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:52 PM PDT 24
Peak memory 200216 kb
Host smart-43647d8d-628f-47c1-8e41-20e04d240cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842240836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1842240836
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2488441048
Short name T14
Test name
Test status
Simulation time 104637445467 ps
CPU time 46.66 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 200240 kb
Host smart-f984aae9-d46a-4bdf-aab9-9e7d3b9581ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488441048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2488441048
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1421017848
Short name T74
Test name
Test status
Simulation time 219751919687 ps
CPU time 619.18 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 07:03:39 PM PDT 24
Peak memory 225128 kb
Host smart-96af655a-c68a-4775-b2cd-1a7148938024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421017848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1421017848
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2737650383
Short name T333
Test name
Test status
Simulation time 690473893 ps
CPU time 1.39 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 06:53:22 PM PDT 24
Peak memory 199384 kb
Host smart-310f31a1-3a6d-4c4c-814b-2fffa8018fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737650383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2737650383
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2595522615
Short name T425
Test name
Test status
Simulation time 40825000021 ps
CPU time 62.03 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:54:24 PM PDT 24
Peak memory 200188 kb
Host smart-55b9dca4-b89c-4b52-ae71-9264b38f5529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595522615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2595522615
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2379785747
Short name T822
Test name
Test status
Simulation time 18639390 ps
CPU time 0.57 seconds
Started Jul 23 06:53:33 PM PDT 24
Finished Jul 23 06:53:35 PM PDT 24
Peak memory 195628 kb
Host smart-c00e92b6-8cc3-4669-8beb-e7db874efa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379785747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2379785747
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3534621565
Short name T1171
Test name
Test status
Simulation time 78081180323 ps
CPU time 61.79 seconds
Started Jul 23 06:53:21 PM PDT 24
Finished Jul 23 06:54:24 PM PDT 24
Peak memory 200196 kb
Host smart-dd8c843a-65df-4851-aa50-badb75feaee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534621565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3534621565
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1719603918
Short name T609
Test name
Test status
Simulation time 76080964889 ps
CPU time 29.06 seconds
Started Jul 23 06:53:26 PM PDT 24
Finished Jul 23 06:53:55 PM PDT 24
Peak memory 200116 kb
Host smart-7d329a29-700c-4088-8f3f-7f9d2123ae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719603918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1719603918
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1752630931
Short name T438
Test name
Test status
Simulation time 27124913442 ps
CPU time 10.23 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:53:31 PM PDT 24
Peak memory 200256 kb
Host smart-82a9a340-671c-467f-9233-9c40d3978199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752630931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1752630931
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2763717607
Short name T1072
Test name
Test status
Simulation time 44976689537 ps
CPU time 39.16 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 200212 kb
Host smart-50877fb0-682f-4967-84d5-9c911292dbfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763717607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2763717607
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3667247524
Short name T1166
Test name
Test status
Simulation time 104203523500 ps
CPU time 190.99 seconds
Started Jul 23 06:53:31 PM PDT 24
Finished Jul 23 06:56:43 PM PDT 24
Peak memory 200244 kb
Host smart-d8b1e0e7-fdda-4c96-9141-3d21f9122ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667247524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3667247524
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1895884011
Short name T380
Test name
Test status
Simulation time 6726975847 ps
CPU time 6.47 seconds
Started Jul 23 06:53:33 PM PDT 24
Finished Jul 23 06:53:40 PM PDT 24
Peak memory 199160 kb
Host smart-f8ffd0a8-2244-4589-80c7-caec87c44414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895884011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1895884011
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4183881278
Short name T754
Test name
Test status
Simulation time 67932426046 ps
CPU time 23.94 seconds
Started Jul 23 06:53:21 PM PDT 24
Finished Jul 23 06:53:46 PM PDT 24
Peak memory 198488 kb
Host smart-d2943001-9b6c-4416-886e-ebf6a085be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183881278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4183881278
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1005901697
Short name T1113
Test name
Test status
Simulation time 13487625144 ps
CPU time 66.96 seconds
Started Jul 23 06:53:33 PM PDT 24
Finished Jul 23 06:54:41 PM PDT 24
Peak memory 200160 kb
Host smart-53e31a3e-149e-4a25-a431-1f324084ee2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005901697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1005901697
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4179241839
Short name T547
Test name
Test status
Simulation time 5632251590 ps
CPU time 42.64 seconds
Started Jul 23 06:53:22 PM PDT 24
Finished Jul 23 06:54:05 PM PDT 24
Peak memory 199692 kb
Host smart-700aa310-ea38-4269-8bae-ff8a9950872c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179241839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4179241839
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1883329210
Short name T1137
Test name
Test status
Simulation time 170053398017 ps
CPU time 56.82 seconds
Started Jul 23 06:53:26 PM PDT 24
Finished Jul 23 06:54:23 PM PDT 24
Peak memory 199568 kb
Host smart-ca21e751-85f7-44ad-806e-35daae7ae526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883329210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1883329210
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4090417512
Short name T334
Test name
Test status
Simulation time 78570046831 ps
CPU time 62.52 seconds
Started Jul 23 06:53:19 PM PDT 24
Finished Jul 23 06:54:23 PM PDT 24
Peak memory 196064 kb
Host smart-1229838c-3ecd-4092-aca9-9efdc3c3a0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090417512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4090417512
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1488577565
Short name T649
Test name
Test status
Simulation time 5727956303 ps
CPU time 7.54 seconds
Started Jul 23 06:53:18 PM PDT 24
Finished Jul 23 06:53:27 PM PDT 24
Peak memory 199896 kb
Host smart-7344b7fe-210f-48fa-821d-6e27c0dc725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488577565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1488577565
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2661708823
Short name T1174
Test name
Test status
Simulation time 160526152360 ps
CPU time 34.58 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 200244 kb
Host smart-e771f958-1479-4623-8260-5bddec6ef9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661708823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2661708823
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4118802771
Short name T1055
Test name
Test status
Simulation time 229367603583 ps
CPU time 863.66 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 07:07:57 PM PDT 24
Peak memory 225028 kb
Host smart-b10883bc-3ed3-48e0-8eb9-708170cab454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118802771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4118802771
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4202188952
Short name T412
Test name
Test status
Simulation time 622797276 ps
CPU time 3.76 seconds
Started Jul 23 06:53:21 PM PDT 24
Finished Jul 23 06:53:26 PM PDT 24
Peak memory 200016 kb
Host smart-0348c884-e6d6-495e-9f2a-73a3f358da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202188952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4202188952
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4156212084
Short name T655
Test name
Test status
Simulation time 45355881106 ps
CPU time 68.92 seconds
Started Jul 23 06:53:20 PM PDT 24
Finished Jul 23 06:54:30 PM PDT 24
Peak memory 200256 kb
Host smart-755dabbe-753f-40ce-b7c5-79569a0caa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156212084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4156212084
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2067157096
Short name T964
Test name
Test status
Simulation time 29687769 ps
CPU time 0.56 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:53:43 PM PDT 24
Peak memory 195628 kb
Host smart-e80b35c4-c887-4623-b7ca-bc658a39d616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067157096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2067157096
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3031050076
Short name T1065
Test name
Test status
Simulation time 141816353567 ps
CPU time 280.2 seconds
Started Jul 23 06:53:33 PM PDT 24
Finished Jul 23 06:58:14 PM PDT 24
Peak memory 200168 kb
Host smart-dc9f397e-2eef-4023-add5-5024c83e7f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031050076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3031050076
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4154848985
Short name T586
Test name
Test status
Simulation time 61576468605 ps
CPU time 88.08 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:55:01 PM PDT 24
Peak memory 200112 kb
Host smart-0319f83a-daf5-49a0-a86c-c05d0a489aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154848985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4154848985
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.104520101
Short name T784
Test name
Test status
Simulation time 20133706618 ps
CPU time 17.06 seconds
Started Jul 23 06:53:33 PM PDT 24
Finished Jul 23 06:53:51 PM PDT 24
Peak memory 200248 kb
Host smart-483d26b9-6935-4a10-b4c4-776024b66346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104520101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.104520101
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.969077899
Short name T1079
Test name
Test status
Simulation time 20569558298 ps
CPU time 34.69 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 199788 kb
Host smart-d4c3e08b-afbb-47c6-8dcd-9bf4c976c07b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969077899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.969077899
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1653292275
Short name T276
Test name
Test status
Simulation time 108926542018 ps
CPU time 178.75 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:56:45 PM PDT 24
Peak memory 200244 kb
Host smart-a125b2a8-9e54-4bb0-9f35-1c767771b65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653292275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1653292275
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3878992703
Short name T898
Test name
Test status
Simulation time 3143917262 ps
CPU time 2.2 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:53:47 PM PDT 24
Peak memory 197228 kb
Host smart-55fff886-fba9-4ae9-b8a2-ff39988de1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878992703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3878992703
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4285712261
Short name T1019
Test name
Test status
Simulation time 134041787888 ps
CPU time 69.05 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:54:42 PM PDT 24
Peak memory 199836 kb
Host smart-c4172317-5243-4148-b481-c22c4756f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285712261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4285712261
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.409285760
Short name T317
Test name
Test status
Simulation time 11722354146 ps
CPU time 611 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 200256 kb
Host smart-11fd9aab-be21-43ab-8326-4f7a636a70ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409285760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.409285760
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2405571630
Short name T1101
Test name
Test status
Simulation time 6794341153 ps
CPU time 16.08 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:53:48 PM PDT 24
Peak memory 199136 kb
Host smart-d217d102-7a58-4bee-bcc8-b62687f6eedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405571630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2405571630
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2968387494
Short name T437
Test name
Test status
Simulation time 27162334193 ps
CPU time 41.8 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:54:15 PM PDT 24
Peak memory 200000 kb
Host smart-3f266ba2-b6af-42e8-b3f0-ed61e53de30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968387494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2968387494
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.203659624
Short name T75
Test name
Test status
Simulation time 1745725765 ps
CPU time 2.62 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:53:36 PM PDT 24
Peak memory 195728 kb
Host smart-4f24e517-7465-466d-bc13-d943cea2e0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203659624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.203659624
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.982637738
Short name T632
Test name
Test status
Simulation time 452839219 ps
CPU time 2.21 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:53:36 PM PDT 24
Peak memory 199168 kb
Host smart-75ce00ec-21b7-404e-a559-2b3c5797fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982637738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.982637738
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2810954399
Short name T16
Test name
Test status
Simulation time 81641829065 ps
CPU time 118.05 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:55:43 PM PDT 24
Peak memory 200228 kb
Host smart-27644eb5-33e7-4d1e-9f83-3371c20cbd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810954399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2810954399
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3723707436
Short name T293
Test name
Test status
Simulation time 38122870744 ps
CPU time 452.39 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 07:01:18 PM PDT 24
Peak memory 216792 kb
Host smart-c5cd7fec-8dcd-43f4-bb58-ecc6d5b1e463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723707436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3723707436
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.844978980
Short name T1033
Test name
Test status
Simulation time 6888590276 ps
CPU time 14.67 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:53:48 PM PDT 24
Peak memory 200028 kb
Host smart-2ed1463d-adb3-4f24-b8f1-b3e6fd5d8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844978980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.844978980
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.644178527
Short name T448
Test name
Test status
Simulation time 42547118210 ps
CPU time 68.8 seconds
Started Jul 23 06:53:32 PM PDT 24
Finished Jul 23 06:54:42 PM PDT 24
Peak memory 200164 kb
Host smart-8be6ee62-25f9-475c-8baa-ffe83e3468cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644178527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.644178527
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2067326856
Short name T579
Test name
Test status
Simulation time 17513184 ps
CPU time 0.55 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:53:46 PM PDT 24
Peak memory 195804 kb
Host smart-628ad9c6-6db7-4201-aab7-96fc08b1fc20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067326856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2067326856
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1723067277
Short name T457
Test name
Test status
Simulation time 141886872542 ps
CPU time 141.74 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:56:07 PM PDT 24
Peak memory 200172 kb
Host smart-6e27834a-5103-4ab5-a6c1-d55a2bc479b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723067277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1723067277
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.796366916
Short name T176
Test name
Test status
Simulation time 34224688526 ps
CPU time 23.58 seconds
Started Jul 23 06:53:41 PM PDT 24
Finished Jul 23 06:54:06 PM PDT 24
Peak memory 200244 kb
Host smart-ce81550b-0351-4f35-9c4d-619893677d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796366916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.796366916
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.2932433663
Short name T1080
Test name
Test status
Simulation time 11048033426 ps
CPU time 1.86 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:53:45 PM PDT 24
Peak memory 198028 kb
Host smart-59bea61f-3aad-43ec-8da4-81131052abff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932433663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2932433663
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_loopback.785523223
Short name T1061
Test name
Test status
Simulation time 1540184762 ps
CPU time 2.94 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 195724 kb
Host smart-18a55afa-b1b4-4ead-86b3-7e0b8a25c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785523223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.785523223
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1070480075
Short name T596
Test name
Test status
Simulation time 57314910239 ps
CPU time 110.63 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:55:36 PM PDT 24
Peak memory 200512 kb
Host smart-3711a743-35bd-42ce-a1ca-a43a012d05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070480075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1070480075
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1924563089
Short name T538
Test name
Test status
Simulation time 9683797188 ps
CPU time 130.61 seconds
Started Jul 23 06:53:41 PM PDT 24
Finished Jul 23 06:55:52 PM PDT 24
Peak memory 200168 kb
Host smart-2846eb8f-3cdc-4e65-b2bb-d66c90c87f78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924563089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1924563089
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.754343029
Short name T622
Test name
Test status
Simulation time 1314045522 ps
CPU time 1.02 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:53:45 PM PDT 24
Peak memory 197148 kb
Host smart-7b77ee83-4b16-48a1-aebb-da7b412322b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754343029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.754343029
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1827330469
Short name T955
Test name
Test status
Simulation time 74259256911 ps
CPU time 28.75 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:54:15 PM PDT 24
Peak memory 199996 kb
Host smart-005dc0a4-ab68-4ab3-b169-d11a722d4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827330469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1827330469
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3058933293
Short name T636
Test name
Test status
Simulation time 3509000191 ps
CPU time 5.4 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:53:51 PM PDT 24
Peak memory 196764 kb
Host smart-bfb8fc08-5c1c-41ac-bdb9-d0665b84a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058933293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3058933293
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2827581305
Short name T739
Test name
Test status
Simulation time 692956758 ps
CPU time 1.41 seconds
Started Jul 23 06:53:45 PM PDT 24
Finished Jul 23 06:53:48 PM PDT 24
Peak memory 199636 kb
Host smart-8da855c6-c8ba-4b23-9ea8-e3812c98908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827581305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2827581305
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3677656402
Short name T695
Test name
Test status
Simulation time 204117151260 ps
CPU time 2602.71 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 07:37:09 PM PDT 24
Peak memory 200244 kb
Host smart-81cd3149-5ec3-4447-81b3-c77f0942c6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677656402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3677656402
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1458854266
Short name T971
Test name
Test status
Simulation time 70517058404 ps
CPU time 1552.89 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 07:19:37 PM PDT 24
Peak memory 231060 kb
Host smart-91cdb5a4-2f4e-44b6-a4bb-6fd09baf9315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458854266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1458854266
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2141480012
Short name T905
Test name
Test status
Simulation time 8723084852 ps
CPU time 8.82 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:53:51 PM PDT 24
Peak memory 199636 kb
Host smart-c88257a8-673d-4acd-b89c-7ab75e0bb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141480012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2141480012
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2912648199
Short name T152
Test name
Test status
Simulation time 72157529847 ps
CPU time 29.59 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:54:13 PM PDT 24
Peak memory 200200 kb
Host smart-b3311e77-dfea-435d-a8c2-a572b89bae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912648199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2912648199
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3873307704
Short name T422
Test name
Test status
Simulation time 13319492 ps
CPU time 0.55 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:53:47 PM PDT 24
Peak memory 194496 kb
Host smart-756f786c-8292-4bdd-96d8-33120b477325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873307704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3873307704
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1799526253
Short name T552
Test name
Test status
Simulation time 9700047427 ps
CPU time 16.68 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:54:02 PM PDT 24
Peak memory 200256 kb
Host smart-34d8516e-4cc8-40f3-9452-f23e35a449e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799526253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1799526253
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1137446699
Short name T826
Test name
Test status
Simulation time 190924997610 ps
CPU time 17.9 seconds
Started Jul 23 06:53:40 PM PDT 24
Finished Jul 23 06:53:59 PM PDT 24
Peak memory 200192 kb
Host smart-580aeb94-dafa-4963-a56e-d8f4e6fa054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137446699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1137446699
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3601811188
Short name T262
Test name
Test status
Simulation time 363730347591 ps
CPU time 36.16 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:54:20 PM PDT 24
Peak memory 200260 kb
Host smart-dc1f437a-834d-4868-a346-3a6d954c0f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601811188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3601811188
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3512888812
Short name T473
Test name
Test status
Simulation time 39157591518 ps
CPU time 16.55 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 199424 kb
Host smart-a4b5b994-89c9-4cc6-b510-9b16087a945d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512888812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3512888812
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.363010751
Short name T846
Test name
Test status
Simulation time 64993682797 ps
CPU time 530.54 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 07:02:35 PM PDT 24
Peak memory 200228 kb
Host smart-b2873fe0-d53e-412c-84cc-0a18188225b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363010751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.363010751
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3379759146
Short name T375
Test name
Test status
Simulation time 3018754318 ps
CPU time 7.94 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 198892 kb
Host smart-2212d51b-8a15-42ab-89c9-948c120e5457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379759146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3379759146
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1038653966
Short name T355
Test name
Test status
Simulation time 4883367032 ps
CPU time 7.74 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:53:54 PM PDT 24
Peak memory 194824 kb
Host smart-2434c3fb-39e2-4597-b9d3-f86da8a6b747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038653966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1038653966
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4124709215
Short name T348
Test name
Test status
Simulation time 15889331415 ps
CPU time 329.79 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:59:16 PM PDT 24
Peak memory 200260 kb
Host smart-b85194b2-ebcf-4dd1-8183-7ece17261ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124709215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4124709215
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.974342422
Short name T107
Test name
Test status
Simulation time 2831014481 ps
CPU time 2.56 seconds
Started Jul 23 06:53:41 PM PDT 24
Finished Jul 23 06:53:45 PM PDT 24
Peak memory 199176 kb
Host smart-d560fda4-a70e-4c87-9c01-84b6856cba2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974342422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.974342422
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3566676491
Short name T716
Test name
Test status
Simulation time 69934441260 ps
CPU time 107.6 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:55:31 PM PDT 24
Peak memory 200048 kb
Host smart-ced18a72-20f1-4053-aa22-46c4b2d76b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566676491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3566676491
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3907514516
Short name T1181
Test name
Test status
Simulation time 1198632733 ps
CPU time 1.16 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:53:46 PM PDT 24
Peak memory 195744 kb
Host smart-093f2aab-499b-42d3-aafb-45bd7b192398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907514516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3907514516
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2471118980
Short name T798
Test name
Test status
Simulation time 6080482845 ps
CPU time 20.48 seconds
Started Jul 23 06:53:44 PM PDT 24
Finished Jul 23 06:54:06 PM PDT 24
Peak memory 200028 kb
Host smart-1c48c99c-d679-4a0f-bbaa-a188d06f1fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471118980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2471118980
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.7906199
Short name T259
Test name
Test status
Simulation time 315901392944 ps
CPU time 1069.43 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 07:11:34 PM PDT 24
Peak memory 200248 kb
Host smart-3deed8bb-c772-41e5-a7e8-82663c7eea35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7906199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.7906199
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2151410906
Short name T123
Test name
Test status
Simulation time 113596972558 ps
CPU time 301.58 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:58:44 PM PDT 24
Peak memory 216880 kb
Host smart-ba3868cb-8023-49ca-bd0f-d6b8b8ec700c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151410906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2151410906
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.793458548
Short name T351
Test name
Test status
Simulation time 9277135761 ps
CPU time 6.29 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:53:52 PM PDT 24
Peak memory 199528 kb
Host smart-a3308093-dadd-4d90-9dc4-cb82dfa6a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793458548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.793458548
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3969436822
Short name T709
Test name
Test status
Simulation time 148147407086 ps
CPU time 157.8 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:56:20 PM PDT 24
Peak memory 200252 kb
Host smart-d254a9ea-aa2a-438c-a300-a592cab20401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969436822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3969436822
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3009444947
Short name T597
Test name
Test status
Simulation time 13545182 ps
CPU time 0.56 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:53:52 PM PDT 24
Peak memory 195268 kb
Host smart-af6e187c-d38e-4001-8dbf-c4c869f364f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009444947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3009444947
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3445275969
Short name T497
Test name
Test status
Simulation time 36855546342 ps
CPU time 29.32 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:54:13 PM PDT 24
Peak memory 200048 kb
Host smart-98f7bc4f-ccc1-4a8a-b9d7-b999a30912de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445275969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3445275969
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.723074690
Short name T743
Test name
Test status
Simulation time 22012029370 ps
CPU time 42.36 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:54:34 PM PDT 24
Peak memory 200176 kb
Host smart-a2e60095-52ff-412e-88a5-e1abf7b8f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723074690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.723074690
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.4117375985
Short name T620
Test name
Test status
Simulation time 14275619556 ps
CPU time 13.54 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:54:05 PM PDT 24
Peak memory 200260 kb
Host smart-941f8e2c-f5c5-45fb-ad4b-861b089fe6d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117375985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4117375985
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1495424992
Short name T1090
Test name
Test status
Simulation time 104118768596 ps
CPU time 362.65 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:59:53 PM PDT 24
Peak memory 200184 kb
Host smart-392d5211-da15-4996-957d-4a2655339858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495424992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1495424992
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.846233430
Short name T415
Test name
Test status
Simulation time 1959348252 ps
CPU time 3.82 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:53:56 PM PDT 24
Peak memory 195640 kb
Host smart-c034fa33-8d46-42a8-b82c-7d884129e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846233430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.846233430
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.592461984
Short name T420
Test name
Test status
Simulation time 166126810871 ps
CPU time 48.66 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:54:39 PM PDT 24
Peak memory 200320 kb
Host smart-7ed17ea4-004f-406f-8990-71f2e10c9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592461984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.592461984
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3250687236
Short name T932
Test name
Test status
Simulation time 24769288751 ps
CPU time 584.02 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 07:03:35 PM PDT 24
Peak memory 200268 kb
Host smart-d46d4b2f-b79a-43d4-acc2-042c46776277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250687236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3250687236
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.29344293
Short name T360
Test name
Test status
Simulation time 3817720109 ps
CPU time 14.74 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 199220 kb
Host smart-f32c1d09-d925-46cb-92d4-e03939f2da7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29344293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.29344293
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4106947761
Short name T455
Test name
Test status
Simulation time 70058333561 ps
CPU time 31.8 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:26 PM PDT 24
Peak memory 200128 kb
Host smart-56e97dad-1901-427f-9010-55f115fe8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106947761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4106947761
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1451559525
Short name T570
Test name
Test status
Simulation time 4591045201 ps
CPU time 6.97 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:53:58 PM PDT 24
Peak memory 196552 kb
Host smart-1bebb73c-39a9-4145-876c-80f333fbc504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451559525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1451559525
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2718281164
Short name T584
Test name
Test status
Simulation time 5835009821 ps
CPU time 9.32 seconds
Started Jul 23 06:53:42 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 200084 kb
Host smart-427f5204-4206-46ef-a794-1ae5f3e53481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718281164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2718281164
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2228517637
Short name T1124
Test name
Test status
Simulation time 206688354737 ps
CPU time 395.5 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 07:00:29 PM PDT 24
Peak memory 200224 kb
Host smart-bf71eb55-50c2-46f9-89c2-5606ed3fe0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228517637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2228517637
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3896980947
Short name T1126
Test name
Test status
Simulation time 598616023010 ps
CPU time 868.57 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 216904 kb
Host smart-18bad35f-3c2a-475f-98a4-2fbba0dd38df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896980947 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3896980947
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2590973649
Short name T1125
Test name
Test status
Simulation time 15244675360 ps
CPU time 3.99 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:53:55 PM PDT 24
Peak memory 200232 kb
Host smart-2c23c08d-de16-4af0-82be-0153c87904cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590973649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2590973649
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2932066010
Short name T539
Test name
Test status
Simulation time 105524566822 ps
CPU time 92.95 seconds
Started Jul 23 06:53:43 PM PDT 24
Finished Jul 23 06:55:18 PM PDT 24
Peak memory 200268 kb
Host smart-72f305b8-09e1-4bb5-84a6-88717698f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932066010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2932066010
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1481316651
Short name T82
Test name
Test status
Simulation time 15049762 ps
CPU time 0.53 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 195628 kb
Host smart-3171e06a-39bf-4c74-a3c1-7b5d41d884e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481316651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1481316651
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2517176963
Short name T524
Test name
Test status
Simulation time 157616078305 ps
CPU time 111.31 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:55:44 PM PDT 24
Peak memory 200232 kb
Host smart-150ce2c5-e897-4e10-acdd-924a3bbeabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517176963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2517176963
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2432146407
Short name T493
Test name
Test status
Simulation time 106541691738 ps
CPU time 37.02 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:54:29 PM PDT 24
Peak memory 200200 kb
Host smart-f743e713-d039-4d3a-9469-1f2f0cbf68bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432146407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2432146407
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.794442250
Short name T1175
Test name
Test status
Simulation time 13287976988 ps
CPU time 23.53 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:17 PM PDT 24
Peak memory 200256 kb
Host smart-a64ea722-b338-4a7f-96a0-e542030ea8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794442250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.794442250
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.912471872
Short name T400
Test name
Test status
Simulation time 21710833779 ps
CPU time 31.07 seconds
Started Jul 23 06:53:50 PM PDT 24
Finished Jul 23 06:54:22 PM PDT 24
Peak memory 199776 kb
Host smart-09035e1a-49b6-48d9-92c1-1d51586c9c8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912471872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.912471872
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1064931713
Short name T873
Test name
Test status
Simulation time 159346757378 ps
CPU time 162.59 seconds
Started Jul 23 06:53:53 PM PDT 24
Finished Jul 23 06:56:37 PM PDT 24
Peak memory 200200 kb
Host smart-33d5aaba-57ba-45e9-9f3a-144e8a7430b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064931713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1064931713
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1007436157
Short name T867
Test name
Test status
Simulation time 8166839105 ps
CPU time 7.25 seconds
Started Jul 23 06:53:52 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 198536 kb
Host smart-cbaca059-b85e-4461-a2d0-20b1e38d3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007436157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1007436157
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.859026763
Short name T280
Test name
Test status
Simulation time 54804175147 ps
CPU time 99.66 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:55:33 PM PDT 24
Peak memory 200100 kb
Host smart-591cdd29-09a9-4f3f-9f25-f3161d65fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859026763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.859026763
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.78768421
Short name T568
Test name
Test status
Simulation time 14045028079 ps
CPU time 210.26 seconds
Started Jul 23 06:53:53 PM PDT 24
Finished Jul 23 06:57:25 PM PDT 24
Peak memory 200232 kb
Host smart-75a95bff-a6a5-49cf-8c8b-974a47bb79fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78768421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.78768421
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3739716111
Short name T1064
Test name
Test status
Simulation time 4501047854 ps
CPU time 6.84 seconds
Started Jul 23 06:53:53 PM PDT 24
Finished Jul 23 06:54:02 PM PDT 24
Peak memory 199704 kb
Host smart-ee7db30e-1a21-4030-ad3f-79072037af54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739716111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3739716111
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.878671605
Short name T616
Test name
Test status
Simulation time 183073989260 ps
CPU time 74.91 seconds
Started Jul 23 06:53:56 PM PDT 24
Finished Jul 23 06:55:12 PM PDT 24
Peak memory 200224 kb
Host smart-770dfaa4-16d4-4c6f-ab15-2d94affc8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878671605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.878671605
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1961097418
Short name T598
Test name
Test status
Simulation time 2699919682 ps
CPU time 5 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:53:58 PM PDT 24
Peak memory 196732 kb
Host smart-3db00bea-ee16-4726-a561-d18fc0bcb095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961097418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1961097418
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.430840420
Short name T49
Test name
Test status
Simulation time 5346158465 ps
CPU time 25.6 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:18 PM PDT 24
Peak memory 199604 kb
Host smart-85c9acb2-f59e-40f9-9e8a-d0b9feff3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430840420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.430840420
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.905221382
Short name T594
Test name
Test status
Simulation time 283492974119 ps
CPU time 308.4 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:59:02 PM PDT 24
Peak memory 200212 kb
Host smart-28f566d5-b2ab-42fb-be36-8268a184972e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905221382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.905221382
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3431604134
Short name T479
Test name
Test status
Simulation time 6549769508 ps
CPU time 14.39 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:08 PM PDT 24
Peak memory 200200 kb
Host smart-cbbdec10-f2a4-4eb8-ab90-6b1da1633d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431604134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3431604134
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2395154682
Short name T764
Test name
Test status
Simulation time 39868456251 ps
CPU time 31.84 seconds
Started Jul 23 06:53:49 PM PDT 24
Finished Jul 23 06:54:22 PM PDT 24
Peak memory 200288 kb
Host smart-0d7fd41b-1383-4f74-acee-db2939cc0227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395154682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2395154682
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3035651590
Short name T549
Test name
Test status
Simulation time 36007089 ps
CPU time 0.57 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 195612 kb
Host smart-eaa35f49-1646-4d92-96f9-b66f18794ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035651590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3035651590
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.121178315
Short name T886
Test name
Test status
Simulation time 45144854154 ps
CPU time 67.8 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 200252 kb
Host smart-5c7bc608-0679-41f3-a3eb-1672c3e7bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121178315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.121178315
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1974065581
Short name T559
Test name
Test status
Simulation time 94487577722 ps
CPU time 142.5 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:53:33 PM PDT 24
Peak memory 200276 kb
Host smart-04236e2f-3e4e-4abe-a340-6bbb11a25af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974065581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1974065581
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1818884295
Short name T835
Test name
Test status
Simulation time 111216936196 ps
CPU time 41.41 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:54 PM PDT 24
Peak memory 199788 kb
Host smart-80b9aff1-a6e4-4203-9455-5e37b832cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818884295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1818884295
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.142983429
Short name T144
Test name
Test status
Simulation time 37647406765 ps
CPU time 26.74 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:38 PM PDT 24
Peak memory 200272 kb
Host smart-5aab5889-02cd-44b2-b86f-679c542da6fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142983429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.142983429
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3204554187
Short name T966
Test name
Test status
Simulation time 155646683183 ps
CPU time 745.09 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 07:03:38 PM PDT 24
Peak memory 200236 kb
Host smart-606f2419-7638-4f33-adea-1bd4713c0959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204554187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3204554187
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2487672261
Short name T523
Test name
Test status
Simulation time 2341407780 ps
CPU time 2.66 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:15 PM PDT 24
Peak memory 197024 kb
Host smart-d0ca7051-7122-429c-bbeb-43889fd14210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487672261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2487672261
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.244518735
Short name T10
Test name
Test status
Simulation time 74914396947 ps
CPU time 83.33 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 200276 kb
Host smart-6d1e42bc-0204-43e5-8d8a-5f5423d83018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244518735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.244518735
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4090203516
Short name T1032
Test name
Test status
Simulation time 24136578796 ps
CPU time 615.86 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 07:01:23 PM PDT 24
Peak memory 200276 kb
Host smart-bb53ae0f-64f7-49ee-a976-c04f3a9e404c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090203516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4090203516
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2011041918
Short name T1025
Test name
Test status
Simulation time 5464144343 ps
CPU time 47.7 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:51:58 PM PDT 24
Peak memory 198804 kb
Host smart-0fb19fde-fb75-4451-bbf1-4735d9bf70cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011041918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2011041918
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2216874202
Short name T130
Test name
Test status
Simulation time 59275104702 ps
CPU time 50.91 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 199820 kb
Host smart-ed68d4b1-0970-484d-861d-254c077467e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216874202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2216874202
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.626674543
Short name T614
Test name
Test status
Simulation time 3880512184 ps
CPU time 2.09 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 196368 kb
Host smart-ceaf7297-5e87-443b-b567-6740aa8414f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626674543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.626674543
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2536630868
Short name T532
Test name
Test status
Simulation time 644135696 ps
CPU time 0.81 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 197368 kb
Host smart-7ec6b22e-d9ff-4e89-8267-6ab0480fac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536630868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2536630868
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3059552000
Short name T193
Test name
Test status
Simulation time 529487319015 ps
CPU time 348.65 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:57:15 PM PDT 24
Peak memory 200164 kb
Host smart-e5ae26fe-97fe-4964-9488-9f6a28ccd1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059552000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3059552000
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.214302115
Short name T72
Test name
Test status
Simulation time 186091978451 ps
CPU time 550.68 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 07:00:22 PM PDT 24
Peak memory 228968 kb
Host smart-8a0096b2-0083-422c-85db-2300701debdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214302115 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.214302115
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2494602510
Short name T1045
Test name
Test status
Simulation time 440544512 ps
CPU time 1.83 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 199924 kb
Host smart-9fdb5469-0904-4793-9fc2-11a87499b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494602510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2494602510
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1183315662
Short name T1069
Test name
Test status
Simulation time 81490297200 ps
CPU time 80.69 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:52:43 PM PDT 24
Peak memory 200244 kb
Host smart-dad5c529-9f1c-4b59-b924-a11cdaee4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183315662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1183315662
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2022922487
Short name T801
Test name
Test status
Simulation time 64385751288 ps
CPU time 28.83 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:22 PM PDT 24
Peak memory 200212 kb
Host smart-714a19b1-d1b0-431a-9c27-070d4488108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022922487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2022922487
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3470156047
Short name T582
Test name
Test status
Simulation time 124978037765 ps
CPU time 602.68 seconds
Started Jul 23 06:53:56 PM PDT 24
Finished Jul 23 07:03:59 PM PDT 24
Peak memory 214424 kb
Host smart-99573a22-d376-4c76-8cd0-1fdf9e537370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470156047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3470156047
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1741864627
Short name T626
Test name
Test status
Simulation time 95875083490 ps
CPU time 49.48 seconds
Started Jul 23 06:53:51 PM PDT 24
Finished Jul 23 06:54:43 PM PDT 24
Peak memory 200172 kb
Host smart-d73afee7-f6ba-4712-be1c-3d6be581f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741864627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1741864627
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2214970257
Short name T548
Test name
Test status
Simulation time 16772688391 ps
CPU time 410.52 seconds
Started Jul 23 06:53:54 PM PDT 24
Finished Jul 23 07:00:46 PM PDT 24
Peak memory 216744 kb
Host smart-21fa4120-2607-4643-b4e6-7fe98050fa65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214970257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2214970257
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.884146763
Short name T244
Test name
Test status
Simulation time 15820474135 ps
CPU time 10.94 seconds
Started Jul 23 06:53:53 PM PDT 24
Finished Jul 23 06:54:06 PM PDT 24
Peak memory 200200 kb
Host smart-da9466d4-0c34-441f-b597-69492d859af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884146763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.884146763
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1498959246
Short name T852
Test name
Test status
Simulation time 40515905515 ps
CPU time 242.84 seconds
Started Jul 23 06:53:56 PM PDT 24
Finished Jul 23 06:58:00 PM PDT 24
Peak memory 216060 kb
Host smart-685ac7e5-3a0c-44c2-be86-56eeb61e31b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498959246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1498959246
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2396930317
Short name T793
Test name
Test status
Simulation time 217030713608 ps
CPU time 73.3 seconds
Started Jul 23 06:53:56 PM PDT 24
Finished Jul 23 06:55:10 PM PDT 24
Peak memory 200252 kb
Host smart-5958f7e0-2dff-4cb4-9fae-512efd3a9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396930317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2396930317
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3498636085
Short name T80
Test name
Test status
Simulation time 75297522487 ps
CPU time 202.5 seconds
Started Jul 23 06:53:52 PM PDT 24
Finished Jul 23 06:57:17 PM PDT 24
Peak memory 216000 kb
Host smart-26fb32b9-8f67-4685-8c5a-bd0d35f73154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498636085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3498636085
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3104922242
Short name T850
Test name
Test status
Simulation time 76948737651 ps
CPU time 107.25 seconds
Started Jul 23 06:53:54 PM PDT 24
Finished Jul 23 06:55:42 PM PDT 24
Peak memory 200236 kb
Host smart-eed06bd0-6739-4cfc-9f8f-9755448614d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104922242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3104922242
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2833173501
Short name T882
Test name
Test status
Simulation time 31047446363 ps
CPU time 30.45 seconds
Started Jul 23 06:53:57 PM PDT 24
Finished Jul 23 06:54:29 PM PDT 24
Peak memory 200200 kb
Host smart-564b3b8d-895b-4f0d-89cc-4911abd40284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833173501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2833173501
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.971722244
Short name T719
Test name
Test status
Simulation time 122283148159 ps
CPU time 353.75 seconds
Started Jul 23 06:53:57 PM PDT 24
Finished Jul 23 06:59:51 PM PDT 24
Peak memory 216780 kb
Host smart-5301a844-0531-4874-b0b6-19c36916238b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971722244 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.971722244
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2282584571
Short name T20
Test name
Test status
Simulation time 25118026287 ps
CPU time 290.2 seconds
Started Jul 23 06:53:58 PM PDT 24
Finished Jul 23 06:58:50 PM PDT 24
Peak memory 216916 kb
Host smart-5f8a3c74-00da-4f1c-b484-ce6845eaea1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282584571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2282584571
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1942063810
Short name T213
Test name
Test status
Simulation time 118750175269 ps
CPU time 46.47 seconds
Started Jul 23 06:53:58 PM PDT 24
Finished Jul 23 06:54:46 PM PDT 24
Peak memory 200136 kb
Host smart-ec58b8f9-ad72-4aa6-8aa5-21128b8111ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942063810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1942063810
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.34542760
Short name T890
Test name
Test status
Simulation time 222354239247 ps
CPU time 912.13 seconds
Started Jul 23 06:53:58 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 225040 kb
Host smart-99a3def0-d41e-4b5b-b9de-05bc2aa6c693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34542760 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.34542760
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1100826915
Short name T1135
Test name
Test status
Simulation time 28279586846 ps
CPU time 45.22 seconds
Started Jul 23 06:53:57 PM PDT 24
Finished Jul 23 06:54:43 PM PDT 24
Peak memory 200152 kb
Host smart-26e1e61f-bd39-450d-b44e-e122cae0c1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100826915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1100826915
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1739604557
Short name T309
Test name
Test status
Simulation time 41956659440 ps
CPU time 410.48 seconds
Started Jul 23 06:53:58 PM PDT 24
Finished Jul 23 07:00:50 PM PDT 24
Peak memory 216932 kb
Host smart-3022391b-9458-4704-b6ca-8afbb3a00135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739604557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1739604557
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1819029074
Short name T401
Test name
Test status
Simulation time 17913811 ps
CPU time 0.55 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 06:51:10 PM PDT 24
Peak memory 195644 kb
Host smart-209a77e7-08e1-41b2-a60c-78b283b08a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819029074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1819029074
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.222996007
Short name T658
Test name
Test status
Simulation time 97104631825 ps
CPU time 37.79 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:45 PM PDT 24
Peak memory 200236 kb
Host smart-19eefd56-a447-4b16-9c8e-5ef62e470747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222996007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.222996007
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.741386959
Short name T490
Test name
Test status
Simulation time 31897013632 ps
CPU time 60.78 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:52:11 PM PDT 24
Peak memory 200268 kb
Host smart-bb0637ea-9941-48b4-a95f-de4eb29d278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741386959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.741386959
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2018420249
Short name T683
Test name
Test status
Simulation time 67866727247 ps
CPU time 92.58 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:52:47 PM PDT 24
Peak memory 200168 kb
Host smart-5b28a0f3-9c46-4d78-bb10-bd7afa253025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018420249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2018420249
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3928785965
Short name T759
Test name
Test status
Simulation time 33339985830 ps
CPU time 65.73 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:52:32 PM PDT 24
Peak memory 200236 kb
Host smart-67b40eec-862b-4a05-8c86-34e3e6ecaf9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928785965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3928785965
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3650374554
Short name T947
Test name
Test status
Simulation time 99958377752 ps
CPU time 166.93 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 200012 kb
Host smart-54a615cf-2b66-435f-b2d5-13404e590f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650374554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3650374554
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3859625993
Short name T921
Test name
Test status
Simulation time 1309180441 ps
CPU time 1.46 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:51:15 PM PDT 24
Peak memory 195672 kb
Host smart-0deea600-b5d7-4169-9af8-f49fb6b23d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859625993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3859625993
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1481939822
Short name T583
Test name
Test status
Simulation time 61337248493 ps
CPU time 49.95 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:52:04 PM PDT 24
Peak memory 200388 kb
Host smart-f0b3233d-5107-4096-8e0e-a1b4cd687f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481939822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1481939822
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.643065799
Short name T494
Test name
Test status
Simulation time 22272932669 ps
CPU time 195.78 seconds
Started Jul 23 06:51:25 PM PDT 24
Finished Jul 23 06:54:44 PM PDT 24
Peak memory 200160 kb
Host smart-f9757f2a-229d-4fbb-8958-6cbeb9aa95f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643065799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.643065799
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.649633030
Short name T87
Test name
Test status
Simulation time 6187981739 ps
CPU time 51.84 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:52:05 PM PDT 24
Peak memory 198500 kb
Host smart-3892f119-34e7-4f1e-83d5-b9f09cc4157b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649633030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.649633030
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1895892381
Short name T310
Test name
Test status
Simulation time 58000851876 ps
CPU time 83.9 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:52:34 PM PDT 24
Peak memory 200184 kb
Host smart-7e86a17a-b0cb-4114-9981-5c161cf7408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895892381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1895892381
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2156459111
Short name T833
Test name
Test status
Simulation time 5223130038 ps
CPU time 6.94 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 196544 kb
Host smart-acccf309-f7fc-4ad4-9f83-b2c05e488bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156459111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2156459111
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1395293979
Short name T912
Test name
Test status
Simulation time 715099664 ps
CPU time 5.39 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 198536 kb
Host smart-cee73055-c986-4769-ae78-46b6e7c90276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395293979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1395293979
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2913676011
Short name T907
Test name
Test status
Simulation time 188914197325 ps
CPU time 89.97 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 06:52:39 PM PDT 24
Peak memory 200252 kb
Host smart-c059268d-678a-4a2a-bad2-d78c2d0ecbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913676011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2913676011
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.529692081
Short name T229
Test name
Test status
Simulation time 92374334848 ps
CPU time 601.28 seconds
Started Jul 23 06:51:06 PM PDT 24
Finished Jul 23 07:01:10 PM PDT 24
Peak memory 216872 kb
Host smart-7053fe33-2b4b-41f3-8192-3e43dcaa037b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529692081 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.529692081
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.959412102
Short name T962
Test name
Test status
Simulation time 736633042 ps
CPU time 2.82 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 198636 kb
Host smart-221db23f-323b-4edb-a923-50a3c408f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959412102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.959412102
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3586296157
Short name T374
Test name
Test status
Simulation time 50780532143 ps
CPU time 21.88 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 200216 kb
Host smart-1af512f7-1fb6-4e9a-aa40-d56b679678fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586296157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3586296157
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4161636943
Short name T1028
Test name
Test status
Simulation time 91138754498 ps
CPU time 216.68 seconds
Started Jul 23 06:53:59 PM PDT 24
Finished Jul 23 06:57:37 PM PDT 24
Peak memory 215056 kb
Host smart-f465460a-a600-4392-a415-1a448a0c858e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161636943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4161636943
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.519725186
Short name T604
Test name
Test status
Simulation time 79687406289 ps
CPU time 243.61 seconds
Started Jul 23 06:57:24 PM PDT 24
Finished Jul 23 07:01:28 PM PDT 24
Peak memory 200196 kb
Host smart-f1d77b84-f12c-4acb-99b4-837c61926510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519725186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.519725186
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2002235233
Short name T1114
Test name
Test status
Simulation time 195464048542 ps
CPU time 422.63 seconds
Started Jul 23 06:57:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 216844 kb
Host smart-7e137930-73dc-4172-b46c-6bd0f3979da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002235233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2002235233
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1472870692
Short name T325
Test name
Test status
Simulation time 65750731738 ps
CPU time 96.76 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 06:59:03 PM PDT 24
Peak memory 200184 kb
Host smart-e8b48f6b-4d84-4e5a-a74b-5f10dd5dd8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472870692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1472870692
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1810213326
Short name T857
Test name
Test status
Simulation time 27912192840 ps
CPU time 342.9 seconds
Started Jul 23 06:57:26 PM PDT 24
Finished Jul 23 07:03:09 PM PDT 24
Peak memory 214808 kb
Host smart-96830167-b11a-4e68-b2e8-2fed0c1bd69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810213326 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1810213326
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.138977687
Short name T45
Test name
Test status
Simulation time 229206223915 ps
CPU time 137.3 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 06:59:43 PM PDT 24
Peak memory 200216 kb
Host smart-1d95f4df-abd5-4d21-b414-d1e05249d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138977687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.138977687
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.312932761
Short name T61
Test name
Test status
Simulation time 58903157553 ps
CPU time 691.73 seconds
Started Jul 23 06:57:26 PM PDT 24
Finished Jul 23 07:08:58 PM PDT 24
Peak memory 208608 kb
Host smart-cc8613a6-0b46-45f4-9d68-f6b24cb3e620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312932761 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.312932761
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3161247637
Short name T295
Test name
Test status
Simulation time 143011314902 ps
CPU time 101 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 06:59:07 PM PDT 24
Peak memory 200180 kb
Host smart-ec639f44-d484-4caa-9155-34fec2ad2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161247637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3161247637
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1969157287
Short name T226
Test name
Test status
Simulation time 153408806513 ps
CPU time 226.29 seconds
Started Jul 23 06:57:23 PM PDT 24
Finished Jul 23 07:01:10 PM PDT 24
Peak memory 200180 kb
Host smart-cbb0a596-5c99-42ea-ac3f-77751f3f0970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969157287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1969157287
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2407245352
Short name T1052
Test name
Test status
Simulation time 18237815600 ps
CPU time 207.02 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 07:00:53 PM PDT 24
Peak memory 211340 kb
Host smart-ce0fe944-4df9-481c-9468-6be3fbeccb3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407245352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2407245352
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2745542655
Short name T369
Test name
Test status
Simulation time 24291732471 ps
CPU time 34.83 seconds
Started Jul 23 06:57:25 PM PDT 24
Finished Jul 23 06:58:00 PM PDT 24
Peak memory 200216 kb
Host smart-7c075276-0c81-4e4a-9f17-978c1e83799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745542655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2745542655
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2650896118
Short name T669
Test name
Test status
Simulation time 188365692441 ps
CPU time 902.35 seconds
Started Jul 23 06:57:24 PM PDT 24
Finished Jul 23 07:12:27 PM PDT 24
Peak memory 225128 kb
Host smart-42f7dfd8-9d35-4f69-aba2-021758e7831e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650896118 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2650896118
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1738679528
Short name T175
Test name
Test status
Simulation time 60960317901 ps
CPU time 36.15 seconds
Started Jul 23 06:57:29 PM PDT 24
Finished Jul 23 06:58:06 PM PDT 24
Peak memory 200184 kb
Host smart-d6f004c2-805c-459f-8741-c3994f04faa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738679528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1738679528
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2282673675
Short name T845
Test name
Test status
Simulation time 341901066988 ps
CPU time 445.71 seconds
Started Jul 23 06:57:28 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 225068 kb
Host smart-9be1fcf5-c97c-40f9-b80e-b37168e4ee92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282673675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2282673675
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.719981387
Short name T250
Test name
Test status
Simulation time 65259217668 ps
CPU time 63.43 seconds
Started Jul 23 06:57:29 PM PDT 24
Finished Jul 23 06:58:33 PM PDT 24
Peak memory 200092 kb
Host smart-6ea65187-3a41-4b6a-886d-c91ea5907b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719981387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.719981387
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1438849612
Short name T1170
Test name
Test status
Simulation time 177739996373 ps
CPU time 65.31 seconds
Started Jul 23 06:57:29 PM PDT 24
Finished Jul 23 06:58:35 PM PDT 24
Peak memory 199740 kb
Host smart-2e59545f-a7f8-4580-a38d-b0c16f28920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438849612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1438849612
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.390219492
Short name T202
Test name
Test status
Simulation time 291409865034 ps
CPU time 993.39 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:14:22 PM PDT 24
Peak memory 227960 kb
Host smart-afd39e80-baea-47ac-84a0-6f5cba3d8c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390219492 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.390219492
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3487898219
Short name T976
Test name
Test status
Simulation time 25094128 ps
CPU time 0.57 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:51:15 PM PDT 24
Peak memory 195636 kb
Host smart-d6a83a78-148a-4313-9eae-8719bcca7cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487898219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3487898219
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2636428393
Short name T196
Test name
Test status
Simulation time 21436570653 ps
CPU time 9.11 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:51:24 PM PDT 24
Peak memory 200104 kb
Host smart-19762b0a-3737-4d94-8e16-cf28d0bf1620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636428393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2636428393
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2681946688
Short name T879
Test name
Test status
Simulation time 37768149941 ps
CPU time 59.58 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:52:13 PM PDT 24
Peak memory 200152 kb
Host smart-fb46063f-8d82-41a6-a3bb-caf552de9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681946688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2681946688
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.1693801922
Short name T413
Test name
Test status
Simulation time 28320303155 ps
CPU time 2.85 seconds
Started Jul 23 06:51:23 PM PDT 24
Finished Jul 23 06:51:29 PM PDT 24
Peak memory 199052 kb
Host smart-8541ed9a-0857-4a90-91b8-f08cc7ff2ad5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693801922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1693801922
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.4024661849
Short name T70
Test name
Test status
Simulation time 80477843780 ps
CPU time 175.49 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:54:09 PM PDT 24
Peak memory 200248 kb
Host smart-d2213daf-371d-4119-b0db-d847b75f811a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024661849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4024661849
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.664535856
Short name T788
Test name
Test status
Simulation time 3156807942 ps
CPU time 3.28 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:51:17 PM PDT 24
Peak memory 199240 kb
Host smart-8a212a28-da24-4764-8ea5-6d1bca30abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664535856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.664535856
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4177461862
Short name T1085
Test name
Test status
Simulation time 19026087213 ps
CPU time 13.16 seconds
Started Jul 23 06:51:30 PM PDT 24
Finished Jul 23 06:51:46 PM PDT 24
Peak memory 196708 kb
Host smart-0d0c4d4f-d298-4fbd-97a4-27d6db6ebfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177461862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4177461862
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4130534086
Short name T673
Test name
Test status
Simulation time 18420828897 ps
CPU time 196.8 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:54:31 PM PDT 24
Peak memory 200240 kb
Host smart-8175352b-c91a-4242-a695-ddf1eefd0058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130534086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4130534086
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2844540202
Short name T787
Test name
Test status
Simulation time 7095475019 ps
CPU time 61.82 seconds
Started Jul 23 06:51:05 PM PDT 24
Finished Jul 23 06:52:10 PM PDT 24
Peak memory 198340 kb
Host smart-aa8c4418-b350-43d1-9940-8a6cdfbff1da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844540202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2844540202
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.306049986
Short name T795
Test name
Test status
Simulation time 19192496470 ps
CPU time 7.33 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:51:28 PM PDT 24
Peak memory 200228 kb
Host smart-ace1b35b-6066-4bea-90f2-c9c0e2cecf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306049986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.306049986
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2825416704
Short name T285
Test name
Test status
Simulation time 38368687570 ps
CPU time 29.9 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:51:45 PM PDT 24
Peak memory 196872 kb
Host smart-3b8b71ff-72fa-4245-90b8-cae0617a5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825416704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2825416704
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2722323717
Short name T9
Test name
Test status
Simulation time 247912013 ps
CPU time 1.55 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:13 PM PDT 24
Peak memory 199024 kb
Host smart-5156ea31-898c-4e2f-84b3-5835bb9d32dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722323717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2722323717
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.134166133
Short name T900
Test name
Test status
Simulation time 318555138405 ps
CPU time 684.69 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 07:02:35 PM PDT 24
Peak memory 200244 kb
Host smart-ebd1e919-ee59-416b-9e26-3b29b96c3a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134166133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.134166133
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.960877554
Short name T768
Test name
Test status
Simulation time 170763762401 ps
CPU time 966.59 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 07:07:36 PM PDT 24
Peak memory 233252 kb
Host smart-abce4049-5065-4ff3-a60d-94dc744e6853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960877554 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.960877554
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3365248912
Short name T938
Test name
Test status
Simulation time 12266220074 ps
CPU time 59.23 seconds
Started Jul 23 06:51:15 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 200080 kb
Host smart-65608022-9d28-460b-aab4-ca0631eb53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365248912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3365248912
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3769436594
Short name T991
Test name
Test status
Simulation time 13794808719 ps
CPU time 5.94 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 200008 kb
Host smart-41f8763e-a163-49c8-a71f-7b99efc0ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769436594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3769436594
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3190686646
Short name T21
Test name
Test status
Simulation time 33386774773 ps
CPU time 195.17 seconds
Started Jul 23 06:57:42 PM PDT 24
Finished Jul 23 07:00:58 PM PDT 24
Peak memory 216120 kb
Host smart-32aea535-2a81-4cb4-913a-91caecddce60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190686646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3190686646
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1307307023
Short name T322
Test name
Test status
Simulation time 155858239059 ps
CPU time 56.3 seconds
Started Jul 23 06:57:44 PM PDT 24
Finished Jul 23 06:58:41 PM PDT 24
Peak memory 200172 kb
Host smart-7e42dbe9-81b4-4e93-a7d5-6f4f26684e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307307023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1307307023
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.976616373
Short name T629
Test name
Test status
Simulation time 54183522653 ps
CPU time 80.84 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:59:09 PM PDT 24
Peak memory 200232 kb
Host smart-9458bb87-455a-45ec-8785-0faef0a78f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976616373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.976616373
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3302439649
Short name T1050
Test name
Test status
Simulation time 9779967084 ps
CPU time 19.41 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:58:06 PM PDT 24
Peak memory 200244 kb
Host smart-776a374f-187e-4fc6-ae4b-0f7890020ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302439649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3302439649
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2982691426
Short name T1000
Test name
Test status
Simulation time 427561257509 ps
CPU time 1314.82 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:19:44 PM PDT 24
Peak memory 228056 kb
Host smart-75eccc1f-d59b-45f9-86ee-091b7a9f9f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982691426 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2982691426
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2735358938
Short name T249
Test name
Test status
Simulation time 243775064845 ps
CPU time 21.2 seconds
Started Jul 23 06:57:41 PM PDT 24
Finished Jul 23 06:58:03 PM PDT 24
Peak memory 200100 kb
Host smart-4658e4db-1b02-4f5b-8028-3ffc6682151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735358938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2735358938
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2538982835
Short name T214
Test name
Test status
Simulation time 18691920134 ps
CPU time 27.94 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:58:16 PM PDT 24
Peak memory 200192 kb
Host smart-6c0eeb32-dc74-40ef-882a-0e5f03d14470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538982835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2538982835
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.999991726
Short name T192
Test name
Test status
Simulation time 54281887368 ps
CPU time 633.52 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:08:22 PM PDT 24
Peak memory 214096 kb
Host smart-f69cf33a-cf87-4652-b7df-c571b38e4d87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999991726 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.999991726
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.976653702
Short name T613
Test name
Test status
Simulation time 154287296136 ps
CPU time 89.82 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 06:59:18 PM PDT 24
Peak memory 200112 kb
Host smart-3ed0e7d1-fa6a-4ca7-a6b6-287ef1fc405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976653702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.976653702
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3685463835
Short name T489
Test name
Test status
Simulation time 60999672268 ps
CPU time 369.17 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 07:03:58 PM PDT 24
Peak memory 210768 kb
Host smart-2e7f860c-8d0a-4da1-838c-71877a4cb1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685463835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3685463835
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2017368409
Short name T445
Test name
Test status
Simulation time 72729209875 ps
CPU time 23.11 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:58:11 PM PDT 24
Peak memory 200256 kb
Host smart-6e7def5b-2487-4c02-b290-164fe454e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017368409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2017368409
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3820019770
Short name T256
Test name
Test status
Simulation time 59608849216 ps
CPU time 359.62 seconds
Started Jul 23 06:57:44 PM PDT 24
Finished Jul 23 07:03:44 PM PDT 24
Peak memory 216032 kb
Host smart-6ce36b2b-2ca0-4b6b-a431-c521eac2226d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820019770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3820019770
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.407852126
Short name T820
Test name
Test status
Simulation time 186015221238 ps
CPU time 326.79 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:03:16 PM PDT 24
Peak memory 200248 kb
Host smart-98dac67b-f6d4-4b46-b833-385c368b659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407852126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.407852126
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3704444957
Short name T258
Test name
Test status
Simulation time 101953217175 ps
CPU time 84.42 seconds
Started Jul 23 06:57:44 PM PDT 24
Finished Jul 23 06:59:09 PM PDT 24
Peak memory 200232 kb
Host smart-8c20b5a8-d6da-4394-a71f-d747dc7eb3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704444957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3704444957
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3947156740
Short name T33
Test name
Test status
Simulation time 18789681827 ps
CPU time 230.28 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:01:38 PM PDT 24
Peak memory 211484 kb
Host smart-e0d78701-337a-4911-af1c-832c70e14a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947156740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3947156740
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2080524757
Short name T973
Test name
Test status
Simulation time 12732197 ps
CPU time 0.54 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:51:21 PM PDT 24
Peak memory 195912 kb
Host smart-bbbac1c6-02d3-4f9a-8782-bc5ce8007991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080524757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2080524757
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2646376934
Short name T114
Test name
Test status
Simulation time 32355339922 ps
CPU time 34.83 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:51:46 PM PDT 24
Peak memory 200188 kb
Host smart-1684ff5f-0532-4fec-a690-4d6a8be79d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646376934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2646376934
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.195595081
Short name T790
Test name
Test status
Simulation time 14011662292 ps
CPU time 25.66 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:51:44 PM PDT 24
Peak memory 200200 kb
Host smart-01859a4e-138d-438d-a93e-080b4d582f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195595081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.195595081
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3317973956
Short name T1089
Test name
Test status
Simulation time 311983232812 ps
CPU time 38.14 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:52:10 PM PDT 24
Peak memory 200172 kb
Host smart-fec27ab2-3e97-44c4-b427-7e35ce45f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317973956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3317973956
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3277821868
Short name T729
Test name
Test status
Simulation time 36704577483 ps
CPU time 15.39 seconds
Started Jul 23 06:51:07 PM PDT 24
Finished Jul 23 06:51:26 PM PDT 24
Peak memory 200224 kb
Host smart-cfa3c76f-1dfc-4614-b2d7-bbb718a1ed4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277821868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3277821868
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1295965055
Short name T491
Test name
Test status
Simulation time 97486690329 ps
CPU time 235.74 seconds
Started Jul 23 06:51:25 PM PDT 24
Finished Jul 23 06:55:24 PM PDT 24
Peak memory 200236 kb
Host smart-67b5b569-8110-43fd-98ef-773bfde8c9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295965055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1295965055
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3605699215
Short name T462
Test name
Test status
Simulation time 7047094083 ps
CPU time 4.62 seconds
Started Jul 23 06:51:19 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 199336 kb
Host smart-4f169b6d-cd05-4c48-94ef-78ee669c75db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605699215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3605699215
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3405365448
Short name T928
Test name
Test status
Simulation time 134707462366 ps
CPU time 68.32 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:52:20 PM PDT 24
Peak memory 208376 kb
Host smart-70715203-05c8-407b-ae78-9901c44bffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405365448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3405365448
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1661709682
Short name T887
Test name
Test status
Simulation time 19587331111 ps
CPU time 811.9 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 07:04:46 PM PDT 24
Peak memory 200208 kb
Host smart-f001814d-23ef-4ad6-8e4d-4f5dcce446e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661709682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1661709682
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3147988729
Short name T744
Test name
Test status
Simulation time 2136495897 ps
CPU time 4.14 seconds
Started Jul 23 06:51:08 PM PDT 24
Finished Jul 23 06:51:15 PM PDT 24
Peak memory 198512 kb
Host smart-633a23c6-727f-464b-993c-51b232b671a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147988729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3147988729
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1402656067
Short name T1057
Test name
Test status
Simulation time 142359197132 ps
CPU time 413.03 seconds
Started Jul 23 06:51:24 PM PDT 24
Finished Jul 23 06:58:21 PM PDT 24
Peak memory 200212 kb
Host smart-be55854e-20bd-4256-8e94-557fb4fb9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402656067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1402656067
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.682406947
Short name T536
Test name
Test status
Simulation time 1533435849 ps
CPU time 2.31 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 195732 kb
Host smart-36c82dcf-df81-48a4-929f-762a1b5facfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682406947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.682406947
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3093229483
Short name T723
Test name
Test status
Simulation time 6067133793 ps
CPU time 14.54 seconds
Started Jul 23 06:51:15 PM PDT 24
Finished Jul 23 06:51:31 PM PDT 24
Peak memory 200012 kb
Host smart-1dfd00ad-b93e-4388-b1fa-df8d8d764699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093229483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3093229483
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3678407874
Short name T1112
Test name
Test status
Simulation time 27486481861 ps
CPU time 30.35 seconds
Started Jul 23 06:51:09 PM PDT 24
Finished Jul 23 06:51:43 PM PDT 24
Peak memory 200244 kb
Host smart-ab45e36f-7b5e-439f-8b88-549ad7d3849f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678407874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3678407874
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.503722974
Short name T119
Test name
Test status
Simulation time 114606093920 ps
CPU time 457.96 seconds
Started Jul 23 06:51:29 PM PDT 24
Finished Jul 23 06:59:10 PM PDT 24
Peak memory 216760 kb
Host smart-0f723fff-5734-47bd-a917-5ee6ceac4004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503722974 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.503722974
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3233658144
Short name T521
Test name
Test status
Simulation time 7564872916 ps
CPU time 11.93 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 200248 kb
Host smart-a02af53e-3758-49d7-9a97-3be02cba32f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233658144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3233658144
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2303905577
Short name T838
Test name
Test status
Simulation time 2007688425 ps
CPU time 1.26 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 196940 kb
Host smart-8ac056e6-68b0-4905-9512-5d8b37ea6f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303905577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2303905577
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3760828448
Short name T498
Test name
Test status
Simulation time 257698430793 ps
CPU time 91.27 seconds
Started Jul 23 06:57:44 PM PDT 24
Finished Jul 23 06:59:17 PM PDT 24
Peak memory 200440 kb
Host smart-77da940a-f05e-4c69-8f85-bace158e3477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760828448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3760828448
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.421515456
Short name T872
Test name
Test status
Simulation time 68220641266 ps
CPU time 327.53 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:03:15 PM PDT 24
Peak memory 214672 kb
Host smart-514bb3e5-1516-4148-9878-f21a28acf2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421515456 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.421515456
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3986692151
Short name T560
Test name
Test status
Simulation time 14171410130 ps
CPU time 21.99 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 06:58:11 PM PDT 24
Peak memory 200212 kb
Host smart-2d96a270-6591-4c3d-96ac-65c5de59b1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986692151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3986692151
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.346681450
Short name T43
Test name
Test status
Simulation time 60504166176 ps
CPU time 816.34 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 216908 kb
Host smart-ef81f5d1-146c-42ee-8aff-bf5c37ffc2ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346681450 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.346681450
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3472780615
Short name T537
Test name
Test status
Simulation time 61583797045 ps
CPU time 104.45 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 06:59:33 PM PDT 24
Peak memory 200248 kb
Host smart-677b49cc-10e0-4855-9451-adae7c19fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472780615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3472780615
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.223494011
Short name T705
Test name
Test status
Simulation time 72064220069 ps
CPU time 528.03 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:06:37 PM PDT 24
Peak memory 215864 kb
Host smart-1a10a318-b139-485b-96ad-1afa44f8f537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223494011 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.223494011
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4052822806
Short name T1168
Test name
Test status
Simulation time 148974574167 ps
CPU time 34.99 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 06:58:24 PM PDT 24
Peak memory 200212 kb
Host smart-334968ae-bd0c-4aff-b808-c25707aad588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052822806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4052822806
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1074190539
Short name T508
Test name
Test status
Simulation time 55072681116 ps
CPU time 495.01 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 216868 kb
Host smart-3c1b6aae-04ad-4293-a79a-8fc5a91cb7e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074190539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1074190539
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2427230920
Short name T1150
Test name
Test status
Simulation time 129600156855 ps
CPU time 249.75 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:01:58 PM PDT 24
Peak memory 200196 kb
Host smart-f893dab6-ad48-4c38-8370-addf7fd9ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427230920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2427230920
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.902621354
Short name T122
Test name
Test status
Simulation time 17848742933 ps
CPU time 149.12 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 07:00:18 PM PDT 24
Peak memory 216848 kb
Host smart-5d0f143e-925e-4c53-b3bf-ca108a6e8898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902621354 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.902621354
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1040476276
Short name T675
Test name
Test status
Simulation time 78307592762 ps
CPU time 110.52 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 06:59:40 PM PDT 24
Peak memory 200168 kb
Host smart-ac85ec30-da68-48d0-9871-5830e7566925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040476276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1040476276
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1031460397
Short name T1023
Test name
Test status
Simulation time 76513386959 ps
CPU time 928.03 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:13:17 PM PDT 24
Peak memory 225116 kb
Host smart-80856320-a520-4cc0-94fa-83fe8365d2b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031460397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1031460397
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.566805402
Short name T563
Test name
Test status
Simulation time 208366511467 ps
CPU time 1310.15 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:19:38 PM PDT 24
Peak memory 228924 kb
Host smart-68aa5601-5e57-4187-b8d4-ce7750604aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566805402 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.566805402
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2764736422
Short name T1068
Test name
Test status
Simulation time 95064281418 ps
CPU time 136.21 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:00:03 PM PDT 24
Peak memory 200216 kb
Host smart-9a7d18fa-43e3-4e4c-ab79-f134156532c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764736422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2764736422
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.132680259
Short name T357
Test name
Test status
Simulation time 25252697880 ps
CPU time 280.33 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 07:02:28 PM PDT 24
Peak memory 216880 kb
Host smart-c3de5f20-7f5b-47c5-a6aa-3784263a7bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132680259 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.132680259
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1716836303
Short name T866
Test name
Test status
Simulation time 96591263003 ps
CPU time 39.96 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:58:28 PM PDT 24
Peak memory 200168 kb
Host smart-aeaffb46-47ab-49a6-89e4-2282b1f2ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716836303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1716836303
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4253356487
Short name T600
Test name
Test status
Simulation time 8687822493 ps
CPU time 80.66 seconds
Started Jul 23 06:57:48 PM PDT 24
Finished Jul 23 06:59:11 PM PDT 24
Peak memory 216268 kb
Host smart-d0357525-0a4a-448e-899c-8872c64de740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253356487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4253356487
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3673462740
Short name T1047
Test name
Test status
Simulation time 225919954733 ps
CPU time 120.69 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:59:49 PM PDT 24
Peak memory 200232 kb
Host smart-b71c0394-3a94-4444-8a14-0552aeada886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673462740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3673462740
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2820025785
Short name T761
Test name
Test status
Simulation time 694491050468 ps
CPU time 997.95 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:14:27 PM PDT 24
Peak memory 232568 kb
Host smart-25acdef5-5a5e-46cf-8f1d-9d8a76a6a29a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820025785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2820025785
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.989052296
Short name T1142
Test name
Test status
Simulation time 35253341 ps
CPU time 0.58 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:51:19 PM PDT 24
Peak memory 195916 kb
Host smart-b2e5290c-d2bd-4cdb-97b9-a09a62b74e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989052296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.989052296
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.556067623
Short name T555
Test name
Test status
Simulation time 134653560729 ps
CPU time 82.8 seconds
Started Jul 23 06:51:17 PM PDT 24
Finished Jul 23 06:52:40 PM PDT 24
Peak memory 200252 kb
Host smart-e7122d4d-1dce-4541-8538-03800b307b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556067623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.556067623
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.889517506
Short name T678
Test name
Test status
Simulation time 32245798070 ps
CPU time 19.87 seconds
Started Jul 23 06:51:21 PM PDT 24
Finished Jul 23 06:51:42 PM PDT 24
Peak memory 199920 kb
Host smart-4b6a58d0-a778-4815-ad9c-acd0443461ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889517506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.889517506
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1748766526
Short name T975
Test name
Test status
Simulation time 26786048090 ps
CPU time 24.41 seconds
Started Jul 23 06:51:17 PM PDT 24
Finished Jul 23 06:51:42 PM PDT 24
Peak memory 200124 kb
Host smart-651fbb81-5e46-4100-bbc8-fbc14c3c82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748766526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1748766526
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4091290435
Short name T741
Test name
Test status
Simulation time 30016336886 ps
CPU time 66.13 seconds
Started Jul 23 06:51:14 PM PDT 24
Finished Jul 23 06:52:22 PM PDT 24
Peak memory 200196 kb
Host smart-83e12a4a-3c22-49d4-8eea-d64affdb0c3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091290435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4091290435
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3067178100
Short name T909
Test name
Test status
Simulation time 90075246592 ps
CPU time 619.28 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 07:01:38 PM PDT 24
Peak memory 200252 kb
Host smart-89150b5c-a51a-4d7e-8e4e-d26cff338ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067178100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3067178100
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3494361088
Short name T482
Test name
Test status
Simulation time 648224623 ps
CPU time 1.35 seconds
Started Jul 23 06:51:12 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 195740 kb
Host smart-be168209-3b26-4d9a-99b4-da159b9d5920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494361088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3494361088
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4005724830
Short name T339
Test name
Test status
Simulation time 143094214181 ps
CPU time 67.06 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:52:28 PM PDT 24
Peak memory 200264 kb
Host smart-22fc6213-69c2-4930-8dad-93b2a656d68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005724830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4005724830
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3853648926
Short name T525
Test name
Test status
Simulation time 12072657513 ps
CPU time 140.39 seconds
Started Jul 23 06:51:22 PM PDT 24
Finished Jul 23 06:53:45 PM PDT 24
Peak memory 200272 kb
Host smart-44bad7cb-968a-4dd1-8223-7fe2ec6bfb22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853648926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3853648926
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.900646554
Short name T681
Test name
Test status
Simulation time 2531884191 ps
CPU time 8.12 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:51:21 PM PDT 24
Peak memory 198284 kb
Host smart-92f83836-09a0-4aeb-b4fe-58614c159ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900646554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.900646554
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2260285382
Short name T562
Test name
Test status
Simulation time 51721179149 ps
CPU time 81.04 seconds
Started Jul 23 06:51:18 PM PDT 24
Finished Jul 23 06:52:40 PM PDT 24
Peak memory 200160 kb
Host smart-5d1da9a8-702e-4849-aeef-e3b1a9fc9497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260285382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2260285382
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4146621482
Short name T463
Test name
Test status
Simulation time 45948312740 ps
CPU time 37.5 seconds
Started Jul 23 06:51:20 PM PDT 24
Finished Jul 23 06:51:59 PM PDT 24
Peak memory 196572 kb
Host smart-60cffc2d-9ef4-4afa-88c6-4537659b9556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146621482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4146621482
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1347174787
Short name T707
Test name
Test status
Simulation time 929086320 ps
CPU time 1.5 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:51:16 PM PDT 24
Peak memory 199732 kb
Host smart-0b41e505-d519-42ba-b23e-973731f1c126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347174787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1347174787
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3934770568
Short name T755
Test name
Test status
Simulation time 90595548032 ps
CPU time 367.33 seconds
Started Jul 23 06:51:10 PM PDT 24
Finished Jul 23 06:57:21 PM PDT 24
Peak memory 216856 kb
Host smart-aa6a2dac-ae90-4f7a-9271-82ecef295f43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934770568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3934770568
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1177162380
Short name T897
Test name
Test status
Simulation time 7283980838 ps
CPU time 31.46 seconds
Started Jul 23 06:51:11 PM PDT 24
Finished Jul 23 06:51:45 PM PDT 24
Peak memory 200028 kb
Host smart-02b38d6e-1a09-4e13-a92c-cc41206e7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177162380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1177162380
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3051180452
Short name T545
Test name
Test status
Simulation time 19874152951 ps
CPU time 3.98 seconds
Started Jul 23 06:51:26 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 198216 kb
Host smart-46fe999d-132d-4aff-b654-0aa5f4cd8963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051180452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3051180452
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.748330939
Short name T599
Test name
Test status
Simulation time 16313845527 ps
CPU time 24.82 seconds
Started Jul 23 06:57:45 PM PDT 24
Finished Jul 23 06:58:12 PM PDT 24
Peak memory 200224 kb
Host smart-46915a70-fdf5-4ef5-99ff-560eef4d63dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748330939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.748330939
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3197537797
Short name T889
Test name
Test status
Simulation time 47588926143 ps
CPU time 247.24 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 07:01:57 PM PDT 24
Peak memory 216364 kb
Host smart-29a5270f-17bb-4ed2-812d-5ac62920bf05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197537797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3197537797
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3494444693
Short name T228
Test name
Test status
Simulation time 108016195673 ps
CPU time 167.68 seconds
Started Jul 23 06:57:46 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 200232 kb
Host smart-d571f838-f9b7-4ea2-bb13-cc62667c1c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494444693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3494444693
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2604784282
Short name T234
Test name
Test status
Simulation time 60742236495 ps
CPU time 79.84 seconds
Started Jul 23 06:57:48 PM PDT 24
Finished Jul 23 06:59:10 PM PDT 24
Peak memory 200228 kb
Host smart-e648b428-6632-4d9d-94c1-cf9f426c01f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604784282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2604784282
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.878469761
Short name T811
Test name
Test status
Simulation time 35886491346 ps
CPU time 351.48 seconds
Started Jul 23 06:57:47 PM PDT 24
Finished Jul 23 07:03:41 PM PDT 24
Peak memory 216508 kb
Host smart-28436c04-11a0-4fad-8861-a9259b7ff5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878469761 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.878469761
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3205785705
Short name T1138
Test name
Test status
Simulation time 10508157683 ps
CPU time 17.02 seconds
Started Jul 23 06:57:55 PM PDT 24
Finished Jul 23 06:58:13 PM PDT 24
Peak memory 199876 kb
Host smart-7eafb5f9-0c13-4d5f-a90c-f261ad7e45c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205785705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3205785705
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2250114443
Short name T1164
Test name
Test status
Simulation time 365422965791 ps
CPU time 567.4 seconds
Started Jul 23 06:57:54 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 216868 kb
Host smart-3f95814a-40b7-4db3-992f-54e7c555fe51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250114443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2250114443
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1856432665
Short name T1038
Test name
Test status
Simulation time 40177504099 ps
CPU time 36.35 seconds
Started Jul 23 06:57:53 PM PDT 24
Finished Jul 23 06:58:30 PM PDT 24
Peak memory 200256 kb
Host smart-c5208a8c-e653-455b-a435-9c5d760465df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856432665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1856432665
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2633647922
Short name T362
Test name
Test status
Simulation time 13881976578 ps
CPU time 17.75 seconds
Started Jul 23 06:57:51 PM PDT 24
Finished Jul 23 06:58:10 PM PDT 24
Peak memory 200232 kb
Host smart-c486a2b2-ff31-4a4f-886b-0f1258de4c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633647922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2633647922
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1080368076
Short name T1134
Test name
Test status
Simulation time 102564451619 ps
CPU time 356.25 seconds
Started Jul 23 06:57:57 PM PDT 24
Finished Jul 23 07:03:54 PM PDT 24
Peak memory 209576 kb
Host smart-a386523a-2cbc-4abe-91cb-d6a2fa7e8ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080368076 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1080368076
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1534745491
Short name T201
Test name
Test status
Simulation time 33019161855 ps
CPU time 19.82 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 06:58:17 PM PDT 24
Peak memory 200212 kb
Host smart-e662498c-db8f-4680-bef7-0ac0cb86d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534745491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1534745491
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1429161133
Short name T60
Test name
Test status
Simulation time 53212629153 ps
CPU time 258.51 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 07:02:15 PM PDT 24
Peak memory 211808 kb
Host smart-19e84b1a-cc31-4416-bdff-d59b8e4c2b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429161133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1429161133
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2437514296
Short name T44
Test name
Test status
Simulation time 17129992443 ps
CPU time 14.04 seconds
Started Jul 23 06:57:55 PM PDT 24
Finished Jul 23 06:58:10 PM PDT 24
Peak memory 200056 kb
Host smart-fef4f1bb-3d64-40c8-b73f-6a33496685cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437514296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2437514296
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4266984604
Short name T42
Test name
Test status
Simulation time 55146341947 ps
CPU time 256.03 seconds
Started Jul 23 06:57:55 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 213960 kb
Host smart-e4b59fbc-1a4e-4747-8575-3900a637241e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266984604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4266984604
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1971743407
Short name T210
Test name
Test status
Simulation time 93630966501 ps
CPU time 35.26 seconds
Started Jul 23 06:57:55 PM PDT 24
Finished Jul 23 06:58:32 PM PDT 24
Peak memory 200212 kb
Host smart-56fdd1f5-398b-4484-895d-8e54194380c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971743407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1971743407
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3071491125
Short name T967
Test name
Test status
Simulation time 24409044440 ps
CPU time 245.03 seconds
Started Jul 23 06:57:56 PM PDT 24
Finished Jul 23 07:02:02 PM PDT 24
Peak memory 216064 kb
Host smart-e07a0e8b-3b27-4453-ba21-8f41ffc3c01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071491125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3071491125
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1852269792
Short name T225
Test name
Test status
Simulation time 51743174747 ps
CPU time 124.69 seconds
Started Jul 23 06:57:53 PM PDT 24
Finished Jul 23 06:59:58 PM PDT 24
Peak memory 200220 kb
Host smart-3277213a-f233-4f0c-99f4-e5ca408b2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852269792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1852269792
Directory /workspace/99.uart_fifo_reset/latest
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