Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	106614	1			T1	350		T2	1		T3	2
all_values[1]	106614	1			T1	350		T2	1		T3	2
all_values[2]	106614	1			T1	350		T2	1		T3	2
all_values[3]	106614	1			T1	350		T2	1		T3	2
all_values[4]	106614	1			T1	350		T2	1		T3	2
all_values[5]	106614	1			T1	350		T2	1		T3	2
all_values[6]	106614	1			T1	350		T2	1		T3	2
all_values[7]	106614	1			T1	350		T2	1		T3	2
all_values[8]	106614	1			T1	350		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

487306

1

T1

1772

T2

4

T3

18

auto[1]

472220

1

T1

1378

T2

5

T5

594

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870066

1

T1

3000

T2

7

T3

13

auto[1]

89460

1

T1

150

T2

2

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29779	1			T1	163		T7	2		T9	30
all_values[0]	auto[0]	auto[1]	25222	1			T1	24		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	32468	1			T1	84		T7	82		T9	3
all_values[0]	auto[1]	auto[1]	19145	1			T1	79		T2	1		T5	18
all_values[1]	auto[0]	auto[0]	54212	1			T1	217		T3	2		T4	2
all_values[1]	auto[0]	auto[1]	1541	1			T9	4		T20	11		T35	7
all_values[1]	auto[1]	auto[0]	49258	1			T1	133		T2	1		T5	5
all_values[1]	auto[1]	auto[1]	1603	1			T5	35		T10	1		T15	15
all_values[2]	auto[0]	auto[0]	50661	1			T1	128		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2891	1			T3	1		T4	1		T7	6
all_values[2]	auto[1]	auto[0]	50583	1			T1	219		T5	138		T7	35
all_values[2]	auto[1]	auto[1]	2479	1			T1	3		T5	6		T7	13
all_values[3]	auto[0]	auto[0]	49284	1			T1	162		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	303	1			T5	3		T13	1		T12	1
all_values[3]	auto[1]	auto[0]	56677	1			T1	188		T2	1		T5	6
all_values[3]	auto[1]	auto[1]	350	1			T10	1		T13	1		T17	1
all_values[4]	auto[0]	auto[0]	55699	1			T1	318		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	425	1			T10	1		T13	4		T17	10
all_values[4]	auto[1]	auto[0]	50014	1			T1	32		T5	40		T6	1
all_values[4]	auto[1]	auto[1]	476	1			T15	10		T13	1		T12	9
all_values[5]	auto[0]	auto[0]	53249	1			T1	3		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	214	1			T10	1		T13	3		T19	4
all_values[5]	auto[1]	auto[0]	52965	1			T1	347		T2	1		T5	18
all_values[5]	auto[1]	auto[1]	186	1			T13	2		T28	2		T30	2
all_values[6]	auto[0]	auto[0]	55796	1			T1	348		T3	2		T4	2
all_values[6]	auto[0]	auto[1]	201	1			T13	3		T19	4		T113	2
all_values[6]	auto[1]	auto[0]	50404	1			T1	2		T2	1		T5	124
all_values[6]	auto[1]	auto[1]	213	1			T10	2		T13	2		T28	2
all_values[7]	auto[0]	auto[0]	54694	1			T1	187		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	350	1			T10	2		T125	1		T244	9
all_values[7]	auto[1]	auto[0]	51203	1			T1	163		T5	162		T7	28
all_values[7]	auto[1]	auto[1]	367	1			T10	3		T12	9		T28	3
all_values[8]	auto[0]	auto[0]	34870	1			T1	183		T5	39		T7	101
all_values[8]	auto[0]	auto[1]	17915	1			T1	39		T2	1		T3	2
all_values[8]	auto[1]	auto[0]	38250	1			T1	123		T9	15		T10	17
all_values[8]	auto[1]	auto[1]	15579	1			T1	5		T5	42		T7	11