Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2220	1			T2	6		T5	1		T6	12
auto[BaudRate115200]	2009	1			T1	1		T3	1		T4	1
auto[BaudRate230400]	2004	1			T6	9		T7	3		T8	2
auto[BaudRate128Kbps]	1877	1			T4	1		T5	1		T6	6
auto[BaudRate256Kbps]	2233	1			T1	2		T5	1		T6	15
auto[BaudRate1Mbps]	1764	1			T3	1		T5	2		T6	6
auto[BaudRate1p5Mbps]	1369	1			T1	2		T7	1		T9	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1458	1			T6	54		T9	8		T17	1
freqs[25]	1151	1			T294	2		T278	2		T269	2
freqs[48]	602	1			T13	21		T118	9		T117	8
freqs[50]	472	1			T1	5		T39	5		T96	2
freqs[100]	1342	1			T35	7		T16	10		T125	46

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	273	1			T6	12		T18	1		T131	1
auto[BaudRate9600]	freqs[25]	201	1			T94	1		T251	3		T137	2
auto[BaudRate9600]	freqs[48]	111	1			T13	1		T113	2		T311	1
auto[BaudRate9600]	freqs[50]	65	1			T96	2		T274	1		T121	1
auto[BaudRate9600]	freqs[100]	205	1			T35	1		T16	10		T125	9
auto[BaudRate115200]	freqs[24]	210	1			T6	6		T18	1		T29	2
auto[BaudRate115200]	freqs[25]	154	1			T269	1		T251	3		T137	2
auto[BaudRate115200]	freqs[48]	81	1			T13	6		T118	3		T117	1
auto[BaudRate115200]	freqs[50]	78	1			T1	1		T46	4		T114	13
auto[BaudRate115200]	freqs[100]	219	1			T35	1		T125	10		T119	2
auto[BaudRate230400]	freqs[24]	198	1			T6	9		T17	1		T18	2
auto[BaudRate230400]	freqs[25]	169	1			T278	1		T269	1		T129	3
auto[BaudRate230400]	freqs[48]	80	1			T13	5		T118	5		T117	3
auto[BaudRate230400]	freqs[50]	60	1			T46	1		T114	3		T275	1
auto[BaudRate230400]	freqs[100]	190	1			T35	2		T125	10		T107	2
auto[BaudRate128Kbps]	freqs[24]	201	1			T6	6		T18	3		T131	1
auto[BaudRate128Kbps]	freqs[25]	163	1			T251	1		T129	2		T289	2
auto[BaudRate128Kbps]	freqs[48]	70	1			T13	1		T117	1		T113	1
auto[BaudRate128Kbps]	freqs[50]	73	1			T121	1		T46	3		T114	6
auto[BaudRate128Kbps]	freqs[100]	165	1			T35	1		T125	1		T119	2
auto[BaudRate256Kbps]	freqs[24]	238	1			T6	15		T9	2		T18	5
auto[BaudRate256Kbps]	freqs[25]	182	1			T294	1		T251	1		T289	2
auto[BaudRate256Kbps]	freqs[48]	60	1			T13	2		T113	2		T311	1
auto[BaudRate256Kbps]	freqs[50]	68	1			T1	2		T39	2		T114	6
auto[BaudRate256Kbps]	freqs[100]	208	1			T125	5		T119	3		T120	5
auto[BaudRate1Mbps]	freqs[24]	219	1			T6	6		T9	4		T18	7
auto[BaudRate1Mbps]	freqs[25]	183	1			T278	1		T251	2		T289	3
auto[BaudRate1Mbps]	freqs[48]	95	1			T13	2		T117	1		T113	4
auto[BaudRate1Mbps]	freqs[50]	52	1			T274	1		T121	4		T114	4
auto[BaudRate1Mbps]	freqs[100]	185	1			T35	2		T125	4		T119	1
auto[BaudRate1p5Mbps]	freqs[25]	99	1			T294	1		T94	1		T251	1
auto[BaudRate1p5Mbps]	freqs[48]	105	1			T13	4		T118	1		T117	2
auto[BaudRate1p5Mbps]	freqs[50]	76	1			T1	2		T39	3		T46	5
auto[BaudRate1p5Mbps]	freqs[100]	170	1			T125	7		T119	2		T120	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded