Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28417597	1			T1	68075		T2	1		T5	328
all_levels[1]	203185	1			T1	1		T5	3		T7	87
all_levels[2]	2639	1			T7	8		T9	17		T10	2
all_levels[3]	1120	1			T7	3		T15	6		T36	2
all_levels[4]	723	1			T5	2		T15	3		T36	1
all_levels[5]	534	1			T15	2		T37	5		T38	3
all_levels[6]	428	1			T5	1		T20	1		T15	5
all_levels[7]	333	1			T5	3		T15	1		T36	1
all_levels[8]	291	1			T15	5		T13	3		T40	1
all_levels[9]	260	1			T5	2		T15	2		T37	4
all_levels[10]	219	1			T8	1		T15	3		T37	1
all_levels[11]	188	1			T20	1		T35	1		T15	3
all_levels[12]	146	1			T5	1		T37	1		T13	1
all_levels[13]	154	1			T5	1		T20	2		T15	1
all_levels[14]	147	1			T20	2		T35	5		T15	1
all_levels[15]	118	1			T15	1		T37	1		T117	2
all_levels[16]	109	1			T15	1		T13	1		T118	1
all_levels[17]	101	1			T5	4		T118	1		T119	1
all_levels[18]	88	1			T20	1		T118	1		T29	1
all_levels[19]	71	1			T20	1		T104	1		T120	1
all_levels[20]	80	1			T118	1		T121	4		T122	1
all_levels[21]	70	1			T118	2		T123	1		T104	1
all_levels[22]	63	1			T13	1		T124	1		T31	1
all_levels[23]	61	1			T13	1		T125	2		T119	1
all_levels[24]	47	1			T8	1		T126	1		T127	2
all_levels[25]	59	1			T117	2		T128	1		T127	1
all_levels[26]	38	1			T35	1		T13	1		T127	1
all_levels[27]	35	1			T8	1		T15	1		T119	1
all_levels[28]	41	1			T15	1		T119	1		T45	1
all_levels[29]	44	1			T10	1		T129	1		T126	2
all_levels[30]	42	1			T88	3		T29	1		T48	1
all_levels[31]	30	1			T31	1		T48	1		T34	1
all_levels[32]	45	1			T130	1		T131	1		T129	1
all_levels[33]	37	1			T118	1		T18	2		T132	1
all_levels[34]	37	1			T128	1		T126	1		T133	1
all_levels[35]	26	1			T5	1		T31	1		T134	1
all_levels[36]	25	1			T35	2		T13	2		T133	1
all_levels[37]	12	1			T122	1		T135	1		T136	1
all_levels[38]	24	1			T137	1		T138	1		T139	1
all_levels[39]	21	1			T128	1		T106	1		T129	1
all_levels[40]	18	1			T10	1		T104	1		T140	1
all_levels[41]	14	1			T125	1		T42	1		T140	1
all_levels[42]	16	1			T125	1		T141	1		T139	1
all_levels[43]	14	1			T13	1		T99	1		T142	1
all_levels[44]	17	1			T120	1		T43	1		T109	4
all_levels[45]	26	1			T137	1		T143	1		T139	1
all_levels[46]	10	1			T10	1		T144	1		T145	3
all_levels[47]	17	1			T144	1		T146	1		T147	1
all_levels[48]	10	1			T148	1		T149	1		T150	1
all_levels[49]	9	1			T29	2		T139	1		T52	2
all_levels[50]	7	1			T151	1		T139	1		T152	1
all_levels[51]	17	1			T123	1		T104	1		T18	1
all_levels[52]	7	1			T128	1		T129	1		T132	1
all_levels[53]	6	1			T153	1		T154	2		T155	1
all_levels[54]	12	1			T132	1		T156	1		T157	2
all_levels[55]	12	1			T158	1		T159	2		T160	1
all_levels[56]	12	1			T161	1		T162	2		T152	2
all_levels[57]	8	1			T134	1		T151	1		T163	1
all_levels[58]	4	1			T43	1		T164	1		T165	1
all_levels[59]	8	1			T91	1		T166	1		T167	1
all_levels[60]	6	1			T13	1		T168	1		T169	1
all_levels[61]	4	1			T13	1		T129	1		T170	1
all_levels[62]	14	1			T130	1		T103	1		T171	2
all_levels[63]	10	1			T171	1		T172	1		T173	1
all_levels[64]	126	1			T10	2		T174	3		T108	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28625074

1

T1

68076

T5

340

T7

1487

auto[1]

4618

1

T2

1

T5

6

T6

12

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[24]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[52] , all_levels[53]]	[auto[1]]	--	--	2
[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28413450	1			T1	68075		T5	323		T7	1389
all_levels[0]	auto[1]	4147	1			T2	1		T5	5		T6	12
all_levels[1]	auto[0]	203101	1			T1	1		T5	3		T7	87
all_levels[1]	auto[1]	84	1			T35	1		T130	1		T90	4
all_levels[2]	auto[0]	2608	1			T7	8		T9	17		T10	2
all_levels[2]	auto[1]	31	1			T140	1		T175	2		T176	1
all_levels[3]	auto[0]	1093	1			T7	3		T15	6		T36	2
all_levels[3]	auto[1]	27	1			T117	3		T119	1		T174	1
all_levels[4]	auto[0]	700	1			T5	2		T15	3		T36	1
all_levels[4]	auto[1]	23	1			T177	1		T178	4		T179	1
all_levels[5]	auto[0]	524	1			T15	2		T37	5		T38	3
all_levels[5]	auto[1]	10	1			T180	1		T176	1		T181	1
all_levels[6]	auto[0]	409	1			T5	1		T20	1		T15	5
all_levels[6]	auto[1]	19	1			T126	2		T182	2		T183	1
all_levels[7]	auto[0]	319	1			T5	3		T15	1		T36	1
all_levels[7]	auto[1]	14	1			T120	1		T127	1		T184	2
all_levels[8]	auto[0]	282	1			T15	5		T13	3		T40	1
all_levels[8]	auto[1]	9	1			T183	1		T185	1		T186	2
all_levels[9]	auto[0]	244	1			T5	2		T15	2		T37	4
all_levels[9]	auto[1]	16	1			T127	1		T34	1		T187	4
all_levels[10]	auto[0]	200	1			T8	1		T15	3		T37	1
all_levels[10]	auto[1]	19	1			T119	1		T188	2		T161	1
all_levels[11]	auto[0]	177	1			T20	1		T35	1		T15	3
all_levels[11]	auto[1]	11	1			T106	1		T91	1		T145	1
all_levels[12]	auto[0]	140	1			T5	1		T37	1		T13	1
all_levels[12]	auto[1]	6	1			T140	1		T189	2		T190	1
all_levels[13]	auto[0]	138	1			T5	1		T20	1		T15	1
all_levels[13]	auto[1]	16	1			T20	1		T191	1		T192	1
all_levels[14]	auto[0]	134	1			T20	2		T35	1		T15	1
all_levels[14]	auto[1]	13	1			T35	4		T174	1		T126	2
all_levels[15]	auto[0]	109	1			T15	1		T37	1		T117	1
all_levels[15]	auto[1]	9	1			T117	1		T120	1		T139	2
all_levels[16]	auto[0]	106	1			T15	1		T13	1		T118	1
all_levels[16]	auto[1]	3	1			T193	1		T194	2		-	-
all_levels[17]	auto[0]	92	1			T5	3		T118	1		T119	1
all_levels[17]	auto[1]	9	1			T5	1		T195	3		T193	1
all_levels[18]	auto[0]	75	1			T20	1		T118	1		T29	1
all_levels[18]	auto[1]	13	1			T185	1		T161	1		T196	1
all_levels[19]	auto[0]	69	1			T20	1		T104	1		T120	1
all_levels[19]	auto[1]	2	1			T197	1		T198	1		-	-
all_levels[20]	auto[0]	75	1			T118	1		T121	1		T122	1
all_levels[20]	auto[1]	5	1			T121	3		T199	1		T200	1
all_levels[21]	auto[0]	62	1			T118	1		T123	1		T104	1
all_levels[21]	auto[1]	8	1			T118	1		T187	1		T201	1
all_levels[22]	auto[0]	56	1			T13	1		T124	1		T31	1
all_levels[22]	auto[1]	7	1			T202	1		T203	1		T204	1
all_levels[23]	auto[0]	55	1			T13	1		T125	2		T119	1
all_levels[23]	auto[1]	6	1			T179	2		T205	3		T206	1
all_levels[24]	auto[0]	47	1			T8	1		T126	1		T127	2
all_levels[25]	auto[0]	53	1			T117	1		T128	1		T127	1
all_levels[25]	auto[1]	6	1			T117	1		T145	1		T207	1
all_levels[26]	auto[0]	36	1			T35	1		T13	1		T127	1
all_levels[26]	auto[1]	2	1			T208	1		T209	1		-	-
all_levels[27]	auto[0]	32	1			T8	1		T15	1		T119	1
all_levels[27]	auto[1]	3	1			T210	1		T211	1		T212	1
all_levels[28]	auto[0]	40	1			T15	1		T119	1		T45	1
all_levels[28]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[29]	auto[0]	39	1			T10	1		T129	1		T126	1
all_levels[29]	auto[1]	5	1			T126	1		T214	2		T203	1
all_levels[30]	auto[0]	37	1			T88	1		T29	1		T48	1
all_levels[30]	auto[1]	5	1			T88	2		T192	1		T215	1
all_levels[31]	auto[0]	29	1			T31	1		T48	1		T34	1
all_levels[31]	auto[1]	1	1			T216	1		-	-		-	-
all_levels[32]	auto[0]	39	1			T130	1		T131	1		T129	1
all_levels[32]	auto[1]	6	1			T217	1		T203	1		T218	2
all_levels[33]	auto[0]	31	1			T118	1		T18	1		T132	1
all_levels[33]	auto[1]	6	1			T18	1		T219	1		T220	1
all_levels[34]	auto[0]	33	1			T128	1		T126	1		T133	1
all_levels[34]	auto[1]	4	1			T221	2		T222	2		-	-
all_levels[35]	auto[0]	21	1			T5	1		T31	1		T134	1
all_levels[35]	auto[1]	5	1			T133	1		T172	2		T112	1
all_levels[36]	auto[0]	23	1			T35	1		T13	2		T133	1
all_levels[36]	auto[1]	2	1			T35	1		T223	1		-	-
all_levels[37]	auto[0]	10	1			T122	1		T135	1		T136	1
all_levels[37]	auto[1]	2	1			T207	2		-	-		-	-
all_levels[38]	auto[0]	21	1			T137	1		T138	1		T139	1
all_levels[38]	auto[1]	3	1			T224	1		T225	2		-	-
all_levels[39]	auto[0]	18	1			T128	1		T106	1		T129	1
all_levels[39]	auto[1]	3	1			T167	1		T52	2		-	-
all_levels[40]	auto[0]	17	1			T10	1		T104	1		T140	1
all_levels[40]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[41]	auto[0]	13	1			T125	1		T42	1		T140	1
all_levels[41]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[42]	auto[0]	14	1			T125	1		T141	1		T139	1
all_levels[42]	auto[1]	2	1			T52	2		-	-		-	-
all_levels[43]	auto[0]	14	1			T13	1		T99	1		T142	1
all_levels[44]	auto[0]	13	1			T120	1		T43	1		T109	1
all_levels[44]	auto[1]	4	1			T109	3		T227	1		-	-
all_levels[45]	auto[0]	20	1			T137	1		T143	1		T139	1
all_levels[45]	auto[1]	6	1			T228	2		T229	2		T230	1
all_levels[46]	auto[0]	8	1			T10	1		T144	1		T145	1
all_levels[46]	auto[1]	2	1			T145	2		-	-		-	-
all_levels[47]	auto[0]	12	1			T144	1		T146	1		T147	1
all_levels[47]	auto[1]	5	1			T231	1		T155	1		T232	3
all_levels[48]	auto[0]	8	1			T148	1		T149	1		T150	1
all_levels[48]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[49]	auto[0]	8	1			T29	2		T139	1		T52	1
all_levels[49]	auto[1]	1	1			T52	1		-	-		-	-
all_levels[50]	auto[0]	7	1			T151	1		T139	1		T152	1
all_levels[51]	auto[0]	14	1			T123	1		T104	1		T18	1
all_levels[51]	auto[1]	3	1			T234	1		T235	1		T236	1
all_levels[52]	auto[0]	7	1			T128	1		T129	1		T132	1
all_levels[53]	auto[0]	6	1			T153	1		T154	2		T155	1
all_levels[54]	auto[0]	11	1			T132	1		T156	1		T157	2
all_levels[54]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[55]	auto[0]	10	1			T158	1		T159	2		T160	1
all_levels[55]	auto[1]	2	1			T238	1		T239	1		-	-
all_levels[56]	auto[0]	10	1			T161	1		T162	1		T152	2
all_levels[56]	auto[1]	2	1			T162	1		T240	1		-	-
all_levels[57]	auto[0]	7	1			T134	1		T151	1		T163	1
all_levels[57]	auto[1]	1	1			T54	1		-	-		-	-
all_levels[58]	auto[0]	4	1			T43	1		T164	1		T165	1
all_levels[59]	auto[0]	8	1			T91	1		T166	1		T167	1
all_levels[60]	auto[0]	6	1			T13	1		T168	1		T169	1
all_levels[61]	auto[0]	4	1			T13	1		T129	1		T170	1
all_levels[62]	auto[0]	10	1			T130	1		T103	1		T171	1
all_levels[62]	auto[1]	4	1			T171	1		T241	1		T242	2
all_levels[63]	auto[0]	9	1			T171	1		T172	1		T173	1
all_levels[63]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[64]	auto[0]	107	1			T10	2		T174	2		T108	1
all_levels[64]	auto[1]	19	1			T174	1		T108	4		T42	1