Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1202 1 T9 3 T20 11 T35 7
all_levels[1] 561 1 T15 12 T17 14 T91 9
all_levels[2] 505 1 T5 35 T15 2 T104 11
all_levels[3] 388 1 T13 2 T12 21 T105 22
all_levels[4] 271 1 T10 1 T106 2 T95 6
all_levels[5] 139 1 T107 2 T108 7 T109 2
all_levels[6] 57 1 T110 8 T111 1 T112 10

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%