Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	106614	1			T1	350		T2	1		T3	2
all_pins[1]	106614	1			T1	350		T2	1		T3	2
all_pins[2]	106614	1			T1	350		T2	1		T3	2
all_pins[3]	106614	1			T1	350		T2	1		T3	2
all_pins[4]	106614	1			T1	350		T2	1		T3	2
all_pins[5]	106614	1			T1	350		T2	1		T3	2
all_pins[6]	106614	1			T1	350		T2	1		T3	2
all_pins[7]	106614	1			T1	350		T2	1		T3	2
all_pins[8]	106614	1			T1	350		T2	1		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	918170	1			T1	3063		T2	8		T3	18
values[0x1]	41356	1			T1	87		T2	1		T5	101
transitions[0x0=>0x1]	32607	1			T1	82		T2	1		T5	100
transitions[0x1=>0x0]	32403	1			T1	81		T5	100		T7	52

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87379	1			T1	271		T3	2		T4	2
all_pins[0]	values[0x1]	19235	1			T1	79		T2	1		T5	18
all_pins[0]	transitions[0x0=>0x1]	18720	1			T1	79		T2	1		T5	18
all_pins[0]	transitions[0x1=>0x0]	1085	1			T5	35		T10	1		T15	15
all_pins[1]	values[0x0]	105014	1			T1	350		T2	1		T3	2
all_pins[1]	values[0x1]	1600	1			T5	35		T10	1		T15	15
all_pins[1]	transitions[0x0=>0x1]	1445	1			T5	35		T15	15		T13	11
all_pins[1]	transitions[0x1=>0x0]	2378	1			T1	3		T5	6		T7	13
all_pins[2]	values[0x0]	104081	1			T1	347		T2	1		T3	2
all_pins[2]	values[0x1]	2533	1			T1	3		T5	6		T7	13
all_pins[2]	transitions[0x0=>0x1]	2452	1			T1	3		T5	6		T7	13
all_pins[2]	transitions[0x1=>0x0]	269	1			T13	1		T17	1		T108	3
all_pins[3]	values[0x0]	106264	1			T1	350		T2	1		T3	2
all_pins[3]	values[0x1]	350	1			T10	1		T13	1		T17	1
all_pins[3]	transitions[0x0=>0x1]	301	1			T10	1		T13	1		T17	1
all_pins[3]	transitions[0x1=>0x0]	427	1			T15	10		T13	1		T12	9
all_pins[4]	values[0x0]	106138	1			T1	350		T2	1		T3	2
all_pins[4]	values[0x1]	476	1			T15	10		T13	1		T12	9
all_pins[4]	transitions[0x0=>0x1]	405	1			T15	10		T12	7		T244	10
all_pins[4]	transitions[0x1=>0x0]	174	1			T13	1		T28	2		T30	2
all_pins[5]	values[0x0]	106369	1			T1	350		T2	1		T3	2
all_pins[5]	values[0x1]	245	1			T13	2		T12	2		T95	1
all_pins[5]	transitions[0x0=>0x1]	187	1			T13	1		T12	2		T95	1
all_pins[5]	transitions[0x1=>0x0]	820	1			T10	2		T15	3		T13	3
all_pins[6]	values[0x0]	105736	1			T1	350		T2	1		T3	2
all_pins[6]	values[0x1]	878	1			T10	2		T15	3		T13	4
all_pins[6]	transitions[0x0=>0x1]	823	1			T10	2		T15	3		T13	4
all_pins[6]	transitions[0x1=>0x0]	312	1			T10	3		T12	9		T28	1
all_pins[7]	values[0x0]	106247	1			T1	350		T2	1		T3	2
all_pins[7]	values[0x1]	367	1			T10	3		T12	9		T28	3
all_pins[7]	transitions[0x0=>0x1]	176	1			T10	3		T111	2		T114	2
all_pins[7]	transitions[0x1=>0x0]	15481	1			T1	5		T5	42		T7	11
all_pins[8]	values[0x0]	90942	1			T1	345		T2	1		T3	2
all_pins[8]	values[0x1]	15672	1			T1	5		T5	42		T7	11
all_pins[8]	transitions[0x0=>0x1]	8098	1			T5	41		T7	11		T8	1
all_pins[8]	transitions[0x1=>0x0]	11457	1			T1	73		T5	17		T7	28