Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6934844	1			T1	15435		T5	272		T7	432
all_levels[1]	1941507	1			T1	1572		T5	5		T7	83
all_levels[2]	367502	1			T1	1567		T5	5		T7	134
all_levels[3]	260309	1			T1	1559		T5	9		T7	66
all_levels[4]	302399	1			T1	1572		T5	2		T7	31
all_levels[5]	314052	1			T1	1575		T5	2		T7	41
all_levels[6]	356026	1			T1	1574		T5	11		T7	22
all_levels[7]	253889	1			T1	1572		T5	7		T7	3
all_levels[8]	516182	1			T1	1572		T5	6		T7	91
all_levels[9]	200935	1			T1	1566		T5	2		T7	1
all_levels[10]	523090	1			T1	1568		T5	4		T7	3
all_levels[11]	208930	1			T1	1569		T5	1		T7	1
all_levels[12]	367310	1			T1	1569		T5	3		T7	1
all_levels[13]	289338	1			T1	1575		T5	5		T9	19
all_levels[14]	266750	1			T1	1566		T5	2		T9	23
all_levels[15]	287896	1			T1	1570		T5	3		T7	73
all_levels[16]	346458	1			T1	1576		T7	22		T9	23
all_levels[17]	276973	1			T1	1559		T7	24		T9	26
all_levels[18]	177784	1			T1	1575		T7	15		T8	4
all_levels[19]	181357	1			T1	1563		T7	18		T9	21
all_levels[20]	181770	1			T1	1574		T5	2		T7	14
all_levels[21]	465562	1			T1	1575		T5	1		T7	17
all_levels[22]	171536	1			T1	1541		T7	8		T9	25
all_levels[23]	278413	1			T1	1577		T7	9		T9	25
all_levels[24]	191953	1			T1	2538		T7	9		T9	18
all_levels[25]	166976	1			T1	1574		T7	18		T9	22
all_levels[26]	197294	1			T1	1575		T7	22		T8	1
all_levels[27]	203793	1			T1	1572		T5	2		T7	10
all_levels[28]	229425	1			T1	1566		T5	2		T7	27
all_levels[29]	309878	1			T1	1575		T7	11		T9	19
all_levels[30]	147095	1			T1	1577		T7	160		T9	19
all_levels[31]	619771	1			T1	1744		T7	27		T9	604
all_levels[32]	11092422	1			T1	2835		T7	95		T8	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28625074

1

T1

68076

T5

340

T7

1487

auto[1]

4345

1

T1

1

T5

6

T7

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6932280	1			T1	15434		T5	268		T7	432
all_levels[0]	auto[1]	2564	1			T1	1		T5	4		T10	2
all_levels[1]	auto[0]	1941222	1			T1	1572		T5	5		T7	83
all_levels[1]	auto[1]	285	1			T20	1		T38	1		T118	1
all_levels[2]	auto[0]	367468	1			T1	1567		T5	5		T7	134
all_levels[2]	auto[1]	34	1			T129	2		T180	1		T325	1
all_levels[3]	auto[0]	260151	1			T1	1559		T5	9		T7	66
all_levels[3]	auto[1]	158	1			T244	19		T90	2		T134	1
all_levels[4]	auto[0]	302366	1			T1	1572		T5	2		T7	31
all_levels[4]	auto[1]	33	1			T253	1		T119	1		T104	1
all_levels[5]	auto[0]	314038	1			T1	1575		T5	2		T7	41
all_levels[5]	auto[1]	14	1			T46	1		T283	1		T188	2
all_levels[6]	auto[0]	355999	1			T1	1574		T5	11		T7	22
all_levels[6]	auto[1]	27	1			T253	1		T140	1		T138	1
all_levels[7]	auto[0]	253800	1			T1	1572		T5	7		T7	3
all_levels[7]	auto[1]	89	1			T13	6		T107	4		T95	2
all_levels[8]	auto[0]	516160	1			T1	1572		T5	6		T7	91
all_levels[8]	auto[1]	22	1			T13	1		T130	1		T18	2
all_levels[9]	auto[0]	200905	1			T1	1566		T5	2		T7	1
all_levels[9]	auto[1]	30	1			T90	3		T129	1		T326	3
all_levels[10]	auto[0]	523060	1			T1	1568		T5	4		T7	3
all_levels[10]	auto[1]	30	1			T251	1		T120	1		T113	1
all_levels[11]	auto[0]	208900	1			T1	1569		T5	1		T7	1
all_levels[11]	auto[1]	30	1			T127	1		T182	3		T191	2
all_levels[12]	auto[0]	367280	1			T1	1569		T5	3		T7	1
all_levels[12]	auto[1]	30	1			T20	2		T130	2		T319	1
all_levels[13]	auto[0]	289312	1			T1	1575		T5	3		T9	19
all_levels[13]	auto[1]	26	1			T5	2		T140	1		T325	1
all_levels[14]	auto[0]	266730	1			T1	1566		T5	2		T9	23
all_levels[14]	auto[1]	20	1			T253	1		T142	1		T195	1
all_levels[15]	auto[0]	287764	1			T1	1570		T5	3		T7	73
all_levels[15]	auto[1]	132	1			T125	1		T276	1		T113	8
all_levels[16]	auto[0]	346444	1			T1	1576		T7	22		T9	23
all_levels[16]	auto[1]	14	1			T174	1		T264	1		T327	1
all_levels[17]	auto[0]	276954	1			T1	1559		T7	24		T9	26
all_levels[17]	auto[1]	19	1			T128	1		T29	1		T126	1
all_levels[18]	auto[0]	177757	1			T1	1575		T7	15		T8	4
all_levels[18]	auto[1]	27	1			T106	2		T288	3		T109	4
all_levels[19]	auto[0]	181331	1			T1	1563		T7	18		T9	21
all_levels[19]	auto[1]	26	1			T317	4		T328	2		T141	2
all_levels[20]	auto[0]	181746	1			T1	1574		T5	2		T7	14
all_levels[20]	auto[1]	24	1			T121	2		T127	1		T158	1
all_levels[21]	auto[0]	465530	1			T1	1575		T5	1		T7	17
all_levels[21]	auto[1]	32	1			T252	1		T123	1		T286	2
all_levels[22]	auto[0]	171510	1			T1	1541		T7	8		T9	25
all_levels[22]	auto[1]	26	1			T151	1		T329	3		T292	1
all_levels[23]	auto[0]	278407	1			T1	1577		T7	9		T9	25
all_levels[23]	auto[1]	6	1			T34	1		T330	1		T135	1
all_levels[24]	auto[0]	191936	1			T1	2538		T7	9		T9	18
all_levels[24]	auto[1]	17	1			T174	1		T120	2		T180	1
all_levels[25]	auto[0]	166967	1			T1	1574		T7	18		T9	22
all_levels[25]	auto[1]	9	1			T108	1		T182	1		T314	1
all_levels[26]	auto[0]	197279	1			T1	1575		T7	22		T8	1
all_levels[26]	auto[1]	15	1			T264	1		T331	2		T332	1
all_levels[27]	auto[0]	203779	1			T1	1572		T5	2		T7	10
all_levels[27]	auto[1]	14	1			T18	3		T120	1		T103	1
all_levels[28]	auto[0]	229390	1			T1	1566		T5	2		T7	27
all_levels[28]	auto[1]	35	1			T124	1		T91	2		T317	1
all_levels[29]	auto[0]	309856	1			T1	1575		T7	11		T9	19
all_levels[29]	auto[1]	22	1			T128	1		T176	1		T325	2
all_levels[30]	auto[0]	147079	1			T1	1577		T7	159		T9	19
all_levels[30]	auto[1]	16	1			T7	1		T333	2		T183	1
all_levels[31]	auto[0]	619748	1			T1	1744		T7	27		T9	604
all_levels[31]	auto[1]	23	1			T38	2		T123	1		T42	1
all_levels[32]	auto[0]	11091926	1			T1	2835		T7	95		T8	2
all_levels[32]	auto[1]	496	1			T20	2		T35	5		T37	1