Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	841	1			T10	4		T13	7		T19	4
all_values[1]	841	1			T10	4		T13	7		T19	4
all_values[2]	841	1			T10	4		T13	7		T19	4
all_values[3]	841	1			T10	4		T13	7		T19	4
all_values[4]	841	1			T10	4		T13	7		T19	4
all_values[5]	841	1			T10	4		T13	7		T19	4
all_values[6]	841	1			T10	4		T13	7		T19	4
all_values[7]	841	1			T10	4		T13	7		T19	4
all_values[8]	841	1			T10	4		T13	7		T19	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4042

1

T10

22

T13

34

T19

26

auto[1]

3527

1

T10

14

T13

29

T19

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2416

1

T10

13

T13

21

T19

10

auto[1]

5153

1

T10

23

T13

42

T19

26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4456

1

T10

21

T13

36

T19

22

auto[1]

3113

1

T10

15

T13

27

T19

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	235	1			T10	1		T13	1		T28	4
all_values[0]	auto[0]	auto[1]	auto[1]	255	1			T10	2		T13	2		T19	3
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T10	1		T13	1		T19	1
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T13	3		T28	2		T32	1
all_values[1]	auto[0]	auto[0]	auto[0]	276	1			T10	2		T19	1		T28	5
all_values[1]	auto[0]	auto[1]	auto[0]	215	1			T10	1		T13	3		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T13	1		T28	1		T113	1
all_values[1]	auto[1]	auto[1]	auto[1]	187	1			T10	1		T13	3		T19	2
all_values[2]	auto[0]	auto[0]	auto[0]	170	1			T10	1		T13	4		T19	1
all_values[2]	auto[0]	auto[0]	auto[1]	95	1			T10	1		T19	2		T114	1
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T13	2		T113	3		T30	1
all_values[2]	auto[0]	auto[1]	auto[1]	87	1			T28	4		T32	1		T111	1
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T10	2		T19	1		T28	1
all_values[2]	auto[1]	auto[1]	auto[1]	140	1			T13	1		T28	2		T32	2
all_values[3]	auto[0]	auto[0]	auto[0]	179	1			T10	3		T13	2		T19	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T30	1		T111	1		T114	1
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T13	2		T19	1		T28	3
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T111	1		T114	1
all_values[3]	auto[1]	auto[0]	auto[1]	161	1			T10	1		T19	1		T28	2
all_values[3]	auto[1]	auto[1]	auto[1]	187	1			T13	2		T32	1		T111	1
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T10	1		T13	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T13	2		T28	1		T114	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T10	1		T19	2		T28	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T28	1		T113	1		T102	2
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T10	1		T13	2		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T10	1		T13	2		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	183	1			T30	2		T32	1		T102	2
all_values[5]	auto[0]	auto[0]	auto[1]	93	1			T13	2		T19	1		T28	1
all_values[5]	auto[0]	auto[1]	auto[0]	134	1			T10	2		T113	1		T103	1
all_values[5]	auto[0]	auto[1]	auto[1]	81	1			T13	2		T28	2		T30	1
all_values[5]	auto[1]	auto[0]	auto[1]	220	1			T13	1		T19	3		T28	4
all_values[5]	auto[1]	auto[1]	auto[1]	130	1			T10	2		T13	2		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T10	2		T13	1		T28	3
all_values[6]	auto[0]	auto[0]	auto[1]	100	1			T13	2		T19	3		T113	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T28	2		T113	1		T30	2
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T10	1		T28	1		T113	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T13	3		T19	1		T28	1
all_values[6]	auto[1]	auto[1]	auto[1]	170	1			T10	1		T13	1		T28	1
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T13	3		T19	1		T28	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T10	1		T28	1		T114	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T13	3		T113	2		T30	1
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T28	1		T30	1		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	189	1			T10	3		T13	1		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	160	1			T28	3		T113	1		T30	2
all_values[8]	auto[0]	auto[0]	auto[1]	262	1			T10	1		T13	3		T19	2
all_values[8]	auto[0]	auto[1]	auto[1]	236	1			T10	1		T19	1		T28	5
all_values[8]	auto[1]	auto[0]	auto[1]	175	1			T10	1		T13	4		T19	1
all_values[8]	auto[1]	auto[1]	auto[1]	168	1			T10	1		T28	1		T113	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal