Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1312
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T1256 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1470948343 Jul 24 04:20:09 PM PDT 24 Jul 24 04:20:10 PM PDT 24 62306680 ps
T1257 /workspace/coverage/cover_reg_top/17.uart_intr_test.2880212022 Jul 24 04:21:11 PM PDT 24 Jul 24 04:21:12 PM PDT 24 35049570 ps
T1258 /workspace/coverage/cover_reg_top/13.uart_intr_test.3794021906 Jul 24 04:25:42 PM PDT 24 Jul 24 04:25:43 PM PDT 24 55084197 ps
T115 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1105201740 Jul 24 04:25:06 PM PDT 24 Jul 24 04:25:08 PM PDT 24 3662565265 ps
T1259 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1163965429 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:43 PM PDT 24 116520662 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3364649306 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:43 PM PDT 24 113015263 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3945085425 Jul 24 04:21:02 PM PDT 24 Jul 24 04:21:03 PM PDT 24 113179586 ps
T1262 /workspace/coverage/cover_reg_top/15.uart_intr_test.1216542379 Jul 24 04:22:42 PM PDT 24 Jul 24 04:22:43 PM PDT 24 15315017 ps
T1263 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.925924156 Jul 24 04:25:20 PM PDT 24 Jul 24 04:25:21 PM PDT 24 21039752 ps
T1264 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1995834484 Jul 24 04:25:53 PM PDT 24 Jul 24 04:25:54 PM PDT 24 54935394 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3306573911 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:48 PM PDT 24 59716851 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1696965604 Jul 24 04:25:53 PM PDT 24 Jul 24 04:25:55 PM PDT 24 182303057 ps
T1267 /workspace/coverage/cover_reg_top/8.uart_intr_test.3811432208 Jul 24 04:25:30 PM PDT 24 Jul 24 04:25:32 PM PDT 24 21904973 ps
T1268 /workspace/coverage/cover_reg_top/18.uart_csr_rw.40907377 Jul 24 04:21:21 PM PDT 24 Jul 24 04:21:22 PM PDT 24 32943656 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_intr_test.3703889473 Jul 24 04:20:19 PM PDT 24 Jul 24 04:20:20 PM PDT 24 43657544 ps
T1270 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1483814654 Jul 24 04:25:45 PM PDT 24 Jul 24 04:25:46 PM PDT 24 15048935 ps
T1271 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3204982638 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:57 PM PDT 24 102022918 ps
T1272 /workspace/coverage/cover_reg_top/49.uart_intr_test.3989359071 Jul 24 04:25:42 PM PDT 24 Jul 24 04:25:43 PM PDT 24 11404124 ps
T1273 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.558451030 Jul 24 04:22:57 PM PDT 24 Jul 24 04:22:57 PM PDT 24 16942771 ps
T62 /workspace/coverage/cover_reg_top/13.uart_csr_rw.515842532 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:57 PM PDT 24 13542957 ps
T1274 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2220568909 Jul 24 04:25:53 PM PDT 24 Jul 24 04:25:55 PM PDT 24 152683666 ps
T1275 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2206038092 Jul 24 04:20:56 PM PDT 24 Jul 24 04:20:57 PM PDT 24 50568458 ps
T1276 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2726225600 Jul 24 04:22:57 PM PDT 24 Jul 24 04:22:58 PM PDT 24 31419797 ps
T1277 /workspace/coverage/cover_reg_top/10.uart_intr_test.482693630 Jul 24 04:25:54 PM PDT 24 Jul 24 04:25:55 PM PDT 24 41804118 ps
T1278 /workspace/coverage/cover_reg_top/32.uart_intr_test.4056947505 Jul 24 04:21:03 PM PDT 24 Jul 24 04:21:04 PM PDT 24 44762462 ps
T1279 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1795293008 Jul 24 04:25:39 PM PDT 24 Jul 24 04:25:40 PM PDT 24 17510945 ps
T1280 /workspace/coverage/cover_reg_top/30.uart_intr_test.530237369 Jul 24 04:22:15 PM PDT 24 Jul 24 04:22:16 PM PDT 24 11929781 ps
T1281 /workspace/coverage/cover_reg_top/5.uart_intr_test.1051640404 Jul 24 04:25:23 PM PDT 24 Jul 24 04:25:24 PM PDT 24 31616619 ps
T1282 /workspace/coverage/cover_reg_top/5.uart_csr_rw.395587648 Jul 24 04:21:25 PM PDT 24 Jul 24 04:21:26 PM PDT 24 35468384 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1040715893 Jul 24 04:20:13 PM PDT 24 Jul 24 04:20:15 PM PDT 24 237156671 ps
T1284 /workspace/coverage/cover_reg_top/47.uart_intr_test.3385282065 Jul 24 04:25:42 PM PDT 24 Jul 24 04:25:43 PM PDT 24 16392602 ps
T1285 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.943850084 Jul 24 04:22:20 PM PDT 24 Jul 24 04:22:21 PM PDT 24 248923885 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2361398907 Jul 24 04:20:10 PM PDT 24 Jul 24 04:20:11 PM PDT 24 264751542 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.597690202 Jul 24 04:25:54 PM PDT 24 Jul 24 04:25:55 PM PDT 24 50824440 ps
T1288 /workspace/coverage/cover_reg_top/9.uart_csr_rw.831752806 Jul 24 04:23:25 PM PDT 24 Jul 24 04:23:26 PM PDT 24 13619038 ps
T1289 /workspace/coverage/cover_reg_top/7.uart_tl_errors.723236562 Jul 24 04:21:23 PM PDT 24 Jul 24 04:21:24 PM PDT 24 84867877 ps
T116 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3372915873 Jul 24 04:23:28 PM PDT 24 Jul 24 04:23:30 PM PDT 24 489734128 ps
T1290 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.918740711 Jul 24 04:21:35 PM PDT 24 Jul 24 04:21:36 PM PDT 24 15918682 ps
T1291 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1587042586 Jul 24 04:25:38 PM PDT 24 Jul 24 04:25:39 PM PDT 24 11221350 ps
T1292 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4099815354 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:22 PM PDT 24 27926713 ps
T1293 /workspace/coverage/cover_reg_top/18.uart_tl_errors.377352655 Jul 24 04:21:04 PM PDT 24 Jul 24 04:21:06 PM PDT 24 44373005 ps
T1294 /workspace/coverage/cover_reg_top/18.uart_intr_test.4217406805 Jul 24 04:25:49 PM PDT 24 Jul 24 04:25:50 PM PDT 24 14924191 ps
T1295 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2394106277 Jul 24 04:25:39 PM PDT 24 Jul 24 04:25:41 PM PDT 24 16428002 ps
T1296 /workspace/coverage/cover_reg_top/28.uart_intr_test.3687501335 Jul 24 04:25:50 PM PDT 24 Jul 24 04:25:50 PM PDT 24 117300090 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_intr_test.2251705019 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:56 PM PDT 24 14350709 ps
T1298 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2753538648 Jul 24 04:22:06 PM PDT 24 Jul 24 04:22:07 PM PDT 24 35385534 ps
T1299 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3970802448 Jul 24 04:25:59 PM PDT 24 Jul 24 04:26:01 PM PDT 24 252533910 ps
T1300 /workspace/coverage/cover_reg_top/5.uart_tl_errors.396936057 Jul 24 04:25:27 PM PDT 24 Jul 24 04:25:29 PM PDT 24 60411932 ps
T1301 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4283780502 Jul 24 04:25:25 PM PDT 24 Jul 24 04:25:26 PM PDT 24 19762692 ps
T1302 /workspace/coverage/cover_reg_top/4.uart_intr_test.2116843408 Jul 24 04:25:49 PM PDT 24 Jul 24 04:25:50 PM PDT 24 25101932 ps
T1303 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.639581888 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:57 PM PDT 24 296998756 ps
T1304 /workspace/coverage/cover_reg_top/20.uart_intr_test.2434427611 Jul 24 04:25:50 PM PDT 24 Jul 24 04:25:51 PM PDT 24 13711563 ps
T1305 /workspace/coverage/cover_reg_top/26.uart_intr_test.1669676118 Jul 24 04:22:43 PM PDT 24 Jul 24 04:22:44 PM PDT 24 13200184 ps
T1306 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2319797397 Jul 24 04:20:14 PM PDT 24 Jul 24 04:20:15 PM PDT 24 99253920 ps
T63 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.470040797 Jul 24 04:20:12 PM PDT 24 Jul 24 04:20:13 PM PDT 24 220544825 ps
T1307 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1765404298 Jul 24 04:25:06 PM PDT 24 Jul 24 04:25:07 PM PDT 24 26647261 ps
T1308 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3825300325 Jul 24 04:24:23 PM PDT 24 Jul 24 04:24:24 PM PDT 24 323406038 ps
T64 /workspace/coverage/cover_reg_top/19.uart_csr_rw.637150472 Jul 24 04:21:17 PM PDT 24 Jul 24 04:21:17 PM PDT 24 156494069 ps
T1309 /workspace/coverage/cover_reg_top/9.uart_intr_test.2648630930 Jul 24 04:25:54 PM PDT 24 Jul 24 04:25:55 PM PDT 24 33856945 ps
T1310 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2473705530 Jul 24 04:21:17 PM PDT 24 Jul 24 04:21:18 PM PDT 24 53475979 ps
T1311 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1181623314 Jul 24 04:24:41 PM PDT 24 Jul 24 04:24:44 PM PDT 24 56913745 ps
T1312 /workspace/coverage/cover_reg_top/21.uart_intr_test.4112693879 Jul 24 04:21:17 PM PDT 24 Jul 24 04:21:18 PM PDT 24 15365319 ps

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3492976229
Short name T10
Test name
Test status
Simulation time 55830775005 ps
CPU time 505.9 seconds
Started Jul 24 04:27:36 PM PDT 24
Finished Jul 24 04:36:02 PM PDT 24
Peak memory 216464 kb
Host smart-de4c1133-a723-46dc-98d5-07d1cf3466de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492976229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3492976229
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.3180181441
Short name T15
Test name
Test status
Simulation time 171140219666 ps
CPU time 1122.1 seconds
Started Jul 24 04:27:45 PM PDT 24
Finished Jul 24 04:46:28 PM PDT 24
Peak memory 200000 kb
Host smart-151e3c6f-7955-42b7-b861-cf80cb2a227c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180181441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3180181441
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3796720475
Short name T30
Test name
Test status
Simulation time 375346349873 ps
CPU time 1212.65 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:45:13 PM PDT 24
Peak memory 225720 kb
Host smart-a47de9ef-dae7-4aae-9d60-29272f407f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796720475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3796720475
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.666326758
Short name T5
Test name
Test status
Simulation time 117109334199 ps
CPU time 330.98 seconds
Started Jul 24 04:30:22 PM PDT 24
Finished Jul 24 04:35:53 PM PDT 24
Peak memory 199972 kb
Host smart-f851a7e2-0ea7-4dac-84cc-a514208ea6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666326758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.666326758
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.4215024270
Short name T20
Test name
Test status
Simulation time 132717070133 ps
CPU time 1065.32 seconds
Started Jul 24 04:27:10 PM PDT 24
Finished Jul 24 04:44:56 PM PDT 24
Peak memory 199948 kb
Host smart-1287e61a-5a4c-4f6b-b6c8-22ae72c66db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215024270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4215024270
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.2725937740
Short name T114
Test name
Test status
Simulation time 182692402069 ps
CPU time 171.35 seconds
Started Jul 24 04:27:48 PM PDT 24
Finished Jul 24 04:30:40 PM PDT 24
Peak memory 199996 kb
Host smart-062d553b-8ffc-458e-b7f5-556bafc8877b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725937740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2725937740
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all.3254423200
Short name T122
Test name
Test status
Simulation time 449291966921 ps
CPU time 454.65 seconds
Started Jul 24 04:28:24 PM PDT 24
Finished Jul 24 04:35:59 PM PDT 24
Peak memory 208360 kb
Host smart-95d813af-23d0-4752-890c-faae6e093e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254423200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3254423200
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_sec_cm.63274381
Short name T25
Test name
Test status
Simulation time 452317987 ps
CPU time 0.84 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:12 PM PDT 24
Peak memory 218288 kb
Host smart-ec91e602-e1f0-4b8a-a7b3-7cc97aec1c19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63274381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.63274381
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/26.uart_stress_all.416016524
Short name T113
Test name
Test status
Simulation time 152637410555 ps
CPU time 819.33 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:41:41 PM PDT 24
Peak memory 199936 kb
Host smart-22ede8e2-5d9e-463b-95bc-6c8050bbee3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416016524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.416016524
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all.1306490319
Short name T128
Test name
Test status
Simulation time 878129316375 ps
CPU time 283.28 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:34:01 PM PDT 24
Peak memory 208308 kb
Host smart-daea5b2c-3ab3-4d54-8962-4555a70f48cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306490319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1306490319
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1752614127
Short name T137
Test name
Test status
Simulation time 142430144208 ps
CPU time 86.91 seconds
Started Jul 24 04:27:44 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 199956 kb
Host smart-444caf3f-5b63-4655-9fe8-3b9f1693ce03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752614127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1752614127
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_stress_all.1761415355
Short name T103
Test name
Test status
Simulation time 288459351285 ps
CPU time 110.25 seconds
Started Jul 24 04:26:58 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199968 kb
Host smart-cef2f730-acbd-47ac-8e98-0e405cc5f247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761415355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1761415355
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all.3167905379
Short name T45
Test name
Test status
Simulation time 438605736772 ps
CPU time 481.88 seconds
Started Jul 24 04:27:53 PM PDT 24
Finished Jul 24 04:35:55 PM PDT 24
Peak memory 199868 kb
Host smart-bf29ed5e-cf6d-474c-af5b-2e7c1d9523aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167905379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3167905379
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.733236200
Short name T163
Test name
Test status
Simulation time 201115875339 ps
CPU time 126.2 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:30:05 PM PDT 24
Peak memory 200008 kb
Host smart-8cbefec1-bb7a-420e-90b3-0bf85cc214ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733236200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.733236200
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4235567302
Short name T83
Test name
Test status
Simulation time 80889689 ps
CPU time 1.3 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:25:04 PM PDT 24
Peak memory 199556 kb
Host smart-f756a2f0-4cad-4ad4-9834-2e827d6266e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235567302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4235567302
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1104513926
Short name T90
Test name
Test status
Simulation time 87125401343 ps
CPU time 160.8 seconds
Started Jul 24 04:30:45 PM PDT 24
Finished Jul 24 04:33:26 PM PDT 24
Peak memory 199988 kb
Host smart-168d4cd9-23b2-4de0-af54-63d86a2bd3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104513926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1104513926
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.1211854267
Short name T13
Test name
Test status
Simulation time 120945587337 ps
CPU time 108.2 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:28:27 PM PDT 24
Peak memory 208484 kb
Host smart-8c44288d-b89d-4998-964c-a2209b74b6bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211854267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1211854267
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_alert_test.2273973408
Short name T22
Test name
Test status
Simulation time 14430699 ps
CPU time 0.57 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 195536 kb
Host smart-b735dc0b-b2d9-484b-bf5a-3a83d6a88d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273973408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2273973408
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_noise_filter.143489062
Short name T7
Test name
Test status
Simulation time 156888372615 ps
CPU time 834.25 seconds
Started Jul 24 04:28:19 PM PDT 24
Finished Jul 24 04:42:14 PM PDT 24
Peak memory 199936 kb
Host smart-f00b66f7-6010-4fb9-8867-c0bfaa018120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143489062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.143489062
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3114089221
Short name T50
Test name
Test status
Simulation time 355497490238 ps
CPU time 719.19 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:40:08 PM PDT 24
Peak memory 224756 kb
Host smart-f6ec827c-9bb0-415b-95f1-c9773e4d1a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114089221 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3114089221
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3267345971
Short name T18
Test name
Test status
Simulation time 87003168485 ps
CPU time 303.16 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:32:52 PM PDT 24
Peak memory 216488 kb
Host smart-d0670433-3340-4b43-b674-fa6b0c3a1c07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267345971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3267345971
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all.343703528
Short name T125
Test name
Test status
Simulation time 49411189428 ps
CPU time 88.65 seconds
Started Jul 24 04:28:29 PM PDT 24
Finished Jul 24 04:29:57 PM PDT 24
Peak memory 200008 kb
Host smart-9d76b616-5684-4a9d-9fc7-9742a715caee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343703528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.343703528
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.254364129
Short name T259
Test name
Test status
Simulation time 332638404101 ps
CPU time 44.72 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 199904 kb
Host smart-d8ee051d-aac7-4755-ab51-9155d20d57c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254364129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.254364129
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3144443528
Short name T246
Test name
Test status
Simulation time 458272372322 ps
CPU time 89.39 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:31:34 PM PDT 24
Peak memory 200016 kb
Host smart-3f46a554-0622-44f9-942c-7c1333130994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144443528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3144443528
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2567877725
Short name T99
Test name
Test status
Simulation time 393121964674 ps
CPU time 1071.94 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:44:32 PM PDT 24
Peak memory 226444 kb
Host smart-745c672c-1569-4aef-89d8-7a615fc2c08a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567877725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2567877725
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.470040797
Short name T63
Test name
Test status
Simulation time 220544825 ps
CPU time 1.36 seconds
Started Jul 24 04:20:12 PM PDT 24
Finished Jul 24 04:20:13 PM PDT 24
Peak memory 198792 kb
Host smart-07cfcfa3-97a2-46a1-89c1-0a7fc0480fe3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470040797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.470040797
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2884330655
Short name T77
Test name
Test status
Simulation time 15830683 ps
CPU time 0.6 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 196080 kb
Host smart-6fe22d1b-af85-4865-9a1b-05fa99a5d36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884330655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2884330655
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3916811667
Short name T49
Test name
Test status
Simulation time 283388246769 ps
CPU time 1621.65 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:56:50 PM PDT 24
Peak memory 229308 kb
Host smart-a1276b84-5156-479a-9442-28e37bfe23a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916811667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3916811667
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.2416650211
Short name T156
Test name
Test status
Simulation time 72440630683 ps
CPU time 365.96 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:32:38 PM PDT 24
Peak memory 199964 kb
Host smart-5e0a876d-8bb5-43b8-9c30-6bfe666b5b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416650211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2416650211
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2600477970
Short name T52
Test name
Test status
Simulation time 348390522853 ps
CPU time 797.21 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:43:17 PM PDT 24
Peak memory 224932 kb
Host smart-81c4d997-19c4-4c11-851b-f5ca6ce313fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600477970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2600477970
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2638123915
Short name T34
Test name
Test status
Simulation time 48599185381 ps
CPU time 599.13 seconds
Started Jul 24 04:26:49 PM PDT 24
Finished Jul 24 04:36:49 PM PDT 24
Peak memory 216660 kb
Host smart-4a7d150f-856f-4d4d-a03e-a5233b6eb4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638123915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2638123915
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.874879988
Short name T161
Test name
Test status
Simulation time 131527311763 ps
CPU time 210 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:33:31 PM PDT 24
Peak memory 199900 kb
Host smart-09e302a2-5874-4f66-be0d-663fddf88772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874879988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.874879988
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3365121977
Short name T171
Test name
Test status
Simulation time 93372523678 ps
CPU time 182.14 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:33:41 PM PDT 24
Peak memory 199944 kb
Host smart-e19d7fab-ffab-44ed-9912-c2c3f09c7a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365121977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3365121977
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4207131761
Short name T174
Test name
Test status
Simulation time 127638545043 ps
CPU time 194.3 seconds
Started Jul 24 04:31:00 PM PDT 24
Finished Jul 24 04:34:14 PM PDT 24
Peak memory 199960 kb
Host smart-e8209a6a-21e4-4a1d-80b1-6d8de2fe7e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207131761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4207131761
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.929567563
Short name T176
Test name
Test status
Simulation time 28507806292 ps
CPU time 21.9 seconds
Started Jul 24 04:31:05 PM PDT 24
Finished Jul 24 04:31:27 PM PDT 24
Peak memory 199972 kb
Host smart-1546a6d3-0dbb-4498-a0a0-78956a346969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929567563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.929567563
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2705972133
Short name T155
Test name
Test status
Simulation time 132563387536 ps
CPU time 467.29 seconds
Started Jul 24 04:30:06 PM PDT 24
Finished Jul 24 04:37:54 PM PDT 24
Peak memory 216532 kb
Host smart-f92a85be-907d-4af0-9198-c23ce8fec99a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705972133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2705972133
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3924003369
Short name T271
Test name
Test status
Simulation time 80294233708 ps
CPU time 30.72 seconds
Started Jul 24 04:26:55 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 199768 kb
Host smart-ad0a2ad0-8cb0-42a5-afc0-63891a6feb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924003369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3924003369
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2081746305
Short name T203
Test name
Test status
Simulation time 169024710581 ps
CPU time 37.3 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:31:41 PM PDT 24
Peak memory 199932 kb
Host smart-1a8b47f0-8ac4-4966-82e8-366fc7a12552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081746305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2081746305
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.652937115
Short name T91
Test name
Test status
Simulation time 150286410134 ps
CPU time 62.74 seconds
Started Jul 24 04:30:46 PM PDT 24
Finished Jul 24 04:31:49 PM PDT 24
Peak memory 200352 kb
Host smart-81776f37-a002-48e0-bd17-2c27d6c85eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652937115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.652937115
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3758230197
Short name T264
Test name
Test status
Simulation time 112604730427 ps
CPU time 240.95 seconds
Started Jul 24 04:31:09 PM PDT 24
Finished Jul 24 04:35:10 PM PDT 24
Peak memory 199928 kb
Host smart-ffe6e166-b50a-40b8-bd80-c67c67c7567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758230197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3758230197
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1109680313
Short name T79
Test name
Test status
Simulation time 129359665 ps
CPU time 1.33 seconds
Started Jul 24 04:21:36 PM PDT 24
Finished Jul 24 04:21:37 PM PDT 24
Peak memory 200200 kb
Host smart-f10f5e48-4530-4a1d-8d20-484f874a285f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109680313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1109680313
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2987011557
Short name T186
Test name
Test status
Simulation time 58791265800 ps
CPU time 660.5 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:37:09 PM PDT 24
Peak memory 215588 kb
Host smart-12babbdc-7f37-43ed-87ef-f15f8bf79db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987011557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2987011557
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2067169847
Short name T140
Test name
Test status
Simulation time 61048339087 ps
CPU time 90.56 seconds
Started Jul 24 04:30:18 PM PDT 24
Finished Jul 24 04:31:49 PM PDT 24
Peak memory 199856 kb
Host smart-a37dde0d-e509-4dce-93e5-9e83b61063f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067169847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2067169847
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.108208785
Short name T149
Test name
Test status
Simulation time 122301866030 ps
CPU time 35.02 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 199520 kb
Host smart-25ef7d33-b335-4052-b1be-28cf132ba4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108208785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.108208785
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3751506731
Short name T207
Test name
Test status
Simulation time 24545387668 ps
CPU time 18.65 seconds
Started Jul 24 04:31:14 PM PDT 24
Finished Jul 24 04:31:33 PM PDT 24
Peak memory 199948 kb
Host smart-1bd9eae9-9034-45c4-8d78-0acf22aa1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751506731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3751506731
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1368570801
Short name T151
Test name
Test status
Simulation time 53504187171 ps
CPU time 49.58 seconds
Started Jul 24 04:29:31 PM PDT 24
Finished Jul 24 04:30:21 PM PDT 24
Peak memory 200012 kb
Host smart-f7f7d5b7-4943-46fb-a73d-afc5528efcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368570801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1368570801
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2737940798
Short name T314
Test name
Test status
Simulation time 207522857581 ps
CPU time 287.99 seconds
Started Jul 24 04:30:11 PM PDT 24
Finished Jul 24 04:34:59 PM PDT 24
Peak memory 199912 kb
Host smart-43b913f4-63ac-4b2e-9766-cff11882153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737940798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2737940798
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.54692114
Short name T110
Test name
Test status
Simulation time 142886296598 ps
CPU time 206.14 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:33:41 PM PDT 24
Peak memory 200080 kb
Host smart-ab8b0f71-65e5-4203-a077-fe9e3d929645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54692114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.54692114
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3320438619
Short name T286
Test name
Test status
Simulation time 47745937761 ps
CPU time 48.18 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:31:09 PM PDT 24
Peak memory 200076 kb
Host smart-1b4648a1-31ef-4dcd-aa11-8fb7319e8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320438619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3320438619
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.2625030407
Short name T234
Test name
Test status
Simulation time 235256073926 ps
CPU time 347.93 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:33:25 PM PDT 24
Peak memory 216020 kb
Host smart-2f4eb3c4-fd00-44c8-8a2d-57fa012154f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625030407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2625030407
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.990668942
Short name T179
Test name
Test status
Simulation time 30000860684 ps
CPU time 48 seconds
Started Jul 24 04:31:13 PM PDT 24
Finished Jul 24 04:32:01 PM PDT 24
Peak memory 199964 kb
Host smart-581608b9-7a00-4bc3-97ba-ee3134f7aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990668942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.990668942
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.355106947
Short name T211
Test name
Test status
Simulation time 64388596411 ps
CPU time 84.67 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:32:45 PM PDT 24
Peak memory 199852 kb
Host smart-faec8dec-6b1f-4368-8509-720bee8c3514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355106947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.355106947
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3268849383
Short name T239
Test name
Test status
Simulation time 86039655267 ps
CPU time 39.84 seconds
Started Jul 24 04:31:21 PM PDT 24
Finished Jul 24 04:32:01 PM PDT 24
Peak memory 200028 kb
Host smart-a93c6e57-36fd-40d7-8faf-4514bf307b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268849383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3268849383
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.459538761
Short name T164
Test name
Test status
Simulation time 572903639496 ps
CPU time 626.69 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:39:00 PM PDT 24
Peak memory 216444 kb
Host smart-e917c2a1-ec53-4fb1-828f-8ac8806fa4a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459538761 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.459538761
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1031934859
Short name T118
Test name
Test status
Simulation time 30038927167 ps
CPU time 27.83 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:30:16 PM PDT 24
Peak memory 199960 kb
Host smart-bb5d5931-f8ac-45af-afc7-e50172c01004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031934859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1031934859
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.102370993
Short name T785
Test name
Test status
Simulation time 159096944426 ps
CPU time 25.65 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 199952 kb
Host smart-985ddc68-7854-4fbb-a237-318d8ced5cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102370993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.102370993
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1601797152
Short name T223
Test name
Test status
Simulation time 175332756036 ps
CPU time 59.45 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:26:02 PM PDT 24
Peak memory 199512 kb
Host smart-990b6d10-f92a-4b88-bd69-db63cc6a9146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601797152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1601797152
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3802955070
Short name T213
Test name
Test status
Simulation time 69646585935 ps
CPU time 107.8 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:31:58 PM PDT 24
Peak memory 200072 kb
Host smart-0caea3d3-bccd-4f86-b255-175fff2e293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802955070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3802955070
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.217968765
Short name T170
Test name
Test status
Simulation time 72241537859 ps
CPU time 28.75 seconds
Started Jul 24 04:26:34 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 199996 kb
Host smart-2b60fda0-47d7-4e52-acd0-6b3c38f7c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217968765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.217968765
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.515022696
Short name T29
Test name
Test status
Simulation time 233290116505 ps
CPU time 844.22 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:40:51 PM PDT 24
Peak memory 216344 kb
Host smart-8459c96e-9bf0-46c0-98e7-42532d8fd64c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515022696 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.515022696
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3406860819
Short name T224
Test name
Test status
Simulation time 52139676492 ps
CPU time 69.22 seconds
Started Jul 24 04:30:17 PM PDT 24
Finished Jul 24 04:31:26 PM PDT 24
Peak memory 199992 kb
Host smart-1f258620-110b-42f3-910b-2b311167bf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406860819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3406860819
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.437622817
Short name T222
Test name
Test status
Simulation time 40168007456 ps
CPU time 27.28 seconds
Started Jul 24 04:26:53 PM PDT 24
Finished Jul 24 04:27:20 PM PDT 24
Peak memory 199924 kb
Host smart-06f146e4-b502-4663-828c-4b674e0c9909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437622817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.437622817
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3725412414
Short name T121
Test name
Test status
Simulation time 44952930995 ps
CPU time 35.55 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:30:57 PM PDT 24
Peak memory 199808 kb
Host smart-c26f88a4-026e-47f6-837a-412e24456101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725412414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3725412414
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3275447253
Short name T1052
Test name
Test status
Simulation time 362360982870 ps
CPU time 46.29 seconds
Started Jul 24 04:30:35 PM PDT 24
Finished Jul 24 04:31:21 PM PDT 24
Peak memory 199992 kb
Host smart-fc58fa70-6921-4b2a-926c-1c53647eb0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275447253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3275447253
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2158296909
Short name T194
Test name
Test status
Simulation time 37457438992 ps
CPU time 25.61 seconds
Started Jul 24 04:30:40 PM PDT 24
Finished Jul 24 04:31:06 PM PDT 24
Peak memory 200048 kb
Host smart-7dfb7257-2168-47ca-911f-ee7df3226a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158296909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2158296909
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.138141036
Short name T240
Test name
Test status
Simulation time 35553927078 ps
CPU time 17.21 seconds
Started Jul 24 04:31:31 PM PDT 24
Finished Jul 24 04:31:48 PM PDT 24
Peak memory 199996 kb
Host smart-eaff360d-8348-4fb1-a04b-87e68fed6e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138141036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.138141036
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1375947665
Short name T227
Test name
Test status
Simulation time 16007367417 ps
CPU time 80.96 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:28:02 PM PDT 24
Peak memory 215756 kb
Host smart-7f85fbc6-98af-4cfd-b404-a2dc4ee3cc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375947665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1375947665
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2116923197
Short name T145
Test name
Test status
Simulation time 126854599656 ps
CPU time 15.46 seconds
Started Jul 24 04:30:58 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 199776 kb
Host smart-a7116060-2760-48b8-85ad-4a84ac83796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116923197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2116923197
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.420031172
Short name T237
Test name
Test status
Simulation time 46398862354 ps
CPU time 17.23 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:28:06 PM PDT 24
Peak memory 199104 kb
Host smart-2bd688c9-2625-4c10-8540-bcceb5412d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420031172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.420031172
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1224341521
Short name T233
Test name
Test status
Simulation time 909321991083 ps
CPU time 1051.75 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:45:28 PM PDT 24
Peak memory 224680 kb
Host smart-e0066b7d-623f-429c-a59b-3c4ebfa6b0d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224341521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1224341521
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3349442242
Short name T226
Test name
Test status
Simulation time 102554189779 ps
CPU time 36.38 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:31:41 PM PDT 24
Peak memory 200000 kb
Host smart-abab0d79-a820-4292-8924-e062ad55fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349442242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3349442242
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2614645695
Short name T198
Test name
Test status
Simulation time 7120145777 ps
CPU time 11.81 seconds
Started Jul 24 04:31:24 PM PDT 24
Finished Jul 24 04:31:36 PM PDT 24
Peak memory 199936 kb
Host smart-d123ec90-7022-412a-b857-2da2cbd24b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614645695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2614645695
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2227873177
Short name T209
Test name
Test status
Simulation time 26352707116 ps
CPU time 45.69 seconds
Started Jul 24 04:31:26 PM PDT 24
Finished Jul 24 04:32:12 PM PDT 24
Peak memory 200016 kb
Host smart-82d55fbc-d54d-4192-babc-99dbe8446e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227873177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2227873177
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1814160500
Short name T54
Test name
Test status
Simulation time 87218655106 ps
CPU time 633.87 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:40:22 PM PDT 24
Peak memory 214156 kb
Host smart-5377ecfe-cc44-4748-8f60-c9c225790c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814160500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1814160500
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3547893642
Short name T243
Test name
Test status
Simulation time 116794239386 ps
CPU time 157.1 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 199972 kb
Host smart-485705d0-6099-414e-8b04-e83229c098dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547893642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3547893642
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.2497939411
Short name T216
Test name
Test status
Simulation time 37381874770 ps
CPU time 59.03 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 199948 kb
Host smart-18a94a77-a13e-4825-8f0f-a6b97db91c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497939411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2497939411
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2361398907
Short name T1286
Test name
Test status
Simulation time 264751542 ps
CPU time 0.65 seconds
Started Jul 24 04:20:10 PM PDT 24
Finished Jul 24 04:20:11 PM PDT 24
Peak memory 195528 kb
Host smart-1a394755-62ed-42fa-9abd-0fe3bcd94191
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361398907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2361398907
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4281072481
Short name T1175
Test name
Test status
Simulation time 44539236 ps
CPU time 0.58 seconds
Started Jul 24 04:20:20 PM PDT 24
Finished Jul 24 04:20:20 PM PDT 24
Peak memory 196144 kb
Host smart-3dbcc86d-2caa-4042-a2b5-95e5d3294d40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281072481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4281072481
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2068375366
Short name T1197
Test name
Test status
Simulation time 142066458 ps
CPU time 0.76 seconds
Started Jul 24 04:20:13 PM PDT 24
Finished Jul 24 04:20:14 PM PDT 24
Peak memory 199516 kb
Host smart-a8c51b3b-d8c5-4d82-9e53-ae22e6a8f315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068375366 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2068375366
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.921828034
Short name T1243
Test name
Test status
Simulation time 27644365 ps
CPU time 0.6 seconds
Started Jul 24 04:20:06 PM PDT 24
Finished Jul 24 04:20:07 PM PDT 24
Peak memory 196048 kb
Host smart-f2b4e40c-b539-4eb3-af00-01dbad157b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921828034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.921828034
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3703889473
Short name T1269
Test name
Test status
Simulation time 43657544 ps
CPU time 0.58 seconds
Started Jul 24 04:20:19 PM PDT 24
Finished Jul 24 04:20:20 PM PDT 24
Peak memory 195032 kb
Host smart-f932bd72-f389-4a8a-bd5e-1acdaf3cd938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703889473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3703889473
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1470948343
Short name T1256
Test name
Test status
Simulation time 62306680 ps
CPU time 0.75 seconds
Started Jul 24 04:20:09 PM PDT 24
Finished Jul 24 04:20:10 PM PDT 24
Peak memory 196060 kb
Host smart-2ac7c344-1997-49f9-bae2-a195bd0921f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470948343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1470948343
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2343721043
Short name T1250
Test name
Test status
Simulation time 33098379 ps
CPU time 0.95 seconds
Started Jul 24 04:20:12 PM PDT 24
Finished Jul 24 04:20:13 PM PDT 24
Peak memory 200868 kb
Host smart-70fa61de-90a3-4d4c-b5de-95f7b8b007e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343721043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2343721043
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2319797397
Short name T1306
Test name
Test status
Simulation time 99253920 ps
CPU time 1.26 seconds
Started Jul 24 04:20:14 PM PDT 24
Finished Jul 24 04:20:15 PM PDT 24
Peak memory 199780 kb
Host smart-958a8bda-1329-4f2a-8578-df26095f445d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319797397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2319797397
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.558451030
Short name T1273
Test name
Test status
Simulation time 16942771 ps
CPU time 0.66 seconds
Started Jul 24 04:22:57 PM PDT 24
Finished Jul 24 04:22:57 PM PDT 24
Peak memory 196132 kb
Host smart-4ed0077b-3e33-45cc-8498-0abeed9ebd99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558451030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.558451030
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3190677960
Short name T1245
Test name
Test status
Simulation time 1163426689 ps
CPU time 2.29 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 198148 kb
Host smart-19b904df-7955-4c4d-9bb6-03fd5d7e04ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190677960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3190677960
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2782104857
Short name T1246
Test name
Test status
Simulation time 1030194093 ps
CPU time 1.62 seconds
Started Jul 24 04:23:08 PM PDT 24
Finished Jul 24 04:23:09 PM PDT 24
Peak memory 196148 kb
Host smart-0e5785b7-1c6d-4825-817f-ad59937d9e3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782104857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2782104857
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2373077592
Short name T1177
Test name
Test status
Simulation time 191049554 ps
CPU time 0.69 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 198888 kb
Host smart-dbcd43bf-6455-4896-8d53-fb00d2ce6d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373077592 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2373077592
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2753538648
Short name T1298
Test name
Test status
Simulation time 35385534 ps
CPU time 0.67 seconds
Started Jul 24 04:22:06 PM PDT 24
Finished Jul 24 04:22:07 PM PDT 24
Peak memory 196176 kb
Host smart-a8045c39-81a0-4e1f-b3e0-53b53594250e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753538648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2753538648
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3441117017
Short name T1244
Test name
Test status
Simulation time 43976670 ps
CPU time 0.54 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 194960 kb
Host smart-cb815fed-7359-49a7-ab93-cbcd4496d3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441117017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3441117017
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3306573911
Short name T1265
Test name
Test status
Simulation time 59716851 ps
CPU time 0.7 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 196316 kb
Host smart-377048ec-6e90-4198-ad92-e4d677a4931a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306573911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3306573911
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1040715893
Short name T1283
Test name
Test status
Simulation time 237156671 ps
CPU time 1.89 seconds
Started Jul 24 04:20:13 PM PDT 24
Finished Jul 24 04:20:15 PM PDT 24
Peak memory 200252 kb
Host smart-ef5cb12a-1e5d-4f37-8819-5e67d735ab83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040715893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1040715893
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.392314400
Short name T1207
Test name
Test status
Simulation time 84618901 ps
CPU time 0.73 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 199992 kb
Host smart-fc3230d3-edb8-4836-ac3b-b6315c83c6dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392314400 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.392314400
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.482693630
Short name T1277
Test name
Test status
Simulation time 41804118 ps
CPU time 0.59 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 195052 kb
Host smart-5d129fb4-ed61-4793-b46b-b4826d3663ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482693630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.482693630
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2768676781
Short name T68
Test name
Test status
Simulation time 119930728 ps
CPU time 0.73 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 197636 kb
Host smart-145a6c5b-515f-4712-968d-0eff870fb120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768676781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2768676781
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1802662227
Short name T1216
Test name
Test status
Simulation time 251979944 ps
CPU time 1.51 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 199460 kb
Host smart-84790a84-df39-46fc-9487-826e7ff80d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802662227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1802662227
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2220568909
Short name T1274
Test name
Test status
Simulation time 152683666 ps
CPU time 1.2 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 199724 kb
Host smart-9c275930-0c96-450b-938e-e342c3fdfcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220568909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2220568909
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.37099865
Short name T1226
Test name
Test status
Simulation time 42086028 ps
CPU time 1.18 seconds
Started Jul 24 04:22:21 PM PDT 24
Finished Jul 24 04:22:22 PM PDT 24
Peak memory 200820 kb
Host smart-efd287a7-ba04-4490-b9ac-75f95f2692fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37099865 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.37099865
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3265739659
Short name T1208
Test name
Test status
Simulation time 32767892 ps
CPU time 0.58 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:21 PM PDT 24
Peak memory 196156 kb
Host smart-0c3c3262-0d96-4cec-95ab-4d1eb1a9a743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265739659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3265739659
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1485019714
Short name T1230
Test name
Test status
Simulation time 11941349 ps
CPU time 0.58 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:39 PM PDT 24
Peak memory 193552 kb
Host smart-79793653-b033-4e61-9834-3d67d068ba5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485019714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1485019714
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1868397309
Short name T1214
Test name
Test status
Simulation time 25031192 ps
CPU time 0.65 seconds
Started Jul 24 04:21:53 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 196260 kb
Host smart-186f2ac5-b678-4491-b80b-85b52f8d7888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868397309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1868397309
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.300133675
Short name T1231
Test name
Test status
Simulation time 230510281 ps
CPU time 1.9 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 200668 kb
Host smart-1342d051-9479-4932-aa44-0da0958c5676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300133675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.300133675
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.885671109
Short name T1233
Test name
Test status
Simulation time 50184290 ps
CPU time 0.92 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:22:20 PM PDT 24
Peak memory 199488 kb
Host smart-af4415d7-5a6c-4f87-a5c1-d1efa786cb00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885671109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.885671109
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2276802327
Short name T1184
Test name
Test status
Simulation time 20370175 ps
CPU time 0.86 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 200484 kb
Host smart-755b88f5-ac76-42f3-b588-c906593e175d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276802327 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2276802327
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.819625845
Short name T70
Test name
Test status
Simulation time 12978573 ps
CPU time 0.6 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 194620 kb
Host smart-8f861c8d-8b2b-46b2-95e0-c6a945f0cca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819625845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.819625845
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2251705019
Short name T1297
Test name
Test status
Simulation time 14350709 ps
CPU time 0.58 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 195032 kb
Host smart-5caef5dd-ce66-4692-8156-7bc3b07ec53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251705019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2251705019
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2394106277
Short name T1295
Test name
Test status
Simulation time 16428002 ps
CPU time 0.72 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 196180 kb
Host smart-4f8f4245-2dba-4da8-aab7-6d05646f203a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394106277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2394106277
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3204982638
Short name T1271
Test name
Test status
Simulation time 102022918 ps
CPU time 1.44 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 200668 kb
Host smart-744bcd4b-bfa7-4b71-b110-b4e08435097c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204982638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3204982638
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.639581888
Short name T1303
Test name
Test status
Simulation time 296998756 ps
CPU time 1.21 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 200036 kb
Host smart-556d59c2-e7b5-4939-a09f-4a5be9f449cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639581888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.639581888
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1610445395
Short name T1252
Test name
Test status
Simulation time 33620767 ps
CPU time 0.64 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 198780 kb
Host smart-25058ab8-1de7-47b6-9ba1-a3b1d108030b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610445395 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1610445395
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.515842532
Short name T62
Test name
Test status
Simulation time 13542957 ps
CPU time 0.58 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 196168 kb
Host smart-420313f2-373e-4e2c-89e9-26d33ed3672c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515842532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.515842532
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3794021906
Short name T1258
Test name
Test status
Simulation time 55084197 ps
CPU time 0.6 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 193880 kb
Host smart-45bba97e-fe7c-4d42-95f8-da3a10dd1884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794021906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3794021906
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.984730892
Short name T73
Test name
Test status
Simulation time 30761233 ps
CPU time 0.63 seconds
Started Jul 24 04:23:43 PM PDT 24
Finished Jul 24 04:23:44 PM PDT 24
Peak memory 196264 kb
Host smart-cceee4b2-a94a-455b-bcf4-6cd16f5ba2a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984730892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.984730892
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3442308493
Short name T1203
Test name
Test status
Simulation time 119637469 ps
CPU time 1.21 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 200720 kb
Host smart-297715c0-c401-49fa-bc31-d4051410d179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442308493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3442308493
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3982289276
Short name T1237
Test name
Test status
Simulation time 88387565 ps
CPU time 1.23 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 199916 kb
Host smart-2957f193-fd9f-4337-9be5-38388b12d5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982289276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3982289276
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3492921784
Short name T1201
Test name
Test status
Simulation time 21573875 ps
CPU time 0.73 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 200184 kb
Host smart-342b33ad-cf44-4aa1-8fff-773fff5e9cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492921784 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3492921784
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.232249184
Short name T1254
Test name
Test status
Simulation time 150460443 ps
CPU time 0.55 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:46 PM PDT 24
Peak memory 196084 kb
Host smart-cacae53d-deea-4423-b305-c8af774a5f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232249184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.232249184
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2453521963
Short name T1212
Test name
Test status
Simulation time 84154022 ps
CPU time 0.58 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 195036 kb
Host smart-5ca76b9e-edb6-486f-8641-432a52956821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453521963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2453521963
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4283780502
Short name T1301
Test name
Test status
Simulation time 19762692 ps
CPU time 0.69 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 196348 kb
Host smart-6982a3b0-dff7-4dce-9f39-4251801366b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283780502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4283780502
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1653361782
Short name T1194
Test name
Test status
Simulation time 470933421 ps
CPU time 1.98 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:08 PM PDT 24
Peak memory 200400 kb
Host smart-2a5ff1c1-d37a-4b49-8b24-d60278cafc35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653361782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1653361782
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3825300325
Short name T1308
Test name
Test status
Simulation time 323406038 ps
CPU time 1.29 seconds
Started Jul 24 04:24:23 PM PDT 24
Finished Jul 24 04:24:24 PM PDT 24
Peak memory 200152 kb
Host smart-e7d3b92d-0455-4481-9d14-de195f882cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825300325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3825300325
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1765404298
Short name T1307
Test name
Test status
Simulation time 26647261 ps
CPU time 0.93 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 199300 kb
Host smart-0c838b3a-963a-4375-a16d-a289defa8a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765404298 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1765404298
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2639693555
Short name T69
Test name
Test status
Simulation time 14473811 ps
CPU time 0.57 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 196092 kb
Host smart-b3829ba4-55b2-49e2-857f-83f12557b372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639693555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2639693555
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1216542379
Short name T1262
Test name
Test status
Simulation time 15315017 ps
CPU time 0.61 seconds
Started Jul 24 04:22:42 PM PDT 24
Finished Jul 24 04:22:43 PM PDT 24
Peak memory 195472 kb
Host smart-667c704a-29c7-45e8-98c7-760226cb6cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216542379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1216542379
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2013855078
Short name T1210
Test name
Test status
Simulation time 30672066 ps
CPU time 0.79 seconds
Started Jul 24 04:22:43 PM PDT 24
Finished Jul 24 04:22:44 PM PDT 24
Peak memory 197996 kb
Host smart-c323ba5e-4091-40af-8656-97c92d3e2bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013855078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2013855078
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3945218010
Short name T1224
Test name
Test status
Simulation time 197181762 ps
CPU time 1.07 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:30 PM PDT 24
Peak memory 200448 kb
Host smart-ce7e30f2-7022-4c38-a809-5fe5ce238e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945218010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3945218010
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.320441528
Short name T85
Test name
Test status
Simulation time 85096449 ps
CPU time 1.26 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 200112 kb
Host smart-5465b29e-0a6d-4799-82ea-e161de3af5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320441528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.320441528
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1217014724
Short name T1239
Test name
Test status
Simulation time 49850773 ps
CPU time 1.24 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 200720 kb
Host smart-805cb5ae-c68d-4417-8a1b-5bca9b5595bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217014724 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1217014724
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3945085425
Short name T1261
Test name
Test status
Simulation time 113179586 ps
CPU time 0.6 seconds
Started Jul 24 04:21:02 PM PDT 24
Finished Jul 24 04:21:03 PM PDT 24
Peak memory 196496 kb
Host smart-a350b1b5-4f4b-416c-9611-f09888c5289e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945085425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3945085425
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.778502592
Short name T1191
Test name
Test status
Simulation time 20505365 ps
CPU time 0.63 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:36 PM PDT 24
Peak memory 195112 kb
Host smart-c1068d69-c4bb-4608-8f90-1085e8dc987f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778502592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.778502592
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.461959156
Short name T76
Test name
Test status
Simulation time 16986039 ps
CPU time 0.64 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:47 PM PDT 24
Peak memory 196612 kb
Host smart-14f0eede-4479-44b4-964e-36a1bbbd2bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461959156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.461959156
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3995286445
Short name T1247
Test name
Test status
Simulation time 24333944 ps
CPU time 1.21 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:30 PM PDT 24
Peak memory 200504 kb
Host smart-9ae45950-e9ed-42ab-8193-974b5071f83f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995286445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3995286445
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1105201740
Short name T115
Test name
Test status
Simulation time 3662565265 ps
CPU time 1.71 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:08 PM PDT 24
Peak memory 199600 kb
Host smart-e84f054b-10a8-4a62-9ec2-3a61412c1e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105201740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1105201740
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1080193084
Short name T1236
Test name
Test status
Simulation time 44922383 ps
CPU time 0.92 seconds
Started Jul 24 04:25:32 PM PDT 24
Finished Jul 24 04:25:34 PM PDT 24
Peak memory 199132 kb
Host smart-451a3bb9-f0ff-4287-b7d7-d36b3b517463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080193084 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1080193084
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2770608155
Short name T1206
Test name
Test status
Simulation time 13226044 ps
CPU time 0.58 seconds
Started Jul 24 04:20:54 PM PDT 24
Finished Jul 24 04:20:55 PM PDT 24
Peak memory 196056 kb
Host smart-637047e0-5197-445f-8e19-66177622c326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770608155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2770608155
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2880212022
Short name T1257
Test name
Test status
Simulation time 35049570 ps
CPU time 0.57 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195120 kb
Host smart-29816fc9-ea2c-4a6f-adf8-af70a6e774f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880212022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2880212022
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.203003465
Short name T1240
Test name
Test status
Simulation time 26050676 ps
CPU time 0.68 seconds
Started Jul 24 04:21:10 PM PDT 24
Finished Jul 24 04:21:11 PM PDT 24
Peak memory 196944 kb
Host smart-7b3460fe-8ade-4541-9b23-834d57a8b9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203003465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.203003465
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1956248620
Short name T1198
Test name
Test status
Simulation time 185606627 ps
CPU time 1.25 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 200084 kb
Host smart-add66ff3-6c6d-48b6-b94b-482ccdae5685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956248620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1956248620
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2206038092
Short name T1275
Test name
Test status
Simulation time 50568458 ps
CPU time 0.92 seconds
Started Jul 24 04:20:56 PM PDT 24
Finished Jul 24 04:20:57 PM PDT 24
Peak memory 199500 kb
Host smart-b89f8805-a485-4820-b61f-068c4ddb5c40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206038092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2206038092
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2948566606
Short name T1253
Test name
Test status
Simulation time 21970148 ps
CPU time 0.72 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:26:00 PM PDT 24
Peak memory 198876 kb
Host smart-b1bc510d-05f4-48f4-afb5-a65be5ec6dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948566606 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2948566606
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.40907377
Short name T1268
Test name
Test status
Simulation time 32943656 ps
CPU time 0.65 seconds
Started Jul 24 04:21:21 PM PDT 24
Finished Jul 24 04:21:22 PM PDT 24
Peak memory 196424 kb
Host smart-be845094-9a8e-4644-8d34-eed29f90e1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40907377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.40907377
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4217406805
Short name T1294
Test name
Test status
Simulation time 14924191 ps
CPU time 0.57 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 194960 kb
Host smart-8e0fe1e1-f56c-4544-9d55-fb64c67bdfaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217406805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4217406805
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1348676440
Short name T74
Test name
Test status
Simulation time 15654129 ps
CPU time 0.62 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 196412 kb
Host smart-6386ef0e-7603-4ff8-8af1-70061b99c7fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348676440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1348676440
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.377352655
Short name T1293
Test name
Test status
Simulation time 44373005 ps
CPU time 1.33 seconds
Started Jul 24 04:21:04 PM PDT 24
Finished Jul 24 04:21:06 PM PDT 24
Peak memory 200772 kb
Host smart-7100584b-f7ab-4bd3-a1e6-4cbd50ea4573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377352655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.377352655
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3285305272
Short name T84
Test name
Test status
Simulation time 164144407 ps
CPU time 0.95 seconds
Started Jul 24 04:21:07 PM PDT 24
Finished Jul 24 04:21:08 PM PDT 24
Peak memory 199864 kb
Host smart-168ea78e-c2d8-4f8f-a4be-1c089aa28711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285305272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3285305272
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2473705530
Short name T1310
Test name
Test status
Simulation time 53475979 ps
CPU time 0.86 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 200488 kb
Host smart-70770fac-ccec-483a-88c8-ee3e17496a4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473705530 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2473705530
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.637150472
Short name T64
Test name
Test status
Simulation time 156494069 ps
CPU time 0.6 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:17 PM PDT 24
Peak memory 196092 kb
Host smart-2ed7b812-6ab5-4562-998c-f75fb5fdbd09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637150472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.637150472
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.955025838
Short name T1176
Test name
Test status
Simulation time 18452230 ps
CPU time 0.58 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 195100 kb
Host smart-5c99c702-1a1f-4398-bc12-0e4d6cde526f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955025838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.955025838
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.925924156
Short name T1263
Test name
Test status
Simulation time 21039752 ps
CPU time 0.65 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 196072 kb
Host smart-113073f5-e9d6-4fe0-8d28-26e4c540bd22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925924156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.925924156
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3472599879
Short name T1217
Test name
Test status
Simulation time 1127727007 ps
CPU time 1.63 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 199988 kb
Host smart-6cddc313-dba1-444f-8b6f-3be8c292a5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472599879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3472599879
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2559467537
Short name T80
Test name
Test status
Simulation time 141660383 ps
CPU time 1.24 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 199684 kb
Host smart-cae51bca-2318-47ea-a6f0-b02bf4644811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559467537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2559467537
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3601960291
Short name T1215
Test name
Test status
Simulation time 24007107 ps
CPU time 0.67 seconds
Started Jul 24 04:22:26 PM PDT 24
Finished Jul 24 04:22:27 PM PDT 24
Peak memory 195412 kb
Host smart-df285781-dc94-42ae-9594-99e8eda915c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601960291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3601960291
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1181623314
Short name T1311
Test name
Test status
Simulation time 56913745 ps
CPU time 2.19 seconds
Started Jul 24 04:24:41 PM PDT 24
Finished Jul 24 04:24:44 PM PDT 24
Peak memory 197428 kb
Host smart-0435320c-a596-42d4-9a44-0b4eabbca38e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181623314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1181623314
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1995834484
Short name T1264
Test name
Test status
Simulation time 54935394 ps
CPU time 0.58 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 195948 kb
Host smart-cc12794c-bcfe-4a5f-a7d0-9d86535f4bef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995834484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1995834484
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2279518998
Short name T1192
Test name
Test status
Simulation time 73995336 ps
CPU time 1.06 seconds
Started Jul 24 04:23:49 PM PDT 24
Finished Jul 24 04:23:51 PM PDT 24
Peak memory 200576 kb
Host smart-53aa58cd-7a60-44da-8d8d-0ddd7880fd93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279518998 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2279518998
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.221942456
Short name T61
Test name
Test status
Simulation time 15223527 ps
CPU time 0.56 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 195992 kb
Host smart-a332c7f1-26c0-4703-9b0b-39cec53fccee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221942456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.221942456
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4093131947
Short name T1199
Test name
Test status
Simulation time 22381819 ps
CPU time 0.57 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:03 PM PDT 24
Peak memory 195124 kb
Host smart-71d30d1a-cdf7-4e9f-9ec5-d3fb041c9f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093131947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4093131947
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3364649306
Short name T1260
Test name
Test status
Simulation time 113015263 ps
CPU time 0.72 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 197652 kb
Host smart-687e282b-f278-4dc1-8c44-78f8a3dd0a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364649306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3364649306
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3154626872
Short name T1204
Test name
Test status
Simulation time 203360123 ps
CPU time 1.43 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 200732 kb
Host smart-807804f7-c8e7-4748-88bf-8dea1d199044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154626872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3154626872
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3790151506
Short name T78
Test name
Test status
Simulation time 43371220 ps
CPU time 0.92 seconds
Started Jul 24 04:25:17 PM PDT 24
Finished Jul 24 04:25:18 PM PDT 24
Peak memory 199740 kb
Host smart-2abf98c7-0606-4727-a5e0-ff0984a1463c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790151506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3790151506
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2434427611
Short name T1304
Test name
Test status
Simulation time 13711563 ps
CPU time 0.59 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:51 PM PDT 24
Peak memory 195072 kb
Host smart-cae48298-baea-4d62-a07b-f266cb5f4c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434427611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2434427611
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4112693879
Short name T1312
Test name
Test status
Simulation time 15365319 ps
CPU time 0.59 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 195100 kb
Host smart-f9fc08cd-4b1e-4b70-bd98-a48eb14de341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112693879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4112693879
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.754457561
Short name T1205
Test name
Test status
Simulation time 30039684 ps
CPU time 0.6 seconds
Started Jul 24 04:21:06 PM PDT 24
Finished Jul 24 04:21:06 PM PDT 24
Peak memory 195096 kb
Host smart-d633b554-3ef1-4d9e-a25d-697db58a1ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754457561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.754457561
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1945671397
Short name T1234
Test name
Test status
Simulation time 50632294 ps
CPU time 0.59 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 195100 kb
Host smart-a2bd794b-b814-4340-98e4-9dc72b159bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945671397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1945671397
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.814297760
Short name T1211
Test name
Test status
Simulation time 12734489 ps
CPU time 0.52 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 194720 kb
Host smart-c371ebd3-f724-4758-9b88-a8554b5b9fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814297760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.814297760
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.538932674
Short name T1185
Test name
Test status
Simulation time 46235293 ps
CPU time 0.57 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195056 kb
Host smart-9987b60a-d92c-45cc-8a83-f6a1aac970f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538932674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.538932674
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1669676118
Short name T1305
Test name
Test status
Simulation time 13200184 ps
CPU time 0.59 seconds
Started Jul 24 04:22:43 PM PDT 24
Finished Jul 24 04:22:44 PM PDT 24
Peak memory 195120 kb
Host smart-0d839162-d17a-4991-86e1-0274b87d84e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669676118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1669676118
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1849534643
Short name T1225
Test name
Test status
Simulation time 43212032 ps
CPU time 0.56 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 195072 kb
Host smart-a50113eb-d088-44b0-b81f-3c6a7cf49bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849534643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1849534643
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3687501335
Short name T1296
Test name
Test status
Simulation time 117300090 ps
CPU time 0.55 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 195040 kb
Host smart-5c0c1394-abb2-42b1-a349-11a2126d256e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687501335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3687501335
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1631164057
Short name T1183
Test name
Test status
Simulation time 40349961 ps
CPU time 0.55 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 195048 kb
Host smart-d6cd7722-058d-45bd-8807-e75e4da02e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631164057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1631164057
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.4056530485
Short name T1186
Test name
Test status
Simulation time 220261805 ps
CPU time 0.66 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:21 PM PDT 24
Peak memory 196100 kb
Host smart-1e83d3a0-d0dc-4bd7-b9ea-5e7d9250c062
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056530485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.4056530485
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1304056475
Short name T59
Test name
Test status
Simulation time 58264486 ps
CPU time 2.26 seconds
Started Jul 24 04:23:55 PM PDT 24
Finished Jul 24 04:23:57 PM PDT 24
Peak memory 198788 kb
Host smart-8e35087c-2234-4653-926a-dc11a42e2912
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304056475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1304056475
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.918740711
Short name T1290
Test name
Test status
Simulation time 15918682 ps
CPU time 0.6 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:36 PM PDT 24
Peak memory 196168 kb
Host smart-f1d37161-b1c4-4b92-9db1-c99c1fe29c5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918740711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.918740711
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4099815354
Short name T1292
Test name
Test status
Simulation time 27926713 ps
CPU time 0.81 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 200448 kb
Host smart-a98c9681-c9b6-45e7-8288-57700dbcd253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099815354 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4099815354
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.706562577
Short name T1213
Test name
Test status
Simulation time 79741204 ps
CPU time 0.61 seconds
Started Jul 24 04:21:37 PM PDT 24
Finished Jul 24 04:21:38 PM PDT 24
Peak memory 196240 kb
Host smart-5fe8aeba-0645-49f3-bf30-0f784f6a3989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706562577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.706562577
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1652897177
Short name T1200
Test name
Test status
Simulation time 24999661 ps
CPU time 0.6 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 194648 kb
Host smart-33b4d6bb-fc0c-4917-a1dd-b774b1a4f52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652897177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1652897177
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4184153440
Short name T1220
Test name
Test status
Simulation time 106263300 ps
CPU time 0.78 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 198184 kb
Host smart-47c91756-f589-40fa-9d56-cde5fc7934dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184153440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4184153440
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1778051197
Short name T1196
Test name
Test status
Simulation time 150218506 ps
CPU time 1.66 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 200440 kb
Host smart-f418470c-da20-45f5-beb9-1abae11078a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778051197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1778051197
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3495273728
Short name T82
Test name
Test status
Simulation time 436431110 ps
CPU time 1.32 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:36 PM PDT 24
Peak memory 200016 kb
Host smart-465831b2-e82e-4621-b143-5b89ea594ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495273728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3495273728
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.530237369
Short name T1280
Test name
Test status
Simulation time 11929781 ps
CPU time 0.58 seconds
Started Jul 24 04:22:15 PM PDT 24
Finished Jul 24 04:22:16 PM PDT 24
Peak memory 194960 kb
Host smart-4d3dcf95-d436-47eb-9101-c74e93883f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530237369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.530237369
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3829443237
Short name T1195
Test name
Test status
Simulation time 35639915 ps
CPU time 0.57 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 193328 kb
Host smart-3bcde147-90f5-48a2-8a9c-0fb2091e986d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829443237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3829443237
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4056947505
Short name T1278
Test name
Test status
Simulation time 44762462 ps
CPU time 0.62 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:04 PM PDT 24
Peak memory 195112 kb
Host smart-4fbc9c69-018b-4194-890e-0a15b1029019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056947505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4056947505
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.551622554
Short name T1248
Test name
Test status
Simulation time 14362933 ps
CPU time 0.58 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 194408 kb
Host smart-ac2cc389-1bef-4582-957b-8e3e396dde4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551622554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.551622554
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2023327741
Short name T1180
Test name
Test status
Simulation time 23684839 ps
CPU time 0.61 seconds
Started Jul 24 04:21:59 PM PDT 24
Finished Jul 24 04:22:00 PM PDT 24
Peak memory 195484 kb
Host smart-8ae4f13c-f5a7-4377-8d20-77174d923f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023327741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2023327741
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1078819493
Short name T1241
Test name
Test status
Simulation time 46310918 ps
CPU time 0.56 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195104 kb
Host smart-0b684093-a2fd-4a36-80de-93f4f2871e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078819493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1078819493
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2136704146
Short name T1242
Test name
Test status
Simulation time 15200444 ps
CPU time 0.62 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 195112 kb
Host smart-f5684d7a-6e89-479a-8b17-17304d95a5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136704146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2136704146
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.237480674
Short name T1255
Test name
Test status
Simulation time 16412857 ps
CPU time 0.58 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195080 kb
Host smart-335b648a-d91d-44bd-b427-eb5caeaac436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237480674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.237480674
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3038420019
Short name T1190
Test name
Test status
Simulation time 18671712 ps
CPU time 0.58 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:04 PM PDT 24
Peak memory 195184 kb
Host smart-3dc848cb-6ced-4156-914a-222fb2d56126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038420019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3038420019
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1762191072
Short name T1182
Test name
Test status
Simulation time 14667392 ps
CPU time 0.57 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 195072 kb
Host smart-6631ca5b-39ee-4306-9015-f2fa7ff15256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762191072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1762191072
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1503435507
Short name T1178
Test name
Test status
Simulation time 68020344 ps
CPU time 0.65 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:21 PM PDT 24
Peak memory 195408 kb
Host smart-0799fe32-7db1-442d-a0ca-0c851c56474a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503435507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1503435507
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1728203457
Short name T60
Test name
Test status
Simulation time 37035244 ps
CPU time 1.43 seconds
Started Jul 24 04:21:04 PM PDT 24
Finished Jul 24 04:21:05 PM PDT 24
Peak memory 198360 kb
Host smart-a517a448-d874-40df-bd5e-5b54a80ed1ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728203457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1728203457
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1748285853
Short name T1181
Test name
Test status
Simulation time 20880226 ps
CPU time 0.59 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 196120 kb
Host smart-f62c603f-00e7-40fd-b7c8-6cd82c7bc86f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748285853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1748285853
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3450305806
Short name T1249
Test name
Test status
Simulation time 202524439 ps
CPU time 0.71 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:05 PM PDT 24
Peak memory 199576 kb
Host smart-6753347f-6ed4-4b79-a295-e90490f41eb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450305806 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3450305806
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1483814654
Short name T1270
Test name
Test status
Simulation time 15048935 ps
CPU time 0.57 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:46 PM PDT 24
Peak memory 196108 kb
Host smart-edc185fc-1b2c-4557-895c-b4fafc0a52c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483814654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1483814654
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2116843408
Short name T1302
Test name
Test status
Simulation time 25101932 ps
CPU time 0.56 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 194728 kb
Host smart-8c3e86a8-d914-4824-9051-26cbda9f5d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116843408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2116843408
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.597690202
Short name T1287
Test name
Test status
Simulation time 50824440 ps
CPU time 0.7 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 197692 kb
Host smart-ea7723db-2403-4fcd-a310-a75d240188be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597690202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.597690202
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4291311196
Short name T1229
Test name
Test status
Simulation time 1195332754 ps
CPU time 1.41 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:12 PM PDT 24
Peak memory 200320 kb
Host smart-ab1f34e8-add3-479e-bf55-064ed2d8e1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291311196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4291311196
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.403971978
Short name T81
Test name
Test status
Simulation time 209817846 ps
CPU time 1.28 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 200080 kb
Host smart-6d43bc8b-adbb-4dbe-9b18-fd52f07f3879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403971978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.403971978
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4238469848
Short name T1223
Test name
Test status
Simulation time 113018002 ps
CPU time 0.57 seconds
Started Jul 24 04:22:07 PM PDT 24
Finished Jul 24 04:22:07 PM PDT 24
Peak memory 195068 kb
Host smart-4e908a51-8eda-4c69-9255-89b20da84c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238469848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4238469848
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.364243787
Short name T1174
Test name
Test status
Simulation time 21414299 ps
CPU time 0.63 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195056 kb
Host smart-983b361a-3a0a-4740-bf65-8caee0f23dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364243787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.364243787
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1397976966
Short name T1251
Test name
Test status
Simulation time 13689943 ps
CPU time 0.58 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 195104 kb
Host smart-a15198f1-6c7a-4e21-8109-980bee972ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397976966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1397976966
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1244470072
Short name T1193
Test name
Test status
Simulation time 27227838 ps
CPU time 0.58 seconds
Started Jul 24 04:21:50 PM PDT 24
Finished Jul 24 04:21:51 PM PDT 24
Peak memory 195248 kb
Host smart-a5bd4a5c-9232-47ea-bd11-9a7c469305e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244470072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1244470072
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1159405427
Short name T1189
Test name
Test status
Simulation time 40706120 ps
CPU time 0.56 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:25:59 PM PDT 24
Peak memory 194988 kb
Host smart-34173482-c5bd-481d-8afa-fd110d450b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159405427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1159405427
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2026298898
Short name T1238
Test name
Test status
Simulation time 19561757 ps
CPU time 0.57 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:03 PM PDT 24
Peak memory 195160 kb
Host smart-c3b356f8-0685-4dc8-8247-6be6d4660f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026298898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2026298898
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3476789499
Short name T1218
Test name
Test status
Simulation time 26834933 ps
CPU time 0.62 seconds
Started Jul 24 04:22:33 PM PDT 24
Finished Jul 24 04:22:33 PM PDT 24
Peak memory 195152 kb
Host smart-f915ef27-8f09-4f34-bfdb-8e21ef4d5610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476789499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3476789499
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3385282065
Short name T1284
Test name
Test status
Simulation time 16392602 ps
CPU time 0.56 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 193896 kb
Host smart-3417fd1d-3028-40a5-bab5-502603694a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385282065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3385282065
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.934003804
Short name T1202
Test name
Test status
Simulation time 46716395 ps
CPU time 0.59 seconds
Started Jul 24 04:21:06 PM PDT 24
Finished Jul 24 04:21:06 PM PDT 24
Peak memory 195112 kb
Host smart-0e7bb3e6-00c1-43ad-9618-44b89a168591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934003804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.934003804
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3989359071
Short name T1272
Test name
Test status
Simulation time 11404124 ps
CPU time 0.57 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 193672 kb
Host smart-f8b09149-3439-4ca0-bafa-1eed52f6b7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989359071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3989359071
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4026625169
Short name T1179
Test name
Test status
Simulation time 240199667 ps
CPU time 1.01 seconds
Started Jul 24 04:22:13 PM PDT 24
Finished Jul 24 04:22:14 PM PDT 24
Peak memory 200576 kb
Host smart-1c390194-2985-4f22-ae5d-2b20842c46ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026625169 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4026625169
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.395587648
Short name T1282
Test name
Test status
Simulation time 35468384 ps
CPU time 0.56 seconds
Started Jul 24 04:21:25 PM PDT 24
Finished Jul 24 04:21:26 PM PDT 24
Peak memory 196196 kb
Host smart-9e5f3f59-f49b-4ce8-a0f7-751a8b064348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395587648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.395587648
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1051640404
Short name T1281
Test name
Test status
Simulation time 31616619 ps
CPU time 0.6 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:24 PM PDT 24
Peak memory 194020 kb
Host smart-16bafc8c-725f-4eeb-9a1b-45d471bf3ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051640404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1051640404
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2480763029
Short name T1232
Test name
Test status
Simulation time 15295671 ps
CPU time 0.69 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:25:45 PM PDT 24
Peak memory 197484 kb
Host smart-46fd49db-63b7-4336-b23f-3668b13a55f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480763029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2480763029
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.396936057
Short name T1300
Test name
Test status
Simulation time 60411932 ps
CPU time 0.83 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 199764 kb
Host smart-25c12017-92b6-4856-af1f-3686d0727541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396936057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.396936057
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.943850084
Short name T1285
Test name
Test status
Simulation time 248923885 ps
CPU time 1.25 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:21 PM PDT 24
Peak memory 199952 kb
Host smart-f7abacf2-f8f0-493d-ba98-31c5df5e6c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943850084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.943850084
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2726225600
Short name T1276
Test name
Test status
Simulation time 31419797 ps
CPU time 0.9 seconds
Started Jul 24 04:22:57 PM PDT 24
Finished Jul 24 04:22:58 PM PDT 24
Peak memory 200548 kb
Host smart-378cde28-caa8-40f6-92c8-1148c8087ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726225600 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2726225600
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1795293008
Short name T1279
Test name
Test status
Simulation time 17510945 ps
CPU time 0.63 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 196184 kb
Host smart-c2cc27e3-06fd-4a65-a274-43247400d14e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795293008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1795293008
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3541008406
Short name T1222
Test name
Test status
Simulation time 56673026 ps
CPU time 0.54 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:25:59 PM PDT 24
Peak memory 194860 kb
Host smart-66318265-eb15-43cb-bdc4-d672b63b00a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541008406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3541008406
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1163965429
Short name T1259
Test name
Test status
Simulation time 116520662 ps
CPU time 0.76 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 197408 kb
Host smart-0e449ed6-6cae-4762-9ba5-33f06daea090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163965429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1163965429
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3970802448
Short name T1299
Test name
Test status
Simulation time 252533910 ps
CPU time 1.28 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:26:01 PM PDT 24
Peak memory 200632 kb
Host smart-4f197887-c4a3-4b28-a2fc-fdad72fd3bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970802448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3970802448
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2547697190
Short name T1209
Test name
Test status
Simulation time 300476971 ps
CPU time 0.87 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 200252 kb
Host smart-2a3972a6-fc33-4c22-ad7c-54f734f92ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547697190 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2547697190
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2214244471
Short name T72
Test name
Test status
Simulation time 171183199 ps
CPU time 0.57 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 195876 kb
Host smart-412ef943-1c06-43b2-ab0f-224fd85ec4e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214244471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2214244471
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2850145179
Short name T1187
Test name
Test status
Simulation time 12726912 ps
CPU time 0.55 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 193948 kb
Host smart-3b08a64b-bb8e-4e30-8b43-afe6f667272e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850145179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2850145179
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2241866630
Short name T75
Test name
Test status
Simulation time 67055582 ps
CPU time 0.66 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 194372 kb
Host smart-0c36dd42-1de3-4828-abb2-c1ca681dad0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241866630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2241866630
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.723236562
Short name T1289
Test name
Test status
Simulation time 84867877 ps
CPU time 1.39 seconds
Started Jul 24 04:21:23 PM PDT 24
Finished Jul 24 04:21:24 PM PDT 24
Peak memory 200740 kb
Host smart-a3d92aa8-ee7a-4be3-9c3b-95f6ab3f9609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723236562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.723236562
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3372915873
Short name T116
Test name
Test status
Simulation time 489734128 ps
CPU time 1.39 seconds
Started Jul 24 04:23:28 PM PDT 24
Finished Jul 24 04:23:30 PM PDT 24
Peak memory 199968 kb
Host smart-ec926509-5bbd-4275-bef4-1dbea461b950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372915873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3372915873
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.158406911
Short name T1221
Test name
Test status
Simulation time 23923741 ps
CPU time 0.73 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 199372 kb
Host smart-88e5abf1-fb11-4f4c-bca1-58c12186e056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158406911 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.158406911
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1587042586
Short name T1291
Test name
Test status
Simulation time 11221350 ps
CPU time 0.56 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:39 PM PDT 24
Peak memory 194564 kb
Host smart-b4607443-1ae3-49b2-b6a4-8ac783494d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587042586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1587042586
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3811432208
Short name T1267
Test name
Test status
Simulation time 21904973 ps
CPU time 0.63 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 193316 kb
Host smart-f7e331ad-c849-49c5-af2a-8649fe7e695a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811432208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3811432208
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1000553585
Short name T1235
Test name
Test status
Simulation time 54481268 ps
CPU time 0.72 seconds
Started Jul 24 04:23:11 PM PDT 24
Finished Jul 24 04:23:12 PM PDT 24
Peak memory 197780 kb
Host smart-3aa47bf5-7dd3-4e80-ae18-9090a8cab859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000553585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1000553585
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2656625383
Short name T1188
Test name
Test status
Simulation time 118042099 ps
CPU time 1.23 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 200260 kb
Host smart-a461e0ba-c5c4-4fd8-93be-d2f47dba4a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656625383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2656625383
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1615232743
Short name T1228
Test name
Test status
Simulation time 77227870 ps
CPU time 1.22 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 200052 kb
Host smart-67bef6a0-2ea5-428e-b85e-a50be8bb1cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615232743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1615232743
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1771097602
Short name T1227
Test name
Test status
Simulation time 263847264 ps
CPU time 1.43 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 200752 kb
Host smart-c4047de8-f1cd-4576-9b42-82fb32752d93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771097602 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1771097602
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.831752806
Short name T1288
Test name
Test status
Simulation time 13619038 ps
CPU time 0.62 seconds
Started Jul 24 04:23:25 PM PDT 24
Finished Jul 24 04:23:26 PM PDT 24
Peak memory 196580 kb
Host smart-25d52d80-2fa5-4665-a885-09a51984bf8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831752806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.831752806
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2648630930
Short name T1309
Test name
Test status
Simulation time 33856945 ps
CPU time 0.57 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 195064 kb
Host smart-9f24ac3b-8dbf-497a-9ada-b47830061314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648630930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2648630930
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1668595298
Short name T71
Test name
Test status
Simulation time 15701296 ps
CPU time 0.7 seconds
Started Jul 24 04:25:32 PM PDT 24
Finished Jul 24 04:25:33 PM PDT 24
Peak memory 195760 kb
Host smart-758fa58f-d99d-4676-9878-d9ab9d99a0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668595298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1668595298
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2092975087
Short name T1219
Test name
Test status
Simulation time 334700497 ps
CPU time 1.28 seconds
Started Jul 24 04:23:11 PM PDT 24
Finished Jul 24 04:23:13 PM PDT 24
Peak memory 200760 kb
Host smart-2c967f6d-53fa-4434-8bd4-89e9de548658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092975087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2092975087
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1696965604
Short name T1266
Test name
Test status
Simulation time 182303057 ps
CPU time 0.9 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 198884 kb
Host smart-214b007e-d354-44f0-a319-69cdd7b9d678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696965604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1696965604
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4095842447
Short name T8
Test name
Test status
Simulation time 85294676323 ps
CPU time 27.82 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:26:14 PM PDT 24
Peak memory 198888 kb
Host smart-c97018b8-c837-4ee2-a1b2-75b2d6d2d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095842447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4095842447
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.737262351
Short name T1002
Test name
Test status
Simulation time 40588619595 ps
CPU time 34.49 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:45 PM PDT 24
Peak memory 199828 kb
Host smart-425f3ad6-4ea7-402e-88c1-4fca0e08ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737262351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.737262351
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.720776989
Short name T354
Test name
Test status
Simulation time 15461606473 ps
CPU time 6.24 seconds
Started Jul 24 04:20:52 PM PDT 24
Finished Jul 24 04:20:58 PM PDT 24
Peak memory 199800 kb
Host smart-a16dc4e5-3671-41ef-89a3-9915e11a7750
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720776989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.720776989
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2833208765
Short name T1037
Test name
Test status
Simulation time 92480067293 ps
CPU time 597.13 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:35:56 PM PDT 24
Peak memory 199956 kb
Host smart-aee46279-d2f9-473d-8982-0939ba76cb6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833208765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2833208765
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3147928924
Short name T1032
Test name
Test status
Simulation time 2158846260 ps
CPU time 1.5 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 196952 kb
Host smart-20232c65-ec47-4f60-ae0f-40d713b4ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147928924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3147928924
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1026311936
Short name T1113
Test name
Test status
Simulation time 41096929378 ps
CPU time 37.28 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:22:12 PM PDT 24
Peak memory 208220 kb
Host smart-ed147c36-60ca-4c21-b3b8-f955f6395cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026311936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1026311936
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1300689316
Short name T837
Test name
Test status
Simulation time 11669326574 ps
CPU time 303.35 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 199960 kb
Host smart-5d68911f-8dba-477b-b2e7-23ef69af78e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300689316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1300689316
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.735600834
Short name T457
Test name
Test status
Simulation time 5443493048 ps
CPU time 22.79 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:26:09 PM PDT 24
Peak memory 197968 kb
Host smart-c304a605-b59b-43f5-9992-33d559cd4c88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735600834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.735600834
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.488555696
Short name T484
Test name
Test status
Simulation time 11673456261 ps
CPU time 24.44 seconds
Started Jul 24 04:25:08 PM PDT 24
Finished Jul 24 04:25:33 PM PDT 24
Peak memory 199708 kb
Host smart-e16d9903-d72e-4589-bc10-f5b7343b8fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488555696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.488555696
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1976197042
Short name T315
Test name
Test status
Simulation time 3784394488 ps
CPU time 6.8 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:17 PM PDT 24
Peak memory 196636 kb
Host smart-05806d0d-2c73-451d-b334-130cce59e5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976197042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1976197042
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3445710059
Short name T87
Test name
Test status
Simulation time 57372913 ps
CPU time 0.81 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:25:17 PM PDT 24
Peak memory 218248 kb
Host smart-1c67b4ab-29b8-4842-93d5-69dd836b3a64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445710059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3445710059
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.445297153
Short name T566
Test name
Test status
Simulation time 556193099 ps
CPU time 2.8 seconds
Started Jul 24 04:22:45 PM PDT 24
Finished Jul 24 04:22:48 PM PDT 24
Peak memory 198336 kb
Host smart-315ec7d0-c618-4057-ad0e-9d830d73040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445297153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.445297153
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.695533398
Short name T575
Test name
Test status
Simulation time 83946077805 ps
CPU time 207.74 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:29:23 PM PDT 24
Peak memory 208272 kb
Host smart-2c5a5f1e-8e3b-4912-a992-13f1f7961d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695533398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.695533398
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.459468762
Short name T996
Test name
Test status
Simulation time 1088240599 ps
CPU time 2.92 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 199252 kb
Host smart-50541f6b-de8f-42fa-9921-54a0a79a403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459468762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.459468762
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1982013939
Short name T513
Test name
Test status
Simulation time 993114719 ps
CPU time 1.38 seconds
Started Jul 24 04:22:36 PM PDT 24
Finished Jul 24 04:22:38 PM PDT 24
Peak memory 199044 kb
Host smart-8f2015a3-a36b-44ff-9d61-c44412548bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982013939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1982013939
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4021606932
Short name T684
Test name
Test status
Simulation time 110055743 ps
CPU time 0.56 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:26:08 PM PDT 24
Peak memory 195688 kb
Host smart-99fa135a-6266-45db-9a59-7f9398b478e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021606932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4021606932
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3507607393
Short name T562
Test name
Test status
Simulation time 14811318257 ps
CPU time 21.8 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:26:35 PM PDT 24
Peak memory 199908 kb
Host smart-f487fc83-f73b-44b3-9d57-ad79b280c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507607393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3507607393
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.656783130
Short name T852
Test name
Test status
Simulation time 75335009542 ps
CPU time 106.08 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:28:05 PM PDT 24
Peak memory 199948 kb
Host smart-ca24fe19-d258-48e6-8dd1-0e720f61575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656783130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.656783130
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.833784896
Short name T463
Test name
Test status
Simulation time 16215040192 ps
CPU time 22.31 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:33 PM PDT 24
Peak memory 200096 kb
Host smart-b09c6970-7b1c-430a-b1e6-a109f1ef9b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833784896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.833784896
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2471019695
Short name T489
Test name
Test status
Simulation time 89718369832 ps
CPU time 243.64 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:30:17 PM PDT 24
Peak memory 199928 kb
Host smart-42cd23a6-89ee-4de3-94aa-1a7050e316bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471019695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2471019695
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2407833787
Short name T1088
Test name
Test status
Simulation time 79231003951 ps
CPU time 156.76 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199988 kb
Host smart-7856a5ec-1004-4545-9ea8-2fc84f8f16be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407833787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2407833787
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3911895776
Short name T1105
Test name
Test status
Simulation time 2788073873 ps
CPU time 2.93 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:26:15 PM PDT 24
Peak memory 195860 kb
Host smart-b47ae6a9-6fd7-4b7b-9f02-859ad39eebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911895776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3911895776
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1906155247
Short name T283
Test name
Test status
Simulation time 18397242975 ps
CPU time 29.52 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 200172 kb
Host smart-306ebd47-8f5b-4201-86ee-5ac32d6bc42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906155247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1906155247
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.605941468
Short name T1006
Test name
Test status
Simulation time 4812137899 ps
CPU time 47.48 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:27:01 PM PDT 24
Peak memory 199996 kb
Host smart-a8a0c838-85ee-445b-9661-51e3c1346050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605941468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.605941468
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1482169887
Short name T642
Test name
Test status
Simulation time 5576856488 ps
CPU time 22.24 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:33 PM PDT 24
Peak memory 198812 kb
Host smart-4a87a548-789a-41c3-a269-ce801820e485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482169887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1482169887
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3056772720
Short name T486
Test name
Test status
Simulation time 19378786512 ps
CPU time 28.55 seconds
Started Jul 24 04:26:08 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 199912 kb
Host smart-f55815c4-70c5-468b-b348-35bb42a63731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056772720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3056772720
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2729645583
Short name T593
Test name
Test status
Simulation time 3837981715 ps
CPU time 1.86 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:26:21 PM PDT 24
Peak memory 196540 kb
Host smart-6fc15d08-90bf-419b-bf9b-0c07438eeeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729645583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2729645583
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.1713277978
Short name T420
Test name
Test status
Simulation time 452042215 ps
CPU time 1.72 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:06 PM PDT 24
Peak memory 199072 kb
Host smart-60f4f693-cb05-4f69-a199-d53a987e8bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713277978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1713277978
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1943109830
Short name T750
Test name
Test status
Simulation time 331071720708 ps
CPU time 207.04 seconds
Started Jul 24 04:26:08 PM PDT 24
Finished Jul 24 04:29:36 PM PDT 24
Peak memory 199916 kb
Host smart-18d97643-1c7e-492c-806d-8846754c1450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943109830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1943109830
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3856530790
Short name T594
Test name
Test status
Simulation time 9957926268 ps
CPU time 5.93 seconds
Started Jul 24 04:26:08 PM PDT 24
Finished Jul 24 04:26:14 PM PDT 24
Peak memory 200032 kb
Host smart-ca0647a2-656c-4064-b7e5-0616bc3b94f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856530790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3856530790
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1231173360
Short name T715
Test name
Test status
Simulation time 19730629078 ps
CPU time 30.87 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 199044 kb
Host smart-019a6b67-8972-4420-94c7-6a554ccd3ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231173360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1231173360
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2318430965
Short name T441
Test name
Test status
Simulation time 42105865 ps
CPU time 0.58 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:26:44 PM PDT 24
Peak memory 195636 kb
Host smart-787d00e0-607e-4b61-8a9e-93be74499bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318430965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2318430965
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3649529250
Short name T972
Test name
Test status
Simulation time 63907202992 ps
CPU time 88.58 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:28:04 PM PDT 24
Peak memory 199884 kb
Host smart-daabff20-5068-43a0-94f6-ca04a720b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649529250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3649529250
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1688303210
Short name T687
Test name
Test status
Simulation time 174689574411 ps
CPU time 35.88 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:27:12 PM PDT 24
Peak memory 199984 kb
Host smart-1f1c8ab6-d3ba-41ba-993c-b8d3896ee7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688303210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1688303210
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.659281044
Short name T108
Test name
Test status
Simulation time 205597620330 ps
CPU time 59.49 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 199884 kb
Host smart-800f857d-d333-4895-94f9-4d92a1a433f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659281044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.659281044
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1460441739
Short name T521
Test name
Test status
Simulation time 22505082968 ps
CPU time 32.45 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:27:08 PM PDT 24
Peak memory 196024 kb
Host smart-97939ada-1235-44fd-bdce-48d1934cb298
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460441739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1460441739
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2598333752
Short name T497
Test name
Test status
Simulation time 71556106742 ps
CPU time 171.5 seconds
Started Jul 24 04:26:33 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199944 kb
Host smart-531b3906-ec4a-421c-a70e-12d98d3ac4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598333752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2598333752
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2390145925
Short name T974
Test name
Test status
Simulation time 595034645 ps
CPU time 0.74 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 195492 kb
Host smart-a0b59833-ddf1-416b-a1b7-dbbca7353987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390145925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2390145925
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3372319005
Short name T649
Test name
Test status
Simulation time 248373540902 ps
CPU time 164.65 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 199992 kb
Host smart-b293211a-d0a6-432f-bf99-a76cc0151e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372319005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3372319005
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4056587770
Short name T845
Test name
Test status
Simulation time 19967777981 ps
CPU time 160.36 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:29:21 PM PDT 24
Peak memory 199948 kb
Host smart-244c104a-c71e-4d34-86b2-da1cdd92042f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056587770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4056587770
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.500558372
Short name T576
Test name
Test status
Simulation time 7160644214 ps
CPU time 13.3 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:54 PM PDT 24
Peak memory 198104 kb
Host smart-c788486b-6cee-49e4-9f72-b9e83365577b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500558372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.500558372
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1213620546
Short name T1071
Test name
Test status
Simulation time 24564185252 ps
CPU time 44.22 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:27:27 PM PDT 24
Peak memory 199816 kb
Host smart-35bb41c3-4420-4f21-869f-21308b8c73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213620546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1213620546
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.196976675
Short name T557
Test name
Test status
Simulation time 2883802613 ps
CPU time 1.62 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 195792 kb
Host smart-0bc9b743-2924-4b79-9baa-ae7659750c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196976675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.196976675
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1667339056
Short name T711
Test name
Test status
Simulation time 5902228390 ps
CPU time 8.14 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 199924 kb
Host smart-709a05fb-7e54-490b-b662-c1225c3bfa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667339056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1667339056
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.4226093951
Short name T508
Test name
Test status
Simulation time 91830989725 ps
CPU time 158.69 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 208244 kb
Host smart-3034e2bc-03a0-49ce-ab22-07b5e52054fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226093951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4226093951
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.425515305
Short name T579
Test name
Test status
Simulation time 778097399 ps
CPU time 2.09 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:26:44 PM PDT 24
Peak memory 198332 kb
Host smart-5805ff1f-c989-4fb8-a81a-1b7569dbb25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425515305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.425515305
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2900448838
Short name T1155
Test name
Test status
Simulation time 69285261626 ps
CPU time 101.91 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 200012 kb
Host smart-f593fa43-fd04-4c43-b8f5-567d9bb1c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900448838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2900448838
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3390624546
Short name T1172
Test name
Test status
Simulation time 166520385026 ps
CPU time 49.38 seconds
Started Jul 24 04:30:11 PM PDT 24
Finished Jul 24 04:31:01 PM PDT 24
Peak memory 199912 kb
Host smart-49dd0cf5-6691-4557-89cc-a650d7fae1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390624546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3390624546
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1488870579
Short name T1134
Test name
Test status
Simulation time 68792553635 ps
CPU time 112.05 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:32:05 PM PDT 24
Peak memory 199872 kb
Host smart-bc5efa23-fe04-4920-a346-0d7c966082ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488870579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1488870579
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1699412915
Short name T252
Test name
Test status
Simulation time 28746555197 ps
CPU time 39.46 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199980 kb
Host smart-62de8f8b-376a-4203-9f2c-4da2a696d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699412915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1699412915
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1797540410
Short name T503
Test name
Test status
Simulation time 24485564398 ps
CPU time 37.05 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:30:49 PM PDT 24
Peak memory 200028 kb
Host smart-f4d23a6a-1fe8-4525-a845-1bf657fa6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797540410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1797540410
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3989772859
Short name T168
Test name
Test status
Simulation time 143683385695 ps
CPU time 30.59 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:30:43 PM PDT 24
Peak memory 199824 kb
Host smart-59f35050-da48-455f-a86a-4824d6acb6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989772859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3989772859
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2488416459
Short name T1012
Test name
Test status
Simulation time 132893215478 ps
CPU time 61.36 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:31:11 PM PDT 24
Peak memory 199896 kb
Host smart-d4a20a5a-7585-4b30-afd1-d3a12d774662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488416459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2488416459
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.480761704
Short name T902
Test name
Test status
Simulation time 275299522130 ps
CPU time 86.57 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:31:42 PM PDT 24
Peak memory 200024 kb
Host smart-f77a088f-d370-4dbc-b7ca-8c69b28aba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480761704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.480761704
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2146297289
Short name T359
Test name
Test status
Simulation time 87885873328 ps
CPU time 34.96 seconds
Started Jul 24 04:30:16 PM PDT 24
Finished Jul 24 04:30:51 PM PDT 24
Peak memory 200324 kb
Host smart-5dc8335b-3525-443b-ac52-fe9c3ec5339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146297289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2146297289
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2113485383
Short name T577
Test name
Test status
Simulation time 32390099 ps
CPU time 0.55 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:26:40 PM PDT 24
Peak memory 195684 kb
Host smart-1f576258-77cc-4f6b-986c-b19fdd58dc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113485383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2113485383
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2947601370
Short name T518
Test name
Test status
Simulation time 184554703041 ps
CPU time 45.49 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:27:18 PM PDT 24
Peak memory 199928 kb
Host smart-11a8a799-5c1a-46df-82d0-d415065d162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947601370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2947601370
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.966960420
Short name T710
Test name
Test status
Simulation time 37210337669 ps
CPU time 45.25 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:27:28 PM PDT 24
Peak memory 199936 kb
Host smart-267cf342-631c-43f9-883e-9cb7711ec27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966960420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.966960420
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.3867744172
Short name T802
Test name
Test status
Simulation time 40635688832 ps
CPU time 71.92 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:27:52 PM PDT 24
Peak memory 199956 kb
Host smart-563317ff-9244-4baf-a110-50c0974fba98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867744172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3867744172
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1010567118
Short name T351
Test name
Test status
Simulation time 49940994879 ps
CPU time 108.64 seconds
Started Jul 24 04:26:44 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 199876 kb
Host smart-59710ac9-feef-4a76-ab10-c3b2f02de430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010567118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1010567118
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.338322137
Short name T831
Test name
Test status
Simulation time 11419891016 ps
CPU time 14.99 seconds
Started Jul 24 04:26:52 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 198548 kb
Host smart-c619f0c9-e6ef-4105-9e93-252fdb8740f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338322137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.338322137
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3589104864
Short name T680
Test name
Test status
Simulation time 47690790012 ps
CPU time 84.41 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:28:06 PM PDT 24
Peak memory 199524 kb
Host smart-f2afa10c-403d-49f4-b496-b968dc935bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589104864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3589104864
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1916228977
Short name T850
Test name
Test status
Simulation time 6766505433 ps
CPU time 13.58 seconds
Started Jul 24 04:26:45 PM PDT 24
Finished Jul 24 04:26:59 PM PDT 24
Peak memory 199192 kb
Host smart-7cbce270-0bf4-444e-bf53-9de842209922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916228977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1916228977
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4122793796
Short name T938
Test name
Test status
Simulation time 95303067008 ps
CPU time 16.37 seconds
Started Jul 24 04:26:47 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 199976 kb
Host smart-46e08186-0605-4e6a-a6b3-46d686639292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122793796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4122793796
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2354710864
Short name T821
Test name
Test status
Simulation time 59337562446 ps
CPU time 92.86 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:28:13 PM PDT 24
Peak memory 196092 kb
Host smart-6e3725ed-c122-4cd8-8195-abcf90eb0400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354710864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2354710864
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1487202349
Short name T310
Test name
Test status
Simulation time 5798273382 ps
CPU time 5.39 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 199852 kb
Host smart-3640742f-845e-4912-a23a-7423601dfe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487202349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1487202349
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1796568679
Short name T1131
Test name
Test status
Simulation time 262134012400 ps
CPU time 415.69 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:33:37 PM PDT 24
Peak memory 208356 kb
Host smart-fb09ac83-1b5f-45fd-beb7-d03c3779bb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796568679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1796568679
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3274381360
Short name T241
Test name
Test status
Simulation time 359735427927 ps
CPU time 1347.33 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:49:09 PM PDT 24
Peak memory 226876 kb
Host smart-af35e21d-d9a3-484e-816e-a70e622caf36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274381360 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3274381360
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.924031565
Short name T675
Test name
Test status
Simulation time 7349355948 ps
CPU time 10.81 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:57 PM PDT 24
Peak memory 199248 kb
Host smart-63652f52-db54-401a-a235-f62254b8d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924031565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.924031565
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2309809122
Short name T824
Test name
Test status
Simulation time 3961641293 ps
CPU time 6.18 seconds
Started Jul 24 04:26:44 PM PDT 24
Finished Jul 24 04:26:50 PM PDT 24
Peak memory 197372 kb
Host smart-ecc94a82-8527-4b6d-9d47-add8965f1ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309809122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2309809122
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1537175772
Short name T262
Test name
Test status
Simulation time 19916423066 ps
CPU time 25.75 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 199916 kb
Host smart-6d588797-0fb7-4db4-b971-b8492201ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537175772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1537175772
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3995096403
Short name T188
Test name
Test status
Simulation time 30471275562 ps
CPU time 46.42 seconds
Started Jul 24 04:30:13 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 199724 kb
Host smart-dca8b904-d036-4757-854b-85d8212673b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995096403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3995096403
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.604707507
Short name T1141
Test name
Test status
Simulation time 22715600189 ps
CPU time 28.6 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:30:44 PM PDT 24
Peak memory 199848 kb
Host smart-317fb304-1121-432e-ab1c-3354e5a0552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604707507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.604707507
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.580114452
Short name T196
Test name
Test status
Simulation time 183426577256 ps
CPU time 118.13 seconds
Started Jul 24 04:30:14 PM PDT 24
Finished Jul 24 04:32:13 PM PDT 24
Peak memory 199992 kb
Host smart-0968c2a6-e6e4-45cc-b398-cb0164217a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580114452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.580114452
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1352380366
Short name T679
Test name
Test status
Simulation time 10123727791 ps
CPU time 17.6 seconds
Started Jul 24 04:30:17 PM PDT 24
Finished Jul 24 04:30:35 PM PDT 24
Peak memory 200000 kb
Host smart-12919bdb-91e4-44ee-8556-2ec8e5df4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352380366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1352380366
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1989029022
Short name T432
Test name
Test status
Simulation time 141605637398 ps
CPU time 209.19 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:33:44 PM PDT 24
Peak memory 199932 kb
Host smart-258a27ff-6349-44e6-bb75-348cd5573be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989029022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1989029022
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1708615892
Short name T189
Test name
Test status
Simulation time 56703420751 ps
CPU time 50.84 seconds
Started Jul 24 04:30:14 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 200012 kb
Host smart-bc351097-c562-4a2d-bcc1-e7b0102c71ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708615892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1708615892
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1903633328
Short name T1117
Test name
Test status
Simulation time 91664906262 ps
CPU time 37.37 seconds
Started Jul 24 04:30:14 PM PDT 24
Finished Jul 24 04:30:51 PM PDT 24
Peak memory 200132 kb
Host smart-f4390e90-e319-40a6-bb17-6cfca25f1c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903633328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1903633328
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3542996690
Short name T941
Test name
Test status
Simulation time 139822982738 ps
CPU time 158.96 seconds
Started Jul 24 04:30:16 PM PDT 24
Finished Jul 24 04:32:55 PM PDT 24
Peak memory 200032 kb
Host smart-bd892b25-3c85-4c63-b478-fb20834671fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542996690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3542996690
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3790242375
Short name T723
Test name
Test status
Simulation time 46698751 ps
CPU time 0.58 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 195032 kb
Host smart-06559b78-281f-45fb-83c8-60a144392c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790242375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3790242375
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.4293265296
Short name T48
Test name
Test status
Simulation time 24844600504 ps
CPU time 23.22 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 199936 kb
Host smart-3da4bc67-7cb6-43fc-99ae-ddb23128e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293265296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.4293265296
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.922797615
Short name T257
Test name
Test status
Simulation time 48619583320 ps
CPU time 79.22 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 200056 kb
Host smart-26fbf141-9910-498a-8bc0-a7dc29ef2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922797615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.922797615
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.825022153
Short name T364
Test name
Test status
Simulation time 14026754452 ps
CPU time 7.89 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:55 PM PDT 24
Peak memory 199924 kb
Host smart-c2cabd99-0148-49e8-b5c6-ae7bc6ac7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825022153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.825022153
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2991314304
Short name T391
Test name
Test status
Simulation time 246529735974 ps
CPU time 108.69 seconds
Started Jul 24 04:26:42 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 199224 kb
Host smart-8d3bc12b-c11e-4b6d-8eca-edf88c536d0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991314304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2991314304
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3880561912
Short name T777
Test name
Test status
Simulation time 64432247774 ps
CPU time 278.73 seconds
Started Jul 24 04:26:38 PM PDT 24
Finished Jul 24 04:31:17 PM PDT 24
Peak memory 199900 kb
Host smart-eeb471af-6736-4b3a-8e02-6b2c6dbf01e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880561912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3880561912
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.778806557
Short name T788
Test name
Test status
Simulation time 8269356396 ps
CPU time 17.53 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:26:59 PM PDT 24
Peak memory 199320 kb
Host smart-c0ae6a59-d398-4352-8e9a-54695d39ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778806557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.778806557
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1202056705
Short name T1171
Test name
Test status
Simulation time 49213145731 ps
CPU time 12.82 seconds
Started Jul 24 04:26:45 PM PDT 24
Finished Jul 24 04:26:57 PM PDT 24
Peak memory 199836 kb
Host smart-51cb2756-a7d7-4e89-ba09-6a615782a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202056705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1202056705
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3449308951
Short name T413
Test name
Test status
Simulation time 31058941922 ps
CPU time 77.06 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:27:58 PM PDT 24
Peak memory 199836 kb
Host smart-e1a085c9-d8fb-488c-a9be-7305111c3cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449308951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3449308951
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3539408899
Short name T380
Test name
Test status
Simulation time 1169020761 ps
CPU time 2.25 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 197020 kb
Host smart-c58de58c-df56-44bf-a10e-ac9db3666e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539408899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3539408899
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1893947043
Short name T916
Test name
Test status
Simulation time 48822829343 ps
CPU time 21.44 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:27:08 PM PDT 24
Peak memory 199964 kb
Host smart-923588fb-686a-46e3-bc7c-681d23e20752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893947043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1893947043
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1095214404
Short name T542
Test name
Test status
Simulation time 3844941574 ps
CPU time 1.7 seconds
Started Jul 24 04:26:38 PM PDT 24
Finished Jul 24 04:26:40 PM PDT 24
Peak memory 195900 kb
Host smart-1ff75501-8101-491d-8bf5-5f650ac75347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095214404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1095214404
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1314787259
Short name T1067
Test name
Test status
Simulation time 286580912 ps
CPU time 1.38 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:48 PM PDT 24
Peak memory 198056 kb
Host smart-a5503c6b-39e8-4131-ae8f-60c1e44a6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314787259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1314787259
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1988786757
Short name T1167
Test name
Test status
Simulation time 304804490343 ps
CPU time 246.13 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:30:47 PM PDT 24
Peak memory 208324 kb
Host smart-df19a1cd-06cb-4dc3-bebc-358d14519079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988786757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1988786757
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2110150585
Short name T943
Test name
Test status
Simulation time 1622357728 ps
CPU time 1.94 seconds
Started Jul 24 04:26:47 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 198268 kb
Host smart-0d17a80b-a34c-4f14-a31e-8183b341a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110150585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2110150585
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.251567727
Short name T1016
Test name
Test status
Simulation time 82486196117 ps
CPU time 30.7 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 199848 kb
Host smart-1b2ffc8a-4106-45d1-874d-19b05b0cc25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251567727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.251567727
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3167777194
Short name T1046
Test name
Test status
Simulation time 218546063427 ps
CPU time 46.48 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 200000 kb
Host smart-7c5d323b-e815-4eab-b7d6-d609fca500db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167777194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3167777194
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2511620745
Short name T725
Test name
Test status
Simulation time 84340353796 ps
CPU time 38.65 seconds
Started Jul 24 04:30:17 PM PDT 24
Finished Jul 24 04:30:55 PM PDT 24
Peak memory 199960 kb
Host smart-44d5cc27-6b84-43ff-b20d-6fcedd4f97e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511620745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2511620745
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3727505009
Short name T1022
Test name
Test status
Simulation time 74351118834 ps
CPU time 23.31 seconds
Started Jul 24 04:30:18 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 199856 kb
Host smart-ea88729b-395e-403a-bf68-b570a7a330ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727505009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3727505009
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3035981928
Short name T292
Test name
Test status
Simulation time 13240551680 ps
CPU time 39.19 seconds
Started Jul 24 04:30:16 PM PDT 24
Finished Jul 24 04:30:56 PM PDT 24
Peak memory 199932 kb
Host smart-42158032-d6ef-4176-b5b9-255b97e82394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035981928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3035981928
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.779077857
Short name T545
Test name
Test status
Simulation time 55672982054 ps
CPU time 97 seconds
Started Jul 24 04:30:14 PM PDT 24
Finished Jul 24 04:31:52 PM PDT 24
Peak memory 199880 kb
Host smart-16d3d26a-813d-4522-872d-5da8eb4503e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779077857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.779077857
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3166228131
Short name T1120
Test name
Test status
Simulation time 65277465858 ps
CPU time 38.19 seconds
Started Jul 24 04:30:17 PM PDT 24
Finished Jul 24 04:30:56 PM PDT 24
Peak memory 199932 kb
Host smart-a6601f0a-9dce-46c8-a0c6-fb287e8173ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166228131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3166228131
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3769238476
Short name T129
Test name
Test status
Simulation time 36056592845 ps
CPU time 15.66 seconds
Started Jul 24 04:30:16 PM PDT 24
Finished Jul 24 04:30:32 PM PDT 24
Peak memory 199632 kb
Host smart-46f62404-9b08-4c44-af2c-3bbc4ba72526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769238476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3769238476
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.815646146
Short name T1086
Test name
Test status
Simulation time 65007877201 ps
CPU time 11.72 seconds
Started Jul 24 04:30:14 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 199940 kb
Host smart-3cba1fa9-cdc3-4d10-8dee-733532b202ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815646146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.815646146
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3593274701
Short name T693
Test name
Test status
Simulation time 34760779 ps
CPU time 0.53 seconds
Started Jul 24 04:26:49 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 194816 kb
Host smart-535c0c68-5a06-4935-9888-5c1d348d43c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593274701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3593274701
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2577802932
Short name T428
Test name
Test status
Simulation time 149807442720 ps
CPU time 53.79 seconds
Started Jul 24 04:26:42 PM PDT 24
Finished Jul 24 04:27:36 PM PDT 24
Peak memory 199936 kb
Host smart-d97e5a22-49bc-435b-a7f8-aa56df07b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577802932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2577802932
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2118643063
Short name T948
Test name
Test status
Simulation time 178090521082 ps
CPU time 141.84 seconds
Started Jul 24 04:26:52 PM PDT 24
Finished Jul 24 04:29:14 PM PDT 24
Peak memory 199924 kb
Host smart-fa0b5d74-5aa2-4022-80f8-f7c487d427d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118643063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2118643063
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4238703467
Short name T654
Test name
Test status
Simulation time 20737320275 ps
CPU time 27.09 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 199988 kb
Host smart-9f5be2e9-d54f-4cc1-a0fd-fc3005f291e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238703467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4238703467
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1137451127
Short name T994
Test name
Test status
Simulation time 30015257571 ps
CPU time 12.44 seconds
Started Jul 24 04:26:52 PM PDT 24
Finished Jul 24 04:27:04 PM PDT 24
Peak memory 198872 kb
Host smart-f69dd265-2788-4bd1-84c7-7e25945d685c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137451127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1137451127
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4030607305
Short name T917
Test name
Test status
Simulation time 115399867468 ps
CPU time 457.66 seconds
Started Jul 24 04:26:53 PM PDT 24
Finished Jul 24 04:34:31 PM PDT 24
Peak memory 199872 kb
Host smart-3840b3ce-a7a6-45d9-b6ce-f7b8f3be1c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030607305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4030607305
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3885743499
Short name T1093
Test name
Test status
Simulation time 1533795886 ps
CPU time 1.77 seconds
Started Jul 24 04:26:44 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 195484 kb
Host smart-d76a3c9d-8fd4-4d66-8daf-c3bae8dce28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885743499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3885743499
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.898941474
Short name T260
Test name
Test status
Simulation time 213220979984 ps
CPU time 45.69 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:27:32 PM PDT 24
Peak memory 200020 kb
Host smart-f1bb4609-9475-4802-97b8-524fc94cdf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898941474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.898941474
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2411241469
Short name T379
Test name
Test status
Simulation time 15546188639 ps
CPU time 821.16 seconds
Started Jul 24 04:26:50 PM PDT 24
Finished Jul 24 04:40:32 PM PDT 24
Peak memory 199940 kb
Host smart-cbe9c7a5-40be-4c65-a146-cca081eeed60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411241469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2411241469
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.586460301
Short name T762
Test name
Test status
Simulation time 3176679958 ps
CPU time 18.39 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:27:05 PM PDT 24
Peak memory 199152 kb
Host smart-87b489e6-4b94-4c86-9bd9-52cd17b107dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586460301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.586460301
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1171674565
Short name T494
Test name
Test status
Simulation time 35350980314 ps
CPU time 31.59 seconds
Started Jul 24 04:26:42 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 199880 kb
Host smart-821ba52c-a1ff-45e8-9fbf-7f79fcd12bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171674565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1171674565
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.643236746
Short name T1043
Test name
Test status
Simulation time 38464851522 ps
CPU time 3.77 seconds
Started Jul 24 04:26:43 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 196256 kb
Host smart-bc7140d3-1a3c-4151-b983-31af6e9fb1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643236746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.643236746
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4018352930
Short name T608
Test name
Test status
Simulation time 5643213089 ps
CPU time 5.97 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 199076 kb
Host smart-ba2f8539-52a0-4958-9df8-c7e0b1af2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018352930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4018352930
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1535014933
Short name T195
Test name
Test status
Simulation time 137727956825 ps
CPU time 132.92 seconds
Started Jul 24 04:26:51 PM PDT 24
Finished Jul 24 04:29:04 PM PDT 24
Peak memory 200040 kb
Host smart-e39ed31d-c3b6-4c72-b05d-a250334e2cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535014933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1535014933
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2993137842
Short name T587
Test name
Test status
Simulation time 1318288254 ps
CPU time 1.56 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:26:48 PM PDT 24
Peak memory 198672 kb
Host smart-bf2d31e4-f30c-4d3c-a531-9d1427cf244f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993137842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2993137842
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2686571191
Short name T367
Test name
Test status
Simulation time 60057618909 ps
CPU time 48 seconds
Started Jul 24 04:26:52 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 199952 kb
Host smart-829ccd2d-6864-4815-b727-5903ff583ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686571191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2686571191
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2128856303
Short name T740
Test name
Test status
Simulation time 82437371215 ps
CPU time 102.6 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:32:04 PM PDT 24
Peak memory 199972 kb
Host smart-411fdaeb-e4ed-4277-8cbd-4822fecf3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128856303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2128856303
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.399840207
Short name T1024
Test name
Test status
Simulation time 131997114921 ps
CPU time 112.05 seconds
Started Jul 24 04:30:20 PM PDT 24
Finished Jul 24 04:32:12 PM PDT 24
Peak memory 199896 kb
Host smart-446269c5-83a7-4ff2-b5ab-a5a630e633bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399840207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.399840207
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1573577797
Short name T581
Test name
Test status
Simulation time 29628235937 ps
CPU time 12.25 seconds
Started Jul 24 04:30:22 PM PDT 24
Finished Jul 24 04:30:34 PM PDT 24
Peak memory 199784 kb
Host smart-c75e362f-541f-426c-b3b8-44b888d86c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573577797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1573577797
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1732434762
Short name T1135
Test name
Test status
Simulation time 6917157524 ps
CPU time 14.86 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:30:37 PM PDT 24
Peak memory 199984 kb
Host smart-17404616-3a05-438d-9a9f-df201b25779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732434762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1732434762
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1557932980
Short name T669
Test name
Test status
Simulation time 22356818402 ps
CPU time 26.1 seconds
Started Jul 24 04:30:22 PM PDT 24
Finished Jul 24 04:30:48 PM PDT 24
Peak memory 200012 kb
Host smart-02b7475a-d09f-46eb-8411-e441ac1136c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557932980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1557932980
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.233803594
Short name T38
Test name
Test status
Simulation time 106719436801 ps
CPU time 91.3 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:31:52 PM PDT 24
Peak memory 199940 kb
Host smart-ce5149cd-077e-4e41-9411-1b385b72e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233803594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.233803594
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4038414012
Short name T952
Test name
Test status
Simulation time 24175093153 ps
CPU time 38.18 seconds
Started Jul 24 04:30:19 PM PDT 24
Finished Jul 24 04:30:57 PM PDT 24
Peak memory 199916 kb
Host smart-dc8e4bf4-6f96-4d91-bf20-2d907b56e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038414012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4038414012
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.844772895
Short name T119
Test name
Test status
Simulation time 37563829735 ps
CPU time 68.26 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:31:29 PM PDT 24
Peak memory 199932 kb
Host smart-543adf2f-6cd3-46cb-9d0a-bedd1acd9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844772895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.844772895
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2921956394
Short name T786
Test name
Test status
Simulation time 71464010590 ps
CPU time 107 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 199852 kb
Host smart-0d77cd3b-bfb3-414f-81e2-191b6a62a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921956394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2921956394
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2538549780
Short name T1000
Test name
Test status
Simulation time 21319059 ps
CPU time 0.58 seconds
Started Jul 24 04:26:59 PM PDT 24
Finished Jul 24 04:27:00 PM PDT 24
Peak memory 195384 kb
Host smart-cbfe449d-9c73-4be5-abbc-d7daf1e0ac82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538549780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2538549780
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.873502739
Short name T627
Test name
Test status
Simulation time 43144679974 ps
CPU time 12.84 seconds
Started Jul 24 04:26:50 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 199856 kb
Host smart-98dfc6d8-a25a-4c3b-86ea-6de9841a245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873502739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.873502739
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1003144108
Short name T166
Test name
Test status
Simulation time 26104552096 ps
CPU time 43.97 seconds
Started Jul 24 04:26:53 PM PDT 24
Finished Jul 24 04:27:37 PM PDT 24
Peak memory 200008 kb
Host smart-e30f2bf7-9f74-44be-90f5-42a330c8f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003144108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1003144108
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.176328961
Short name T862
Test name
Test status
Simulation time 163335877775 ps
CPU time 253.02 seconds
Started Jul 24 04:26:50 PM PDT 24
Finished Jul 24 04:31:03 PM PDT 24
Peak memory 200052 kb
Host smart-10a9940b-8131-4722-b5a0-332db3c9de5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176328961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.176328961
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3467073307
Short name T1050
Test name
Test status
Simulation time 120595588180 ps
CPU time 331.39 seconds
Started Jul 24 04:26:59 PM PDT 24
Finished Jul 24 04:32:30 PM PDT 24
Peak memory 199992 kb
Host smart-2ebb6157-3298-476a-ad28-04314b3c42b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467073307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3467073307
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3007173700
Short name T516
Test name
Test status
Simulation time 10238427213 ps
CPU time 7.55 seconds
Started Jul 24 04:26:55 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 199880 kb
Host smart-54fc6b7c-7ebf-4745-86c9-263b9310144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007173700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3007173700
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.280268306
Short name T304
Test name
Test status
Simulation time 275639006136 ps
CPU time 128.06 seconds
Started Jul 24 04:26:55 PM PDT 24
Finished Jul 24 04:29:03 PM PDT 24
Peak memory 199884 kb
Host smart-8f93fefd-c199-4ea5-b760-c07167193422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280268306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.280268306
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2394308877
Short name T517
Test name
Test status
Simulation time 20076672647 ps
CPU time 419.73 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:34:01 PM PDT 24
Peak memory 199868 kb
Host smart-804e7973-f9a0-4c09-9968-9424c913760b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394308877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2394308877
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.838128031
Short name T498
Test name
Test status
Simulation time 6210971947 ps
CPU time 25.99 seconds
Started Jul 24 04:26:53 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 199148 kb
Host smart-d662c586-df80-4068-bfad-f32b615c71df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838128031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.838128031
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1294945863
Short name T867
Test name
Test status
Simulation time 45898176275 ps
CPU time 19.4 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:21 PM PDT 24
Peak memory 195888 kb
Host smart-786ec187-b962-4782-82d4-48c802933872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294945863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1294945863
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.131843455
Short name T900
Test name
Test status
Simulation time 727475282 ps
CPU time 1.43 seconds
Started Jul 24 04:26:52 PM PDT 24
Finished Jul 24 04:26:54 PM PDT 24
Peak memory 200284 kb
Host smart-a43cb22b-bb5a-4cce-9182-29ecc1326e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131843455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.131843455
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2488583887
Short name T955
Test name
Test status
Simulation time 105000518333 ps
CPU time 1145.6 seconds
Started Jul 24 04:26:56 PM PDT 24
Finished Jul 24 04:46:02 PM PDT 24
Peak memory 224852 kb
Host smart-5a43607d-87ee-4d6a-bbaf-1284664e4bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488583887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2488583887
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2034880252
Short name T699
Test name
Test status
Simulation time 6728458498 ps
CPU time 16.48 seconds
Started Jul 24 04:26:57 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 199808 kb
Host smart-b5d8b9eb-cf8b-4e6e-8894-419c323dce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034880252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2034880252
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.840157464
Short name T416
Test name
Test status
Simulation time 66391198231 ps
CPU time 20.75 seconds
Started Jul 24 04:26:53 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 199200 kb
Host smart-dc1dfeab-e78e-4844-a1e9-8c4b53b3f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840157464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.840157464
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3796040871
Short name T989
Test name
Test status
Simulation time 73868881104 ps
CPU time 52.32 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:31:13 PM PDT 24
Peak memory 199896 kb
Host smart-305d08bf-7007-41b6-8574-4e30787bc07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796040871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3796040871
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3012303793
Short name T538
Test name
Test status
Simulation time 117869631256 ps
CPU time 184.87 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:33:26 PM PDT 24
Peak memory 199872 kb
Host smart-51ccc0cc-3562-4697-87aa-8b269484bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012303793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3012303793
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1856998350
Short name T906
Test name
Test status
Simulation time 11842199485 ps
CPU time 8.77 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:30:30 PM PDT 24
Peak memory 199732 kb
Host smart-faa51562-984c-4881-b26b-c4865cb36151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856998350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1856998350
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2310575133
Short name T1041
Test name
Test status
Simulation time 86980629251 ps
CPU time 30.14 seconds
Started Jul 24 04:30:20 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199912 kb
Host smart-17b7ade7-2884-4533-bc58-c2023959a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310575133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2310575133
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3840273795
Short name T868
Test name
Test status
Simulation time 97420307172 ps
CPU time 52.66 seconds
Started Jul 24 04:30:21 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 199964 kb
Host smart-2c0cdb59-02f6-419a-92fb-4fd02933d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840273795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3840273795
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1675042908
Short name T232
Test name
Test status
Simulation time 335482368181 ps
CPU time 69.31 seconds
Started Jul 24 04:30:20 PM PDT 24
Finished Jul 24 04:31:30 PM PDT 24
Peak memory 199932 kb
Host smart-c9a99fb3-5bcd-4174-a39f-5ba73b8aa0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675042908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1675042908
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1213033748
Short name T763
Test name
Test status
Simulation time 268329180427 ps
CPU time 57.23 seconds
Started Jul 24 04:30:26 PM PDT 24
Finished Jul 24 04:31:23 PM PDT 24
Peak memory 199884 kb
Host smart-4cbfb18f-ffac-4ebe-b9d2-bb28c3332e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213033748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1213033748
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2482454702
Short name T940
Test name
Test status
Simulation time 80612379918 ps
CPU time 65.24 seconds
Started Jul 24 04:30:28 PM PDT 24
Finished Jul 24 04:31:33 PM PDT 24
Peak memory 200044 kb
Host smart-91adf940-7bae-41c0-9c6f-271740f7d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482454702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2482454702
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.198515344
Short name T665
Test name
Test status
Simulation time 82371824 ps
CPU time 0.54 seconds
Started Jul 24 04:27:02 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 195292 kb
Host smart-6bc71c59-6987-45ab-bd0d-b4ac769601a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198515344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.198515344
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4030186153
Short name T1144
Test name
Test status
Simulation time 78071015487 ps
CPU time 53.98 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 199896 kb
Host smart-27f96575-9987-400d-b41d-8e67a97c9c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030186153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4030186153
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1263932809
Short name T1087
Test name
Test status
Simulation time 36399229710 ps
CPU time 15.95 seconds
Started Jul 24 04:27:06 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 199924 kb
Host smart-11363ad2-8d19-4a8d-a111-b80be3d91df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263932809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1263932809
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.60583404
Short name T1151
Test name
Test status
Simulation time 105116840587 ps
CPU time 39.61 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 199924 kb
Host smart-2374f15b-dd0f-465d-9a66-34bed29d03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60583404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.60583404
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1082167655
Short name T389
Test name
Test status
Simulation time 17329774392 ps
CPU time 29.54 seconds
Started Jul 24 04:27:03 PM PDT 24
Finished Jul 24 04:27:33 PM PDT 24
Peak memory 199828 kb
Host smart-4bba8ca7-b81b-46ce-b058-e2ed8d3086ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082167655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1082167655
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2558600703
Short name T629
Test name
Test status
Simulation time 63823815939 ps
CPU time 142.33 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:29:23 PM PDT 24
Peak memory 199996 kb
Host smart-91a8430e-9bb2-4503-aa2f-e47ff30e08bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558600703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2558600703
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4159727902
Short name T604
Test name
Test status
Simulation time 1992002151 ps
CPU time 1.63 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:03 PM PDT 24
Peak memory 197456 kb
Host smart-044f4dcc-f5c6-4e88-a03e-d3e286cf7117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159727902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4159727902
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2582200729
Short name T640
Test name
Test status
Simulation time 229023741656 ps
CPU time 24.88 seconds
Started Jul 24 04:27:03 PM PDT 24
Finished Jul 24 04:27:28 PM PDT 24
Peak memory 200588 kb
Host smart-cb514638-89a1-4061-a837-686fd02270d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582200729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2582200729
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2863054024
Short name T1079
Test name
Test status
Simulation time 21910560087 ps
CPU time 79.47 seconds
Started Jul 24 04:27:02 PM PDT 24
Finished Jul 24 04:28:21 PM PDT 24
Peak memory 200000 kb
Host smart-67641ebf-42d2-4c70-bc56-d6a519e564c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863054024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2863054024
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2927355833
Short name T558
Test name
Test status
Simulation time 5826742745 ps
CPU time 11.98 seconds
Started Jul 24 04:27:06 PM PDT 24
Finished Jul 24 04:27:18 PM PDT 24
Peak memory 198620 kb
Host smart-52f49b93-0170-46c0-9ec5-00338effa2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927355833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2927355833
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4106331180
Short name T332
Test name
Test status
Simulation time 164932533912 ps
CPU time 34.48 seconds
Started Jul 24 04:27:03 PM PDT 24
Finished Jul 24 04:27:38 PM PDT 24
Peak memory 199972 kb
Host smart-bd13a1e2-a41c-4e57-9925-252b124d540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106331180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4106331180
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.154380456
Short name T1011
Test name
Test status
Simulation time 2713074924 ps
CPU time 4.24 seconds
Started Jul 24 04:27:06 PM PDT 24
Finished Jul 24 04:27:10 PM PDT 24
Peak memory 195764 kb
Host smart-37844d59-c8a7-429d-b986-33fcd1fd228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154380456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.154380456
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.363998678
Short name T735
Test name
Test status
Simulation time 5441414454 ps
CPU time 11.46 seconds
Started Jul 24 04:26:59 PM PDT 24
Finished Jul 24 04:27:11 PM PDT 24
Peak memory 199972 kb
Host smart-c34bf703-20d8-40b2-971c-855fca187842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363998678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.363998678
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2772250375
Short name T267
Test name
Test status
Simulation time 68954598882 ps
CPU time 23.83 seconds
Started Jul 24 04:27:03 PM PDT 24
Finished Jul 24 04:27:27 PM PDT 24
Peak memory 199824 kb
Host smart-e96e5674-c48f-4498-9f88-5ecb57bf8a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772250375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2772250375
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2815271333
Short name T773
Test name
Test status
Simulation time 61621266025 ps
CPU time 1001.22 seconds
Started Jul 24 04:27:03 PM PDT 24
Finished Jul 24 04:43:45 PM PDT 24
Peak memory 224932 kb
Host smart-8402f8bd-c113-42c7-bbac-049b715d0229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815271333 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2815271333
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3055015785
Short name T385
Test name
Test status
Simulation time 835491388 ps
CPU time 2.92 seconds
Started Jul 24 04:27:04 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 198792 kb
Host smart-90d212e5-1d00-4b46-8ef0-86d5b2026866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055015785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3055015785
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.157875321
Short name T611
Test name
Test status
Simulation time 35849694000 ps
CPU time 29.71 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:31 PM PDT 24
Peak memory 199888 kb
Host smart-29ded21c-f512-4fa5-bac3-f41172c40c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157875321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.157875321
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.706235892
Short name T236
Test name
Test status
Simulation time 29057744406 ps
CPU time 44.2 seconds
Started Jul 24 04:30:27 PM PDT 24
Finished Jul 24 04:31:11 PM PDT 24
Peak memory 199952 kb
Host smart-807c660b-4b27-4d84-b883-665fd24601e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706235892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.706235892
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3451393523
Short name T1124
Test name
Test status
Simulation time 29422272171 ps
CPU time 13.53 seconds
Started Jul 24 04:30:27 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 199872 kb
Host smart-8b3b077e-fb6d-444a-aefd-4b3c1a6efc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451393523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3451393523
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.427837334
Short name T1148
Test name
Test status
Simulation time 45949271141 ps
CPU time 23.63 seconds
Started Jul 24 04:30:26 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199888 kb
Host smart-59d76da8-2492-4276-b09e-2f55d55fda47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427837334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.427837334
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2741435814
Short name T1042
Test name
Test status
Simulation time 71066917352 ps
CPU time 21.48 seconds
Started Jul 24 04:30:29 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199980 kb
Host smart-62e09a87-d4bf-40dc-ab24-56c283a00a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741435814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2741435814
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3265351057
Short name T1173
Test name
Test status
Simulation time 103204175870 ps
CPU time 50.42 seconds
Started Jul 24 04:30:26 PM PDT 24
Finished Jul 24 04:31:17 PM PDT 24
Peak memory 199952 kb
Host smart-a932fd50-cb71-415b-8283-3c51c480775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265351057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3265351057
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4014955622
Short name T826
Test name
Test status
Simulation time 16093634878 ps
CPU time 15.57 seconds
Started Jul 24 04:30:26 PM PDT 24
Finished Jul 24 04:30:42 PM PDT 24
Peak memory 199952 kb
Host smart-a89a43cd-69f4-4e2a-b190-76cdc810c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014955622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4014955622
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4130916133
Short name T1031
Test name
Test status
Simulation time 19137297765 ps
CPU time 18.59 seconds
Started Jul 24 04:30:26 PM PDT 24
Finished Jul 24 04:30:44 PM PDT 24
Peak memory 199936 kb
Host smart-28e16e45-a554-4e12-85a5-25a1808b2c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130916133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4130916133
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3499844486
Short name T42
Test name
Test status
Simulation time 41930579981 ps
CPU time 54.01 seconds
Started Jul 24 04:30:28 PM PDT 24
Finished Jul 24 04:31:22 PM PDT 24
Peak memory 199996 kb
Host smart-0c6b9eba-4a36-4fad-b9ed-c107b847b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499844486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3499844486
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.398243270
Short name T490
Test name
Test status
Simulation time 102968450334 ps
CPU time 11.84 seconds
Started Jul 24 04:30:25 PM PDT 24
Finished Jul 24 04:30:37 PM PDT 24
Peak memory 200012 kb
Host smart-18317bc6-8833-479d-bb65-8a5518b36a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398243270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.398243270
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3941741732
Short name T182
Test name
Test status
Simulation time 71468066738 ps
CPU time 61.29 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:31:40 PM PDT 24
Peak memory 199884 kb
Host smart-8b678a23-0ee6-4922-9db9-6ec829ceb78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941741732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3941741732
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3050683727
Short name T810
Test name
Test status
Simulation time 33990660 ps
CPU time 0.55 seconds
Started Jul 24 04:27:08 PM PDT 24
Finished Jul 24 04:27:08 PM PDT 24
Peak memory 194700 kb
Host smart-33898597-4dd7-4225-acd0-ce241e8755f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050683727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3050683727
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4283728706
Short name T683
Test name
Test status
Simulation time 74669268782 ps
CPU time 29.76 seconds
Started Jul 24 04:27:05 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 199872 kb
Host smart-81e8fdf3-9ecf-4bfa-9a86-386eb14217a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283728706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4283728706
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2437638876
Short name T273
Test name
Test status
Simulation time 40233206295 ps
CPU time 77.72 seconds
Started Jul 24 04:27:08 PM PDT 24
Finished Jul 24 04:28:26 PM PDT 24
Peak memory 199988 kb
Host smart-e494a992-4a2c-4a23-95f2-6fa3463c80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437638876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2437638876
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2313624332
Short name T569
Test name
Test status
Simulation time 50418955115 ps
CPU time 28.79 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 199868 kb
Host smart-a8a18561-9090-4e0e-92c8-dac219c2b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313624332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2313624332
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2184008271
Short name T27
Test name
Test status
Simulation time 2091550976 ps
CPU time 3.29 seconds
Started Jul 24 04:27:10 PM PDT 24
Finished Jul 24 04:27:13 PM PDT 24
Peak memory 195672 kb
Host smart-3ea68c24-4c9d-4845-8909-06b2d10a51a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184008271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2184008271
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2900998646
Short name T349
Test name
Test status
Simulation time 159419518880 ps
CPU time 209.85 seconds
Started Jul 24 04:27:12 PM PDT 24
Finished Jul 24 04:30:42 PM PDT 24
Peak memory 199888 kb
Host smart-905a2770-0948-4126-884b-c494ddb98df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900998646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2900998646
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.4085992727
Short name T394
Test name
Test status
Simulation time 7022772410 ps
CPU time 12.25 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:23 PM PDT 24
Peak memory 199772 kb
Host smart-96e59ba5-78be-4476-8717-9a8c4f988326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085992727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4085992727
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1869521893
Short name T903
Test name
Test status
Simulation time 17148834039 ps
CPU time 7.6 seconds
Started Jul 24 04:27:09 PM PDT 24
Finished Jul 24 04:27:17 PM PDT 24
Peak memory 195748 kb
Host smart-9cd3c85a-a2a4-4f32-ba2b-552702c7ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869521893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1869521893
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2812050217
Short name T1130
Test name
Test status
Simulation time 7055643184 ps
CPU time 347.37 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:32:59 PM PDT 24
Peak memory 199924 kb
Host smart-bb7eeebb-d8c6-4e45-b364-8f9514326158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812050217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2812050217
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.940716729
Short name T682
Test name
Test status
Simulation time 4321714737 ps
CPU time 8.74 seconds
Started Jul 24 04:27:09 PM PDT 24
Finished Jul 24 04:27:17 PM PDT 24
Peak memory 198872 kb
Host smart-c9668d65-0e7b-4f8b-a798-b53da6faddee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940716729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.940716729
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4290217547
Short name T291
Test name
Test status
Simulation time 131491014521 ps
CPU time 35.34 seconds
Started Jul 24 04:27:07 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 199668 kb
Host smart-449e9f12-0998-486a-b2c9-e64699b4caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290217547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4290217547
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1190162154
Short name T921
Test name
Test status
Simulation time 2743524347 ps
CPU time 2.75 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 196436 kb
Host smart-93cc6a27-c13a-4d86-bc36-7ad4637bed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190162154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1190162154
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.216761588
Short name T572
Test name
Test status
Simulation time 6063423076 ps
CPU time 10.4 seconds
Started Jul 24 04:27:01 PM PDT 24
Finished Jul 24 04:27:12 PM PDT 24
Peak memory 199820 kb
Host smart-4c5a6e7f-80e8-4b4e-bf4b-2840631d96d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216761588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.216761588
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.167958891
Short name T1048
Test name
Test status
Simulation time 45389523203 ps
CPU time 423.09 seconds
Started Jul 24 04:27:16 PM PDT 24
Finished Jul 24 04:34:20 PM PDT 24
Peak memory 208304 kb
Host smart-3090f66d-03ed-4cfc-b3b1-04ed1398fd38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167958891 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.167958891
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3104860026
Short name T499
Test name
Test status
Simulation time 7439774458 ps
CPU time 13.65 seconds
Started Jul 24 04:27:12 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 199808 kb
Host smart-0d9b6b73-ec60-4166-a85b-5a2f0269aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104860026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3104860026
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1665364525
Short name T41
Test name
Test status
Simulation time 84351568432 ps
CPU time 32.5 seconds
Started Jul 24 04:27:02 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 199948 kb
Host smart-cdc86678-90c8-4bed-ba8e-b46ce1532be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665364525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1665364525
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2913509132
Short name T253
Test name
Test status
Simulation time 9041589820 ps
CPU time 17.94 seconds
Started Jul 24 04:30:32 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199988 kb
Host smart-35224dc4-0cd9-4ccc-a29d-c9027d4abb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913509132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2913509132
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1698390617
Short name T1109
Test name
Test status
Simulation time 192085320041 ps
CPU time 73.51 seconds
Started Jul 24 04:30:33 PM PDT 24
Finished Jul 24 04:31:47 PM PDT 24
Peak memory 199992 kb
Host smart-a3916c2b-56a4-429c-8499-73a05f9b816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698390617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1698390617
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2622626676
Short name T832
Test name
Test status
Simulation time 110365593070 ps
CPU time 169.88 seconds
Started Jul 24 04:30:32 PM PDT 24
Finished Jul 24 04:33:22 PM PDT 24
Peak memory 199924 kb
Host smart-84f1c083-7c9c-4a23-99e0-2fa8d22e7639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622626676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2622626676
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2940900800
Short name T823
Test name
Test status
Simulation time 53908696768 ps
CPU time 24.54 seconds
Started Jul 24 04:30:33 PM PDT 24
Finished Jul 24 04:30:58 PM PDT 24
Peak memory 199980 kb
Host smart-52d2d678-59a4-4a83-9a0d-0653a93f1a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940900800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2940900800
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.477456446
Short name T123
Test name
Test status
Simulation time 194699290487 ps
CPU time 198.5 seconds
Started Jul 24 04:30:36 PM PDT 24
Finished Jul 24 04:33:55 PM PDT 24
Peak memory 199996 kb
Host smart-c0f92597-4bbb-4424-b0af-aea71597c33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477456446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.477456446
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.134387800
Short name T328
Test name
Test status
Simulation time 31522936549 ps
CPU time 45.75 seconds
Started Jul 24 04:30:32 PM PDT 24
Finished Jul 24 04:31:17 PM PDT 24
Peak memory 200076 kb
Host smart-0d5c317c-cfc2-4a29-83c5-26f93c4d0355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134387800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.134387800
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4226504686
Short name T618
Test name
Test status
Simulation time 112041584101 ps
CPU time 144.6 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:32:58 PM PDT 24
Peak memory 200012 kb
Host smart-433c550b-3020-4439-a58a-70c965287ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226504686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4226504686
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1794923790
Short name T787
Test name
Test status
Simulation time 146642137348 ps
CPU time 200.99 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:33:55 PM PDT 24
Peak memory 199924 kb
Host smart-aec7a0e9-8e86-4b84-825c-115937a98d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794923790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1794923790
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2587833151
Short name T899
Test name
Test status
Simulation time 74786955520 ps
CPU time 112.39 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:32:27 PM PDT 24
Peak memory 200016 kb
Host smart-b684ad4d-9e6c-432b-8fc5-50dd8f0840f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587833151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2587833151
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.204510375
Short name T1060
Test name
Test status
Simulation time 40934851 ps
CPU time 0.55 seconds
Started Jul 24 04:27:15 PM PDT 24
Finished Jul 24 04:27:16 PM PDT 24
Peak memory 195456 kb
Host smart-bd6d2fd7-3c50-4277-96a1-576108c4fab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204510375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.204510375
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3058440217
Short name T603
Test name
Test status
Simulation time 32329448630 ps
CPU time 50.66 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:28:02 PM PDT 24
Peak memory 199852 kb
Host smart-14447516-af79-4554-ac18-50b8173109ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058440217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3058440217
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.969652998
Short name T1061
Test name
Test status
Simulation time 49416209744 ps
CPU time 21.12 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:32 PM PDT 24
Peak memory 199936 kb
Host smart-16125b61-f5c1-4c0d-9b79-c5b11a0f1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969652998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.969652998
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3861732172
Short name T761
Test name
Test status
Simulation time 186466800537 ps
CPU time 248.04 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:31:27 PM PDT 24
Peak memory 199880 kb
Host smart-d753689e-2996-493d-b7e4-256b7d087650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861732172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3861732172
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2047406775
Short name T980
Test name
Test status
Simulation time 52439900964 ps
CPU time 10 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 199024 kb
Host smart-4f0ffbaa-7b28-46ca-b594-c45d173adfa6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047406775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2047406775
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2989198260
Short name T272
Test name
Test status
Simulation time 110850791789 ps
CPU time 880.59 seconds
Started Jul 24 04:27:12 PM PDT 24
Finished Jul 24 04:41:53 PM PDT 24
Peak memory 199992 kb
Host smart-402c3d53-c30c-48ff-991d-c743b5b592af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989198260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2989198260
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2407746796
Short name T619
Test name
Test status
Simulation time 5122661882 ps
CPU time 4.12 seconds
Started Jul 24 04:27:14 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 199820 kb
Host smart-5a87a925-cc8c-4424-b69b-3f0aa46601bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407746796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2407746796
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3290851305
Short name T276
Test name
Test status
Simulation time 95073274798 ps
CPU time 37.32 seconds
Started Jul 24 04:27:10 PM PDT 24
Finished Jul 24 04:27:47 PM PDT 24
Peak memory 200040 kb
Host smart-d91aee69-d50a-4e31-bf2e-40f7e526b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290851305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3290851305
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4234495891
Short name T835
Test name
Test status
Simulation time 14404870109 ps
CPU time 723.16 seconds
Started Jul 24 04:27:18 PM PDT 24
Finished Jul 24 04:39:22 PM PDT 24
Peak memory 199908 kb
Host smart-4c65c51b-c54a-4686-b0b8-0bfbe2f3c467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234495891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4234495891
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1159799871
Short name T600
Test name
Test status
Simulation time 3258069515 ps
CPU time 10.89 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 198036 kb
Host smart-79af06fb-cd13-43e4-824b-e5123252a97c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159799871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1159799871
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1503828175
Short name T313
Test name
Test status
Simulation time 266885926909 ps
CPU time 521.72 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:35:53 PM PDT 24
Peak memory 199932 kb
Host smart-1fd78d5e-7359-456b-93aa-23aa498e50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503828175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1503828175
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3297108617
Short name T933
Test name
Test status
Simulation time 3724752365 ps
CPU time 6.63 seconds
Started Jul 24 04:27:10 PM PDT 24
Finished Jul 24 04:27:17 PM PDT 24
Peak memory 196168 kb
Host smart-2dd56df9-3dd6-44cd-908b-831bb6c286d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297108617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3297108617
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2996156395
Short name T417
Test name
Test status
Simulation time 5787332657 ps
CPU time 9.64 seconds
Started Jul 24 04:27:09 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 199536 kb
Host smart-5866700e-50f8-4cb4-b394-35dc61163503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996156395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2996156395
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1508821731
Short name T1019
Test name
Test status
Simulation time 188232723644 ps
CPU time 361.75 seconds
Started Jul 24 04:27:14 PM PDT 24
Finished Jul 24 04:33:16 PM PDT 24
Peak memory 208380 kb
Host smart-21ff77bf-e2c1-4943-ad55-7ac1e147732d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508821731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1508821731
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3335866720
Short name T321
Test name
Test status
Simulation time 13128787251 ps
CPU time 86.14 seconds
Started Jul 24 04:27:13 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 216444 kb
Host smart-61444102-e122-4975-900a-c2c6c3d09e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335866720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3335866720
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3440539624
Short name T970
Test name
Test status
Simulation time 7052851923 ps
CPU time 13.27 seconds
Started Jul 24 04:27:16 PM PDT 24
Finished Jul 24 04:27:29 PM PDT 24
Peak memory 199996 kb
Host smart-f827013a-4717-4e03-82d4-f6b80a8b424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440539624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3440539624
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2386535448
Short name T701
Test name
Test status
Simulation time 64531447111 ps
CPU time 105.7 seconds
Started Jul 24 04:27:06 PM PDT 24
Finished Jul 24 04:28:52 PM PDT 24
Peak memory 199948 kb
Host smart-aefa49f4-16f8-4928-a738-fa561d6ae02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386535448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2386535448
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3081843088
Short name T153
Test name
Test status
Simulation time 176821434947 ps
CPU time 259.13 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:34:54 PM PDT 24
Peak memory 199984 kb
Host smart-666a2b66-941a-4989-a7b4-228fce74756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081843088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3081843088
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3549134169
Short name T661
Test name
Test status
Simulation time 13649698867 ps
CPU time 27.41 seconds
Started Jul 24 04:30:35 PM PDT 24
Finished Jul 24 04:31:03 PM PDT 24
Peak memory 199996 kb
Host smart-e103138e-2c3e-423f-8ee2-09e6b32286c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549134169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3549134169
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1918072249
Short name T288
Test name
Test status
Simulation time 21745505811 ps
CPU time 30.73 seconds
Started Jul 24 04:30:33 PM PDT 24
Finished Jul 24 04:31:04 PM PDT 24
Peak memory 199896 kb
Host smart-dd8763ff-67d7-4d4a-9ddc-5fe6a1cee7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918072249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1918072249
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3102567160
Short name T885
Test name
Test status
Simulation time 23588232486 ps
CPU time 24.03 seconds
Started Jul 24 04:30:35 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 200008 kb
Host smart-37e70855-04b2-44fc-93c7-fba938a33717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102567160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3102567160
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2256378168
Short name T319
Test name
Test status
Simulation time 59471817060 ps
CPU time 46.99 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:31:21 PM PDT 24
Peak memory 199908 kb
Host smart-30f75325-5bc4-4744-80fa-43b508da53cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256378168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2256378168
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1728476840
Short name T1027
Test name
Test status
Simulation time 106831179851 ps
CPU time 196.54 seconds
Started Jul 24 04:30:35 PM PDT 24
Finished Jul 24 04:33:52 PM PDT 24
Peak memory 199996 kb
Host smart-7ddff1f4-9a5d-4bcd-b928-540b81a5ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728476840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1728476840
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.655148228
Short name T190
Test name
Test status
Simulation time 28769917020 ps
CPU time 40.3 seconds
Started Jul 24 04:30:34 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 199928 kb
Host smart-831f7c12-a22c-4e97-a25a-85995a842f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655148228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.655148228
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.321848724
Short name T934
Test name
Test status
Simulation time 21062299254 ps
CPU time 8.5 seconds
Started Jul 24 04:30:37 PM PDT 24
Finished Jul 24 04:30:46 PM PDT 24
Peak memory 199600 kb
Host smart-cdd70cf8-9a2a-4657-88d8-6c1bc8c256c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321848724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.321848724
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3419956713
Short name T396
Test name
Test status
Simulation time 113708039 ps
CPU time 0.56 seconds
Started Jul 24 04:27:25 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 195360 kb
Host smart-960f0ed2-7f82-4be0-bb90-9951b5a8a180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419956713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3419956713
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1716112470
Short name T960
Test name
Test status
Simulation time 298671024708 ps
CPU time 375.49 seconds
Started Jul 24 04:27:22 PM PDT 24
Finished Jul 24 04:33:37 PM PDT 24
Peak memory 199936 kb
Host smart-3aa68870-e89e-4919-b737-2c69a5a87a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716112470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1716112470
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3370961372
Short name T937
Test name
Test status
Simulation time 119599849798 ps
CPU time 39.24 seconds
Started Jul 24 04:27:14 PM PDT 24
Finished Jul 24 04:27:53 PM PDT 24
Peak memory 199924 kb
Host smart-e92829b3-32c9-441e-beef-99273400a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370961372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3370961372
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3520012967
Short name T598
Test name
Test status
Simulation time 16948739627 ps
CPU time 26.4 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 199916 kb
Host smart-72b96f30-a902-4b34-8410-a05391e9271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520012967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3520012967
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.8307801
Short name T17
Test name
Test status
Simulation time 12436715098 ps
CPU time 6.7 seconds
Started Jul 24 04:27:12 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 199508 kb
Host smart-ba6a9c61-c710-4de0-84d3-d82434d61675
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8307801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.8307801
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.429047570
Short name T9
Test name
Test status
Simulation time 94253247743 ps
CPU time 162.64 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:30:02 PM PDT 24
Peak memory 199912 kb
Host smart-37ae2726-1a1f-49d5-8082-11ebb956377f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429047570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.429047570
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3639370287
Short name T452
Test name
Test status
Simulation time 4110293758 ps
CPU time 10.41 seconds
Started Jul 24 04:27:15 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 199692 kb
Host smart-4c06d1aa-0e80-4223-be79-175a5250c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639370287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3639370287
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.981921097
Short name T302
Test name
Test status
Simulation time 63988148017 ps
CPU time 111.11 seconds
Started Jul 24 04:27:11 PM PDT 24
Finished Jul 24 04:29:02 PM PDT 24
Peak memory 208360 kb
Host smart-61a4dc3e-a15a-4ad1-bddd-194ef399810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981921097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.981921097
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.652087534
Short name T298
Test name
Test status
Simulation time 21423561739 ps
CPU time 497.72 seconds
Started Jul 24 04:27:16 PM PDT 24
Finished Jul 24 04:35:34 PM PDT 24
Peak memory 199960 kb
Host smart-b7ec5558-bbd0-4d0b-a583-75d7a545919b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652087534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.652087534
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4023650945
Short name T907
Test name
Test status
Simulation time 7018742256 ps
CPU time 16.62 seconds
Started Jul 24 04:27:15 PM PDT 24
Finished Jul 24 04:27:32 PM PDT 24
Peak memory 199228 kb
Host smart-542e2347-314f-43fc-8ccd-85ccf4fe78a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023650945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4023650945
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3277500812
Short name T781
Test name
Test status
Simulation time 62354874230 ps
CPU time 28.25 seconds
Started Jul 24 04:27:12 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 199944 kb
Host smart-91b6ae74-8d6c-4d0e-adc2-38deae295c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277500812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3277500812
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4061394566
Short name T635
Test name
Test status
Simulation time 1868304515 ps
CPU time 2.67 seconds
Started Jul 24 04:27:15 PM PDT 24
Finished Jul 24 04:27:18 PM PDT 24
Peak memory 195392 kb
Host smart-3fb3ce9a-848a-4440-9996-18d276b3c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061394566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4061394566
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3234750539
Short name T779
Test name
Test status
Simulation time 465324558 ps
CPU time 1.23 seconds
Started Jul 24 04:27:17 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 198888 kb
Host smart-9967aa36-90cc-49f0-8ca3-d041751e9488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234750539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3234750539
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2949321122
Short name T525
Test name
Test status
Simulation time 214436083648 ps
CPU time 132.69 seconds
Started Jul 24 04:27:28 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 216304 kb
Host smart-c1c8c862-ea0a-4b68-b880-b5de4c2ac9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949321122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2949321122
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2725594648
Short name T843
Test name
Test status
Simulation time 97916525196 ps
CPU time 459.74 seconds
Started Jul 24 04:27:22 PM PDT 24
Finished Jul 24 04:35:02 PM PDT 24
Peak memory 216604 kb
Host smart-1754c078-cbd5-424d-9199-d5bb68d56286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725594648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2725594648
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1868955963
Short name T423
Test name
Test status
Simulation time 1263796993 ps
CPU time 1.81 seconds
Started Jul 24 04:27:13 PM PDT 24
Finished Jul 24 04:27:15 PM PDT 24
Peak memory 198728 kb
Host smart-e4c21d65-a755-4b90-a76f-79e2a7b5655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868955963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1868955963
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1646718881
Short name T712
Test name
Test status
Simulation time 154493714947 ps
CPU time 72.17 seconds
Started Jul 24 04:27:13 PM PDT 24
Finished Jul 24 04:28:25 PM PDT 24
Peak memory 200076 kb
Host smart-354d2cdc-6234-4f8e-9d2e-89b93a1b4e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646718881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1646718881
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2994617879
Short name T1009
Test name
Test status
Simulation time 34481025766 ps
CPU time 13.11 seconds
Started Jul 24 04:30:38 PM PDT 24
Finished Jul 24 04:30:52 PM PDT 24
Peak memory 199988 kb
Host smart-dd3cb81d-0343-4dc8-ac56-9b4bd5b77c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994617879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2994617879
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2110187418
Short name T296
Test name
Test status
Simulation time 152625860920 ps
CPU time 41.05 seconds
Started Jul 24 04:31:31 PM PDT 24
Finished Jul 24 04:32:12 PM PDT 24
Peak memory 200008 kb
Host smart-c125c158-4438-47a5-87f0-ec0ccefc40ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110187418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2110187418
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2710910032
Short name T141
Test name
Test status
Simulation time 39674804254 ps
CPU time 50.31 seconds
Started Jul 24 04:30:37 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 199912 kb
Host smart-c6f25869-ce0e-400a-91e3-b31b2e0a95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710910032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2710910032
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.471260474
Short name T990
Test name
Test status
Simulation time 26679319077 ps
CPU time 17.38 seconds
Started Jul 24 04:30:42 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 199848 kb
Host smart-2da164a6-c293-41a8-b221-db3db02a0a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471260474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.471260474
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1493244473
Short name T999
Test name
Test status
Simulation time 39280042089 ps
CPU time 63.47 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:31:43 PM PDT 24
Peak memory 200040 kb
Host smart-b575e6b1-a1ec-49f2-b28f-9612510939b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493244473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1493244473
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1260625187
Short name T1077
Test name
Test status
Simulation time 12379979703 ps
CPU time 22.45 seconds
Started Jul 24 04:30:38 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 199920 kb
Host smart-1e27108c-c64e-455e-9e83-1dbdd38d683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260625187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1260625187
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4039460558
Short name T592
Test name
Test status
Simulation time 19452339631 ps
CPU time 37.86 seconds
Started Jul 24 04:30:38 PM PDT 24
Finished Jul 24 04:31:16 PM PDT 24
Peak memory 199960 kb
Host smart-ffa6d5d5-48ae-4157-8274-faf0d431ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039460558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4039460558
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1629130911
Short name T956
Test name
Test status
Simulation time 62607551525 ps
CPU time 44.46 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:31:24 PM PDT 24
Peak memory 199844 kb
Host smart-e79ad199-a09f-4ac1-a9ea-826ae7890505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629130911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1629130911
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2025245467
Short name T221
Test name
Test status
Simulation time 35583655215 ps
CPU time 19.65 seconds
Started Jul 24 04:30:41 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 200016 kb
Host smart-9db33971-c798-40ec-be31-9c493b412678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025245467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2025245467
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3482153192
Short name T880
Test name
Test status
Simulation time 18375097 ps
CPU time 0.55 seconds
Started Jul 24 04:27:18 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 195708 kb
Host smart-ba8e5819-441c-4bef-8bcb-157cac65c24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482153192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3482153192
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.620118880
Short name T677
Test name
Test status
Simulation time 145904354484 ps
CPU time 92.42 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 200096 kb
Host smart-68935ca0-73b3-4add-b3b1-b0616fa49fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620118880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.620118880
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2248890301
Short name T368
Test name
Test status
Simulation time 35318894555 ps
CPU time 15.22 seconds
Started Jul 24 04:27:20 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 199708 kb
Host smart-ef33af08-0c09-4740-a3d4-8094de625a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248890301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2248890301
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.483561706
Short name T758
Test name
Test status
Simulation time 17360346062 ps
CPU time 14.27 seconds
Started Jul 24 04:27:18 PM PDT 24
Finished Jul 24 04:27:33 PM PDT 24
Peak memory 199968 kb
Host smart-db76baac-19c0-4081-9fd2-9820e9df27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483561706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.483561706
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2294109329
Short name T534
Test name
Test status
Simulation time 65205112182 ps
CPU time 25.13 seconds
Started Jul 24 04:27:23 PM PDT 24
Finished Jul 24 04:27:49 PM PDT 24
Peak memory 199920 kb
Host smart-ec178537-8b71-4b27-907a-7840ebc6a51a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294109329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2294109329
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2932124041
Short name T1146
Test name
Test status
Simulation time 144961092708 ps
CPU time 180.3 seconds
Started Jul 24 04:27:20 PM PDT 24
Finished Jul 24 04:30:20 PM PDT 24
Peak memory 199968 kb
Host smart-bafeda5d-c942-4fea-aa60-027fbf9ffd5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932124041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2932124041
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3449227836
Short name T485
Test name
Test status
Simulation time 1100187804 ps
CPU time 1.79 seconds
Started Jul 24 04:27:20 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 195676 kb
Host smart-e995ef46-f50a-4eb0-8e3a-39a4952b6284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449227836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3449227836
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.4200059478
Short name T279
Test name
Test status
Simulation time 34508479003 ps
CPU time 167.42 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:30:06 PM PDT 24
Peak memory 200120 kb
Host smart-8e28e449-842f-4ead-bb07-4dc48749f6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200059478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4200059478
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2018919316
Short name T488
Test name
Test status
Simulation time 4232170374 ps
CPU time 209.4 seconds
Started Jul 24 04:27:26 PM PDT 24
Finished Jul 24 04:30:56 PM PDT 24
Peak memory 199852 kb
Host smart-338cde0f-d9f4-40a3-a605-df57350c8336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018919316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2018919316
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4190950866
Short name T913
Test name
Test status
Simulation time 5331114973 ps
CPU time 9.7 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:27:29 PM PDT 24
Peak memory 198652 kb
Host smart-98e3cef1-79ca-4254-aca0-29eb37db4004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190950866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4190950866
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3548348412
Short name T370
Test name
Test status
Simulation time 93141324750 ps
CPU time 43.9 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:28:03 PM PDT 24
Peak memory 199896 kb
Host smart-117d5c6b-2e4e-4d6b-ab3b-e3a554dd3935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548348412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3548348412
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3683815460
Short name T1115
Test name
Test status
Simulation time 34518513818 ps
CPU time 35.61 seconds
Started Jul 24 04:27:22 PM PDT 24
Finished Jul 24 04:27:57 PM PDT 24
Peak memory 196304 kb
Host smart-0f0930f4-53ab-47ce-92af-59f0bde74c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683815460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3683815460
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1511304313
Short name T522
Test name
Test status
Simulation time 509561383 ps
CPU time 1.26 seconds
Started Jul 24 04:27:21 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 198208 kb
Host smart-74aa1e67-55c6-4c34-b367-2ebfe3acdc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511304313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1511304313
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2165778037
Short name T1003
Test name
Test status
Simulation time 509220147637 ps
CPU time 529.33 seconds
Started Jul 24 04:27:19 PM PDT 24
Finished Jul 24 04:36:09 PM PDT 24
Peak memory 208688 kb
Host smart-1555371d-ec31-42c3-82ea-41abf4da1e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165778037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2165778037
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3277498797
Short name T695
Test name
Test status
Simulation time 1102024638 ps
CPU time 2.19 seconds
Started Jul 24 04:27:18 PM PDT 24
Finished Jul 24 04:27:21 PM PDT 24
Peak memory 198792 kb
Host smart-7be4042e-493e-4eb3-8504-2d8fd2f7cb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277498797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3277498797
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1850212128
Short name T923
Test name
Test status
Simulation time 65375706618 ps
CPU time 127.13 seconds
Started Jul 24 04:27:25 PM PDT 24
Finished Jul 24 04:29:33 PM PDT 24
Peak memory 199908 kb
Host smart-e7504100-9eeb-4358-b022-785cebed09a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850212128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1850212128
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3092920023
Short name T1149
Test name
Test status
Simulation time 30751452557 ps
CPU time 44.06 seconds
Started Jul 24 04:30:37 PM PDT 24
Finished Jul 24 04:31:21 PM PDT 24
Peak memory 199916 kb
Host smart-e0da0434-b302-4276-9d60-c4d695206fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092920023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3092920023
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4263638714
Short name T235
Test name
Test status
Simulation time 17465402856 ps
CPU time 21.07 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 199928 kb
Host smart-13ef316a-ab2e-438a-96b3-1e41fa8cc8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263638714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4263638714
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4056582699
Short name T126
Test name
Test status
Simulation time 74580947894 ps
CPU time 137.72 seconds
Started Jul 24 04:30:44 PM PDT 24
Finished Jul 24 04:33:01 PM PDT 24
Peak memory 199976 kb
Host smart-06039201-3e5e-4a27-8299-316e09658ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056582699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4056582699
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3035294600
Short name T331
Test name
Test status
Simulation time 29365784693 ps
CPU time 20.1 seconds
Started Jul 24 04:30:37 PM PDT 24
Finished Jul 24 04:30:58 PM PDT 24
Peak memory 199968 kb
Host smart-77cd3c20-2f6e-4b68-90d6-3d550192f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035294600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3035294600
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3826505044
Short name T35
Test name
Test status
Simulation time 70811537813 ps
CPU time 122.61 seconds
Started Jul 24 04:30:38 PM PDT 24
Finished Jul 24 04:32:41 PM PDT 24
Peak memory 200016 kb
Host smart-58699b66-2635-4e11-9402-57658f88da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826505044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3826505044
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.355450920
Short name T167
Test name
Test status
Simulation time 38456360342 ps
CPU time 14.7 seconds
Started Jul 24 04:30:38 PM PDT 24
Finished Jul 24 04:30:53 PM PDT 24
Peak memory 199996 kb
Host smart-e9209ef6-bb6d-4547-b451-b0325ef8e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355450920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.355450920
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2186628270
Short name T967
Test name
Test status
Simulation time 12497703942 ps
CPU time 18.84 seconds
Started Jul 24 04:30:43 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 199976 kb
Host smart-c5866cb0-3382-428f-926d-0897a55f2c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186628270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2186628270
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3124158444
Short name T770
Test name
Test status
Simulation time 10231560 ps
CPU time 0.55 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:12 PM PDT 24
Peak memory 194344 kb
Host smart-cb0b1b60-9fef-45b2-b647-9d0e8f60981a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124158444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3124158444
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2657717107
Short name T764
Test name
Test status
Simulation time 38771833876 ps
CPU time 13.23 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:26:27 PM PDT 24
Peak memory 199968 kb
Host smart-99843107-65c3-43c0-abff-4ce246798fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657717107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2657717107
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3165005761
Short name T630
Test name
Test status
Simulation time 135406573333 ps
CPU time 133.54 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:28:23 PM PDT 24
Peak memory 199968 kb
Host smart-eeaa8b2e-e8b6-43e0-a155-c59391fe9690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165005761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3165005761
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1469892822
Short name T726
Test name
Test status
Simulation time 22911158626 ps
CPU time 34.15 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:45 PM PDT 24
Peak memory 199940 kb
Host smart-1ac08237-55d5-4311-a25d-9db1e36396ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469892822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1469892822
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2789175966
Short name T107
Test name
Test status
Simulation time 46385356582 ps
CPU time 98.27 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:27:50 PM PDT 24
Peak memory 199952 kb
Host smart-f8b1bbdd-6859-460c-9648-650a6004130c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789175966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2789175966
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4010719977
Short name T343
Test name
Test status
Simulation time 234042271432 ps
CPU time 407.6 seconds
Started Jul 24 04:26:15 PM PDT 24
Finished Jul 24 04:33:03 PM PDT 24
Peak memory 200008 kb
Host smart-fc7da580-2cf9-4895-93d4-0469daa8ca38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010719977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4010719977
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2012625280
Short name T336
Test name
Test status
Simulation time 2313567359 ps
CPU time 4.06 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:26:24 PM PDT 24
Peak memory 197240 kb
Host smart-bcce3c54-acc8-44f2-bac9-c031a6fcaef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012625280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2012625280
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2682270324
Short name T1007
Test name
Test status
Simulation time 46807190975 ps
CPU time 88.03 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:28:09 PM PDT 24
Peak memory 208072 kb
Host smart-64c3c77d-5a0d-41b5-a332-a5d3b333a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682270324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2682270324
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1018291416
Short name T678
Test name
Test status
Simulation time 49538925953 ps
CPU time 179.19 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:29:09 PM PDT 24
Peak memory 200044 kb
Host smart-4268553b-5bd3-4dfc-ae9b-5910e280987c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018291416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1018291416
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2420514873
Short name T442
Test name
Test status
Simulation time 5083164078 ps
CPU time 10.81 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:26:29 PM PDT 24
Peak memory 199132 kb
Host smart-91fe7afd-fc38-4492-931d-d75c43947ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420514873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2420514873
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1552708153
Short name T1116
Test name
Test status
Simulation time 347867593155 ps
CPU time 43.55 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:27:25 PM PDT 24
Peak memory 199720 kb
Host smart-bd3160d3-6b97-4bf9-b8b1-d75113203a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552708153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1552708153
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.792838978
Short name T718
Test name
Test status
Simulation time 6107338661 ps
CPU time 9.5 seconds
Started Jul 24 04:26:08 PM PDT 24
Finished Jul 24 04:26:18 PM PDT 24
Peak memory 196344 kb
Host smart-77149644-dbc3-47b4-8eac-219309d132ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792838978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.792838978
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2349096206
Short name T26
Test name
Test status
Simulation time 59827084 ps
CPU time 0.73 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:26:15 PM PDT 24
Peak memory 218324 kb
Host smart-579aa71c-9bf2-4195-8747-b3c56f4c7a1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349096206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2349096206
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.534637588
Short name T373
Test name
Test status
Simulation time 458853612 ps
CPU time 1.38 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:26:12 PM PDT 24
Peak memory 199700 kb
Host smart-350e45e3-df35-4ea8-9f36-26549910c2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534637588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.534637588
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3279245241
Short name T803
Test name
Test status
Simulation time 14075878419 ps
CPU time 185.83 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:29:17 PM PDT 24
Peak memory 199948 kb
Host smart-53c440f9-98a6-4cdd-9834-34187fed4904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279245241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3279245241
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1558954673
Short name T502
Test name
Test status
Simulation time 737562097 ps
CPU time 2.71 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 198652 kb
Host smart-d37366db-3a90-4483-920f-7c4c49dc707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558954673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1558954673
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.235002438
Short name T853
Test name
Test status
Simulation time 98478974735 ps
CPU time 176.45 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 199916 kb
Host smart-a9c823cb-d7f9-4bf0-a4f9-4b783c8f6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235002438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.235002438
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1497879918
Short name T795
Test name
Test status
Simulation time 12799641 ps
CPU time 0.54 seconds
Started Jul 24 04:27:25 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 195352 kb
Host smart-5d4c8fb4-8f88-49eb-85c5-24c401095993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497879918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1497879918
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3524667336
Short name T643
Test name
Test status
Simulation time 159634819616 ps
CPU time 204.38 seconds
Started Jul 24 04:27:27 PM PDT 24
Finished Jul 24 04:30:51 PM PDT 24
Peak memory 199880 kb
Host smart-360fd350-67e1-4ca2-94d1-19b4a7df38c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524667336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3524667336
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.492350473
Short name T914
Test name
Test status
Simulation time 179007529218 ps
CPU time 236.87 seconds
Started Jul 24 04:27:26 PM PDT 24
Finished Jul 24 04:31:23 PM PDT 24
Peak memory 199928 kb
Host smart-0ee203b5-e9c2-4764-9fcd-87b510a94f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492350473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.492350473
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.950781520
Short name T1170
Test name
Test status
Simulation time 135428424222 ps
CPU time 54.38 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:28:19 PM PDT 24
Peak memory 199888 kb
Host smart-13ac1cc6-21e6-454e-bcbe-571207f5205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950781520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.950781520
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2412537093
Short name T467
Test name
Test status
Simulation time 117908681941 ps
CPU time 86.04 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 199968 kb
Host smart-cce21219-459c-4839-b85a-c13d674d2932
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412537093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2412537093
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2218526893
Short name T1099
Test name
Test status
Simulation time 108961252587 ps
CPU time 929.11 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:42:59 PM PDT 24
Peak memory 199952 kb
Host smart-fd6cd439-8a64-43b5-a226-ba368d7fce8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218526893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2218526893
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.482484633
Short name T1153
Test name
Test status
Simulation time 1920898964 ps
CPU time 3.44 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:27:28 PM PDT 24
Peak memory 196088 kb
Host smart-9c14cde0-68eb-4147-a92b-3b17ee5917af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482484633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.482484633
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3503876767
Short name T277
Test name
Test status
Simulation time 81495134891 ps
CPU time 174.28 seconds
Started Jul 24 04:27:26 PM PDT 24
Finished Jul 24 04:30:21 PM PDT 24
Peak memory 208296 kb
Host smart-566e925f-9956-425a-9969-1d6ca9c8c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503876767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3503876767
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3065832460
Short name T702
Test name
Test status
Simulation time 20300228950 ps
CPU time 240.47 seconds
Started Jul 24 04:27:27 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 200000 kb
Host smart-b48f088c-00ef-496d-a322-6b86193ae161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065832460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3065832460
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.774067699
Short name T14
Test name
Test status
Simulation time 4410613756 ps
CPU time 32.32 seconds
Started Jul 24 04:27:23 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 199160 kb
Host smart-341a52df-f5ca-4f49-9b76-61ea5a856b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774067699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.774067699
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1063526120
Short name T568
Test name
Test status
Simulation time 243065435553 ps
CPU time 107.39 seconds
Started Jul 24 04:27:26 PM PDT 24
Finished Jul 24 04:29:13 PM PDT 24
Peak memory 199880 kb
Host smart-a0cabc4e-d57f-4989-8261-ff1d44cb956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063526120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1063526120
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3101604205
Short name T355
Test name
Test status
Simulation time 2509228427 ps
CPU time 2.53 seconds
Started Jul 24 04:27:27 PM PDT 24
Finished Jul 24 04:27:30 PM PDT 24
Peak memory 195756 kb
Host smart-b69010b6-218a-4dae-9065-7b8a1c69c277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101604205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3101604205
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4165265644
Short name T430
Test name
Test status
Simulation time 457705545 ps
CPU time 1.8 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:27:32 PM PDT 24
Peak memory 199720 kb
Host smart-eea8e791-d7b9-40b9-928f-c6d7f82861c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165265644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4165265644
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.412142196
Short name T993
Test name
Test status
Simulation time 355032193201 ps
CPU time 250.74 seconds
Started Jul 24 04:27:25 PM PDT 24
Finished Jul 24 04:31:36 PM PDT 24
Peak memory 199848 kb
Host smart-2f160cbd-55ad-430c-b076-8df963dcf6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412142196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.412142196
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2734861107
Short name T403
Test name
Test status
Simulation time 1690015503 ps
CPU time 2.23 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:27:33 PM PDT 24
Peak memory 200020 kb
Host smart-6b7b509c-d1b8-46e1-85f8-c9dbbad9451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734861107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2734861107
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2052565349
Short name T285
Test name
Test status
Simulation time 65197301348 ps
CPU time 240.42 seconds
Started Jul 24 04:27:28 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 199984 kb
Host smart-93969ef9-2d6b-4f25-a74d-b7d61e3aa4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052565349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2052565349
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.687790469
Short name T325
Test name
Test status
Simulation time 127331163554 ps
CPU time 99.22 seconds
Started Jul 24 04:30:44 PM PDT 24
Finished Jul 24 04:32:24 PM PDT 24
Peak memory 199972 kb
Host smart-c54afea0-e7fe-45ab-a511-eacd84f70ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687790469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.687790469
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1911655170
Short name T214
Test name
Test status
Simulation time 25183053373 ps
CPU time 20.15 seconds
Started Jul 24 04:30:43 PM PDT 24
Finished Jul 24 04:31:04 PM PDT 24
Peak memory 200040 kb
Host smart-b9d31ccd-1b30-42c2-aa01-b730bcfc92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911655170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1911655170
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1591338550
Short name T1103
Test name
Test status
Simulation time 25964918345 ps
CPU time 19.95 seconds
Started Jul 24 04:30:42 PM PDT 24
Finished Jul 24 04:31:03 PM PDT 24
Peak memory 199856 kb
Host smart-a3793e8b-9c13-4e8a-855e-ee40cf112838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591338550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1591338550
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1943109890
Short name T662
Test name
Test status
Simulation time 54284607008 ps
CPU time 20.28 seconds
Started Jul 24 04:30:44 PM PDT 24
Finished Jul 24 04:31:04 PM PDT 24
Peak memory 199984 kb
Host smart-38797944-07d6-4c39-9cee-47af1ed78476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943109890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1943109890
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3339331084
Short name T736
Test name
Test status
Simulation time 4134658235 ps
CPU time 7.12 seconds
Started Jul 24 04:30:43 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199876 kb
Host smart-57e0227c-fe38-4295-bf14-4d86431190cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339331084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3339331084
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.941473462
Short name T1165
Test name
Test status
Simulation time 19502284483 ps
CPU time 29.1 seconds
Started Jul 24 04:30:43 PM PDT 24
Finished Jul 24 04:31:12 PM PDT 24
Peak memory 199912 kb
Host smart-300d33a8-9e9a-4e24-8832-6646f9d68eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941473462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.941473462
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4276353100
Short name T238
Test name
Test status
Simulation time 53492813791 ps
CPU time 19.57 seconds
Started Jul 24 04:30:42 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 199996 kb
Host smart-7bc4dc7f-54ec-4198-a1af-314f2eb9914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276353100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4276353100
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.587705364
Short name T220
Test name
Test status
Simulation time 34412224765 ps
CPU time 29.1 seconds
Started Jul 24 04:30:45 PM PDT 24
Finished Jul 24 04:31:15 PM PDT 24
Peak memory 200412 kb
Host smart-425f2972-f18f-4d1b-86d6-da8b1e2a117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587705364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.587705364
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2631147067
Short name T329
Test name
Test status
Simulation time 9895079221 ps
CPU time 16.59 seconds
Started Jul 24 04:30:42 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 199984 kb
Host smart-23bd3de0-c77a-42c0-aa02-a5eaa09d0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631147067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2631147067
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3188813508
Short name T515
Test name
Test status
Simulation time 30089377291 ps
CPU time 23.19 seconds
Started Jul 24 04:30:50 PM PDT 24
Finished Jul 24 04:31:13 PM PDT 24
Peak memory 200008 kb
Host smart-7d503a73-3945-4562-9733-b26d18c8cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188813508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3188813508
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4011684632
Short name T347
Test name
Test status
Simulation time 16874486 ps
CPU time 0.54 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:37 PM PDT 24
Peak memory 194964 kb
Host smart-9c514926-1ef3-4ee3-aea9-d1c85cfc7d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011684632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4011684632
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2721525230
Short name T623
Test name
Test status
Simulation time 127699264420 ps
CPU time 29.2 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:27:59 PM PDT 24
Peak memory 199988 kb
Host smart-12eb7ec3-950d-4bd1-8cbb-b4333bcdd3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721525230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2721525230
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1471067889
Short name T1082
Test name
Test status
Simulation time 128464383930 ps
CPU time 222.62 seconds
Started Jul 24 04:27:26 PM PDT 24
Finished Jul 24 04:31:09 PM PDT 24
Peak memory 200016 kb
Host smart-445cbbac-b624-4475-95ec-3f99b0283eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471067889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1471067889
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4000149623
Short name T782
Test name
Test status
Simulation time 224050580330 ps
CPU time 126.8 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 199772 kb
Host smart-4ca8c440-29c8-4048-b7de-a7cc32deda74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000149623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4000149623
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3695313561
Short name T792
Test name
Test status
Simulation time 14492823060 ps
CPU time 22.84 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:27:47 PM PDT 24
Peak memory 197752 kb
Host smart-0a8c8ad9-9c5c-400a-95ab-0c8ded509d9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695313561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3695313561
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3748964916
Short name T985
Test name
Test status
Simulation time 135048904030 ps
CPU time 475.85 seconds
Started Jul 24 04:27:32 PM PDT 24
Finished Jul 24 04:35:28 PM PDT 24
Peak memory 199888 kb
Host smart-fa8305f0-a5e4-40bd-aedb-380d52bdfff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748964916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3748964916
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1794950951
Short name T337
Test name
Test status
Simulation time 4347345335 ps
CPU time 16.25 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:27:48 PM PDT 24
Peak memory 199664 kb
Host smart-390cd359-d8c0-4b85-9436-8513ca6c7624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794950951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1794950951
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2583996246
Short name T554
Test name
Test status
Simulation time 59356491190 ps
CPU time 97.2 seconds
Started Jul 24 04:27:25 PM PDT 24
Finished Jul 24 04:29:02 PM PDT 24
Peak memory 198708 kb
Host smart-194071f0-b88f-47f4-ab2c-3b66a1c11e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583996246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2583996246
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2280911988
Short name T1
Test name
Test status
Simulation time 7715654929 ps
CPU time 139.3 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:29:51 PM PDT 24
Peak memory 199984 kb
Host smart-e02d7cb8-b2c1-4738-b7ff-aee5cf91dc04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280911988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2280911988
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1114200931
Short name T491
Test name
Test status
Simulation time 1809806413 ps
CPU time 9.11 seconds
Started Jul 24 04:27:29 PM PDT 24
Finished Jul 24 04:27:39 PM PDT 24
Peak memory 198008 kb
Host smart-35b41205-f6bb-487f-9d4c-89c92ec510ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114200931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1114200931
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3761969492
Short name T854
Test name
Test status
Simulation time 25601737943 ps
CPU time 39.37 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:28:11 PM PDT 24
Peak memory 200048 kb
Host smart-1549e1b7-386c-4571-9b5d-b5f68084204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761969492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3761969492
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2818348201
Short name T818
Test name
Test status
Simulation time 42726372097 ps
CPU time 14.9 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 195732 kb
Host smart-4f6dfd1c-3fe7-40bb-a27e-a884eea48ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818348201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2818348201
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3048816051
Short name T620
Test name
Test status
Simulation time 491043495 ps
CPU time 1.76 seconds
Started Jul 24 04:27:29 PM PDT 24
Finished Jul 24 04:27:30 PM PDT 24
Peak memory 198340 kb
Host smart-87e69852-94ee-44e1-859e-1cfbfeae104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048816051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3048816051
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3123961222
Short name T1018
Test name
Test status
Simulation time 416314443098 ps
CPU time 669.42 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:38:40 PM PDT 24
Peak memory 199904 kb
Host smart-f0185481-6217-45a4-990b-47b8142bb02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123961222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3123961222
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.866905761
Short name T910
Test name
Test status
Simulation time 1013938169 ps
CPU time 4.21 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 198508 kb
Host smart-ed7c28c4-2e92-4481-8a5d-34f65cb9a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866905761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.866905761
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.177232965
Short name T897
Test name
Test status
Simulation time 7546244333 ps
CPU time 12.37 seconds
Started Jul 24 04:27:24 PM PDT 24
Finished Jul 24 04:27:37 PM PDT 24
Peak memory 199948 kb
Host smart-af76cce6-3aa1-464d-933f-566de6d58886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177232965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.177232965
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3618289801
Short name T327
Test name
Test status
Simulation time 16616150135 ps
CPU time 25.72 seconds
Started Jul 24 04:30:48 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 200076 kb
Host smart-10bd13bc-f976-4351-b7e6-85cd4265a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618289801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3618289801
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.60969717
Short name T799
Test name
Test status
Simulation time 74301228460 ps
CPU time 27.41 seconds
Started Jul 24 04:30:47 PM PDT 24
Finished Jul 24 04:31:15 PM PDT 24
Peak memory 199984 kb
Host smart-d272ed9f-18c4-4e64-adcb-c760d051046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60969717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.60969717
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.594457280
Short name T1111
Test name
Test status
Simulation time 177549484279 ps
CPU time 79.61 seconds
Started Jul 24 04:30:50 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 199988 kb
Host smart-5154e7ce-2384-4037-b70b-20d2c0528ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594457280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.594457280
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3888459145
Short name T1094
Test name
Test status
Simulation time 146050153834 ps
CPU time 104.24 seconds
Started Jul 24 04:30:49 PM PDT 24
Finished Jul 24 04:32:33 PM PDT 24
Peak memory 199836 kb
Host smart-7224556b-c204-4e92-a34e-beee6cc7e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888459145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3888459145
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1597119677
Short name T727
Test name
Test status
Simulation time 207185517694 ps
CPU time 168.83 seconds
Started Jul 24 04:30:48 PM PDT 24
Finished Jul 24 04:33:37 PM PDT 24
Peak memory 199924 kb
Host smart-fd497b40-e02c-41c0-8879-82a94ac85a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597119677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1597119677
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2707760771
Short name T184
Test name
Test status
Simulation time 138812268484 ps
CPU time 58.53 seconds
Started Jul 24 04:30:49 PM PDT 24
Finished Jul 24 04:31:47 PM PDT 24
Peak memory 199916 kb
Host smart-8e490000-da42-4b09-9bc9-17ccca884de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707760771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2707760771
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.600167343
Short name T185
Test name
Test status
Simulation time 52690633220 ps
CPU time 22.01 seconds
Started Jul 24 04:30:48 PM PDT 24
Finished Jul 24 04:31:10 PM PDT 24
Peak memory 199840 kb
Host smart-7ff5a98a-bf7a-4620-9a39-c0d4a6ed2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600167343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.600167343
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3859321360
Short name T796
Test name
Test status
Simulation time 156452594551 ps
CPU time 72.61 seconds
Started Jul 24 04:30:47 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 199980 kb
Host smart-0cff15f9-c7a0-44b3-9679-86b9664fbab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859321360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3859321360
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.47958226
Short name T450
Test name
Test status
Simulation time 26017385948 ps
CPU time 41.03 seconds
Started Jul 24 04:30:47 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 199904 kb
Host smart-6297d99a-0d8e-4370-8303-2f77add922c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47958226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.47958226
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1391795198
Short name T1038
Test name
Test status
Simulation time 173813802322 ps
CPU time 105.85 seconds
Started Jul 24 04:30:54 PM PDT 24
Finished Jul 24 04:32:40 PM PDT 24
Peak memory 200012 kb
Host smart-749db670-7b75-469c-9991-185cd41059a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391795198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1391795198
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1783423499
Short name T519
Test name
Test status
Simulation time 12650457 ps
CPU time 0.55 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:27:44 PM PDT 24
Peak memory 195592 kb
Host smart-6c81e29e-a4b0-4f8e-b4fa-7460e3b75e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783423499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1783423499
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2434800868
Short name T971
Test name
Test status
Simulation time 19912199768 ps
CPU time 17.5 seconds
Started Jul 24 04:27:33 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 200012 kb
Host smart-e3cd9b2b-dba7-480b-991a-009574b1865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434800868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2434800868
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.963119253
Short name T263
Test name
Test status
Simulation time 29519240766 ps
CPU time 26.54 seconds
Started Jul 24 04:27:32 PM PDT 24
Finished Jul 24 04:27:59 PM PDT 24
Peak memory 199884 kb
Host smart-3fbfb74d-da5b-4f56-8bf8-40346c91557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963119253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.963119253
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4136198473
Short name T376
Test name
Test status
Simulation time 9568577286 ps
CPU time 15 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 199656 kb
Host smart-ad48ceac-1852-4515-be31-3bd28ab13fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136198473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4136198473
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.122925961
Short name T320
Test name
Test status
Simulation time 248749856623 ps
CPU time 348.19 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:33:26 PM PDT 24
Peak memory 199408 kb
Host smart-a31491da-ce58-4a6c-b29e-20e056bbee72
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122925961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.122925961
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2722280458
Short name T419
Test name
Test status
Simulation time 73765066514 ps
CPU time 155.25 seconds
Started Jul 24 04:27:36 PM PDT 24
Finished Jul 24 04:30:12 PM PDT 24
Peak memory 199912 kb
Host smart-7d9e13a2-15b2-4a4e-91c2-7eea53cd59b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722280458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2722280458
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.37026154
Short name T1159
Test name
Test status
Simulation time 2292224465 ps
CPU time 1.02 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:38 PM PDT 24
Peak memory 196172 kb
Host smart-428e1fd8-f902-42d1-ad8a-e26714c95e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37026154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.37026154
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3983121487
Short name T621
Test name
Test status
Simulation time 9870762376 ps
CPU time 1.48 seconds
Started Jul 24 04:27:38 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 194720 kb
Host smart-e083d68e-0b3b-4d8f-b556-0700410d00c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983121487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3983121487
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1416441464
Short name T299
Test name
Test status
Simulation time 13742323848 ps
CPU time 679.11 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:38:57 PM PDT 24
Peak memory 200136 kb
Host smart-bd446f05-e122-47ad-a5d7-dd028ef70fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416441464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1416441464
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.187956924
Short name T408
Test name
Test status
Simulation time 2413687009 ps
CPU time 6.04 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 198540 kb
Host smart-e74b8896-e7bb-4293-8163-853eb06b3c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187956924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.187956924
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1004079571
Short name T987
Test name
Test status
Simulation time 20663607987 ps
CPU time 17.35 seconds
Started Jul 24 04:27:36 PM PDT 24
Finished Jul 24 04:27:54 PM PDT 24
Peak memory 199992 kb
Host smart-e0cdc79d-b8a2-48bc-b459-cd19169534a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004079571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1004079571
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.649701553
Short name T894
Test name
Test status
Simulation time 4358590999 ps
CPU time 7.27 seconds
Started Jul 24 04:27:39 PM PDT 24
Finished Jul 24 04:27:47 PM PDT 24
Peak memory 196532 kb
Host smart-1c1ea6db-2d64-44af-a6dd-3c020286dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649701553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.649701553
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.4007195876
Short name T458
Test name
Test status
Simulation time 440753019 ps
CPU time 2.07 seconds
Started Jul 24 04:27:31 PM PDT 24
Finished Jul 24 04:27:33 PM PDT 24
Peak memory 198880 kb
Host smart-a3934e56-797c-4a20-a11f-b957495abc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007195876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.4007195876
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2757635259
Short name T950
Test name
Test status
Simulation time 10937990051 ps
CPU time 112.58 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:29:36 PM PDT 24
Peak memory 208388 kb
Host smart-2de4612d-f2f1-4470-8712-3d54534a2d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757635259 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2757635259
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.732397572
Short name T1147
Test name
Test status
Simulation time 14636391410 ps
CPU time 11.26 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:27:53 PM PDT 24
Peak memory 199916 kb
Host smart-36b3acb7-96d4-4ff2-a886-83d83430855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732397572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.732397572
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3297189536
Short name T922
Test name
Test status
Simulation time 6236125951 ps
CPU time 9.77 seconds
Started Jul 24 04:27:30 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 196652 kb
Host smart-ae6e103b-32a2-4bec-8380-cf4c0bd94094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297189536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3297189536
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1567094012
Short name T473
Test name
Test status
Simulation time 11334905781 ps
CPU time 8.42 seconds
Started Jul 24 04:30:55 PM PDT 24
Finished Jul 24 04:31:03 PM PDT 24
Peak memory 199932 kb
Host smart-17a3fddf-0c5a-4bfe-9298-fef3ed729d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567094012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1567094012
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1388734387
Short name T480
Test name
Test status
Simulation time 29693082728 ps
CPU time 45.83 seconds
Started Jul 24 04:30:54 PM PDT 24
Finished Jul 24 04:31:40 PM PDT 24
Peak memory 199896 kb
Host smart-95a03910-c23f-4ad0-a448-78fd9986099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388734387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1388734387
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1253252282
Short name T429
Test name
Test status
Simulation time 36502940993 ps
CPU time 17.95 seconds
Started Jul 24 04:30:53 PM PDT 24
Finished Jul 24 04:31:11 PM PDT 24
Peak memory 199856 kb
Host smart-5b48435f-717a-4b36-b06e-da3f04f684ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253252282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1253252282
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1244932849
Short name T714
Test name
Test status
Simulation time 82663932619 ps
CPU time 232.77 seconds
Started Jul 24 04:30:54 PM PDT 24
Finished Jul 24 04:34:47 PM PDT 24
Peak memory 200016 kb
Host smart-95da09ba-2b91-4e4f-8cc4-ba358b3402dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244932849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1244932849
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1932609644
Short name T333
Test name
Test status
Simulation time 96062231092 ps
CPU time 16.65 seconds
Started Jul 24 04:30:53 PM PDT 24
Finished Jul 24 04:31:09 PM PDT 24
Peak memory 199884 kb
Host smart-e4049ef7-a481-4e0f-9649-2a49efb35322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932609644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1932609644
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2051990695
Short name T625
Test name
Test status
Simulation time 51478039957 ps
CPU time 67.19 seconds
Started Jul 24 04:30:52 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 199484 kb
Host smart-7e7b769e-fe9d-4665-9668-8f9560051c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051990695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2051990695
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2856201058
Short name T540
Test name
Test status
Simulation time 145312088937 ps
CPU time 102.86 seconds
Started Jul 24 04:30:53 PM PDT 24
Finished Jul 24 04:32:36 PM PDT 24
Peak memory 199840 kb
Host smart-7bad040f-73c8-42b5-8101-1bfe4e16d724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856201058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2856201058
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4259950790
Short name T133
Test name
Test status
Simulation time 19556747098 ps
CPU time 57.87 seconds
Started Jul 24 04:30:58 PM PDT 24
Finished Jul 24 04:31:57 PM PDT 24
Peak memory 199980 kb
Host smart-c1c737d0-8659-48b8-9185-1c740ad79346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259950790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4259950790
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3286533220
Short name T106
Test name
Test status
Simulation time 18059711429 ps
CPU time 14.64 seconds
Started Jul 24 04:30:59 PM PDT 24
Finished Jul 24 04:31:14 PM PDT 24
Peak memory 200060 kb
Host smart-03f12b36-5377-4b90-ad0c-a957e705d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286533220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3286533220
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3191056925
Short name T877
Test name
Test status
Simulation time 28042293435 ps
CPU time 37.93 seconds
Started Jul 24 04:30:58 PM PDT 24
Finished Jul 24 04:31:37 PM PDT 24
Peak memory 199984 kb
Host smart-40e0dca8-ce3c-4f04-b42d-cd4517c806e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191056925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3191056925
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2990939676
Short name T874
Test name
Test status
Simulation time 17009751 ps
CPU time 0.56 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 195660 kb
Host smart-b8660e6c-929c-4a6b-8065-1423e17fd936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990939676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2990939676
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2227239685
Short name T911
Test name
Test status
Simulation time 74098816510 ps
CPU time 30.97 seconds
Started Jul 24 04:27:40 PM PDT 24
Finished Jul 24 04:28:11 PM PDT 24
Peak memory 199876 kb
Host smart-a77e9186-2e22-4ab9-be1e-215cd060e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227239685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2227239685
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4264103874
Short name T697
Test name
Test status
Simulation time 139031918972 ps
CPU time 49.3 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 199944 kb
Host smart-589b8254-b471-4f08-b359-77aa026f2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264103874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4264103874
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2511894998
Short name T739
Test name
Test status
Simulation time 25960615696 ps
CPU time 37.75 seconds
Started Jul 24 04:27:38 PM PDT 24
Finished Jul 24 04:28:16 PM PDT 24
Peak memory 199924 kb
Host smart-532d083e-06b1-4d43-bb14-8e0ca2ef5e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511894998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2511894998
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2415323927
Short name T324
Test name
Test status
Simulation time 79888492208 ps
CPU time 37.35 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:28:21 PM PDT 24
Peak memory 199960 kb
Host smart-3c38ceaa-952c-4c2c-aed4-b5bbb47a434d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415323927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2415323927
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3224515595
Short name T647
Test name
Test status
Simulation time 99141438626 ps
CPU time 248.84 seconds
Started Jul 24 04:27:45 PM PDT 24
Finished Jul 24 04:31:54 PM PDT 24
Peak memory 199992 kb
Host smart-f4a2a393-524f-4206-bd13-6214f69675e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224515595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3224515595
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3256358759
Short name T887
Test name
Test status
Simulation time 6501343841 ps
CPU time 3.8 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 198692 kb
Host smart-624c0fff-4e39-4e27-8f71-c26b0ae0429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256358759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3256358759
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3887299261
Short name T40
Test name
Test status
Simulation time 207259986246 ps
CPU time 57.07 seconds
Started Jul 24 04:27:41 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 200104 kb
Host smart-8a2e55a2-d453-4d98-b7c9-7b2982439344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887299261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3887299261
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.786248725
Short name T468
Test name
Test status
Simulation time 12138143406 ps
CPU time 144.59 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:30:07 PM PDT 24
Peak memory 199908 kb
Host smart-f1369304-9cf1-4ae2-8130-7e55afb417ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786248725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.786248725
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.698404522
Short name T16
Test name
Test status
Simulation time 4320312285 ps
CPU time 35.74 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:28:19 PM PDT 24
Peak memory 198264 kb
Host smart-07a4fd13-7cca-4537-a3af-60d65a6b5ab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698404522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.698404522
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2891600828
Short name T477
Test name
Test status
Simulation time 3902848661 ps
CPU time 6.52 seconds
Started Jul 24 04:27:45 PM PDT 24
Finished Jul 24 04:27:52 PM PDT 24
Peak memory 196096 kb
Host smart-1d853696-fa8a-4c6e-a082-429a592c09b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891600828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2891600828
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3649973575
Short name T738
Test name
Test status
Simulation time 516592066 ps
CPU time 1.29 seconds
Started Jul 24 04:27:38 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 199820 kb
Host smart-a0df6807-dd9e-41e9-9952-e55ee6b98d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649973575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3649973575
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1706762179
Short name T401
Test name
Test status
Simulation time 7048455586 ps
CPU time 2.09 seconds
Started Jul 24 04:27:45 PM PDT 24
Finished Jul 24 04:27:48 PM PDT 24
Peak memory 199952 kb
Host smart-f12867bc-0aba-42ff-80d6-e80960c446ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706762179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1706762179
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.579562977
Short name T1154
Test name
Test status
Simulation time 39139648762 ps
CPU time 66.37 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:28:43 PM PDT 24
Peak memory 199896 kb
Host smart-11e0d87c-df64-49fc-9302-a3d0351c140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579562977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.579562977
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.788438946
Short name T143
Test name
Test status
Simulation time 77814693633 ps
CPU time 119.04 seconds
Started Jul 24 04:30:59 PM PDT 24
Finished Jul 24 04:32:58 PM PDT 24
Peak memory 199972 kb
Host smart-a17d9700-6609-41f5-9c54-a624af8c5f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788438946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.788438946
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3383053778
Short name T225
Test name
Test status
Simulation time 78887790855 ps
CPU time 67.64 seconds
Started Jul 24 04:31:00 PM PDT 24
Finished Jul 24 04:32:08 PM PDT 24
Peak memory 199936 kb
Host smart-dc486e6a-2110-4a16-a6d8-8d6f5601d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383053778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3383053778
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2329252389
Short name T774
Test name
Test status
Simulation time 334328266150 ps
CPU time 23.98 seconds
Started Jul 24 04:31:00 PM PDT 24
Finished Jul 24 04:31:25 PM PDT 24
Peak memory 200000 kb
Host smart-8a097de0-7bc7-42ce-ba5c-d837d596f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329252389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2329252389
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1138039528
Short name T988
Test name
Test status
Simulation time 22854597179 ps
CPU time 17.81 seconds
Started Jul 24 04:31:01 PM PDT 24
Finished Jul 24 04:31:19 PM PDT 24
Peak memory 198980 kb
Host smart-d8621591-991b-4b24-8d32-01865be9c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138039528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1138039528
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2032533819
Short name T120
Test name
Test status
Simulation time 23126423143 ps
CPU time 32.47 seconds
Started Jul 24 04:31:01 PM PDT 24
Finished Jul 24 04:31:34 PM PDT 24
Peak memory 200088 kb
Host smart-d74cd34f-da72-4dba-8f64-f02f0fd58473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032533819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2032533819
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3144417808
Short name T177
Test name
Test status
Simulation time 50245927920 ps
CPU time 33.87 seconds
Started Jul 24 04:30:58 PM PDT 24
Finished Jul 24 04:31:32 PM PDT 24
Peak memory 199776 kb
Host smart-176ff081-d159-4b2c-963e-4550354ff2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144417808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3144417808
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4053347692
Short name T406
Test name
Test status
Simulation time 25827817168 ps
CPU time 26.77 seconds
Started Jul 24 04:30:57 PM PDT 24
Finished Jul 24 04:31:24 PM PDT 24
Peak memory 200048 kb
Host smart-40182cb1-df3e-487c-a29e-1dc718059f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053347692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4053347692
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.547947295
Short name T855
Test name
Test status
Simulation time 209016381866 ps
CPU time 59.64 seconds
Started Jul 24 04:31:03 PM PDT 24
Finished Jul 24 04:32:03 PM PDT 24
Peak memory 199904 kb
Host smart-cfdeca7d-fd99-449d-a0a9-43be9ba2bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547947295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.547947295
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1494533092
Short name T435
Test name
Test status
Simulation time 57900543 ps
CPU time 0.57 seconds
Started Jul 24 04:27:50 PM PDT 24
Finished Jul 24 04:27:50 PM PDT 24
Peak memory 195436 kb
Host smart-c630f656-8258-484f-bd2c-2ad4a2d92600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494533092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1494533092
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3693629555
Short name T926
Test name
Test status
Simulation time 35321503352 ps
CPU time 13.7 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 199900 kb
Host smart-3a1ea9fb-8595-46f0-a5ca-fd141acccf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693629555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3693629555
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1217836429
Short name T595
Test name
Test status
Simulation time 145832103251 ps
CPU time 185.9 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:30:49 PM PDT 24
Peak memory 199992 kb
Host smart-9a553610-b392-43ed-a45a-4fdf9f504556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217836429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1217836429
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.111801095
Short name T925
Test name
Test status
Simulation time 71564831343 ps
CPU time 26.09 seconds
Started Jul 24 04:27:42 PM PDT 24
Finished Jul 24 04:28:08 PM PDT 24
Peak memory 199704 kb
Host smart-f3759401-0fee-4af0-a9b6-2c26b6a1e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111801095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.111801095
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4286640330
Short name T580
Test name
Test status
Simulation time 39117081616 ps
CPU time 12.79 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 198760 kb
Host smart-2ed9c715-d236-4d4a-8969-ce3700e7ee1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286640330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4286640330
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1326023795
Short name T659
Test name
Test status
Simulation time 91792205524 ps
CPU time 204.52 seconds
Started Jul 24 04:27:51 PM PDT 24
Finished Jul 24 04:31:15 PM PDT 24
Peak memory 199996 kb
Host smart-a735abf4-c662-45e8-9758-86ca7e735100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326023795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1326023795
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3770968777
Short name T873
Test name
Test status
Simulation time 3237410237 ps
CPU time 4.52 seconds
Started Jul 24 04:27:50 PM PDT 24
Finished Jul 24 04:27:54 PM PDT 24
Peak memory 198792 kb
Host smart-8d865b75-3cb4-4e9e-8dec-3daa56e0e183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770968777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3770968777
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.470638750
Short name T817
Test name
Test status
Simulation time 153656066684 ps
CPU time 109.6 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 199940 kb
Host smart-f80b664f-e082-4bfd-878e-835393d23f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470638750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.470638750
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3927210087
Short name T639
Test name
Test status
Simulation time 21700095769 ps
CPU time 407.32 seconds
Started Jul 24 04:27:48 PM PDT 24
Finished Jul 24 04:34:35 PM PDT 24
Peak memory 199852 kb
Host smart-77f1f597-a466-4815-907c-ebb71f8ad892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927210087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3927210087
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2521785239
Short name T905
Test name
Test status
Simulation time 5925956652 ps
CPU time 54.17 seconds
Started Jul 24 04:27:44 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 198280 kb
Host smart-36653247-90eb-49f4-8d7e-b1c3a5da3610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521785239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2521785239
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.270055685
Short name T820
Test name
Test status
Simulation time 96404105184 ps
CPU time 144.41 seconds
Started Jul 24 04:27:41 PM PDT 24
Finished Jul 24 04:30:06 PM PDT 24
Peak memory 199936 kb
Host smart-a4301c8e-24d6-4411-bea2-6a0229d77a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270055685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.270055685
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.737640961
Short name T447
Test name
Test status
Simulation time 4616042351 ps
CPU time 7.58 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 196528 kb
Host smart-c918ee40-6245-4566-8a8f-118f38372b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737640961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.737640961
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1329026977
Short name T1126
Test name
Test status
Simulation time 725441219 ps
CPU time 1.72 seconds
Started Jul 24 04:27:44 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 198560 kb
Host smart-ae618496-6b0e-4e89-a0e9-6e2f6b8d8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329026977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1329026977
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3436499883
Short name T265
Test name
Test status
Simulation time 1991060999 ps
CPU time 1.91 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 198404 kb
Host smart-99d3d188-2369-4c88-a20c-a1cfad073538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436499883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3436499883
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.18805208
Short name T731
Test name
Test status
Simulation time 113797969407 ps
CPU time 146.73 seconds
Started Jul 24 04:27:43 PM PDT 24
Finished Jul 24 04:30:10 PM PDT 24
Peak memory 199972 kb
Host smart-46a6414f-b831-442b-8ec3-48dd1604955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18805208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.18805208
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1584645062
Short name T330
Test name
Test status
Simulation time 66331304301 ps
CPU time 99.28 seconds
Started Jul 24 04:31:07 PM PDT 24
Finished Jul 24 04:32:47 PM PDT 24
Peak memory 200412 kb
Host smart-39951206-9fc5-42f6-8735-4a96bfd4c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584645062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1584645062
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1356305418
Short name T596
Test name
Test status
Simulation time 64428966873 ps
CPU time 47.86 seconds
Started Jul 24 04:31:03 PM PDT 24
Finished Jul 24 04:31:51 PM PDT 24
Peak memory 199880 kb
Host smart-82e5674d-b79d-466d-b718-7ec2e7ff7128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356305418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1356305418
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1044532872
Short name T656
Test name
Test status
Simulation time 58649434762 ps
CPU time 144.08 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:33:28 PM PDT 24
Peak memory 199996 kb
Host smart-86329a59-1e66-4aad-91c4-115fa918a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044532872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1044532872
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2933608379
Short name T93
Test name
Test status
Simulation time 65457472001 ps
CPU time 182.03 seconds
Started Jul 24 04:31:03 PM PDT 24
Finished Jul 24 04:34:05 PM PDT 24
Peak memory 200328 kb
Host smart-532c393e-36e6-4a0f-b74d-3d1a2ec6a9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933608379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2933608379
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2650197309
Short name T686
Test name
Test status
Simulation time 101105896393 ps
CPU time 155.35 seconds
Started Jul 24 04:31:03 PM PDT 24
Finished Jul 24 04:33:39 PM PDT 24
Peak memory 199972 kb
Host smart-9ae6d9bb-72ee-42a6-9d67-fe77d274cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650197309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2650197309
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2239371676
Short name T784
Test name
Test status
Simulation time 256069880544 ps
CPU time 23.76 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 200076 kb
Host smart-3f730507-46b8-4dee-b1d2-77af3bc6f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239371676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2239371676
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1782662562
Short name T751
Test name
Test status
Simulation time 112900962512 ps
CPU time 79.95 seconds
Started Jul 24 04:31:05 PM PDT 24
Finished Jul 24 04:32:25 PM PDT 24
Peak memory 200028 kb
Host smart-752f2754-e75d-4ce5-b8f5-35212cf13434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782662562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1782662562
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1706311088
Short name T1098
Test name
Test status
Simulation time 25552054463 ps
CPU time 54.12 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 199960 kb
Host smart-d416705e-343b-460a-a1d4-948972f6af86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706311088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1706311088
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4127210262
Short name T523
Test name
Test status
Simulation time 74027602408 ps
CPU time 35.03 seconds
Started Jul 24 04:31:03 PM PDT 24
Finished Jul 24 04:31:38 PM PDT 24
Peak memory 200012 kb
Host smart-7afa2160-8546-4284-b9d0-116b16ba0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127210262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4127210262
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3054798200
Short name T255
Test name
Test status
Simulation time 441119412943 ps
CPU time 46.49 seconds
Started Jul 24 04:31:04 PM PDT 24
Finished Jul 24 04:31:51 PM PDT 24
Peak memory 200020 kb
Host smart-b52cb8b8-6794-48f3-971d-3816ef622b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054798200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3054798200
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1920963448
Short name T501
Test name
Test status
Simulation time 38947407 ps
CPU time 0.52 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:27:55 PM PDT 24
Peak memory 195288 kb
Host smart-3673d5f2-3e1d-4fef-899c-18623fc55a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920963448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1920963448
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3882772462
Short name T160
Test name
Test status
Simulation time 151792528713 ps
CPU time 49.91 seconds
Started Jul 24 04:27:50 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 199940 kb
Host smart-68182df5-e2ba-4b7a-bfd3-87214e882d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882772462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3882772462
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3120570023
Short name T963
Test name
Test status
Simulation time 33086772729 ps
CPU time 50.62 seconds
Started Jul 24 04:27:48 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 200052 kb
Host smart-0adf0fe9-e331-4158-91fc-4873ca3a86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120570023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3120570023
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.2492458266
Short name T531
Test name
Test status
Simulation time 27482140859 ps
CPU time 29.19 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:28:19 PM PDT 24
Peak memory 199568 kb
Host smart-6964c5c2-09c1-4730-86e4-f3dc497c2c1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492458266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2492458266
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1129697178
Short name T1138
Test name
Test status
Simulation time 117502455949 ps
CPU time 580.87 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:37:35 PM PDT 24
Peak memory 200040 kb
Host smart-03db112e-2274-4447-9411-838a2f5421c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129697178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1129697178
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2639460638
Short name T589
Test name
Test status
Simulation time 10395855734 ps
CPU time 12.32 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:28:06 PM PDT 24
Peak memory 200056 kb
Host smart-a3cca5fb-8471-4114-96df-5d132c591c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639460638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2639460638
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.281630471
Short name T535
Test name
Test status
Simulation time 80852847294 ps
CPU time 86.18 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:29:16 PM PDT 24
Peak memory 208120 kb
Host smart-fbf84787-babf-46f1-ba7b-604878f24cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281630471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.281630471
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2198158085
Short name T968
Test name
Test status
Simulation time 2378860488 ps
CPU time 96.55 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 199900 kb
Host smart-4d626e03-fe54-40e6-86e4-805371992282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198158085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2198158085
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1423323261
Short name T400
Test name
Test status
Simulation time 5164301494 ps
CPU time 48.1 seconds
Started Jul 24 04:27:50 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 199988 kb
Host smart-4ac9fbcf-f7ac-44ca-b83c-f79b3e265b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423323261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1423323261
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1303465621
Short name T964
Test name
Test status
Simulation time 24965253686 ps
CPU time 45.86 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:28:35 PM PDT 24
Peak memory 199680 kb
Host smart-5a42677f-0531-4fe0-8c7b-b51204da65ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303465621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1303465621
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1832241082
Short name T947
Test name
Test status
Simulation time 6321242817 ps
CPU time 10.35 seconds
Started Jul 24 04:27:53 PM PDT 24
Finished Jul 24 04:28:03 PM PDT 24
Peak memory 196332 kb
Host smart-920609a2-d9c8-4f7a-9703-f6fec538c208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832241082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1832241082
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1055151936
Short name T492
Test name
Test status
Simulation time 335496060 ps
CPU time 0.89 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:27:50 PM PDT 24
Peak memory 198380 kb
Host smart-9e9324e3-5999-4c86-a204-39490919f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055151936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1055151936
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.851013011
Short name T532
Test name
Test status
Simulation time 404671592 ps
CPU time 1.79 seconds
Started Jul 24 04:27:50 PM PDT 24
Finished Jul 24 04:27:52 PM PDT 24
Peak memory 198232 kb
Host smart-58f7882b-7e45-440a-9fef-6c0290c3ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851013011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.851013011
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.508880838
Short name T511
Test name
Test status
Simulation time 5902114451 ps
CPU time 2.83 seconds
Started Jul 24 04:27:48 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 197684 kb
Host smart-867f4c94-42be-4add-972e-2b920b98f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508880838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.508880838
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3475965112
Short name T1121
Test name
Test status
Simulation time 14458879619 ps
CPU time 23.46 seconds
Started Jul 24 04:31:05 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 199892 kb
Host smart-b0b046da-9c4e-419c-8993-dcb4518c4b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475965112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3475965112
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2413881367
Short name T1054
Test name
Test status
Simulation time 123718513200 ps
CPU time 213.16 seconds
Started Jul 24 04:31:14 PM PDT 24
Finished Jul 24 04:34:48 PM PDT 24
Peak memory 199996 kb
Host smart-cb1bfbd6-03bf-405e-9b59-29c4681f61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413881367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2413881367
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1470076878
Short name T199
Test name
Test status
Simulation time 19055237675 ps
CPU time 15.54 seconds
Started Jul 24 04:31:09 PM PDT 24
Finished Jul 24 04:31:25 PM PDT 24
Peak memory 200080 kb
Host smart-8ca18b6e-a986-4edc-aec5-2cd0a98290b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470076878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1470076878
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1960565636
Short name T146
Test name
Test status
Simulation time 158664713826 ps
CPU time 59.84 seconds
Started Jul 24 04:31:14 PM PDT 24
Finished Jul 24 04:32:14 PM PDT 24
Peak memory 199936 kb
Host smart-1ea5f51c-d71e-4d90-a8f8-32cfaa913387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960565636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1960565636
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1016970920
Short name T798
Test name
Test status
Simulation time 7470327199 ps
CPU time 6.69 seconds
Started Jul 24 04:31:08 PM PDT 24
Finished Jul 24 04:31:15 PM PDT 24
Peak memory 199780 kb
Host smart-65b5ceea-8b76-4264-8ebb-ed825507953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016970920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1016970920
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1074637682
Short name T864
Test name
Test status
Simulation time 201352002788 ps
CPU time 93.29 seconds
Started Jul 24 04:31:09 PM PDT 24
Finished Jul 24 04:32:43 PM PDT 24
Peak memory 200180 kb
Host smart-d4cdd3d1-7f86-43f4-b9a9-0fa20bacf647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074637682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1074637682
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.362916143
Short name T1118
Test name
Test status
Simulation time 44291449 ps
CPU time 0.53 seconds
Started Jul 24 04:27:57 PM PDT 24
Finished Jul 24 04:27:58 PM PDT 24
Peak memory 195652 kb
Host smart-3fcfa760-1cb6-4000-9226-09a420a1617f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362916143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.362916143
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.574999386
Short name T898
Test name
Test status
Simulation time 19235738708 ps
CPU time 28.58 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 199988 kb
Host smart-a06b9e9c-1467-44d5-ac68-dcc3e737b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574999386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.574999386
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2905520385
Short name T694
Test name
Test status
Simulation time 87158176486 ps
CPU time 27.52 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:28:21 PM PDT 24
Peak memory 198400 kb
Host smart-b04658d3-2686-44a8-a97f-089728f13c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905520385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2905520385
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2323014752
Short name T1104
Test name
Test status
Simulation time 102954722323 ps
CPU time 148.61 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:30:23 PM PDT 24
Peak memory 200048 kb
Host smart-aceff433-786f-4cbe-b230-c4728fa0563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323014752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2323014752
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3656125446
Short name T775
Test name
Test status
Simulation time 171213093802 ps
CPU time 208.64 seconds
Started Jul 24 04:27:54 PM PDT 24
Finished Jul 24 04:31:23 PM PDT 24
Peak memory 199912 kb
Host smart-d3c3567f-26f5-4e6f-a042-76ac6539d4d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656125446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3656125446
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.228058574
Short name T539
Test name
Test status
Simulation time 217933873822 ps
CPU time 227.39 seconds
Started Jul 24 04:27:57 PM PDT 24
Finished Jul 24 04:31:45 PM PDT 24
Peak memory 200012 kb
Host smart-e1a71f19-f213-40e6-b8b7-1f177be63eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228058574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.228058574
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4060670261
Short name T685
Test name
Test status
Simulation time 6085716661 ps
CPU time 3.55 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:05 PM PDT 24
Peak memory 199612 kb
Host smart-13a4369a-08e0-4f07-b9d4-a66f6acdfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060670261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4060670261
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.550717841
Short name T584
Test name
Test status
Simulation time 59526499790 ps
CPU time 91.64 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 199996 kb
Host smart-7325eb0e-9feb-4599-80db-f126ba8ed384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550717841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.550717841
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1411458554
Short name T953
Test name
Test status
Simulation time 8662682555 ps
CPU time 108.75 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:29:57 PM PDT 24
Peak memory 199780 kb
Host smart-22840358-e62a-4b71-b6b0-480b323b3374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411458554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1411458554
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.833795277
Short name T973
Test name
Test status
Simulation time 7268869328 ps
CPU time 61.67 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:28:57 PM PDT 24
Peak memory 199232 kb
Host smart-1214343a-a86d-4892-a5fa-55e64b8668a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833795277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.833795277
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1270227519
Short name T830
Test name
Test status
Simulation time 34120947223 ps
CPU time 69.26 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:29:04 PM PDT 24
Peak memory 199812 kb
Host smart-41ce306d-a19e-41c0-ab93-67eff365cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270227519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1270227519
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.513638698
Short name T780
Test name
Test status
Simulation time 4930748641 ps
CPU time 1.03 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 196804 kb
Host smart-8286f82e-f734-4a13-a821-44845cf01c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513638698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.513638698
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.570426785
Short name T386
Test name
Test status
Simulation time 317777594 ps
CPU time 1.21 seconds
Started Jul 24 04:27:56 PM PDT 24
Finished Jul 24 04:27:57 PM PDT 24
Peak memory 198384 kb
Host smart-a9cfaa60-9076-4217-839e-ce16f12a17a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570426785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.570426785
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3296781074
Short name T157
Test name
Test status
Simulation time 444649017381 ps
CPU time 1146 seconds
Started Jul 24 04:27:55 PM PDT 24
Finished Jul 24 04:47:02 PM PDT 24
Peak memory 225868 kb
Host smart-58f54fdf-df01-413a-8818-388a20b45dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296781074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3296781074
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4208708409
Short name T670
Test name
Test status
Simulation time 901730370 ps
CPU time 2.89 seconds
Started Jul 24 04:27:56 PM PDT 24
Finished Jul 24 04:27:59 PM PDT 24
Peak memory 199172 kb
Host smart-d7c9e726-4412-4a7e-b1b8-8bc6f9c9eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208708409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4208708409
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3508183106
Short name T828
Test name
Test status
Simulation time 97248379647 ps
CPU time 29.5 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 199748 kb
Host smart-787d1b3a-24a5-4266-93b1-b7193b752f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508183106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3508183106
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.17075375
Short name T827
Test name
Test status
Simulation time 10105657269 ps
CPU time 15.29 seconds
Started Jul 24 04:31:06 PM PDT 24
Finished Jul 24 04:31:22 PM PDT 24
Peak memory 199972 kb
Host smart-6452c9bc-f30b-4b33-ae47-d296c418fd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17075375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.17075375
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.645888623
Short name T138
Test name
Test status
Simulation time 41225111370 ps
CPU time 59.75 seconds
Started Jul 24 04:31:09 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 199820 kb
Host smart-bf6a4b8b-fe13-47d4-8139-9ae592084d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645888623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.645888623
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2238802717
Short name T932
Test name
Test status
Simulation time 36402354452 ps
CPU time 17.17 seconds
Started Jul 24 04:31:11 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 200352 kb
Host smart-dd6e807a-3555-4e3f-abda-bc2d99d70c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238802717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2238802717
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.231174904
Short name T632
Test name
Test status
Simulation time 74497988679 ps
CPU time 113.37 seconds
Started Jul 24 04:31:15 PM PDT 24
Finished Jul 24 04:33:08 PM PDT 24
Peak memory 199992 kb
Host smart-4b616528-9225-43ec-a455-d0bd778ad56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231174904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.231174904
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3620180283
Short name T507
Test name
Test status
Simulation time 163985267470 ps
CPU time 37.77 seconds
Started Jul 24 04:31:13 PM PDT 24
Finished Jul 24 04:31:51 PM PDT 24
Peak memory 199488 kb
Host smart-a0bafb52-60a1-402d-9bba-6d40c0937faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620180283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3620180283
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4039402796
Short name T175
Test name
Test status
Simulation time 86596005991 ps
CPU time 19.77 seconds
Started Jul 24 04:31:14 PM PDT 24
Finished Jul 24 04:31:34 PM PDT 24
Peak memory 199996 kb
Host smart-8f05a38b-31b0-43c0-9219-742a9bbd57b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039402796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4039402796
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2555473268
Short name T1125
Test name
Test status
Simulation time 85734992060 ps
CPU time 481.76 seconds
Started Jul 24 04:31:13 PM PDT 24
Finished Jul 24 04:39:15 PM PDT 24
Peak memory 199912 kb
Host smart-8cac9a66-612c-47e5-b2df-865426bfb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555473268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2555473268
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2909085979
Short name T109
Test name
Test status
Simulation time 44838055568 ps
CPU time 35.73 seconds
Started Jul 24 04:31:16 PM PDT 24
Finished Jul 24 04:31:52 PM PDT 24
Peak memory 199876 kb
Host smart-538124be-a3ad-4ed3-9b54-45f057b60c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909085979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2909085979
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1663535554
Short name T21
Test name
Test status
Simulation time 40741277 ps
CPU time 0.55 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:28:00 PM PDT 24
Peak memory 195712 kb
Host smart-3d36d1f0-ef8e-4b29-9763-f60c446fe7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663535554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1663535554
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3592009155
Short name T104
Test name
Test status
Simulation time 82434907118 ps
CPU time 25.03 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 199972 kb
Host smart-f554cfe7-eb72-4fc9-9336-dff160ec949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592009155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3592009155
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.950684130
Short name T636
Test name
Test status
Simulation time 226838216973 ps
CPU time 350.82 seconds
Started Jul 24 04:27:58 PM PDT 24
Finished Jul 24 04:33:49 PM PDT 24
Peak memory 199968 kb
Host smart-6749dc28-1499-423e-a7b9-c47c1074bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950684130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.950684130
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2841266126
Short name T631
Test name
Test status
Simulation time 111723592119 ps
CPU time 149.95 seconds
Started Jul 24 04:27:58 PM PDT 24
Finished Jul 24 04:30:28 PM PDT 24
Peak memory 199812 kb
Host smart-23cb3fda-d326-470b-bda1-e6d12908d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841266126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2841266126
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.216033157
Short name T12
Test name
Test status
Simulation time 28257002469 ps
CPU time 42.84 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:28:42 PM PDT 24
Peak memory 200020 kb
Host smart-70840488-43d3-4b3c-8b92-5d60e5ef7719
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216033157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.216033157
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.234078672
Short name T465
Test name
Test status
Simulation time 121097469666 ps
CPU time 762.65 seconds
Started Jul 24 04:28:04 PM PDT 24
Finished Jul 24 04:40:47 PM PDT 24
Peak memory 199968 kb
Host smart-29cafd7a-a74b-49d1-ba03-a71bfb938831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234078672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.234078672
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3664134616
Short name T412
Test name
Test status
Simulation time 4569701045 ps
CPU time 2.44 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:03 PM PDT 24
Peak memory 195992 kb
Host smart-95b7d7b6-f21f-4466-b416-250cb2c2b030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664134616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3664134616
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2237900250
Short name T561
Test name
Test status
Simulation time 97114859887 ps
CPU time 39.16 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 199868 kb
Host smart-904ab1f8-7666-482f-8fa1-5f0b58316b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237900250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2237900250
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2251166505
Short name T433
Test name
Test status
Simulation time 16193137378 ps
CPU time 165.93 seconds
Started Jul 24 04:27:58 PM PDT 24
Finished Jul 24 04:30:45 PM PDT 24
Peak memory 199968 kb
Host smart-9c805ed8-be7d-4fff-b162-4a85e340c63f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251166505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2251166505
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2472062830
Short name T958
Test name
Test status
Simulation time 6507242080 ps
CPU time 51.72 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:53 PM PDT 24
Peak memory 199104 kb
Host smart-1eb60703-f125-4c99-a0ec-a4af3a0599d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472062830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2472062830
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.292555319
Short name T1100
Test name
Test status
Simulation time 42194047168 ps
CPU time 4.16 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:28:04 PM PDT 24
Peak memory 196964 kb
Host smart-169cf593-079a-4392-a067-47d13b0e1853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292555319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.292555319
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.25862650
Short name T634
Test name
Test status
Simulation time 5396072170 ps
CPU time 5.96 seconds
Started Jul 24 04:27:56 PM PDT 24
Finished Jul 24 04:28:02 PM PDT 24
Peak memory 200288 kb
Host smart-fe28ed97-afb4-4650-a112-0cae2ffc620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25862650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.25862650
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3762911463
Short name T878
Test name
Test status
Simulation time 217098416341 ps
CPU time 902.25 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:43:03 PM PDT 24
Peak memory 199940 kb
Host smart-c453fbc0-d9e6-48f5-b260-1e2517d7f2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762911463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3762911463
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3505059229
Short name T1161
Test name
Test status
Simulation time 51210987008 ps
CPU time 542.73 seconds
Started Jul 24 04:28:02 PM PDT 24
Finished Jul 24 04:37:04 PM PDT 24
Peak memory 216404 kb
Host smart-8e3203c5-f698-4d2e-b274-a23ccc9090ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505059229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3505059229
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4146153400
Short name T856
Test name
Test status
Simulation time 6453437371 ps
CPU time 19.31 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:20 PM PDT 24
Peak memory 199376 kb
Host smart-541a841e-8c45-438a-aa3e-3f31b04a4d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146153400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4146153400
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1341909220
Short name T251
Test name
Test status
Simulation time 151584945598 ps
CPU time 65.67 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199996 kb
Host smart-b59df5ab-14e7-4589-9db6-4392f2b8a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341909220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1341909220
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3987658224
Short name T181
Test name
Test status
Simulation time 118475242162 ps
CPU time 168.25 seconds
Started Jul 24 04:31:14 PM PDT 24
Finished Jul 24 04:34:03 PM PDT 24
Peak memory 199936 kb
Host smart-4814d1e2-ab6c-443f-8370-7724bd113215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987658224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3987658224
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1216096681
Short name T88
Test name
Test status
Simulation time 63484517100 ps
CPU time 63.31 seconds
Started Jul 24 04:31:18 PM PDT 24
Finished Jul 24 04:32:22 PM PDT 24
Peak memory 200052 kb
Host smart-afd5086b-7f8b-4bb7-b619-430cecf72a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216096681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1216096681
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2197092136
Short name T628
Test name
Test status
Simulation time 57865708991 ps
CPU time 22.25 seconds
Started Jul 24 04:31:19 PM PDT 24
Finished Jul 24 04:31:42 PM PDT 24
Peak memory 199824 kb
Host smart-aa96ae86-2e46-44f0-902f-22d208546af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197092136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2197092136
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3544726696
Short name T904
Test name
Test status
Simulation time 34186773452 ps
CPU time 27.83 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:31:48 PM PDT 24
Peak memory 199996 kb
Host smart-8623b904-4a26-4170-a06f-7e228da62bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544726696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3544726696
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3921009987
Short name T187
Test name
Test status
Simulation time 134301991726 ps
CPU time 69.31 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:32:29 PM PDT 24
Peak memory 199888 kb
Host smart-3b9aaab3-824f-4805-970f-f58ed6e50a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921009987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3921009987
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.643059102
Short name T178
Test name
Test status
Simulation time 102921895991 ps
CPU time 77.26 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:32:37 PM PDT 24
Peak memory 199928 kb
Host smart-7f7ad2c5-3a80-45e5-9d23-f4de3aea5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643059102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.643059102
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1696300309
Short name T231
Test name
Test status
Simulation time 36735631410 ps
CPU time 49.74 seconds
Started Jul 24 04:31:18 PM PDT 24
Finished Jul 24 04:32:08 PM PDT 24
Peak memory 199840 kb
Host smart-ce5d4e4c-7210-42e7-b671-70193fbe1749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696300309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1696300309
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.98756494
Short name T1139
Test name
Test status
Simulation time 26898950 ps
CPU time 0.55 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:28:05 PM PDT 24
Peak memory 195508 kb
Host smart-90789432-5187-4cc3-a3f7-9d2a82aa8a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98756494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.98756494
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.691256617
Short name T506
Test name
Test status
Simulation time 167629636219 ps
CPU time 101.86 seconds
Started Jul 24 04:27:59 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 199952 kb
Host smart-c066cb5b-72f3-432c-bf2e-edc6f35a64fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691256617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.691256617
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.933612853
Short name T602
Test name
Test status
Simulation time 129601835775 ps
CPU time 37.36 seconds
Started Jul 24 04:28:00 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 199896 kb
Host smart-c38ffc8a-15e7-4049-9a36-17a1032ad703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933612853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.933612853
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2884196310
Short name T206
Test name
Test status
Simulation time 191543230493 ps
CPU time 76.28 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:29:17 PM PDT 24
Peak memory 200008 kb
Host smart-f22c338b-8832-4702-a2ff-024f7a84e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884196310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2884196310
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.665889812
Short name T95
Test name
Test status
Simulation time 14649653205 ps
CPU time 2.81 seconds
Started Jul 24 04:28:00 PM PDT 24
Finished Jul 24 04:28:03 PM PDT 24
Peak memory 199632 kb
Host smart-5a14527b-3057-41eb-93cf-11608ffbb718
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665889812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.665889812
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2508701979
Short name T89
Test name
Test status
Simulation time 67301614260 ps
CPU time 572.23 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:37:40 PM PDT 24
Peak memory 199472 kb
Host smart-605b05fe-ac6e-462f-a897-e0cb68640ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508701979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2508701979
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3607482478
Short name T335
Test name
Test status
Simulation time 2018405588 ps
CPU time 3.99 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:28:09 PM PDT 24
Peak memory 198476 kb
Host smart-3cf924b2-f334-470a-840c-6694ab0705f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607482478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3607482478
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2949891464
Short name T1045
Test name
Test status
Simulation time 18928173849 ps
CPU time 25.33 seconds
Started Jul 24 04:27:58 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 200064 kb
Host smart-47d59cce-0cf8-4e04-83b6-fcdfc389d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949891464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2949891464
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4260686827
Short name T622
Test name
Test status
Simulation time 17502566248 ps
CPU time 433.08 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:35:18 PM PDT 24
Peak memory 199912 kb
Host smart-6a38fc4b-95a3-4f67-a1a7-2e927768d009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260686827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4260686827
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.211308098
Short name T765
Test name
Test status
Simulation time 2053860662 ps
CPU time 2.01 seconds
Started Jul 24 04:28:00 PM PDT 24
Finished Jul 24 04:28:02 PM PDT 24
Peak memory 198388 kb
Host smart-7c014c0b-887e-45c1-b29d-891c9fe1f47b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211308098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.211308098
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1403124420
Short name T158
Test name
Test status
Simulation time 78430315338 ps
CPU time 16.04 seconds
Started Jul 24 04:28:06 PM PDT 24
Finished Jul 24 04:28:22 PM PDT 24
Peak memory 199752 kb
Host smart-36444dfa-0397-40ce-909d-5cc466986cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403124420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1403124420
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2583820452
Short name T438
Test name
Test status
Simulation time 29624363036 ps
CPU time 10.05 seconds
Started Jul 24 04:28:06 PM PDT 24
Finished Jul 24 04:28:16 PM PDT 24
Peak memory 196548 kb
Host smart-3b45c50b-ec40-44d0-959d-199446537b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583820452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2583820452
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.290377918
Short name T366
Test name
Test status
Simulation time 309318558 ps
CPU time 1.05 seconds
Started Jul 24 04:28:01 PM PDT 24
Finished Jul 24 04:28:02 PM PDT 24
Peak memory 198640 kb
Host smart-88de1d53-efa2-4eef-9605-3db778437d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290377918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.290377918
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4044409646
Short name T997
Test name
Test status
Simulation time 142220293930 ps
CPU time 240.27 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:32:08 PM PDT 24
Peak memory 215472 kb
Host smart-48f20226-23df-4f2c-af68-7bc219836c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044409646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4044409646
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.316947210
Short name T56
Test name
Test status
Simulation time 58769455571 ps
CPU time 307.44 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:33:13 PM PDT 24
Peak memory 216604 kb
Host smart-eccd36f7-cea6-4340-8a93-6a9a9dbbe87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316947210 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.316947210
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2533149032
Short name T1059
Test name
Test status
Simulation time 7082385687 ps
CPU time 8.62 seconds
Started Jul 24 04:28:06 PM PDT 24
Finished Jul 24 04:28:14 PM PDT 24
Peak memory 199984 kb
Host smart-04b18663-cc35-4778-b963-0a7b998a6f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533149032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2533149032
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1023087294
Short name T860
Test name
Test status
Simulation time 219338118770 ps
CPU time 37.48 seconds
Started Jul 24 04:28:04 PM PDT 24
Finished Jul 24 04:28:42 PM PDT 24
Peak memory 199908 kb
Host smart-6c69a398-b7ce-42fc-9c59-2320a80e3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023087294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1023087294
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2512440174
Short name T890
Test name
Test status
Simulation time 46199300283 ps
CPU time 120.33 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:33:20 PM PDT 24
Peak memory 199964 kb
Host smart-094a60ee-f3ef-4497-9486-c805cc806579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512440174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2512440174
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2581009151
Short name T1068
Test name
Test status
Simulation time 10985348254 ps
CPU time 17.33 seconds
Started Jul 24 04:31:24 PM PDT 24
Finished Jul 24 04:31:42 PM PDT 24
Peak memory 199704 kb
Host smart-f6fb6ac3-815a-43b4-987a-09579aa641e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581009151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2581009151
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1221927645
Short name T493
Test name
Test status
Simulation time 16949362232 ps
CPU time 27.56 seconds
Started Jul 24 04:31:18 PM PDT 24
Finished Jul 24 04:31:46 PM PDT 24
Peak memory 199916 kb
Host smart-90c680a3-7350-4118-ade4-f2cb2b0a1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221927645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1221927645
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2468430853
Short name T681
Test name
Test status
Simulation time 113167668116 ps
CPU time 36.01 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:32:01 PM PDT 24
Peak memory 199868 kb
Host smart-4f690308-2392-4eff-821b-73eaf0044624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468430853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2468430853
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.639492202
Short name T162
Test name
Test status
Simulation time 21072917089 ps
CPU time 11.55 seconds
Started Jul 24 04:31:21 PM PDT 24
Finished Jul 24 04:31:33 PM PDT 24
Peak memory 199912 kb
Host smart-547bd874-766e-4b7b-a5ad-db126b941053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639492202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.639492202
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1405563286
Short name T193
Test name
Test status
Simulation time 48734385117 ps
CPU time 49 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:32:14 PM PDT 24
Peak memory 199876 kb
Host smart-75fe1409-9cb4-4e0a-b1bc-27672c27f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405563286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1405563286
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2624585571
Short name T771
Test name
Test status
Simulation time 47987243933 ps
CPU time 60.87 seconds
Started Jul 24 04:31:20 PM PDT 24
Finished Jul 24 04:32:21 PM PDT 24
Peak memory 199928 kb
Host smart-61ca8697-ecc6-4066-bab8-bf166c1d5fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624585571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2624585571
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.486778646
Short name T228
Test name
Test status
Simulation time 19975164217 ps
CPU time 27.88 seconds
Started Jul 24 04:31:26 PM PDT 24
Finished Jul 24 04:31:54 PM PDT 24
Peak memory 199840 kb
Host smart-9874c5b9-1d1f-4085-b4b8-75272a3e2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486778646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.486778646
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3630095235
Short name T1057
Test name
Test status
Simulation time 26360042435 ps
CPU time 21.9 seconds
Started Jul 24 04:31:19 PM PDT 24
Finished Jul 24 04:31:41 PM PDT 24
Peak memory 199992 kb
Host smart-53132825-6786-4798-a02e-cd8537e3cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630095235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3630095235
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4173090882
Short name T378
Test name
Test status
Simulation time 35679796091 ps
CPU time 31.83 seconds
Started Jul 24 04:31:26 PM PDT 24
Finished Jul 24 04:31:58 PM PDT 24
Peak memory 199960 kb
Host smart-9ebcdb31-1bc8-4b83-9f07-593ff8a70e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173090882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4173090882
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.312573568
Short name T461
Test name
Test status
Simulation time 31509348 ps
CPU time 0.56 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:12 PM PDT 24
Peak memory 195420 kb
Host smart-cea33abf-8a44-4ef9-b116-259470877f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312573568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.312573568
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2689199697
Short name T245
Test name
Test status
Simulation time 133210306093 ps
CPU time 119.31 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:30:05 PM PDT 24
Peak memory 199972 kb
Host smart-4b2824fe-b5e3-4c01-969d-b89a21543a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689199697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2689199697
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1586330722
Short name T392
Test name
Test status
Simulation time 50605760461 ps
CPU time 41.04 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:28:46 PM PDT 24
Peak memory 200028 kb
Host smart-28daefaa-3366-456b-9a41-c301b4507e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586330722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1586330722
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3029587357
Short name T504
Test name
Test status
Simulation time 71853899145 ps
CPU time 47.59 seconds
Started Jul 24 04:28:07 PM PDT 24
Finished Jul 24 04:28:54 PM PDT 24
Peak memory 199920 kb
Host smart-2dd856e8-0f22-48e1-a0e2-2ee66d9b7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029587357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3029587357
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1235906222
Short name T281
Test name
Test status
Simulation time 34681026945 ps
CPU time 14.93 seconds
Started Jul 24 04:28:14 PM PDT 24
Finished Jul 24 04:28:29 PM PDT 24
Peak memory 199892 kb
Host smart-887ccca0-c260-4d61-af0a-11694997ebea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235906222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1235906222
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1943626725
Short name T1110
Test name
Test status
Simulation time 117686694683 ps
CPU time 929.82 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:43:42 PM PDT 24
Peak memory 199884 kb
Host smart-e747f4d6-26ee-42b2-b7fa-8ac1e4037669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943626725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1943626725
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2148693464
Short name T1035
Test name
Test status
Simulation time 1697135751 ps
CPU time 4.45 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:16 PM PDT 24
Peak memory 198560 kb
Host smart-dd8fa2e2-9730-4643-92e1-023ab8f3e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148693464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2148693464
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.401006354
Short name T1053
Test name
Test status
Simulation time 6536013368 ps
CPU time 10.26 seconds
Started Jul 24 04:28:11 PM PDT 24
Finished Jul 24 04:28:22 PM PDT 24
Peak memory 198016 kb
Host smart-98c1b3f1-d5f5-4105-9ba1-38a5cbf62a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401006354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.401006354
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3652555874
Short name T250
Test name
Test status
Simulation time 15129824731 ps
CPU time 867.86 seconds
Started Jul 24 04:28:10 PM PDT 24
Finished Jul 24 04:42:38 PM PDT 24
Peak memory 200152 kb
Host smart-2edad568-4e8f-4233-a050-206bb5fdec19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652555874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3652555874
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2306389479
Short name T338
Test name
Test status
Simulation time 2985284583 ps
CPU time 4.76 seconds
Started Jul 24 04:28:08 PM PDT 24
Finished Jul 24 04:28:13 PM PDT 24
Peak memory 198276 kb
Host smart-86459564-ac5b-445a-8bff-80dc4ffb4ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306389479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2306389479
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1320999085
Short name T641
Test name
Test status
Simulation time 34567102210 ps
CPU time 25.59 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 200048 kb
Host smart-9e06b3b5-ef8a-4b77-aebd-b4187f3b0681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320999085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1320999085
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1193071537
Short name T732
Test name
Test status
Simulation time 1588900359 ps
CPU time 2.76 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:15 PM PDT 24
Peak memory 195552 kb
Host smart-8ab44248-a346-4bd5-97c4-f1825fda9429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193071537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1193071537
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3739599890
Short name T94
Test name
Test status
Simulation time 5895519334 ps
CPU time 7.86 seconds
Started Jul 24 04:28:07 PM PDT 24
Finished Jul 24 04:28:15 PM PDT 24
Peak memory 199980 kb
Host smart-b1f387b3-6c34-4023-8152-00093495ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739599890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3739599890
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.96699031
Short name T1101
Test name
Test status
Simulation time 213500855256 ps
CPU time 734.61 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:40:36 PM PDT 24
Peak memory 208284 kb
Host smart-b0c88048-e967-435e-85b6-55911fa87365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96699031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.96699031
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2115260158
Short name T1169
Test name
Test status
Simulation time 50299962255 ps
CPU time 595.87 seconds
Started Jul 24 04:28:10 PM PDT 24
Finished Jul 24 04:38:06 PM PDT 24
Peak memory 216480 kb
Host smart-78e8b237-1e6e-489e-b77c-cb47ae9e9a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115260158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2115260158
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1380083048
Short name T692
Test name
Test status
Simulation time 11950102908 ps
CPU time 33.86 seconds
Started Jul 24 04:28:13 PM PDT 24
Finished Jul 24 04:28:47 PM PDT 24
Peak memory 199712 kb
Host smart-7a9f5805-f087-4181-a733-121469f837bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380083048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1380083048
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1145468479
Short name T706
Test name
Test status
Simulation time 165201586288 ps
CPU time 62.64 seconds
Started Jul 24 04:28:05 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 199944 kb
Host smart-4a48b24f-7aa4-4c34-bef2-a49b310f786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145468479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1145468479
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2042392935
Short name T556
Test name
Test status
Simulation time 62009460293 ps
CPU time 98.23 seconds
Started Jul 24 04:31:24 PM PDT 24
Finished Jul 24 04:33:02 PM PDT 24
Peak memory 200132 kb
Host smart-d6147993-ecdd-4b74-89e9-020cf049bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042392935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2042392935
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3752087193
Short name T415
Test name
Test status
Simulation time 142299989475 ps
CPU time 13.66 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:31:39 PM PDT 24
Peak memory 197568 kb
Host smart-374d1e45-d41b-4bf4-9349-38281f0edc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752087193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3752087193
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3582696414
Short name T755
Test name
Test status
Simulation time 54882835461 ps
CPU time 38.7 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:32:04 PM PDT 24
Peak memory 199976 kb
Host smart-a3704e9f-63f7-4ba4-a0a4-0d0a6ca5ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582696414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3582696414
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1100142960
Short name T512
Test name
Test status
Simulation time 49781066400 ps
CPU time 63.29 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:32:28 PM PDT 24
Peak memory 200012 kb
Host smart-057f4ede-dfeb-4f88-b009-55c4faef384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100142960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1100142960
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.32023960
Short name T197
Test name
Test status
Simulation time 17486480782 ps
CPU time 29.03 seconds
Started Jul 24 04:31:26 PM PDT 24
Finished Jul 24 04:31:55 PM PDT 24
Peak memory 200016 kb
Host smart-5e5e9107-1f26-4228-ac31-007bb266f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32023960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.32023960
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.735292772
Short name T767
Test name
Test status
Simulation time 235427222814 ps
CPU time 164.85 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:34:10 PM PDT 24
Peak memory 199992 kb
Host smart-74c314df-7680-4e44-9eab-fa942318d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735292772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.735292772
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2208480350
Short name T822
Test name
Test status
Simulation time 98520567067 ps
CPU time 90.93 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:32:57 PM PDT 24
Peak memory 200076 kb
Host smart-c53b21e3-fdf8-4855-80c0-62dd359fd185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208480350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2208480350
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1679138179
Short name T172
Test name
Test status
Simulation time 109912842742 ps
CPU time 176.2 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:34:22 PM PDT 24
Peak memory 200048 kb
Host smart-3897cbe5-135b-4cdd-b506-5defcd888100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679138179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1679138179
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.199131593
Short name T924
Test name
Test status
Simulation time 80089263565 ps
CPU time 22.23 seconds
Started Jul 24 04:31:27 PM PDT 24
Finished Jul 24 04:31:50 PM PDT 24
Peak memory 200004 kb
Host smart-8c854264-a7bb-4c38-8463-dfc0152e218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199131593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.199131593
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2749256822
Short name T434
Test name
Test status
Simulation time 53593979 ps
CPU time 0.57 seconds
Started Jul 24 04:26:26 PM PDT 24
Finished Jul 24 04:26:27 PM PDT 24
Peak memory 195356 kb
Host smart-deefa143-a091-4e9a-bde1-038de987b88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749256822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2749256822
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1609741809
Short name T734
Test name
Test status
Simulation time 136698768861 ps
CPU time 67.45 seconds
Started Jul 24 04:26:15 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 199928 kb
Host smart-d1a7bc45-b183-4f60-8957-c77d0a8e2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609741809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1609741809
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.949548884
Short name T936
Test name
Test status
Simulation time 71201111612 ps
CPU time 49.96 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:27:30 PM PDT 24
Peak memory 199516 kb
Host smart-9034ae84-3f0c-40ce-9da1-7506d211e5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949548884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.949548884
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.2408517685
Short name T819
Test name
Test status
Simulation time 37954475967 ps
CPU time 61.8 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 199716 kb
Host smart-f270a2a8-2970-49d9-8aaa-43a6cf99557a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408517685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2408517685
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3869203375
Short name T829
Test name
Test status
Simulation time 79876331140 ps
CPU time 168.93 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199972 kb
Host smart-ea9aad14-d19c-4c4f-91ee-bc8639fa0af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869203375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3869203375
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3543272155
Short name T995
Test name
Test status
Simulation time 7038112817 ps
CPU time 7.31 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 198780 kb
Host smart-8d4384f6-644a-4a7a-b327-107a3ccd05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543272155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3543272155
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3092298840
Short name T1039
Test name
Test status
Simulation time 182455479343 ps
CPU time 67.56 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:27:29 PM PDT 24
Peak memory 200172 kb
Host smart-108fd927-2493-4e8d-b2d0-132f1642b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092298840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3092298840
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1094681828
Short name T928
Test name
Test status
Simulation time 22005388378 ps
CPU time 255.19 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:30:33 PM PDT 24
Peak memory 199948 kb
Host smart-81884b0c-692a-4a7d-aae7-82f2e7fe7a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094681828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1094681828
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2147866467
Short name T357
Test name
Test status
Simulation time 3399360858 ps
CPU time 6.18 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:26:24 PM PDT 24
Peak memory 198784 kb
Host smart-8263f732-7891-47f4-a2a0-52c2c0adad58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147866467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2147866467
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.681746386
Short name T599
Test name
Test status
Simulation time 72546722872 ps
CPU time 14.06 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 200040 kb
Host smart-d9808856-0579-4119-b089-55dfd852db64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681746386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.681746386
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2978657232
Short name T455
Test name
Test status
Simulation time 4848751104 ps
CPU time 1.52 seconds
Started Jul 24 04:26:25 PM PDT 24
Finished Jul 24 04:26:27 PM PDT 24
Peak memory 196796 kb
Host smart-df6f9d8c-b297-4e2c-80e9-7abe8e77f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978657232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2978657232
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1946598856
Short name T24
Test name
Test status
Simulation time 99278315 ps
CPU time 0.86 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:26:19 PM PDT 24
Peak memory 218276 kb
Host smart-2e879096-a857-4ba3-808a-929af22a055d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946598856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1946598856
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.101638092
Short name T808
Test name
Test status
Simulation time 470390078 ps
CPU time 1.07 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:26:11 PM PDT 24
Peak memory 198236 kb
Host smart-3c09e867-4020-4c7f-a08d-19fa5154528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101638092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.101638092
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.599376964
Short name T483
Test name
Test status
Simulation time 240799071201 ps
CPU time 1567.37 seconds
Started Jul 24 04:26:17 PM PDT 24
Finished Jul 24 04:52:25 PM PDT 24
Peak memory 199904 kb
Host smart-381f0d24-3027-4ec9-ab80-8e46fbc95383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599376964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.599376964
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3193548398
Short name T475
Test name
Test status
Simulation time 1386281378 ps
CPU time 2.33 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:26:15 PM PDT 24
Peak memory 199360 kb
Host smart-ed7e7444-ce81-4f06-be36-8c4e3e837630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193548398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3193548398
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3832620021
Short name T270
Test name
Test status
Simulation time 160069041323 ps
CPU time 57.04 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:27:39 PM PDT 24
Peak memory 199656 kb
Host smart-2432a799-de86-47bf-989b-6571dd7310fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832620021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3832620021
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1764466435
Short name T772
Test name
Test status
Simulation time 20123908 ps
CPU time 0.53 seconds
Started Jul 24 04:28:17 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 194912 kb
Host smart-59886254-33ec-43fe-8502-7365292b9cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764466435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1764466435
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3905116461
Short name T637
Test name
Test status
Simulation time 44737063877 ps
CPU time 37.66 seconds
Started Jul 24 04:28:13 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 199904 kb
Host smart-c2bfce24-b8b8-47a5-8f3e-de542816eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905116461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3905116461
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3020470582
Short name T404
Test name
Test status
Simulation time 116267869566 ps
CPU time 539.71 seconds
Started Jul 24 04:28:13 PM PDT 24
Finished Jul 24 04:37:13 PM PDT 24
Peak memory 199972 kb
Host smart-587322da-9e2d-401d-a701-7332408766b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020470582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3020470582
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3643886967
Short name T1106
Test name
Test status
Simulation time 13981299136 ps
CPU time 20.05 seconds
Started Jul 24 04:28:20 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 199984 kb
Host smart-d18a835a-ed86-4f0f-a1e0-ffec618f79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643886967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3643886967
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4155436462
Short name T456
Test name
Test status
Simulation time 7217904808 ps
CPU time 4.79 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 199956 kb
Host smart-3ba7b970-bfc8-4280-b63c-67e8f840538e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155436462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4155436462
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3876430218
Short name T776
Test name
Test status
Simulation time 66408524495 ps
CPU time 83.09 seconds
Started Jul 24 04:28:18 PM PDT 24
Finished Jul 24 04:29:42 PM PDT 24
Peak memory 199928 kb
Host smart-6007a3e0-afd8-4c45-b62d-9e1c33592bda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876430218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3876430218
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1494179203
Short name T334
Test name
Test status
Simulation time 7170234489 ps
CPU time 19.48 seconds
Started Jul 24 04:28:15 PM PDT 24
Finished Jul 24 04:28:35 PM PDT 24
Peak memory 199208 kb
Host smart-f9749468-b871-4cfa-8abd-ab71cd7e6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494179203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1494179203
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.626199236
Short name T393
Test name
Test status
Simulation time 60458693705 ps
CPU time 104.94 seconds
Started Jul 24 04:28:14 PM PDT 24
Finished Jul 24 04:29:59 PM PDT 24
Peak memory 200024 kb
Host smart-c69631f5-1ffe-4acd-8ef4-998ce2e72a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626199236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.626199236
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2372726547
Short name T696
Test name
Test status
Simulation time 11436360756 ps
CPU time 637.56 seconds
Started Jul 24 04:28:15 PM PDT 24
Finished Jul 24 04:38:53 PM PDT 24
Peak memory 199956 kb
Host smart-32654daa-e76b-408d-83db-61206af26de5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372726547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2372726547
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3740693482
Short name T478
Test name
Test status
Simulation time 4649460361 ps
CPU time 8.54 seconds
Started Jul 24 04:28:12 PM PDT 24
Finished Jul 24 04:28:21 PM PDT 24
Peak memory 198520 kb
Host smart-5407d50a-7705-4561-b881-2a0d35e54e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740693482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3740693482
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.938516376
Short name T451
Test name
Test status
Simulation time 61089468672 ps
CPU time 89.16 seconds
Started Jul 24 04:28:13 PM PDT 24
Finished Jul 24 04:29:42 PM PDT 24
Peak memory 199948 kb
Host smart-3214e8bc-73bc-49b4-b83a-6ae946b3d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938516376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.938516376
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.247289755
Short name T524
Test name
Test status
Simulation time 5105724831 ps
CPU time 2.38 seconds
Started Jul 24 04:28:13 PM PDT 24
Finished Jul 24 04:28:16 PM PDT 24
Peak memory 196312 kb
Host smart-09cc9457-69bd-49e2-98b1-6f2fa79944a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247289755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.247289755
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.335090884
Short name T901
Test name
Test status
Simulation time 308668813 ps
CPU time 0.91 seconds
Started Jul 24 04:28:10 PM PDT 24
Finished Jul 24 04:28:11 PM PDT 24
Peak memory 198464 kb
Host smart-aa88f41b-95d6-447a-bc4f-cd010577a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335090884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.335090884
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1798605889
Short name T407
Test name
Test status
Simulation time 109062092597 ps
CPU time 116.98 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:30:19 PM PDT 24
Peak memory 199984 kb
Host smart-9ccd253c-ade8-4a6c-8b4b-9a400cbbe939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798605889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1798605889
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3996084506
Short name T1074
Test name
Test status
Simulation time 70272515002 ps
CPU time 586.72 seconds
Started Jul 24 04:28:17 PM PDT 24
Finished Jul 24 04:38:04 PM PDT 24
Peak memory 213508 kb
Host smart-9fa3a3a2-9bd0-4ce5-b1b3-7d7006b1c56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996084506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3996084506
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2259813835
Short name T648
Test name
Test status
Simulation time 508104396 ps
CPU time 2.16 seconds
Started Jul 24 04:28:20 PM PDT 24
Finished Jul 24 04:28:22 PM PDT 24
Peak memory 199760 kb
Host smart-6f0fb0c9-d22d-4130-96f0-ec39f59207e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259813835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2259813835
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1567368995
Short name T36
Test name
Test status
Simulation time 41817864873 ps
CPU time 64.2 seconds
Started Jul 24 04:28:10 PM PDT 24
Finished Jul 24 04:29:14 PM PDT 24
Peak memory 199892 kb
Host smart-20b47071-cc79-46f8-b0e1-4d507205d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567368995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1567368995
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1192549193
Short name T341
Test name
Test status
Simulation time 14749246 ps
CPU time 0.54 seconds
Started Jul 24 04:28:16 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 195364 kb
Host smart-9e52659f-f706-4444-855f-10d71c8fae3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192549193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1192549193
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2628157102
Short name T597
Test name
Test status
Simulation time 12895816644 ps
CPU time 19.67 seconds
Started Jul 24 04:28:19 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 199884 kb
Host smart-08e0b365-2bc3-4478-8bca-d0b8a4c42a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628157102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2628157102
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3704258609
Short name T1158
Test name
Test status
Simulation time 85026053108 ps
CPU time 21.94 seconds
Started Jul 24 04:28:18 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 199956 kb
Host smart-c84d6100-d07d-453a-882b-a63a2e96887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704258609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3704258609
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3065604835
Short name T949
Test name
Test status
Simulation time 26097708599 ps
CPU time 50.01 seconds
Started Jul 24 04:28:16 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 200016 kb
Host smart-da04feb1-8c02-4008-818a-1b5b8a2dfcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065604835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3065604835
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3446364642
Short name T674
Test name
Test status
Simulation time 54383620834 ps
CPU time 77.98 seconds
Started Jul 24 04:28:16 PM PDT 24
Finished Jul 24 04:29:35 PM PDT 24
Peak memory 199980 kb
Host smart-39cb5701-2e67-479a-a86c-8bc4357f0d86
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446364642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3446364642
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2069686607
Short name T612
Test name
Test status
Simulation time 94205122882 ps
CPU time 246.49 seconds
Started Jul 24 04:28:16 PM PDT 24
Finished Jul 24 04:32:22 PM PDT 24
Peak memory 199904 kb
Host smart-46aaba94-747c-41dc-b1e0-a832561a92c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069686607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2069686607
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3065277946
Short name T360
Test name
Test status
Simulation time 7550096267 ps
CPU time 9.7 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 199528 kb
Host smart-0c0b5953-caba-4c32-ab01-d375d6f07a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065277946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3065277946
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3035111839
Short name T790
Test name
Test status
Simulation time 20430308473 ps
CPU time 246.16 seconds
Started Jul 24 04:28:16 PM PDT 24
Finished Jul 24 04:32:22 PM PDT 24
Peak memory 200064 kb
Host smart-259f7054-1100-4b39-b018-2dc4ef5346de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035111839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3035111839
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2394869434
Short name T728
Test name
Test status
Simulation time 5058936141 ps
CPU time 22.31 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:28:44 PM PDT 24
Peak memory 199536 kb
Host smart-3deb094e-27cc-4bf1-af0d-77371b7dfabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394869434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2394869434
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1130710351
Short name T759
Test name
Test status
Simulation time 24167990590 ps
CPU time 15.41 seconds
Started Jul 24 04:28:17 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 199936 kb
Host smart-33da176e-90ae-4e7c-ac82-6b45e8cea584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130710351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1130710351
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3256621019
Short name T586
Test name
Test status
Simulation time 4617528461 ps
CPU time 4.41 seconds
Started Jul 24 04:28:26 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 196456 kb
Host smart-0f0cdef2-59d4-43d5-836d-68830868c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256621019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3256621019
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.680914013
Short name T807
Test name
Test status
Simulation time 6155765659 ps
CPU time 13.98 seconds
Started Jul 24 04:28:17 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 199852 kb
Host smart-bc423124-7181-4517-ae4f-05e4c17adb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680914013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.680914013
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1431534505
Short name T650
Test name
Test status
Simulation time 519586379135 ps
CPU time 974.21 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:44:37 PM PDT 24
Peak memory 208240 kb
Host smart-0abcb551-e075-4631-8c4b-d61080daeffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431534505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1431534505
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3893821318
Short name T549
Test name
Test status
Simulation time 381693721976 ps
CPU time 1419.74 seconds
Started Jul 24 04:28:18 PM PDT 24
Finished Jul 24 04:51:58 PM PDT 24
Peak memory 226312 kb
Host smart-2917c3af-e13e-444c-ad85-470888ca85b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893821318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3893821318
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1805567639
Short name T811
Test name
Test status
Simulation time 1683003288 ps
CPU time 1.44 seconds
Started Jul 24 04:28:18 PM PDT 24
Finished Jul 24 04:28:20 PM PDT 24
Peak memory 198276 kb
Host smart-c1b4f7df-1ca2-4b93-936e-a07c0bb71146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805567639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1805567639
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.627880955
Short name T402
Test name
Test status
Simulation time 17035868042 ps
CPU time 15.67 seconds
Started Jul 24 04:28:17 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 197916 kb
Host smart-8b2c009a-afc4-4f9a-8bd4-5337948644e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627880955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.627880955
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2258388976
Short name T340
Test name
Test status
Simulation time 169488450 ps
CPU time 0.54 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 195380 kb
Host smart-5acfc37b-4379-46e9-90ef-54ce42408eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258388976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2258388976
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3821185362
Short name T1107
Test name
Test status
Simulation time 23662897968 ps
CPU time 36.85 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:29:00 PM PDT 24
Peak memory 199988 kb
Host smart-38a5454e-f57d-49f2-9363-39018e7407c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821185362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3821185362
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2998532909
Short name T444
Test name
Test status
Simulation time 12826592556 ps
CPU time 20.97 seconds
Started Jul 24 04:28:22 PM PDT 24
Finished Jul 24 04:28:43 PM PDT 24
Peak memory 199928 kb
Host smart-5687c11d-8e29-40d7-87fd-4579a5fa33a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998532909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2998532909
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3148785158
Short name T139
Test name
Test status
Simulation time 106900667391 ps
CPU time 44.52 seconds
Started Jul 24 04:28:22 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199880 kb
Host smart-e0b35666-4027-4878-b950-34a6925a3428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148785158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3148785158
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1284349829
Short name T1040
Test name
Test status
Simulation time 4403123387 ps
CPU time 22.69 seconds
Started Jul 24 04:28:24 PM PDT 24
Finished Jul 24 04:28:47 PM PDT 24
Peak memory 199964 kb
Host smart-51010189-6e30-4f8f-b20c-a4e907a2f031
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284349829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1284349829
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3870394971
Short name T797
Test name
Test status
Simulation time 232321454433 ps
CPU time 247.02 seconds
Started Jul 24 04:28:24 PM PDT 24
Finished Jul 24 04:32:31 PM PDT 24
Peak memory 199936 kb
Host smart-aed74d79-c6bd-4057-b23c-85f798ee84fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870394971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3870394971
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2500106018
Short name T358
Test name
Test status
Simulation time 838064095 ps
CPU time 1.94 seconds
Started Jul 24 04:28:22 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 197164 kb
Host smart-d14f1181-f393-4029-b977-879f69842db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500106018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2500106018
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2794275247
Short name T487
Test name
Test status
Simulation time 31249447460 ps
CPU time 49.45 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 200028 kb
Host smart-9e5f4775-bb28-41fa-b90e-dcaa8a955794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794275247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2794275247
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3485334393
Short name T1112
Test name
Test status
Simulation time 11468633374 ps
CPU time 596.99 seconds
Started Jul 24 04:28:22 PM PDT 24
Finished Jul 24 04:38:19 PM PDT 24
Peak memory 200016 kb
Host smart-773a9000-1751-419a-975f-32aea022351d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485334393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3485334393
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3990838633
Short name T986
Test name
Test status
Simulation time 6836321527 ps
CPU time 61.94 seconds
Started Jul 24 04:28:24 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 198124 kb
Host smart-7763716b-fdec-40c0-bb22-96f85fea98d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990838633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3990838633
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.725204002
Short name T975
Test name
Test status
Simulation time 28206653725 ps
CPU time 46.22 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:29:10 PM PDT 24
Peak memory 200020 kb
Host smart-4a41180e-c6d8-42b0-8390-4ec75dc3f57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725204002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.725204002
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3559337784
Short name T1069
Test name
Test status
Simulation time 1541713731 ps
CPU time 1.82 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:28:25 PM PDT 24
Peak memory 195480 kb
Host smart-5635726f-609f-49b4-9ede-c141a1861c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559337784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3559337784
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.485874346
Short name T495
Test name
Test status
Simulation time 925164563 ps
CPU time 1.23 seconds
Started Jul 24 04:28:18 PM PDT 24
Finished Jul 24 04:28:20 PM PDT 24
Peak memory 199928 kb
Host smart-24784a9f-a983-4fa5-91da-0dfe59bcb9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485874346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.485874346
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1653764012
Short name T19
Test name
Test status
Simulation time 90419854937 ps
CPU time 1113.44 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:46:57 PM PDT 24
Peak memory 216528 kb
Host smart-1a370e10-ad56-4689-ac9f-2e605730f9ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653764012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1653764012
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1856136917
Short name T585
Test name
Test status
Simulation time 4300000514 ps
CPU time 1.33 seconds
Started Jul 24 04:28:24 PM PDT 24
Finished Jul 24 04:28:25 PM PDT 24
Peak memory 199600 kb
Host smart-4403626e-ddbf-46fb-a96c-41daeb454983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856136917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1856136917
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.66865785
Short name T247
Test name
Test status
Simulation time 14132271109 ps
CPU time 10.45 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 199968 kb
Host smart-5f407968-10aa-438c-8f91-699b1cbebc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66865785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.66865785
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2745509378
Short name T836
Test name
Test status
Simulation time 12007460 ps
CPU time 0.54 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:28:28 PM PDT 24
Peak memory 194740 kb
Host smart-79a339b4-9bd7-404f-a264-2cfe21517827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745509378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2745509378
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1650832548
Short name T1028
Test name
Test status
Simulation time 99949927124 ps
CPU time 43.18 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:29:06 PM PDT 24
Peak memory 199928 kb
Host smart-673d6176-661d-4c8d-b922-183bac16439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650832548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1650832548
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4268264454
Short name T930
Test name
Test status
Simulation time 182070334414 ps
CPU time 138.65 seconds
Started Jul 24 04:28:23 PM PDT 24
Finished Jul 24 04:30:42 PM PDT 24
Peak memory 199976 kb
Host smart-6338ce52-5c02-4414-9d52-8d725211aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268264454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4268264454
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1100907490
Short name T217
Test name
Test status
Simulation time 20102326942 ps
CPU time 14.22 seconds
Started Jul 24 04:28:28 PM PDT 24
Finished Jul 24 04:28:43 PM PDT 24
Peak memory 200016 kb
Host smart-821f01ec-f457-4476-b7f3-97eb0abc891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100907490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1100907490
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.36026617
Short name T544
Test name
Test status
Simulation time 14758427949 ps
CPU time 7.42 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 199612 kb
Host smart-3d87ce77-dd41-4ba4-8070-ad40ba202775
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.36026617
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3833211240
Short name T345
Test name
Test status
Simulation time 113894034341 ps
CPU time 699.46 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:40:07 PM PDT 24
Peak memory 199888 kb
Host smart-fc9f133a-45b5-491d-b417-cd81fa2488a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833211240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3833211240
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2024906259
Short name T984
Test name
Test status
Simulation time 1118990754 ps
CPU time 2.96 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:28:30 PM PDT 24
Peak memory 198440 kb
Host smart-201d246b-8323-4794-b0fc-1224a467f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024906259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2024906259
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.643294333
Short name T912
Test name
Test status
Simulation time 120254566672 ps
CPU time 241.07 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:32:28 PM PDT 24
Peak memory 200092 kb
Host smart-a093f5bf-e53e-4181-9d39-f7508c48a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643294333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.643294333
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1385379788
Short name T387
Test name
Test status
Simulation time 18171887414 ps
CPU time 86.82 seconds
Started Jul 24 04:28:28 PM PDT 24
Finished Jul 24 04:29:56 PM PDT 24
Peak memory 200348 kb
Host smart-60c6e6d2-4df0-4408-ac55-3ccf178ceaa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385379788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1385379788
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3268938442
Short name T1066
Test name
Test status
Simulation time 2230623186 ps
CPU time 6.29 seconds
Started Jul 24 04:28:32 PM PDT 24
Finished Jul 24 04:28:38 PM PDT 24
Peak memory 197988 kb
Host smart-c8a9d8ec-f504-4371-ac05-005e4b234ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268938442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3268938442
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2622817460
Short name T945
Test name
Test status
Simulation time 29139400097 ps
CPU time 11.57 seconds
Started Jul 24 04:28:28 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 199848 kb
Host smart-571fd969-fa4a-46e3-9d1f-1ba697b2ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622817460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2622817460
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3777257591
Short name T1008
Test name
Test status
Simulation time 35433361695 ps
CPU time 5.51 seconds
Started Jul 24 04:28:29 PM PDT 24
Finished Jul 24 04:28:35 PM PDT 24
Peak memory 196440 kb
Host smart-7d147c82-8849-439a-8a28-118a59366620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777257591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3777257591
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3536038473
Short name T294
Test name
Test status
Simulation time 290777491 ps
CPU time 1.11 seconds
Started Jul 24 04:28:22 PM PDT 24
Finished Jul 24 04:28:23 PM PDT 24
Peak memory 199720 kb
Host smart-4b18b9ac-7c5c-4def-aafd-38b0b28d6c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536038473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3536038473
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.359269205
Short name T268
Test name
Test status
Simulation time 43104764760 ps
CPU time 249.78 seconds
Started Jul 24 04:28:30 PM PDT 24
Finished Jul 24 04:32:40 PM PDT 24
Peak memory 215608 kb
Host smart-0906d339-020d-42f7-8984-59b6825290c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359269205 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.359269205
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2737928962
Short name T1132
Test name
Test status
Simulation time 6337027365 ps
CPU time 21.27 seconds
Started Jul 24 04:28:28 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199868 kb
Host smart-9f931d8d-3b80-49e3-8ea5-7d5cc2780f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737928962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2737928962
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1574671731
Short name T668
Test name
Test status
Simulation time 116205452864 ps
CPU time 58.42 seconds
Started Jul 24 04:28:21 PM PDT 24
Finished Jul 24 04:29:20 PM PDT 24
Peak memory 199956 kb
Host smart-c91ca908-0efc-48db-9f61-5b933e545860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574671731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1574671731
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.571578196
Short name T721
Test name
Test status
Simulation time 20409808 ps
CPU time 0.53 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 195352 kb
Host smart-8ba292e3-8393-4e22-a50f-0d25a282117a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571578196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.571578196
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.104456378
Short name T766
Test name
Test status
Simulation time 121897106807 ps
CPU time 84.91 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:29:59 PM PDT 24
Peak memory 199956 kb
Host smart-88486a1d-bedc-4037-87a4-0e42a4b6e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104456378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.104456378
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3130757586
Short name T961
Test name
Test status
Simulation time 49497043689 ps
CPU time 75.93 seconds
Started Jul 24 04:28:29 PM PDT 24
Finished Jul 24 04:29:45 PM PDT 24
Peak memory 200012 kb
Host smart-c668de1a-778f-4f09-a11d-7309a118b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130757586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3130757586
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3334025835
Short name T200
Test name
Test status
Simulation time 26644865624 ps
CPU time 43.47 seconds
Started Jul 24 04:28:29 PM PDT 24
Finished Jul 24 04:29:13 PM PDT 24
Peak memory 199900 kb
Host smart-e2df647b-8ed4-410e-9bba-688194c1c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334025835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3334025835
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3154531506
Short name T371
Test name
Test status
Simulation time 33333916260 ps
CPU time 29.84 seconds
Started Jul 24 04:28:30 PM PDT 24
Finished Jul 24 04:29:00 PM PDT 24
Peak memory 199864 kb
Host smart-2af81c99-d765-4b1e-a789-8c708bcc1c01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154531506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3154531506
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1912273299
Short name T704
Test name
Test status
Simulation time 84408976921 ps
CPU time 222.6 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:32:17 PM PDT 24
Peak memory 199908 kb
Host smart-35122fe9-4f73-4adf-a0bd-e67a9bf7b199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912273299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1912273299
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3543970548
Short name T530
Test name
Test status
Simulation time 3883844075 ps
CPU time 4.96 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 199688 kb
Host smart-41aec210-4ac7-4cc0-a459-5bd54b21ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543970548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3543970548
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.4258287967
Short name T624
Test name
Test status
Simulation time 176003678796 ps
CPU time 112.57 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 208008 kb
Host smart-4c7b01f1-3788-49da-be85-b31af84c29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258287967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.4258287967
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3585341424
Short name T888
Test name
Test status
Simulation time 22367418892 ps
CPU time 275.19 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:33:08 PM PDT 24
Peak memory 199976 kb
Host smart-48f442e3-fcb6-48c5-bd3b-d5653ffccee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585341424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3585341424
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1093687916
Short name T414
Test name
Test status
Simulation time 2870030766 ps
CPU time 4.96 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:28:32 PM PDT 24
Peak memory 199084 kb
Host smart-a81f7395-720a-4a0f-a5ee-05ef803ed653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093687916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1093687916
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1954644212
Short name T1128
Test name
Test status
Simulation time 126661000173 ps
CPU time 60.21 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:29:33 PM PDT 24
Peak memory 199836 kb
Host smart-89d88f6d-9c26-4c63-8f44-e8b2fd424536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954644212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1954644212
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1670912604
Short name T965
Test name
Test status
Simulation time 823475581 ps
CPU time 1.72 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:36 PM PDT 24
Peak memory 195412 kb
Host smart-7e46cae6-3932-4d84-83d1-43eaa173a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670912604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1670912604
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2620563781
Short name T395
Test name
Test status
Simulation time 5583359627 ps
CPU time 4.17 seconds
Started Jul 24 04:28:29 PM PDT 24
Finished Jul 24 04:28:34 PM PDT 24
Peak memory 199976 kb
Host smart-d49406f0-5207-413c-944a-d3a063f51fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620563781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2620563781
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2852723963
Short name T1085
Test name
Test status
Simulation time 366880701078 ps
CPU time 1406.42 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:52:00 PM PDT 24
Peak memory 200000 kb
Host smart-781a46ef-cde1-4224-8331-30683c2a51df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852723963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2852723963
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2658823413
Short name T543
Test name
Test status
Simulation time 56230133063 ps
CPU time 1192.81 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:48:28 PM PDT 24
Peak memory 216704 kb
Host smart-99844f3f-b0b8-4a54-928d-84d2ca921bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658823413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2658823413
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.4151724435
Short name T946
Test name
Test status
Simulation time 7393752108 ps
CPU time 8.33 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:28:42 PM PDT 24
Peak memory 199432 kb
Host smart-1576eb00-7981-47bf-8af6-c2cfd7faa61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151724435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.4151724435
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2482261577
Short name T305
Test name
Test status
Simulation time 149358462501 ps
CPU time 96.33 seconds
Started Jul 24 04:28:27 PM PDT 24
Finished Jul 24 04:30:04 PM PDT 24
Peak memory 199952 kb
Host smart-8b936978-82a8-47a9-8534-60e696f33487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482261577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2482261577
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1503673625
Short name T23
Test name
Test status
Simulation time 18185780 ps
CPU time 0.54 seconds
Started Jul 24 04:28:38 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 194856 kb
Host smart-228e8410-e30b-47b8-bd94-87a12ea5ba2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503673625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1503673625
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1644399877
Short name T136
Test name
Test status
Simulation time 87100207861 ps
CPU time 38.33 seconds
Started Jul 24 04:28:32 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 199940 kb
Host smart-f0cbce9c-3552-4e15-b814-a54ab3583575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644399877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1644399877
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3494668780
Short name T857
Test name
Test status
Simulation time 25261992263 ps
CPU time 31.99 seconds
Started Jul 24 04:28:35 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199820 kb
Host smart-f3afd11c-8beb-49a5-b034-42ed5f193bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494668780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3494668780
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3776751289
Short name T117
Test name
Test status
Simulation time 16019738815 ps
CPU time 13.62 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:28:47 PM PDT 24
Peak memory 200028 kb
Host smart-caf8339f-7848-4f47-adcb-9e42823d33ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776751289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3776751289
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2554102228
Short name T757
Test name
Test status
Simulation time 34305369407 ps
CPU time 48.12 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 199852 kb
Host smart-bbb1be71-e99c-4792-9453-421ad09d6072
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554102228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2554102228
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3111287074
Short name T316
Test name
Test status
Simulation time 36720511706 ps
CPU time 37.42 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 199852 kb
Host smart-9d435327-8b12-4e1d-9716-4b29d3385f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111287074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3111287074
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3093078010
Short name T374
Test name
Test status
Simulation time 7102008325 ps
CPU time 10.75 seconds
Started Jul 24 04:28:33 PM PDT 24
Finished Jul 24 04:28:45 PM PDT 24
Peak memory 199072 kb
Host smart-9b5d0757-32f3-4890-8871-dc8af39ad7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093078010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3093078010
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1802432618
Short name T876
Test name
Test status
Simulation time 130552460651 ps
CPU time 49.02 seconds
Started Jul 24 04:28:35 PM PDT 24
Finished Jul 24 04:29:24 PM PDT 24
Peak memory 198840 kb
Host smart-8f308d1f-c5d3-4e86-be1f-4763eb917bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802432618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1802432618
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2975215140
Short name T445
Test name
Test status
Simulation time 16815826956 ps
CPU time 58.08 seconds
Started Jul 24 04:28:35 PM PDT 24
Finished Jul 24 04:29:33 PM PDT 24
Peak memory 199852 kb
Host smart-4ad1e103-4864-4d41-a9fd-8c7888a1f39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975215140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2975215140
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.374724671
Short name T812
Test name
Test status
Simulation time 2343818422 ps
CPU time 15.67 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:50 PM PDT 24
Peak memory 198864 kb
Host smart-d5054644-037a-4822-bab9-e9197d63779a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374724671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.374724671
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2436607812
Short name T1015
Test name
Test status
Simulation time 88126940783 ps
CPU time 21.3 seconds
Started Jul 24 04:28:35 PM PDT 24
Finished Jul 24 04:28:57 PM PDT 24
Peak memory 199992 kb
Host smart-de7c1a98-676d-45cf-8a0c-e29b3d452721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436607812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2436607812
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.4245413880
Short name T698
Test name
Test status
Simulation time 3990626467 ps
CPU time 6.24 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 196488 kb
Host smart-d52150cd-b709-4a4e-8bb5-f78a28cba326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245413880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.4245413880
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1858998464
Short name T482
Test name
Test status
Simulation time 877100168 ps
CPU time 1.75 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:36 PM PDT 24
Peak memory 199652 kb
Host smart-84ad2e2f-c831-41c5-bb38-7bedb6d4d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858998464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1858998464
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2504756875
Short name T1096
Test name
Test status
Simulation time 170815781722 ps
CPU time 261.49 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:32:56 PM PDT 24
Peak memory 199980 kb
Host smart-e9314917-98a2-46ec-86da-a8e1f86201b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504756875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2504756875
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1642140970
Short name T690
Test name
Test status
Simulation time 1753986799 ps
CPU time 2 seconds
Started Jul 24 04:28:34 PM PDT 24
Finished Jul 24 04:28:36 PM PDT 24
Peak memory 198856 kb
Host smart-2d50ffd8-ba95-4abc-95d4-93ca28e6cebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642140970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1642140970
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.928915648
Short name T312
Test name
Test status
Simulation time 10036203659 ps
CPU time 14.31 seconds
Started Jul 24 04:28:35 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199684 kb
Host smart-793e03c0-db5b-4859-9f38-4d9729bc0135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928915648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.928915648
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2829797099
Short name T1157
Test name
Test status
Simulation time 31548362 ps
CPU time 0.53 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:43 PM PDT 24
Peak memory 194340 kb
Host smart-e885ae25-4491-4f10-b5a1-c3faa4b3e661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829797099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2829797099
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2129571877
Short name T869
Test name
Test status
Simulation time 38464477158 ps
CPU time 63.1 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:29:42 PM PDT 24
Peak memory 199932 kb
Host smart-aafb4ac1-5e87-41dd-aa8a-927a6ef2244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129571877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2129571877
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4179267292
Short name T169
Test name
Test status
Simulation time 215619452659 ps
CPU time 209.43 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 199872 kb
Host smart-7e126615-0023-4c21-8a60-4e135f780ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179267292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4179267292
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1852141067
Short name T462
Test name
Test status
Simulation time 66251047174 ps
CPU time 32.34 seconds
Started Jul 24 04:28:40 PM PDT 24
Finished Jul 24 04:29:13 PM PDT 24
Peak memory 199996 kb
Host smart-2d39db75-6df4-4c79-87ef-977c05090530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852141067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1852141067
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2287896438
Short name T1152
Test name
Test status
Simulation time 81743518802 ps
CPU time 705.22 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:40:25 PM PDT 24
Peak memory 200032 kb
Host smart-e342f6bf-45b6-46a1-8e54-c37fd197dcea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287896438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2287896438
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.836089552
Short name T601
Test name
Test status
Simulation time 5582909945 ps
CPU time 6.53 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:28:46 PM PDT 24
Peak memory 198536 kb
Host smart-08aa02ce-bed8-4d10-8b3d-ab61961e2d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836089552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.836089552
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2997584966
Short name T46
Test name
Test status
Simulation time 45867443909 ps
CPU time 43.22 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:29:27 PM PDT 24
Peak memory 198940 kb
Host smart-5727c9ca-8f28-4517-9a81-ff5a93f324b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997584966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2997584966
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3037486530
Short name T709
Test name
Test status
Simulation time 19569482752 ps
CPU time 1191.83 seconds
Started Jul 24 04:28:40 PM PDT 24
Finished Jul 24 04:48:32 PM PDT 24
Peak memory 199928 kb
Host smart-d7567756-3b1d-4025-b8bd-bd7877065b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037486530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3037486530
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2979930318
Short name T633
Test name
Test status
Simulation time 1605942341 ps
CPU time 1.92 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:44 PM PDT 24
Peak memory 198348 kb
Host smart-9e216df8-43b7-4cc7-8711-6de0b6ebbf21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979930318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2979930318
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.645290825
Short name T43
Test name
Test status
Simulation time 43520195488 ps
CPU time 51.64 seconds
Started Jul 24 04:28:38 PM PDT 24
Finished Jul 24 04:29:30 PM PDT 24
Peak memory 200032 kb
Host smart-5e4764f5-97f3-4cd8-9a04-65b818824a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645290825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.645290825
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.98401946
Short name T1156
Test name
Test status
Simulation time 2801376293 ps
CPU time 1.3 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:44 PM PDT 24
Peak memory 196300 kb
Host smart-a48cd5b7-7d40-4dbb-bfa4-dde4adf0edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98401946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.98401946
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1071396082
Short name T541
Test name
Test status
Simulation time 153240495 ps
CPU time 0.76 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 197064 kb
Host smart-bbc68cf9-e4ab-4dfa-b12f-20cd485ed6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071396082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1071396082
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.331405061
Short name T833
Test name
Test status
Simulation time 51449327880 ps
CPU time 11.21 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:28:50 PM PDT 24
Peak memory 199864 kb
Host smart-f45f9545-0ccd-4fdf-a54f-e67d6c1a7536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331405061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.331405061
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2755438014
Short name T424
Test name
Test status
Simulation time 90357958159 ps
CPU time 253.52 seconds
Started Jul 24 04:28:40 PM PDT 24
Finished Jul 24 04:32:53 PM PDT 24
Peak memory 216580 kb
Host smart-c86d729a-da7f-4e97-84b5-4b5d0f381c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755438014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2755438014
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3584347580
Short name T651
Test name
Test status
Simulation time 9296474371 ps
CPU time 10.24 seconds
Started Jul 24 04:28:40 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 199964 kb
Host smart-7ccaaa0c-ef72-4106-9252-aca702923e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584347580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3584347580
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.439315121
Short name T717
Test name
Test status
Simulation time 53355243629 ps
CPU time 11.53 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:54 PM PDT 24
Peak memory 199692 kb
Host smart-389c3dbf-2723-46fa-9041-4778bc5738cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439315121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.439315121
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1998999274
Short name T353
Test name
Test status
Simulation time 82971794 ps
CPU time 0.54 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 195668 kb
Host smart-99244563-d8a9-41a3-8216-25535d659205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998999274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1998999274
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2859900936
Short name T570
Test name
Test status
Simulation time 44663317129 ps
CPU time 59.93 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:29:44 PM PDT 24
Peak memory 199888 kb
Host smart-cd2da83d-4389-4176-9b93-ce7bc411f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859900936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2859900936
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.462173448
Short name T655
Test name
Test status
Simulation time 48136979397 ps
CPU time 38.52 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:29:23 PM PDT 24
Peak memory 200016 kb
Host smart-b8fd9e27-1b60-4cae-b041-901a975b4e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462173448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.462173448
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.724530393
Short name T219
Test name
Test status
Simulation time 85547317691 ps
CPU time 35.49 seconds
Started Jul 24 04:28:43 PM PDT 24
Finished Jul 24 04:29:18 PM PDT 24
Peak memory 200008 kb
Host smart-4bfea58a-c889-40ec-916e-5cba92eeb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724530393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.724530393
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2213379517
Short name T834
Test name
Test status
Simulation time 163364039155 ps
CPU time 63.56 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 199960 kb
Host smart-852044e5-c063-48be-a653-6424f1bb0ca1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213379517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2213379517
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4241550256
Short name T1081
Test name
Test status
Simulation time 97069373057 ps
CPU time 505.57 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:37:10 PM PDT 24
Peak memory 200000 kb
Host smart-963ce932-36cc-4b09-80f2-6b4ee285fd54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241550256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4241550256
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2164907670
Short name T560
Test name
Test status
Simulation time 7307316272 ps
CPU time 2.76 seconds
Started Jul 24 04:28:45 PM PDT 24
Finished Jul 24 04:28:48 PM PDT 24
Peak memory 199192 kb
Host smart-fa1a1574-e1c3-40ca-8b31-ed994e31b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164907670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2164907670
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1704692622
Short name T1127
Test name
Test status
Simulation time 9031273035 ps
CPU time 6.51 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199916 kb
Host smart-a4d7e266-e191-4319-b9d7-37c2d25298ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704692622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1704692622
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1590326485
Short name T405
Test name
Test status
Simulation time 8439877932 ps
CPU time 245.64 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:32:48 PM PDT 24
Peak memory 199880 kb
Host smart-85682424-9d53-4dde-b5de-52fb90a64927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590326485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1590326485
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.922282714
Short name T657
Test name
Test status
Simulation time 4987481457 ps
CPU time 39 seconds
Started Jul 24 04:28:43 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 198704 kb
Host smart-b555c099-32ee-402e-a2be-ba8c5755a6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922282714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.922282714
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3762712634
Short name T427
Test name
Test status
Simulation time 25917060757 ps
CPU time 41.27 seconds
Started Jul 24 04:28:44 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199464 kb
Host smart-aff593b7-119c-417c-8964-8fbfd6519553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762712634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3762712634
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3730874223
Short name T274
Test name
Test status
Simulation time 38741772488 ps
CPU time 31.58 seconds
Started Jul 24 04:28:43 PM PDT 24
Finished Jul 24 04:29:15 PM PDT 24
Peak memory 196076 kb
Host smart-c0517caf-e5e1-4f83-b1ca-7742d6a170ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730874223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3730874223
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3282946315
Short name T398
Test name
Test status
Simulation time 450034685 ps
CPU time 1.89 seconds
Started Jul 24 04:28:40 PM PDT 24
Finished Jul 24 04:28:42 PM PDT 24
Peak memory 199800 kb
Host smart-75935ae0-645d-4ba7-8e87-3bee96f395ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282946315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3282946315
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2585473590
Short name T293
Test name
Test status
Simulation time 187335397408 ps
CPU time 397.9 seconds
Started Jul 24 04:28:48 PM PDT 24
Finished Jul 24 04:35:26 PM PDT 24
Peak memory 200024 kb
Host smart-14a9002f-a27c-444e-9e59-139ecbe26acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585473590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2585473590
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3951510489
Short name T11
Test name
Test status
Simulation time 892164550 ps
CPU time 1.51 seconds
Started Jul 24 04:28:42 PM PDT 24
Finished Jul 24 04:28:44 PM PDT 24
Peak memory 198524 kb
Host smart-07264092-c924-4a79-b476-feabb7162cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951510489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3951510489
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1156269980
Short name T390
Test name
Test status
Simulation time 893624338 ps
CPU time 0.88 seconds
Started Jul 24 04:28:39 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 197656 kb
Host smart-6f3e6cdb-89f1-4750-9a57-80d393e35cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156269980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1156269980
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3090421679
Short name T1090
Test name
Test status
Simulation time 107928308 ps
CPU time 0.51 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:28:56 PM PDT 24
Peak memory 195448 kb
Host smart-ea9520d2-f0fe-48cf-894f-876c3b3cd6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090421679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3090421679
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.593121186
Short name T124
Test name
Test status
Simulation time 225232270373 ps
CPU time 53.18 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:29:43 PM PDT 24
Peak memory 200016 kb
Host smart-372e606c-d560-49e3-89a8-9e0121e1b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593121186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.593121186
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.552265810
Short name T1140
Test name
Test status
Simulation time 100281182865 ps
CPU time 163.18 seconds
Started Jul 24 04:28:51 PM PDT 24
Finished Jul 24 04:31:34 PM PDT 24
Peak memory 199984 kb
Host smart-ced318a6-4554-4f98-8d32-cd2049799630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552265810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.552265810
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.178684304
Short name T1029
Test name
Test status
Simulation time 44420255663 ps
CPU time 46.73 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 200412 kb
Host smart-2913214c-f806-4868-84a5-ad79f69d1b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178684304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.178684304
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2057472304
Short name T1108
Test name
Test status
Simulation time 42276886332 ps
CPU time 57.17 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 198936 kb
Host smart-de0a3358-d92b-4d3d-a15f-9797acee08c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057472304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2057472304
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2033675033
Short name T39
Test name
Test status
Simulation time 81260725654 ps
CPU time 382.51 seconds
Started Jul 24 04:28:53 PM PDT 24
Finished Jul 24 04:35:16 PM PDT 24
Peak memory 199884 kb
Host smart-babe7347-efcf-4670-929b-a57662bc5025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033675033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2033675033
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3587833150
Short name T840
Test name
Test status
Simulation time 2225129383 ps
CPU time 3.81 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:28:54 PM PDT 24
Peak memory 196924 kb
Host smart-3b596c81-308c-4ec9-bf26-8ad104b284fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587833150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3587833150
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1697031411
Short name T1123
Test name
Test status
Simulation time 79983022269 ps
CPU time 36.41 seconds
Started Jul 24 04:28:52 PM PDT 24
Finished Jul 24 04:29:28 PM PDT 24
Peak memory 198764 kb
Host smart-e7f485f9-df9f-4910-bb8c-3a51ba7d2cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697031411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1697031411
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4251695272
Short name T909
Test name
Test status
Simulation time 8441325108 ps
CPU time 54.58 seconds
Started Jul 24 04:28:58 PM PDT 24
Finished Jul 24 04:29:52 PM PDT 24
Peak memory 199948 kb
Host smart-3293c079-334d-4df0-ab46-4584f8ea146c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251695272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4251695272
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2496753249
Short name T1055
Test name
Test status
Simulation time 2327321382 ps
CPU time 3.8 seconds
Started Jul 24 04:28:47 PM PDT 24
Finished Jul 24 04:28:51 PM PDT 24
Peak memory 197896 kb
Host smart-a73fcd31-beea-4e1f-a0de-402e4978a8e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496753249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2496753249
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3668590980
Short name T583
Test name
Test status
Simulation time 37578543213 ps
CPU time 18.1 seconds
Started Jul 24 04:28:49 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199876 kb
Host smart-fa76843d-abb9-4ab8-acdb-fd5e29419b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668590980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3668590980
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3286471080
Short name T356
Test name
Test status
Simulation time 4357960182 ps
CPU time 1.14 seconds
Started Jul 24 04:28:49 PM PDT 24
Finished Jul 24 04:28:50 PM PDT 24
Peak memory 196428 kb
Host smart-f075d9a3-3632-471a-9175-8f9d3a2d1323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286471080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3286471080
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2383784783
Short name T346
Test name
Test status
Simulation time 980981380 ps
CPU time 1.31 seconds
Started Jul 24 04:28:54 PM PDT 24
Finished Jul 24 04:28:55 PM PDT 24
Peak memory 199744 kb
Host smart-5766db63-ed19-41a1-9f25-d612077603dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383784783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2383784783
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.583356522
Short name T1034
Test name
Test status
Simulation time 247663486643 ps
CPU time 121.47 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:30:56 PM PDT 24
Peak memory 200068 kb
Host smart-0f27ef8a-5652-45e3-97aa-7bece0f4fdc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583356522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.583356522
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2971770256
Short name T768
Test name
Test status
Simulation time 28093325049 ps
CPU time 593.74 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:38:49 PM PDT 24
Peak memory 216696 kb
Host smart-e89e235e-c7ea-4759-93be-419b4a0eb741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971770256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2971770256
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2914653744
Short name T881
Test name
Test status
Simulation time 6868238361 ps
CPU time 23.22 seconds
Started Jul 24 04:28:52 PM PDT 24
Finished Jul 24 04:29:15 PM PDT 24
Peak memory 199832 kb
Host smart-dca84f3c-5d0f-4591-8e32-a032918b8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914653744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2914653744
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1907087340
Short name T644
Test name
Test status
Simulation time 132149467993 ps
CPU time 48.22 seconds
Started Jul 24 04:28:50 PM PDT 24
Finished Jul 24 04:29:38 PM PDT 24
Peak memory 199916 kb
Host smart-5b2cd105-b920-4afa-8153-1fcc5a1d299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907087340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1907087340
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.722585430
Short name T1063
Test name
Test status
Simulation time 12347844 ps
CPU time 0.69 seconds
Started Jul 24 04:29:02 PM PDT 24
Finished Jul 24 04:29:03 PM PDT 24
Peak memory 195796 kb
Host smart-49978965-44a0-469d-bc4c-a4d6fe728c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722585430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.722585430
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.344624765
Short name T865
Test name
Test status
Simulation time 19127484638 ps
CPU time 19.55 seconds
Started Jul 24 04:28:58 PM PDT 24
Finished Jul 24 04:29:18 PM PDT 24
Peak memory 200016 kb
Host smart-dad16cd9-5d84-437b-9a6b-fa4de5f45450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344624765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.344624765
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1500353205
Short name T422
Test name
Test status
Simulation time 11678023303 ps
CPU time 18.65 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:29:14 PM PDT 24
Peak memory 199852 kb
Host smart-f70452c0-5b9d-4114-be4e-84da42545152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500353205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1500353205
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2477210378
Short name T326
Test name
Test status
Simulation time 18542961175 ps
CPU time 8.31 seconds
Started Jul 24 04:28:58 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 199888 kb
Host smart-1698ff00-1e2f-490b-87b1-a005a2453908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477210378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2477210378
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1304724572
Short name T606
Test name
Test status
Simulation time 17613798429 ps
CPU time 29.08 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199972 kb
Host smart-fab394cf-bc62-4671-a0a2-928dc56409f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304724572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1304724572
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4029597337
Short name T866
Test name
Test status
Simulation time 37393903911 ps
CPU time 127.77 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:31:03 PM PDT 24
Peak memory 200020 kb
Host smart-6a66f50c-7602-4563-a687-86e34c29116d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029597337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4029597337
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1390291431
Short name T871
Test name
Test status
Simulation time 5574519821 ps
CPU time 2.8 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:28:59 PM PDT 24
Peak memory 198640 kb
Host smart-d115f1ee-0681-40b4-b03a-c7d96297043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390291431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1390291431
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1421747638
Short name T275
Test name
Test status
Simulation time 53264938774 ps
CPU time 43.13 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:29:39 PM PDT 24
Peak memory 200172 kb
Host smart-bbcadc60-755a-4470-873b-48c243a24980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421747638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1421747638
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.927509909
Short name T1072
Test name
Test status
Simulation time 6128045757 ps
CPU time 249.74 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:33:05 PM PDT 24
Peak memory 200020 kb
Host smart-3c99709e-7226-45b9-a81e-5534c265a458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927509909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.927509909
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.451166384
Short name T1166
Test name
Test status
Simulation time 1700257335 ps
CPU time 3.44 seconds
Started Jul 24 04:28:57 PM PDT 24
Finished Jul 24 04:29:00 PM PDT 24
Peak memory 198808 kb
Host smart-c0d0e119-ae14-4bb8-b996-e2f86228e23c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451166384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.451166384
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1740226810
Short name T377
Test name
Test status
Simulation time 41586286096 ps
CPU time 15.76 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 199628 kb
Host smart-ac980152-b4eb-48c7-bfca-a9d42711954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740226810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1740226810
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3824039336
Short name T1070
Test name
Test status
Simulation time 4357711288 ps
CPU time 7.19 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:29:03 PM PDT 24
Peak memory 196308 kb
Host smart-7498b9d9-bd0d-44e3-9df1-252abd4128ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824039336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3824039336
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1390530826
Short name T616
Test name
Test status
Simulation time 5465053577 ps
CPU time 10.24 seconds
Started Jul 24 04:28:59 PM PDT 24
Finished Jul 24 04:29:09 PM PDT 24
Peak memory 199688 kb
Host smart-339e85d9-5cfb-4caf-9e9e-8ed1c9b54243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390530826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1390530826
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3615358537
Short name T448
Test name
Test status
Simulation time 242527941441 ps
CPU time 1081.97 seconds
Started Jul 24 04:28:54 PM PDT 24
Finished Jul 24 04:46:57 PM PDT 24
Peak memory 199840 kb
Host smart-76452ba0-8fc2-4007-bb41-1842b07f9b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615358537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3615358537
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4137513684
Short name T977
Test name
Test status
Simulation time 155171470768 ps
CPU time 1432.87 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:52:48 PM PDT 24
Peak memory 225184 kb
Host smart-a0f5372d-cbe0-40b4-bd89-3cf5fc592197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137513684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4137513684
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.993131775
Short name T1084
Test name
Test status
Simulation time 6059147963 ps
CPU time 21.88 seconds
Started Jul 24 04:28:55 PM PDT 24
Finished Jul 24 04:29:17 PM PDT 24
Peak memory 199736 kb
Host smart-281aebe9-4491-4edf-a9c7-14f86c042f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993131775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.993131775
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2152369665
Short name T301
Test name
Test status
Simulation time 29190898336 ps
CPU time 75.2 seconds
Started Jul 24 04:28:56 PM PDT 24
Finished Jul 24 04:30:11 PM PDT 24
Peak memory 199896 kb
Host smart-7ebba429-4835-465f-acd5-7b6975eea774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152369665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2152369665
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.283970841
Short name T839
Test name
Test status
Simulation time 40302767 ps
CPU time 0.57 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:26:24 PM PDT 24
Peak memory 195444 kb
Host smart-4ae09e2b-b923-4069-b92c-f35971177952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283970841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.283970841
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3069013502
Short name T307
Test name
Test status
Simulation time 102458950886 ps
CPU time 245.58 seconds
Started Jul 24 04:26:17 PM PDT 24
Finished Jul 24 04:30:23 PM PDT 24
Peak memory 199996 kb
Host smart-bac0258f-5a5e-40e1-83f7-f1c066124cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069013502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3069013502
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3063544523
Short name T529
Test name
Test status
Simulation time 10569953617 ps
CPU time 10.66 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:26:34 PM PDT 24
Peak memory 199704 kb
Host smart-c94efbcb-26d2-44f9-ac7e-ba4bb59e2454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063544523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3063544523
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2726142454
Short name T210
Test name
Test status
Simulation time 72633234833 ps
CPU time 115.53 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:29:33 PM PDT 24
Peak memory 197364 kb
Host smart-f8fb5b2e-bf09-4362-80a6-5c989386c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726142454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2726142454
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.640521997
Short name T361
Test name
Test status
Simulation time 14008856415 ps
CPU time 4.5 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:26:26 PM PDT 24
Peak memory 199688 kb
Host smart-4db9cbb3-6333-4ad7-b3f6-60ea7d8d5b90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640521997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.640521997
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3277123103
Short name T800
Test name
Test status
Simulation time 108543579391 ps
CPU time 386.73 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:32:48 PM PDT 24
Peak memory 200036 kb
Host smart-ae0f02a5-1b46-4606-84a3-c8f29712d23f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277123103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3277123103
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.848394008
Short name T6
Test name
Test status
Simulation time 12574587649 ps
CPU time 9.84 seconds
Started Jul 24 04:26:24 PM PDT 24
Finished Jul 24 04:26:34 PM PDT 24
Peak memory 199168 kb
Host smart-b4da8b83-956d-4c47-a291-90bf23eaafa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848394008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.848394008
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2033554389
Short name T409
Test name
Test status
Simulation time 86778850535 ps
CPU time 158.24 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 200036 kb
Host smart-447da17a-e160-4b48-abc1-cdf8e69f545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033554389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2033554389
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3808001546
Short name T743
Test name
Test status
Simulation time 11283840224 ps
CPU time 310.06 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:31:41 PM PDT 24
Peak memory 199960 kb
Host smart-5be76bb3-727b-4be3-989d-09fc92b8b570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808001546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3808001546
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1597037974
Short name T383
Test name
Test status
Simulation time 5668201317 ps
CPU time 42.44 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 198572 kb
Host smart-9ac42184-5d7a-4a78-a54f-161efdc5b989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597037974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1597037974
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3740123829
Short name T154
Test name
Test status
Simulation time 187166585067 ps
CPU time 413.82 seconds
Started Jul 24 04:26:20 PM PDT 24
Finished Jul 24 04:33:14 PM PDT 24
Peak memory 200052 kb
Host smart-99dd1381-ee3e-45ad-975d-657c71e310a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740123829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3740123829
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2734794208
Short name T295
Test name
Test status
Simulation time 1698565356 ps
CPU time 3.04 seconds
Started Jul 24 04:26:26 PM PDT 24
Finished Jul 24 04:26:30 PM PDT 24
Peak memory 195612 kb
Host smart-7a8f3c69-30f8-4546-b123-09d258b1033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734794208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2734794208
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1326492942
Short name T86
Test name
Test status
Simulation time 125449771 ps
CPU time 0.74 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:26:24 PM PDT 24
Peak memory 218092 kb
Host smart-1d8eb06b-a2c3-4390-b055-fbc0fcebc560
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326492942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1326492942
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.565290737
Short name T969
Test name
Test status
Simulation time 272279646 ps
CPU time 0.96 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 198892 kb
Host smart-503a839d-8eda-4ab5-9410-7bbc0e4b85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565290737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.565290737
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4129764756
Short name T744
Test name
Test status
Simulation time 110159768979 ps
CPU time 51.46 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:27:11 PM PDT 24
Peak memory 199964 kb
Host smart-2ac5f1b7-0c84-4ff6-bf43-848bce278a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129764756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4129764756
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2176702432
Short name T67
Test name
Test status
Simulation time 213122279949 ps
CPU time 1202.86 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:46:26 PM PDT 24
Peak memory 228872 kb
Host smart-0f51812a-ee2d-4df6-9019-d1b48a902499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176702432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2176702432
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.18158270
Short name T309
Test name
Test status
Simulation time 1941334938 ps
CPU time 1.9 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 198504 kb
Host smart-ee155475-4a3d-4a11-b27a-b61e539609d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18158270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.18158270
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1031241406
Short name T783
Test name
Test status
Simulation time 51855769703 ps
CPU time 162.01 seconds
Started Jul 24 04:26:20 PM PDT 24
Finished Jul 24 04:29:02 PM PDT 24
Peak memory 199836 kb
Host smart-46f94b1f-d9a2-411b-9361-2eddc0a4a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031241406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1031241406
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1801445619
Short name T915
Test name
Test status
Simulation time 10662289 ps
CPU time 0.57 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:01 PM PDT 24
Peak memory 195312 kb
Host smart-de94c4c4-38a8-49b0-9b7f-0e7e8f5f01be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801445619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1801445619
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.4292537120
Short name T464
Test name
Test status
Simulation time 20421791982 ps
CPU time 30.31 seconds
Started Jul 24 04:29:02 PM PDT 24
Finished Jul 24 04:29:32 PM PDT 24
Peak memory 199980 kb
Host smart-5318e81b-82df-4abf-991d-d11622c1c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292537120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4292537120
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1351699229
Short name T942
Test name
Test status
Simulation time 157180355134 ps
CPU time 115.04 seconds
Started Jul 24 04:29:04 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 200048 kb
Host smart-c4b41918-b2b3-4de3-887e-87fc32c80eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351699229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1351699229
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.349574685
Short name T752
Test name
Test status
Simulation time 118092317785 ps
CPU time 53.41 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:54 PM PDT 24
Peak memory 199996 kb
Host smart-b0eb47eb-acb5-44ff-88e4-8ddf1cb98a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349574685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.349574685
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3732933413
Short name T1143
Test name
Test status
Simulation time 23818839867 ps
CPU time 36.55 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 199444 kb
Host smart-5f2bdae9-3870-4653-b84e-55126696032b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732933413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3732933413
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.185179046
Short name T362
Test name
Test status
Simulation time 284444861905 ps
CPU time 109.24 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:30:49 PM PDT 24
Peak memory 199964 kb
Host smart-eda60bc9-8eb2-4265-b9bc-a634afc5e5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185179046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.185179046
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3992109956
Short name T859
Test name
Test status
Simulation time 9436107782 ps
CPU time 8.86 seconds
Started Jul 24 04:29:03 PM PDT 24
Finished Jul 24 04:29:12 PM PDT 24
Peak memory 199792 kb
Host smart-e1cb5935-bc37-4570-87f4-5314e42f1c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992109956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3992109956
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.4031616660
Short name T1129
Test name
Test status
Simulation time 6389356617 ps
CPU time 10.48 seconds
Started Jul 24 04:29:04 PM PDT 24
Finished Jul 24 04:29:15 PM PDT 24
Peak memory 199956 kb
Host smart-2353a7fe-73ac-416a-b3f6-d25805bf65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031616660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4031616660
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3464536210
Short name T959
Test name
Test status
Simulation time 3511558889 ps
CPU time 187.13 seconds
Started Jul 24 04:29:02 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 200076 kb
Host smart-a708c6b6-c1fc-4ec6-b0f4-f5c631aba399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464536210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3464536210
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1300468703
Short name T1004
Test name
Test status
Simulation time 1673818836 ps
CPU time 7.56 seconds
Started Jul 24 04:29:01 PM PDT 24
Finished Jul 24 04:29:09 PM PDT 24
Peak memory 198148 kb
Host smart-ea024801-b099-4d0e-b5f0-1ec7ba4eb543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300468703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1300468703
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2702804552
Short name T957
Test name
Test status
Simulation time 38350235328 ps
CPU time 41.54 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:42 PM PDT 24
Peak memory 199932 kb
Host smart-d30b6879-ebf1-42b8-aab5-595e4557e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702804552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2702804552
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2291375902
Short name T804
Test name
Test status
Simulation time 44363273433 ps
CPU time 72.58 seconds
Started Jul 24 04:29:02 PM PDT 24
Finished Jul 24 04:30:14 PM PDT 24
Peak memory 195864 kb
Host smart-9ecb3473-4e8b-468b-9256-58ebf5179282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291375902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2291375902
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1994171345
Short name T3
Test name
Test status
Simulation time 559739571 ps
CPU time 2.1 seconds
Started Jul 24 04:28:59 PM PDT 24
Finished Jul 24 04:29:02 PM PDT 24
Peak memory 198916 kb
Host smart-05418c16-8264-4c29-b69a-f1f37f60e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994171345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1994171345
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3342903170
Short name T410
Test name
Test status
Simulation time 230322462881 ps
CPU time 421.75 seconds
Started Jul 24 04:29:01 PM PDT 24
Finished Jul 24 04:36:03 PM PDT 24
Peak memory 216056 kb
Host smart-0c6759b0-280d-406e-bdab-63f4faf9b142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342903170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3342903170
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2944445341
Short name T1026
Test name
Test status
Simulation time 65930972120 ps
CPU time 407.35 seconds
Started Jul 24 04:29:02 PM PDT 24
Finished Jul 24 04:35:50 PM PDT 24
Peak memory 215596 kb
Host smart-014c64f8-9df8-4149-a7e3-afdadbd8205c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944445341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2944445341
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2558142344
Short name T582
Test name
Test status
Simulation time 7836258142 ps
CPU time 6.88 seconds
Started Jul 24 04:29:01 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 199996 kb
Host smart-58d7abea-215a-45b1-90d7-632ac4ba2b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558142344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2558142344
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2820757872
Short name T588
Test name
Test status
Simulation time 6136820365 ps
CPU time 8.77 seconds
Started Jul 24 04:29:01 PM PDT 24
Finished Jul 24 04:29:10 PM PDT 24
Peak memory 198868 kb
Host smart-ef87e07e-83f8-48b2-8ed2-9ba46dba2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820757872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2820757872
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3500297207
Short name T689
Test name
Test status
Simulation time 38502767 ps
CPU time 0.5 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 194764 kb
Host smart-539c0741-e122-4dbe-9eac-ea321895bec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500297207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3500297207
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2015764708
Short name T1001
Test name
Test status
Simulation time 20029317687 ps
CPU time 29.93 seconds
Started Jul 24 04:29:01 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 200008 kb
Host smart-bccb7846-821a-4e74-89fc-9c58a992cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015764708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2015764708
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3119501393
Short name T841
Test name
Test status
Simulation time 203032446001 ps
CPU time 189.24 seconds
Started Jul 24 04:29:08 PM PDT 24
Finished Jul 24 04:32:17 PM PDT 24
Peak memory 199836 kb
Host smart-e63d3fb2-4c4d-4c96-a7fd-7cba98384702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119501393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3119501393
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1084002119
Short name T192
Test name
Test status
Simulation time 48181514404 ps
CPU time 89.71 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:30:36 PM PDT 24
Peak memory 199936 kb
Host smart-a7899921-ed5b-4ec5-b6f6-b0df464db0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084002119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1084002119
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3129947393
Short name T691
Test name
Test status
Simulation time 31833445429 ps
CPU time 53.41 seconds
Started Jul 24 04:29:08 PM PDT 24
Finished Jul 24 04:30:02 PM PDT 24
Peak memory 198404 kb
Host smart-868ebcf4-bcc5-4390-a114-e6896f4755c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129947393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3129947393
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.824800212
Short name T891
Test name
Test status
Simulation time 99569015049 ps
CPU time 315.64 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:34:23 PM PDT 24
Peak memory 199904 kb
Host smart-37557d12-0ea7-41fb-b5a3-11712a7c57bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824800212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.824800212
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3510055378
Short name T809
Test name
Test status
Simulation time 3891654055 ps
CPU time 9.29 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:29:16 PM PDT 24
Peak memory 199436 kb
Host smart-0606a9c4-46a8-46cd-b0f2-0ee976def642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510055378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3510055378
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2662889837
Short name T1014
Test name
Test status
Simulation time 115107544205 ps
CPU time 54.99 seconds
Started Jul 24 04:29:09 PM PDT 24
Finished Jul 24 04:30:04 PM PDT 24
Peak memory 208320 kb
Host smart-3f1a1444-6bbf-404d-9bd4-b28f0749606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662889837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2662889837
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3576190784
Short name T1010
Test name
Test status
Simulation time 13733930921 ps
CPU time 136.49 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:31:27 PM PDT 24
Peak memory 199972 kb
Host smart-75aff183-e73a-4208-b664-7971b7ab39df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576190784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3576190784
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2463676476
Short name T927
Test name
Test status
Simulation time 4610129945 ps
CPU time 33.92 seconds
Started Jul 24 04:29:06 PM PDT 24
Finished Jul 24 04:29:40 PM PDT 24
Peak memory 198956 kb
Host smart-e7473aad-5bf5-462a-9500-427920cd2847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463676476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2463676476
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1557012111
Short name T165
Test name
Test status
Simulation time 88196998251 ps
CPU time 114.33 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 199968 kb
Host smart-655d13ff-546a-4805-8f09-94510df0f061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557012111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1557012111
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2494901555
Short name T546
Test name
Test status
Simulation time 34202482874 ps
CPU time 13.83 seconds
Started Jul 24 04:29:08 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 196112 kb
Host smart-015e2c0c-4a6c-44b6-bc2a-ad920510a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494901555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2494901555
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.733772869
Short name T676
Test name
Test status
Simulation time 722784439 ps
CPU time 2.28 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:02 PM PDT 24
Peak memory 198696 kb
Host smart-b04fb8b3-fa3c-4a3f-996f-20303cd2af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733772869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.733772869
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1855313532
Short name T208
Test name
Test status
Simulation time 105338964721 ps
CPU time 41.87 seconds
Started Jul 24 04:29:08 PM PDT 24
Finished Jul 24 04:29:50 PM PDT 24
Peak memory 199916 kb
Host smart-bb1a7822-eea7-4b30-b04d-1c9b03dc5151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855313532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1855313532
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4029898198
Short name T33
Test name
Test status
Simulation time 20820828188 ps
CPU time 184.85 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:32:15 PM PDT 24
Peak memory 215868 kb
Host smart-1624f217-e5cd-43ca-8c7f-3b7c271f08bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029898198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4029898198
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1140563591
Short name T667
Test name
Test status
Simulation time 7034881699 ps
CPU time 16.28 seconds
Started Jul 24 04:29:11 PM PDT 24
Finished Jul 24 04:29:27 PM PDT 24
Peak memory 199636 kb
Host smart-3872f011-0f35-46e6-9260-11c997de9af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140563591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1140563591
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2112036814
Short name T375
Test name
Test status
Simulation time 17752913754 ps
CPU time 8.1 seconds
Started Jul 24 04:29:00 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 199904 kb
Host smart-4c4c9840-2b38-4de9-ac4e-10bb3e5de2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112036814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2112036814
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3516487312
Short name T976
Test name
Test status
Simulation time 53829235 ps
CPU time 0.56 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:29:15 PM PDT 24
Peak memory 195400 kb
Host smart-de54559a-70ea-4c80-b33c-2cfddfcc9252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516487312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3516487312
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.968434432
Short name T144
Test name
Test status
Simulation time 32346309512 ps
CPU time 52.35 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:30:03 PM PDT 24
Peak memory 200064 kb
Host smart-3c74d890-ea93-4138-be66-2c3bd9c712bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968434432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.968434432
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1427411510
Short name T249
Test name
Test status
Simulation time 53364692956 ps
CPU time 44.85 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:29:52 PM PDT 24
Peak memory 199724 kb
Host smart-26342ac1-0b9a-48ce-b0bd-7cba022eb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427411510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1427411510
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3678896840
Short name T449
Test name
Test status
Simulation time 55207795070 ps
CPU time 25 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:29:35 PM PDT 24
Peak memory 200000 kb
Host smart-324234c3-8ad8-4006-a70d-25b24878eb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678896840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3678896840
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.4058122842
Short name T605
Test name
Test status
Simulation time 21831546163 ps
CPU time 8.55 seconds
Started Jul 24 04:29:09 PM PDT 24
Finished Jul 24 04:29:18 PM PDT 24
Peak memory 199956 kb
Host smart-f258b606-3bc2-4ae2-ab88-e15d338dd69d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058122842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4058122842
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2301020348
Short name T978
Test name
Test status
Simulation time 103501842746 ps
CPU time 131.98 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:31:27 PM PDT 24
Peak memory 200000 kb
Host smart-ea510c1d-0afc-426a-ba16-8567d86502be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301020348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2301020348
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1302532164
Short name T436
Test name
Test status
Simulation time 2105595924 ps
CPU time 2.53 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:29:16 PM PDT 24
Peak memory 197588 kb
Host smart-f2f30344-ad40-463b-ba9b-9b4c58585f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302532164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1302532164
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1794166756
Short name T476
Test name
Test status
Simulation time 53227810677 ps
CPU time 274.03 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:33:44 PM PDT 24
Peak memory 199256 kb
Host smart-72a33910-38e2-4783-a941-144cbea1e0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794166756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1794166756
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2846623978
Short name T861
Test name
Test status
Simulation time 11063332206 ps
CPU time 144.65 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:31:39 PM PDT 24
Peak memory 200072 kb
Host smart-69395d0e-075a-4b4b-887f-1ed76e9a440d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846623978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2846623978
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3141809813
Short name T842
Test name
Test status
Simulation time 3059235819 ps
CPU time 10.42 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:29:21 PM PDT 24
Peak memory 198952 kb
Host smart-42206cb3-b487-4dea-8133-105124c8df2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141809813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3141809813
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1253673981
Short name T756
Test name
Test status
Simulation time 20692816432 ps
CPU time 15.62 seconds
Started Jul 24 04:29:13 PM PDT 24
Finished Jul 24 04:29:28 PM PDT 24
Peak memory 199988 kb
Host smart-1dc610a7-29d1-452b-8439-4b37bcb8268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253673981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1253673981
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.947210201
Short name T96
Test name
Test status
Simulation time 69043943484 ps
CPU time 57.14 seconds
Started Jul 24 04:29:10 PM PDT 24
Finished Jul 24 04:30:07 PM PDT 24
Peak memory 195880 kb
Host smart-de5b4c31-35d7-4974-86c0-cef051030269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947210201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.947210201
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3961689339
Short name T555
Test name
Test status
Simulation time 283883658 ps
CPU time 1 seconds
Started Jul 24 04:29:07 PM PDT 24
Finished Jul 24 04:29:08 PM PDT 24
Peak memory 198576 kb
Host smart-4014a9e8-f555-40a6-81e1-695549cc7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961689339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3961689339
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1427939429
Short name T746
Test name
Test status
Simulation time 281527430406 ps
CPU time 253.34 seconds
Started Jul 24 04:29:13 PM PDT 24
Finished Jul 24 04:33:27 PM PDT 24
Peak memory 208364 kb
Host smart-0f815b0f-8f22-4286-b14f-0ff32f222d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427939429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1427939429
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3978714177
Short name T1013
Test name
Test status
Simulation time 213072346011 ps
CPU time 342.65 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:34:57 PM PDT 24
Peak memory 216396 kb
Host smart-c0b424d6-a7ce-4910-87b8-8014a01455e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978714177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3978714177
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.878294738
Short name T500
Test name
Test status
Simulation time 6741832826 ps
CPU time 9.39 seconds
Started Jul 24 04:29:13 PM PDT 24
Finished Jul 24 04:29:23 PM PDT 24
Peak memory 199980 kb
Host smart-4746d159-0897-4b28-aa5c-4348938a60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878294738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.878294738
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1747843258
Short name T289
Test name
Test status
Simulation time 61438456548 ps
CPU time 23.08 seconds
Started Jul 24 04:29:08 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 199940 kb
Host smart-2dc1c04b-2079-459b-be2d-169336671116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747843258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1747843258
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3037515582
Short name T510
Test name
Test status
Simulation time 12713047 ps
CPU time 0.54 seconds
Started Jul 24 04:29:20 PM PDT 24
Finished Jul 24 04:29:21 PM PDT 24
Peak memory 195064 kb
Host smart-9d942932-980f-4197-8ffd-cd0e997ee59e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037515582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3037515582
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3015457457
Short name T1036
Test name
Test status
Simulation time 183620455647 ps
CPU time 209.47 seconds
Started Jul 24 04:29:13 PM PDT 24
Finished Jul 24 04:32:43 PM PDT 24
Peak memory 199892 kb
Host smart-8a12146d-2415-40cc-94ad-18d58fd8f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015457457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3015457457
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3473227597
Short name T287
Test name
Test status
Simulation time 117370328919 ps
CPU time 43.98 seconds
Started Jul 24 04:29:15 PM PDT 24
Finished Jul 24 04:30:00 PM PDT 24
Peak memory 199900 kb
Host smart-d528ed3d-b0dd-4765-9fe1-1173cf25342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473227597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3473227597
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2472381256
Short name T590
Test name
Test status
Simulation time 27150951464 ps
CPU time 38.03 seconds
Started Jul 24 04:29:16 PM PDT 24
Finished Jul 24 04:29:54 PM PDT 24
Peak memory 199884 kb
Host smart-61c915c2-5a70-4e21-ae10-bf140ae3b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472381256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2472381256
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4203735154
Short name T481
Test name
Test status
Simulation time 57942694581 ps
CPU time 93.11 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:30:52 PM PDT 24
Peak memory 199920 kb
Host smart-83768e0f-c25e-4aaa-8978-a1edfb8c9a4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203735154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4203735154
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2351585401
Short name T284
Test name
Test status
Simulation time 97921813259 ps
CPU time 106.78 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 200168 kb
Host smart-a9868d11-a031-4465-860e-59a578a7b066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351585401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2351585401
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3684290534
Short name T1047
Test name
Test status
Simulation time 3830186714 ps
CPU time 8.76 seconds
Started Jul 24 04:29:16 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199868 kb
Host smart-d2091807-080c-4a41-8b02-7403a31b9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684290534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3684290534
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1406312011
Short name T754
Test name
Test status
Simulation time 68273177426 ps
CPU time 100.94 seconds
Started Jul 24 04:29:15 PM PDT 24
Finished Jul 24 04:30:57 PM PDT 24
Peak memory 198500 kb
Host smart-3c8f6829-6ddf-4db5-a81a-c4ff2fe141b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406312011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1406312011
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.249085701
Short name T527
Test name
Test status
Simulation time 10025277749 ps
CPU time 166.99 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:32:02 PM PDT 24
Peak memory 199928 kb
Host smart-b6b6b0f6-3e22-40d0-8226-c60170d22913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249085701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.249085701
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.278941972
Short name T713
Test name
Test status
Simulation time 6927705492 ps
CPU time 14.86 seconds
Started Jul 24 04:29:15 PM PDT 24
Finished Jul 24 04:29:30 PM PDT 24
Peak memory 198304 kb
Host smart-577ad6e3-3149-45af-b4f0-bf4f30a2bb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278941972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.278941972
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1083520583
Short name T1023
Test name
Test status
Simulation time 103647902903 ps
CPU time 38.1 seconds
Started Jul 24 04:29:12 PM PDT 24
Finished Jul 24 04:29:51 PM PDT 24
Peak memory 199824 kb
Host smart-bdbe1602-0ad3-4aab-9c35-20b9ce0f886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083520583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1083520583
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3909878481
Short name T613
Test name
Test status
Simulation time 41169072635 ps
CPU time 11.66 seconds
Started Jul 24 04:30:15 PM PDT 24
Finished Jul 24 04:30:27 PM PDT 24
Peak memory 195476 kb
Host smart-1b61e7d6-2f08-4b15-a24e-9d046f658281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909878481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3909878481
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.920602450
Short name T614
Test name
Test status
Simulation time 6287374242 ps
CPU time 7.84 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 199948 kb
Host smart-66ce5a3d-e90e-4c3c-8c6e-e5580a6982a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920602450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.920602450
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.290333522
Short name T1080
Test name
Test status
Simulation time 1053625043663 ps
CPU time 871.26 seconds
Started Jul 24 04:29:19 PM PDT 24
Finished Jul 24 04:43:50 PM PDT 24
Peak memory 216496 kb
Host smart-f3c2b69d-5b85-4976-8642-559ba64e0f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290333522 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.290333522
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1844450885
Short name T610
Test name
Test status
Simulation time 381175840 ps
CPU time 1.06 seconds
Started Jul 24 04:29:13 PM PDT 24
Finished Jul 24 04:29:14 PM PDT 24
Peak memory 198768 kb
Host smart-1aa3234c-864d-4eaa-9b1d-ec097b35c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844450885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1844450885
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.654231907
Short name T303
Test name
Test status
Simulation time 11694145887 ps
CPU time 10.79 seconds
Started Jul 24 04:29:14 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199808 kb
Host smart-191a3c63-426f-48d4-9885-ca5048fdb5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654231907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.654231907
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.305695777
Short name T660
Test name
Test status
Simulation time 40927977 ps
CPU time 0.54 seconds
Started Jul 24 04:29:19 PM PDT 24
Finished Jul 24 04:29:20 PM PDT 24
Peak memory 194688 kb
Host smart-cfe73704-cf63-4186-bb33-f55ce0c20793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305695777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.305695777
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2126333692
Short name T159
Test name
Test status
Simulation time 46330147205 ps
CPU time 10.83 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:29:28 PM PDT 24
Peak memory 199948 kb
Host smart-11c7d163-5d42-4557-b3cc-ba59cbfe42cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126333692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2126333692
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1596963303
Short name T311
Test name
Test status
Simulation time 32203109846 ps
CPU time 41.95 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:30:00 PM PDT 24
Peak memory 199928 kb
Host smart-f932897d-465c-4b63-b344-c2ed913b8a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596963303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1596963303
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.561390872
Short name T892
Test name
Test status
Simulation time 91133201978 ps
CPU time 162.62 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:32:01 PM PDT 24
Peak memory 199988 kb
Host smart-7f79e052-0ea6-47dd-b43f-c5878a7c4574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561390872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.561390872
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.727017734
Short name T244
Test name
Test status
Simulation time 34708872619 ps
CPU time 45.34 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:30:04 PM PDT 24
Peak memory 200020 kb
Host smart-ee1fe0a7-d568-4104-8b51-48cd4d6cb953
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727017734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.727017734
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.37605225
Short name T256
Test name
Test status
Simulation time 170242815043 ps
CPU time 396.6 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:35:55 PM PDT 24
Peak memory 199952 kb
Host smart-720d7ec2-46bd-486a-8a0b-ec88a35ec586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37605225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.37605225
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2689227334
Short name T472
Test name
Test status
Simulation time 8728554739 ps
CPU time 10.26 seconds
Started Jul 24 04:29:20 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 199956 kb
Host smart-a01a0786-0f65-43a7-94db-a013b2715978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689227334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2689227334
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2588359348
Short name T563
Test name
Test status
Simulation time 15586123702 ps
CPU time 13.92 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 197828 kb
Host smart-d90fdea5-252b-4179-8210-12c9dbc8f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588359348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2588359348
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.583371419
Short name T1076
Test name
Test status
Simulation time 30454066573 ps
CPU time 1677.2 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:57:16 PM PDT 24
Peak memory 199804 kb
Host smart-021d8a79-d653-44cb-93e7-77166c2fc218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583371419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.583371419
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3808916082
Short name T666
Test name
Test status
Simulation time 4495177499 ps
CPU time 6.98 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:29:24 PM PDT 24
Peak memory 197892 kb
Host smart-b34742d5-0071-4e67-b2bb-1bc2d41befde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808916082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3808916082
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.204512269
Short name T879
Test name
Test status
Simulation time 50070552033 ps
CPU time 22.39 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:46 PM PDT 24
Peak memory 199436 kb
Host smart-9ad6a9ca-b18d-4eab-b014-c691ceeec137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204512269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.204512269
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3651666744
Short name T719
Test name
Test status
Simulation time 4251788593 ps
CPU time 7.38 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 196312 kb
Host smart-050352e1-b5e7-4970-b815-a9a8e6a6fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651666744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3651666744
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1928669396
Short name T308
Test name
Test status
Simulation time 713860357 ps
CPU time 2.51 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:29:21 PM PDT 24
Peak memory 199524 kb
Host smart-9fd450f8-b2ed-489a-9714-c138d56c84b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928669396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1928669396
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.308364017
Short name T730
Test name
Test status
Simulation time 236710547504 ps
CPU time 756.2 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:41:54 PM PDT 24
Peak memory 199888 kb
Host smart-23f9d94d-ba26-47fd-95ee-bc6f1e202713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308364017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.308364017
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3057065533
Short name T1089
Test name
Test status
Simulation time 9864148563 ps
CPU time 117.72 seconds
Started Jul 24 04:29:19 PM PDT 24
Finished Jul 24 04:31:17 PM PDT 24
Peak memory 209412 kb
Host smart-897fded2-c0ce-444d-b2e2-d5119ea8ae8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057065533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3057065533
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3753930575
Short name T421
Test name
Test status
Simulation time 867675067 ps
CPU time 2.08 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:29:20 PM PDT 24
Peak memory 198716 kb
Host smart-afd056a9-a7a7-429e-95f1-d6b8c8bea872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753930575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3753930575
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2892029966
Short name T653
Test name
Test status
Simulation time 44486307801 ps
CPU time 13.42 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:29:31 PM PDT 24
Peak memory 198428 kb
Host smart-f0b85164-964d-400a-986b-1ef08c6b2905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892029966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2892029966
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3566841477
Short name T895
Test name
Test status
Simulation time 17108560 ps
CPU time 0.53 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 194324 kb
Host smart-cf4b56b5-6200-4402-89a8-1ff2bb319f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566841477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3566841477
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.564867200
Short name T131
Test name
Test status
Simulation time 69418637187 ps
CPU time 34.15 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 199988 kb
Host smart-88b59938-9fe6-4bd5-9fce-0f185643d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564867200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.564867200
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1661586309
Short name T851
Test name
Test status
Simulation time 185884749564 ps
CPU time 85.27 seconds
Started Jul 24 04:29:17 PM PDT 24
Finished Jul 24 04:30:42 PM PDT 24
Peak memory 199884 kb
Host smart-444e0dfb-ad36-463f-a190-e9c966bdd14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661586309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1661586309
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4222160215
Short name T180
Test name
Test status
Simulation time 34848614582 ps
CPU time 55.08 seconds
Started Jul 24 04:29:18 PM PDT 24
Finished Jul 24 04:30:13 PM PDT 24
Peak memory 199792 kb
Host smart-b801d154-250a-470b-a8d4-113e599f76b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222160215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4222160215
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1540728600
Short name T664
Test name
Test status
Simulation time 194554525495 ps
CPU time 114.2 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:31:18 PM PDT 24
Peak memory 199896 kb
Host smart-ee32bc44-959e-44e1-a5f9-2e0131049c07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540728600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1540728600
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3730071240
Short name T1163
Test name
Test status
Simulation time 111026489756 ps
CPU time 189.03 seconds
Started Jul 24 04:29:26 PM PDT 24
Finished Jul 24 04:32:35 PM PDT 24
Peak memory 199884 kb
Host smart-a09b56ce-0f90-45b4-a2f2-02f6723254fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730071240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3730071240
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.892031386
Short name T425
Test name
Test status
Simulation time 1052260709 ps
CPU time 2.08 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:27 PM PDT 24
Peak memory 195548 kb
Host smart-c2c02c0e-a009-4c2d-8570-f93cf5ef1e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892031386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.892031386
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1452146493
Short name T453
Test name
Test status
Simulation time 14447824192 ps
CPU time 12.81 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:38 PM PDT 24
Peak memory 200236 kb
Host smart-57329579-5e0a-49c2-b821-3e4c21c353f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452146493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1452146493
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3042104527
Short name T1142
Test name
Test status
Simulation time 5045997512 ps
CPU time 18.32 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:43 PM PDT 24
Peak memory 200000 kb
Host smart-91a0230f-1e34-4611-bb11-5132ea95aab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042104527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3042104527
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.81713341
Short name T2
Test name
Test status
Simulation time 2382945573 ps
CPU time 2.7 seconds
Started Jul 24 04:29:19 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 199024 kb
Host smart-0ef1d55a-5b28-46e2-afcf-5286f9d34eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81713341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.81713341
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2052426765
Short name T825
Test name
Test status
Simulation time 26916825050 ps
CPU time 6.52 seconds
Started Jul 24 04:29:25 PM PDT 24
Finished Jul 24 04:29:32 PM PDT 24
Peak memory 198356 kb
Host smart-3ff3f760-9abf-40ca-a2cc-9968e1702017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052426765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2052426765
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2427693506
Short name T454
Test name
Test status
Simulation time 1451858260 ps
CPU time 2.6 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 195640 kb
Host smart-3dd30b1b-be75-4ad9-bea7-23709b4ca500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427693506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2427693506
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.588797516
Short name T479
Test name
Test status
Simulation time 463772466 ps
CPU time 2.34 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 198828 kb
Host smart-ea9a38a8-6e0a-4588-8620-f14ed81a3a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588797516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.588797516
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2969725597
Short name T102
Test name
Test status
Simulation time 129340330066 ps
CPU time 167.24 seconds
Started Jul 24 04:29:26 PM PDT 24
Finished Jul 24 04:32:13 PM PDT 24
Peak memory 208312 kb
Host smart-18bdc582-7cc1-49bd-86ef-e09096bb5fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969725597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2969725597
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1931603047
Short name T1164
Test name
Test status
Simulation time 58825896254 ps
CPU time 875.03 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:43:59 PM PDT 24
Peak memory 216528 kb
Host smart-c7632caf-0b06-490b-be2c-73b270e6f90d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931603047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1931603047
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.315969582
Short name T278
Test name
Test status
Simulation time 823163882 ps
CPU time 1.22 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 199120 kb
Host smart-a24a522e-b998-469a-83d7-04d560d69011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315969582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.315969582
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3228761712
Short name T565
Test name
Test status
Simulation time 68061102677 ps
CPU time 105.57 seconds
Started Jul 24 04:29:19 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 199916 kb
Host smart-b0b4e5c6-9f53-45ad-8e58-0c39fb99dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228761712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3228761712
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1484507015
Short name T363
Test name
Test status
Simulation time 13348192 ps
CPU time 0.53 seconds
Started Jul 24 04:29:49 PM PDT 24
Finished Jul 24 04:29:50 PM PDT 24
Peak memory 195376 kb
Host smart-c3715ecb-4886-48ae-befe-e3452cd19514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484507015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1484507015
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3415625620
Short name T37
Test name
Test status
Simulation time 46355952508 ps
CPU time 80.08 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:30:44 PM PDT 24
Peak memory 200016 kb
Host smart-f01d12b2-60af-49b2-b362-83d2428ec49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415625620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3415625620
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1414208090
Short name T571
Test name
Test status
Simulation time 9525927547 ps
CPU time 13.38 seconds
Started Jul 24 04:29:25 PM PDT 24
Finished Jul 24 04:29:39 PM PDT 24
Peak memory 199992 kb
Host smart-ef4f65bd-1b99-43b8-8624-a4fd802c20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414208090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1414208090
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3449139347
Short name T201
Test name
Test status
Simulation time 292915229049 ps
CPU time 27.55 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:51 PM PDT 24
Peak memory 200060 kb
Host smart-e2817e86-3f55-4388-bac0-eb71d293d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449139347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3449139347
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3248883692
Short name T1017
Test name
Test status
Simulation time 5060767236 ps
CPU time 4.67 seconds
Started Jul 24 04:29:27 PM PDT 24
Finished Jul 24 04:29:32 PM PDT 24
Peak memory 196672 kb
Host smart-ddc944af-66fd-4845-9c48-f1d30fb34d9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248883692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3248883692
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.612397356
Short name T872
Test name
Test status
Simulation time 80676520525 ps
CPU time 282.27 seconds
Started Jul 24 04:29:30 PM PDT 24
Finished Jul 24 04:34:12 PM PDT 24
Peak memory 200020 kb
Host smart-25333a5b-68cf-4fe0-b6e4-fd1c71f5dbc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612397356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.612397356
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2917024696
Short name T348
Test name
Test status
Simulation time 70284982 ps
CPU time 0.61 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:29:29 PM PDT 24
Peak memory 195796 kb
Host smart-85a7b13e-56e3-41a8-8cb3-f9bb66f08ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917024696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2917024696
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2291836101
Short name T1075
Test name
Test status
Simulation time 112781821530 ps
CPU time 54.59 seconds
Started Jul 24 04:29:27 PM PDT 24
Finished Jul 24 04:30:21 PM PDT 24
Peak memory 208356 kb
Host smart-7d1023d8-1c1e-4f55-84e5-df78d60d7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291836101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2291836101
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.483024727
Short name T769
Test name
Test status
Simulation time 7964162264 ps
CPU time 81.94 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 199968 kb
Host smart-0cdbf9d4-7173-4c01-baf3-84e70c0e1d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483024727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.483024727
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2274010772
Short name T737
Test name
Test status
Simulation time 7470024872 ps
CPU time 15.32 seconds
Started Jul 24 04:29:23 PM PDT 24
Finished Jul 24 04:29:38 PM PDT 24
Peak memory 199248 kb
Host smart-b3f46090-f91a-4d03-89ee-24732ba46809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274010772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2274010772
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2411599664
Short name T607
Test name
Test status
Simulation time 41844151376 ps
CPU time 57.2 seconds
Started Jul 24 04:29:29 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 199960 kb
Host smart-80765060-e1e8-4486-a67b-e67d879d9d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411599664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2411599664
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3566583126
Short name T431
Test name
Test status
Simulation time 4490565736 ps
CPU time 2.11 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:29:30 PM PDT 24
Peak memory 196780 kb
Host smart-3baf3bd0-a8bc-43cc-b9e9-d1304d889c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566583126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3566583126
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2363118851
Short name T645
Test name
Test status
Simulation time 531781568 ps
CPU time 1.55 seconds
Started Jul 24 04:29:24 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 198960 kb
Host smart-b2f6031f-5c0e-4fc0-bdac-ac46a34de496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363118851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2363118851
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1194661583
Short name T112
Test name
Test status
Simulation time 120163368074 ps
CPU time 282.45 seconds
Started Jul 24 04:29:27 PM PDT 24
Finished Jul 24 04:34:10 PM PDT 24
Peak memory 199972 kb
Host smart-8e27614b-3cb9-4b63-8f9c-ded7d0e1a2b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194661583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1194661583
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.717838991
Short name T547
Test name
Test status
Simulation time 70400693985 ps
CPU time 927.45 seconds
Started Jul 24 04:29:29 PM PDT 24
Finished Jul 24 04:44:56 PM PDT 24
Peak memory 216460 kb
Host smart-8ce64141-dc12-4a8b-a3d1-5bfd4dd4ac34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717838991 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.717838991
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3758255336
Short name T533
Test name
Test status
Simulation time 6323937673 ps
CPU time 17.22 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:29:45 PM PDT 24
Peak memory 199356 kb
Host smart-af4d4ce4-a293-4487-bd41-7bfc12f64b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758255336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3758255336
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1089779636
Short name T418
Test name
Test status
Simulation time 20562437761 ps
CPU time 10.15 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:29:39 PM PDT 24
Peak memory 199972 kb
Host smart-e93aab79-3bec-4a8d-b8e2-42c40a787dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089779636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1089779636
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1167997294
Short name T672
Test name
Test status
Simulation time 33238803 ps
CPU time 0.57 seconds
Started Jul 24 04:29:41 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 195604 kb
Host smart-ebeb020e-4d45-44e2-96b7-b72a6880e4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167997294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1167997294
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3039692379
Short name T896
Test name
Test status
Simulation time 227406172435 ps
CPU time 308.07 seconds
Started Jul 24 04:29:33 PM PDT 24
Finished Jul 24 04:34:41 PM PDT 24
Peak memory 199792 kb
Host smart-5d55351c-55ca-44fe-9d65-4354e6abafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039692379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3039692379
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1777774080
Short name T863
Test name
Test status
Simulation time 23722820785 ps
CPU time 46.98 seconds
Started Jul 24 04:29:34 PM PDT 24
Finished Jul 24 04:30:21 PM PDT 24
Peak memory 199884 kb
Host smart-430d99a4-d61a-4be9-b831-4e4a9255a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777774080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1777774080
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.3726279245
Short name T426
Test name
Test status
Simulation time 51487911418 ps
CPU time 24.9 seconds
Started Jul 24 04:29:32 PM PDT 24
Finished Jul 24 04:29:57 PM PDT 24
Peak memory 199844 kb
Host smart-d6c4abd0-cdb7-46b0-ac35-7dfa8cae6d9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726279245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3726279245
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4023793382
Short name T849
Test name
Test status
Simulation time 135882346629 ps
CPU time 120.58 seconds
Started Jul 24 04:29:38 PM PDT 24
Finished Jul 24 04:31:39 PM PDT 24
Peak memory 199948 kb
Host smart-4b52a003-2c7c-4968-804d-553fed61aa2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023793382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4023793382
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2498477858
Short name T886
Test name
Test status
Simulation time 3616608182 ps
CPU time 1.35 seconds
Started Jul 24 04:29:33 PM PDT 24
Finished Jul 24 04:29:35 PM PDT 24
Peak memory 196856 kb
Host smart-342fc571-4a9b-4563-8e50-7da754448d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498477858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2498477858
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3814390725
Short name T443
Test name
Test status
Simulation time 70970686299 ps
CPU time 106.83 seconds
Started Jul 24 04:29:34 PM PDT 24
Finished Jul 24 04:31:21 PM PDT 24
Peak memory 199644 kb
Host smart-9c36df02-7f4f-4524-8c23-f80ffe96c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814390725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3814390725
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1637763611
Short name T318
Test name
Test status
Simulation time 13931523543 ps
CPU time 559.01 seconds
Started Jul 24 04:29:32 PM PDT 24
Finished Jul 24 04:38:51 PM PDT 24
Peak memory 200088 kb
Host smart-0489529f-512a-4139-9f6f-5266889b25d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637763611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1637763611
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.836559047
Short name T749
Test name
Test status
Simulation time 1584185140 ps
CPU time 5.84 seconds
Started Jul 24 04:29:34 PM PDT 24
Finished Jul 24 04:29:40 PM PDT 24
Peak memory 197800 kb
Host smart-e0721bfc-7f2f-4abd-bc98-68f79dbdcbfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836559047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.836559047
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2876971890
Short name T384
Test name
Test status
Simulation time 18494278251 ps
CPU time 28.78 seconds
Started Jul 24 04:29:34 PM PDT 24
Finished Jul 24 04:30:03 PM PDT 24
Peak memory 199780 kb
Host smart-01231308-8b4a-4b91-9be8-64964c8dca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876971890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2876971890
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.630974972
Short name T939
Test name
Test status
Simulation time 5150909168 ps
CPU time 2.53 seconds
Started Jul 24 04:29:35 PM PDT 24
Finished Jul 24 04:29:38 PM PDT 24
Peak memory 196524 kb
Host smart-85a8e011-b7ed-4f96-b1b1-7270db52254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630974972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.630974972
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3878629489
Short name T1021
Test name
Test status
Simulation time 694871997 ps
CPU time 1.49 seconds
Started Jul 24 04:29:28 PM PDT 24
Finished Jul 24 04:29:30 PM PDT 24
Peak memory 198648 kb
Host smart-c0946921-59fb-482b-84c9-7771183f61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878629489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3878629489
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4160059718
Short name T982
Test name
Test status
Simulation time 118237329889 ps
CPU time 128.32 seconds
Started Jul 24 04:29:38 PM PDT 24
Finished Jul 24 04:31:46 PM PDT 24
Peak memory 208360 kb
Host smart-507736bc-86ab-4d94-a382-418857b1efbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160059718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4160059718
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3334669022
Short name T741
Test name
Test status
Simulation time 24835490122 ps
CPU time 286.85 seconds
Started Jul 24 04:29:39 PM PDT 24
Finished Jul 24 04:34:26 PM PDT 24
Peak memory 216648 kb
Host smart-9c75c503-10fb-4558-93e8-1de752670f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334669022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3334669022
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1443695726
Short name T1025
Test name
Test status
Simulation time 1083989822 ps
CPU time 2.56 seconds
Started Jul 24 04:29:33 PM PDT 24
Finished Jul 24 04:29:35 PM PDT 24
Peak memory 199124 kb
Host smart-b1bb0775-548c-4f71-9359-d4ca17620556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443695726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1443695726
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3677621027
Short name T638
Test name
Test status
Simulation time 9253262935 ps
CPU time 17.91 seconds
Started Jul 24 04:29:29 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 200032 kb
Host smart-b3846935-865a-4412-a9d8-5d53e8c2ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677621027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3677621027
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2330246897
Short name T339
Test name
Test status
Simulation time 35119304 ps
CPU time 0.54 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:43 PM PDT 24
Peak memory 195312 kb
Host smart-dfbbfbf2-5fad-4f32-8c46-75eed28001ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330246897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2330246897
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1183240656
Short name T148
Test name
Test status
Simulation time 53914016002 ps
CPU time 19.8 seconds
Started Jul 24 04:29:38 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 199952 kb
Host smart-471ef3a8-866f-4fdd-b209-11fc64590e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183240656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1183240656
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1688045701
Short name T152
Test name
Test status
Simulation time 72283086077 ps
CPU time 47.58 seconds
Started Jul 24 04:29:39 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 199932 kb
Host smart-ce386fda-ac6c-4c17-9df8-85234693f2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688045701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1688045701
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.237673097
Short name T870
Test name
Test status
Simulation time 68462586266 ps
CPU time 157.39 seconds
Started Jul 24 04:29:39 PM PDT 24
Finished Jul 24 04:32:16 PM PDT 24
Peak memory 199952 kb
Host smart-89fdbb55-a0b6-4ba6-91e0-26fa5c054c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237673097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.237673097
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2829835279
Short name T663
Test name
Test status
Simulation time 343870065824 ps
CPU time 133.23 seconds
Started Jul 24 04:29:37 PM PDT 24
Finished Jul 24 04:31:51 PM PDT 24
Peak memory 199720 kb
Host smart-f2b731dd-0ff7-4d59-97db-e8394fc9b001
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829835279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2829835279
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2644815900
Short name T381
Test name
Test status
Simulation time 234073433867 ps
CPU time 122.38 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:31:46 PM PDT 24
Peak memory 199916 kb
Host smart-35e6d822-586c-4c43-b7c7-abc748105d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644815900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2644815900
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3597410703
Short name T1056
Test name
Test status
Simulation time 11279625354 ps
CPU time 5.14 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:49 PM PDT 24
Peak memory 199736 kb
Host smart-4c941e3d-19eb-4593-92b8-eb5a1736a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597410703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3597410703
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1982648180
Short name T794
Test name
Test status
Simulation time 229302363691 ps
CPU time 30.79 seconds
Started Jul 24 04:29:38 PM PDT 24
Finished Jul 24 04:30:09 PM PDT 24
Peak memory 198336 kb
Host smart-037321b7-8c75-49d7-9410-0f9d91ce7e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982648180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1982648180
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2026152298
Short name T342
Test name
Test status
Simulation time 6660359113 ps
CPU time 373.92 seconds
Started Jul 24 04:29:45 PM PDT 24
Finished Jul 24 04:35:59 PM PDT 24
Peak memory 199976 kb
Host smart-26e805ad-9b85-42c5-a49f-6785c52ac153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026152298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2026152298
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3010656256
Short name T350
Test name
Test status
Simulation time 2750113669 ps
CPU time 11.75 seconds
Started Jul 24 04:29:42 PM PDT 24
Finished Jul 24 04:29:53 PM PDT 24
Peak memory 199064 kb
Host smart-5c66327f-721b-4346-8f9e-99bc89c4fa8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010656256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3010656256
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1592859839
Short name T858
Test name
Test status
Simulation time 14903709497 ps
CPU time 22.28 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:30:07 PM PDT 24
Peak memory 200000 kb
Host smart-945b7106-b2fc-47e4-8b77-3958a116390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592859839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1592859839
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1443467809
Short name T884
Test name
Test status
Simulation time 2026597813 ps
CPU time 1.36 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:45 PM PDT 24
Peak memory 195436 kb
Host smart-553986af-4fd0-444b-bf4f-4439e180ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443467809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1443467809
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2971993403
Short name T893
Test name
Test status
Simulation time 892478791 ps
CPU time 3.15 seconds
Started Jul 24 04:29:40 PM PDT 24
Finished Jul 24 04:29:43 PM PDT 24
Peak memory 198256 kb
Host smart-0723f404-1e5d-4a88-8037-c9166c1c1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971993403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2971993403
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.82189402
Short name T111
Test name
Test status
Simulation time 177873252829 ps
CPU time 378.42 seconds
Started Jul 24 04:29:47 PM PDT 24
Finished Jul 24 04:36:05 PM PDT 24
Peak memory 199940 kb
Host smart-d31c01cb-f813-4b17-99e2-1f58b4459359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82189402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.82189402
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3665206165
Short name T550
Test name
Test status
Simulation time 46779951122 ps
CPU time 125.82 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:31:49 PM PDT 24
Peak memory 215492 kb
Host smart-e2b026e3-0bfb-4d17-90e8-14262e8b2400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665206165 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3665206165
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.371725384
Short name T801
Test name
Test status
Simulation time 1665222536 ps
CPU time 1.79 seconds
Started Jul 24 04:29:45 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 199896 kb
Host smart-b0bfa99b-2513-4cb6-abb1-047a5ee33c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371725384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.371725384
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4116524567
Short name T528
Test name
Test status
Simulation time 39328380807 ps
CPU time 21.05 seconds
Started Jul 24 04:29:40 PM PDT 24
Finished Jul 24 04:30:01 PM PDT 24
Peak memory 200064 kb
Host smart-75ce1f17-ef5b-4482-8bcb-784cbb226d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116524567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4116524567
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1964997519
Short name T805
Test name
Test status
Simulation time 11606709 ps
CPU time 0.55 seconds
Started Jul 24 04:29:46 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 194792 kb
Host smart-c3133e35-221d-4bb1-a7c6-82efbccd9b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964997519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1964997519
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.966412846
Short name T919
Test name
Test status
Simulation time 99217969105 ps
CPU time 217.43 seconds
Started Jul 24 04:30:40 PM PDT 24
Finished Jul 24 04:34:17 PM PDT 24
Peak memory 199872 kb
Host smart-409867b3-8b95-4ad2-86c1-cff837f9e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966412846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.966412846
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.846165677
Short name T908
Test name
Test status
Simulation time 19557778583 ps
CPU time 28.49 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:30:12 PM PDT 24
Peak memory 199864 kb
Host smart-c887980f-249e-4677-819f-284201ed6c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846165677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.846165677
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1945963997
Short name T1150
Test name
Test status
Simulation time 23077961807 ps
CPU time 38.78 seconds
Started Jul 24 04:29:45 PM PDT 24
Finished Jul 24 04:30:24 PM PDT 24
Peak memory 199996 kb
Host smart-2714b7fd-c3b3-47f1-8471-39e34ab9b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945963997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1945963997
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1961143979
Short name T753
Test name
Test status
Simulation time 17185516711 ps
CPU time 13.61 seconds
Started Jul 24 04:29:45 PM PDT 24
Finished Jul 24 04:29:59 PM PDT 24
Peak memory 200044 kb
Host smart-dd2bcd01-828e-4a45-a5af-d958385f931e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961143979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1961143979
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1747575640
Short name T1114
Test name
Test status
Simulation time 20182067810 ps
CPU time 101.04 seconds
Started Jul 24 04:30:39 PM PDT 24
Finished Jul 24 04:32:20 PM PDT 24
Peak memory 199960 kb
Host smart-06770017-93d5-4123-8e66-c12ced277620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747575640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1747575640
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.546152852
Short name T954
Test name
Test status
Simulation time 1547856635 ps
CPU time 2.87 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:29:47 PM PDT 24
Peak memory 197008 kb
Host smart-c63309af-0461-473a-9f6c-f5af31f1ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546152852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.546152852
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.369036387
Short name T703
Test name
Test status
Simulation time 131039691677 ps
CPU time 73.43 seconds
Started Jul 24 04:30:40 PM PDT 24
Finished Jul 24 04:31:54 PM PDT 24
Peak memory 199724 kb
Host smart-ae8c395e-86ca-4e95-b95f-5fe1ccacb77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369036387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.369036387
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1003525630
Short name T1095
Test name
Test status
Simulation time 30516908079 ps
CPU time 432.56 seconds
Started Jul 24 04:29:42 PM PDT 24
Finished Jul 24 04:36:55 PM PDT 24
Peak memory 200128 kb
Host smart-38f84009-5639-4f44-9500-633a195ec493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003525630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1003525630
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.605810867
Short name T716
Test name
Test status
Simulation time 4728971052 ps
CPU time 10.18 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:29:54 PM PDT 24
Peak memory 198280 kb
Host smart-8515fdda-f7dc-4c4c-96c5-830a5542ae64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605810867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.605810867
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1958630386
Short name T173
Test name
Test status
Simulation time 48077801279 ps
CPU time 14.05 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 199320 kb
Host smart-ae17e7c4-cbd9-442d-8337-e8cd1a1f10f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958630386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1958630386
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2210161199
Short name T1092
Test name
Test status
Simulation time 623154265 ps
CPU time 1.46 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:45 PM PDT 24
Peak memory 195672 kb
Host smart-23d385ab-f639-46ef-89da-391d1de6f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210161199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2210161199
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1694588687
Short name T548
Test name
Test status
Simulation time 5482822016 ps
CPU time 9.95 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:29:53 PM PDT 24
Peak memory 199972 kb
Host smart-0a7ccbf5-b9e7-4c0f-bfcd-4bf382da7015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694588687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1694588687
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2637684639
Short name T459
Test name
Test status
Simulation time 216844973702 ps
CPU time 665.43 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:40:50 PM PDT 24
Peak memory 199900 kb
Host smart-9620fb48-bdab-4510-8859-af882cd5a481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637684639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2637684639
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2268809306
Short name T700
Test name
Test status
Simulation time 410194785773 ps
CPU time 1054.14 seconds
Started Jul 24 04:29:43 PM PDT 24
Finished Jul 24 04:47:18 PM PDT 24
Peak memory 226104 kb
Host smart-4e5649ae-70ce-45fa-9064-ccbc09ce56e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268809306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2268809306
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2330470050
Short name T1119
Test name
Test status
Simulation time 6478993108 ps
CPU time 16.79 seconds
Started Jul 24 04:29:44 PM PDT 24
Finished Jul 24 04:30:02 PM PDT 24
Peak memory 200364 kb
Host smart-17f88cb8-2485-49b6-9fc2-bf4fb2b690d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330470050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2330470050
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1494443586
Short name T814
Test name
Test status
Simulation time 133162173717 ps
CPU time 58.13 seconds
Started Jul 24 04:29:46 PM PDT 24
Finished Jul 24 04:30:44 PM PDT 24
Peak memory 200096 kb
Host smart-7a9b4039-8242-454d-a178-690279756b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494443586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1494443586
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3458168902
Short name T966
Test name
Test status
Simulation time 20863110 ps
CPU time 0.59 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:38 PM PDT 24
Peak memory 193172 kb
Host smart-fb2a635f-94f4-4832-b3a1-ecc6e1d5f46f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458168902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3458168902
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.176651109
Short name T526
Test name
Test status
Simulation time 48475113168 ps
CPU time 49 seconds
Started Jul 24 04:27:49 PM PDT 24
Finished Jul 24 04:28:39 PM PDT 24
Peak memory 199752 kb
Host smart-f44e2029-94cf-45d3-a7d3-651c7b7f3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176651109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.176651109
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2439071430
Short name T132
Test name
Test status
Simulation time 17196389238 ps
CPU time 25.79 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:26:53 PM PDT 24
Peak memory 199460 kb
Host smart-42a04f05-a87b-44d5-8d7e-2bfe8b5e539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439071430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2439071430
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4293661820
Short name T317
Test name
Test status
Simulation time 77657718552 ps
CPU time 12.35 seconds
Started Jul 24 04:26:25 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 199948 kb
Host smart-7078a923-e442-475c-be3b-4e38895f032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293661820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4293661820
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1108878625
Short name T446
Test name
Test status
Simulation time 6552942887 ps
CPU time 3.29 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 194208 kb
Host smart-b8292529-303b-4361-9a5c-99cb5952c603
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108878625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1108878625
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2549546875
Short name T724
Test name
Test status
Simulation time 123033175209 ps
CPU time 356.05 seconds
Started Jul 24 04:26:30 PM PDT 24
Finished Jul 24 04:32:27 PM PDT 24
Peak memory 199992 kb
Host smart-0499ecb3-569a-4936-9a20-fbb527b4974f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549546875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2549546875
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1054283485
Short name T411
Test name
Test status
Simulation time 6304873681 ps
CPU time 4.84 seconds
Started Jul 24 04:26:26 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 198112 kb
Host smart-48b8bd08-cd78-4fab-ad28-72da417ff2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054283485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1054283485
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.708153396
Short name T474
Test name
Test status
Simulation time 52494156475 ps
CPU time 50.92 seconds
Started Jul 24 04:26:30 PM PDT 24
Finished Jul 24 04:27:21 PM PDT 24
Peak memory 200020 kb
Host smart-5933e738-8d28-43d1-a9bb-3d1953b6160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708153396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.708153396
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2453390913
Short name T261
Test name
Test status
Simulation time 11010450691 ps
CPU time 210.74 seconds
Started Jul 24 04:26:17 PM PDT 24
Finished Jul 24 04:29:48 PM PDT 24
Peak memory 199976 kb
Host smart-dcda3108-c871-4b08-8784-d2f0b9d917c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453390913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2453390913
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.4272525514
Short name T514
Test name
Test status
Simulation time 6233468221 ps
CPU time 26.21 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:28:04 PM PDT 24
Peak memory 195336 kb
Host smart-11126a1c-a07c-4c1e-bcd0-2831be7a93af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272525514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4272525514
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3760320225
Short name T92
Test name
Test status
Simulation time 90108131865 ps
CPU time 120.72 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:28:22 PM PDT 24
Peak memory 200012 kb
Host smart-e72dce7f-1ae6-45c9-b251-87a6628c1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760320225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3760320225
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1476773953
Short name T44
Test name
Test status
Simulation time 2798207076 ps
CPU time 5.17 seconds
Started Jul 24 04:27:37 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 194056 kb
Host smart-d6e2dde7-8768-4578-b416-7e5c35c4e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476773953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1476773953
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3012492333
Short name T844
Test name
Test status
Simulation time 542157318 ps
CPU time 1.78 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:26:29 PM PDT 24
Peak memory 199336 kb
Host smart-f693c150-1c6b-4ba7-ad29-c48a01681008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012492333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3012492333
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1868008318
Short name T509
Test name
Test status
Simulation time 90938897158 ps
CPU time 416.43 seconds
Started Jul 24 04:26:25 PM PDT 24
Finished Jul 24 04:33:22 PM PDT 24
Peak memory 199952 kb
Host smart-59e1a08b-977d-4b2e-801c-e1cc3125a601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868008318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1868008318
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2915066746
Short name T944
Test name
Test status
Simulation time 76207619563 ps
CPU time 572.45 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:35:54 PM PDT 24
Peak memory 226196 kb
Host smart-84ab3b04-b941-423f-b274-d4177cb61c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915066746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2915066746
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1889301193
Short name T815
Test name
Test status
Simulation time 864231554 ps
CPU time 2.59 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:26:34 PM PDT 24
Peak memory 198304 kb
Host smart-34252bb7-4e33-4ad7-9dfc-afa627c906e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889301193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1889301193
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.356157303
Short name T254
Test name
Test status
Simulation time 11657666590 ps
CPU time 4.26 seconds
Started Jul 24 04:26:22 PM PDT 24
Finished Jul 24 04:26:26 PM PDT 24
Peak memory 196808 kb
Host smart-609e1957-5fcf-4b46-9e2e-bb83d4d4eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356157303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.356157303
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.727826155
Short name T578
Test name
Test status
Simulation time 52678993586 ps
CPU time 21.93 seconds
Started Jul 24 04:29:49 PM PDT 24
Finished Jul 24 04:30:11 PM PDT 24
Peak memory 199904 kb
Host smart-682e29b4-8e46-4e5b-a4c2-d94cafb51183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727826155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.727826155
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4162830487
Short name T816
Test name
Test status
Simulation time 214832968348 ps
CPU time 946.34 seconds
Started Jul 24 04:29:52 PM PDT 24
Finished Jul 24 04:45:39 PM PDT 24
Peak memory 232924 kb
Host smart-ef19a4dd-758c-447f-ba7a-a4e5d14207f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162830487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4162830487
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.195678725
Short name T242
Test name
Test status
Simulation time 130518333056 ps
CPU time 33.61 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:30:22 PM PDT 24
Peak memory 199956 kb
Host smart-e743475e-ccfb-4052-97c8-fe51ea53425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195678725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.195678725
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1114278429
Short name T282
Test name
Test status
Simulation time 243605911028 ps
CPU time 633.87 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:40:22 PM PDT 24
Peak memory 225896 kb
Host smart-87110ea5-379e-4efa-9aaa-e83efc914467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114278429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1114278429
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.534317160
Short name T793
Test name
Test status
Simulation time 213961550705 ps
CPU time 52.33 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 199988 kb
Host smart-280955d5-975d-4139-ad91-265f4ca12cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534317160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.534317160
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3672384146
Short name T981
Test name
Test status
Simulation time 21734926566 ps
CPU time 95.87 seconds
Started Jul 24 04:29:50 PM PDT 24
Finished Jul 24 04:31:26 PM PDT 24
Peak memory 208420 kb
Host smart-ce2bb437-e97e-41a1-9273-9a5b7f56a8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672384146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3672384146
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1459901004
Short name T883
Test name
Test status
Simulation time 18920434063 ps
CPU time 30.88 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:30:19 PM PDT 24
Peak memory 200016 kb
Host smart-89571c40-50c9-4fb8-b5a7-451cfd45edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459901004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1459901004
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3867067363
Short name T215
Test name
Test status
Simulation time 12070896050 ps
CPU time 18.61 seconds
Started Jul 24 04:29:49 PM PDT 24
Finished Jul 24 04:30:07 PM PDT 24
Peak memory 199952 kb
Host smart-38570d86-21b4-4ed6-9eb7-5a380e13d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867067363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3867067363
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1145095946
Short name T53
Test name
Test status
Simulation time 107691129152 ps
CPU time 1228.43 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:50:17 PM PDT 24
Peak memory 224684 kb
Host smart-6cc0b5e2-0d2d-4e10-b7a0-22f04c6fa3d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145095946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1145095946
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3874277712
Short name T300
Test name
Test status
Simulation time 65015365357 ps
CPU time 90.34 seconds
Started Jul 24 04:29:47 PM PDT 24
Finished Jul 24 04:31:18 PM PDT 24
Peak memory 199984 kb
Host smart-ca103864-e97d-4c87-bcc8-964728f94ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874277712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3874277712
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2236313177
Short name T720
Test name
Test status
Simulation time 309193535702 ps
CPU time 1103.03 seconds
Started Jul 24 04:29:49 PM PDT 24
Finished Jul 24 04:48:12 PM PDT 24
Peak memory 216516 kb
Host smart-1faf46aa-cfb8-41da-9e84-d2e939881926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236313177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2236313177
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3994976106
Short name T1083
Test name
Test status
Simulation time 16590557393 ps
CPU time 46.69 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:30:34 PM PDT 24
Peak memory 199996 kb
Host smart-f8bf2541-c844-48b7-9d95-c958d2a337ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994976106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3994976106
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4099841570
Short name T882
Test name
Test status
Simulation time 35875041387 ps
CPU time 311.53 seconds
Started Jul 24 04:29:48 PM PDT 24
Finished Jul 24 04:35:00 PM PDT 24
Peak memory 216552 kb
Host smart-fc63cced-4f72-40d4-9c13-5c086bcfe3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099841570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4099841570
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1466832234
Short name T469
Test name
Test status
Simulation time 111220415254 ps
CPU time 98.58 seconds
Started Jul 24 04:29:47 PM PDT 24
Finished Jul 24 04:31:25 PM PDT 24
Peak memory 215856 kb
Host smart-505192cc-1aa6-45bd-9115-3fcb50c07db4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466832234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1466832234
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4268403657
Short name T609
Test name
Test status
Simulation time 19706787138 ps
CPU time 29.2 seconds
Started Jul 24 04:29:50 PM PDT 24
Finished Jul 24 04:30:19 PM PDT 24
Peak memory 199968 kb
Host smart-c6e974bb-d660-47e2-89b7-a9bb17de631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268403657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4268403657
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1881633796
Short name T1168
Test name
Test status
Simulation time 185482017682 ps
CPU time 142.41 seconds
Started Jul 24 04:29:50 PM PDT 24
Finished Jul 24 04:32:13 PM PDT 24
Peak memory 199928 kb
Host smart-f26681fd-e744-4f33-909d-2c48289db0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881633796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1881633796
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.481389989
Short name T439
Test name
Test status
Simulation time 10342562 ps
CPU time 0.61 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 194316 kb
Host smart-79442e35-158b-47ef-900a-42027427e3fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481389989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.481389989
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4122379768
Short name T889
Test name
Test status
Simulation time 69999525075 ps
CPU time 141.22 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:28:49 PM PDT 24
Peak memory 199924 kb
Host smart-c7f691ae-a04f-4838-ad0a-18418796c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122379768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4122379768
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.282019963
Short name T813
Test name
Test status
Simulation time 28042468453 ps
CPU time 11.77 seconds
Started Jul 24 04:26:30 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 199992 kb
Host smart-94201889-7134-4652-b1f6-83a6fb700d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282019963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.282019963
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.504253594
Short name T615
Test name
Test status
Simulation time 64509467242 ps
CPU time 28.09 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:27:01 PM PDT 24
Peak memory 200000 kb
Host smart-20d71d64-8013-4612-af3b-d92f29e97622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504253594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.504253594
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3360916679
Short name T440
Test name
Test status
Simulation time 24832939722 ps
CPU time 37.73 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 199940 kb
Host smart-2ae0cea7-0128-46ed-98ff-84614fc09157
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360916679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3360916679
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1550872692
Short name T671
Test name
Test status
Simulation time 202332136138 ps
CPU time 530.96 seconds
Started Jul 24 04:26:25 PM PDT 24
Finished Jul 24 04:35:16 PM PDT 24
Peak memory 199908 kb
Host smart-8bbe92d4-667e-4f83-aee9-ebd6ca496146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550872692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1550872692
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1593811241
Short name T505
Test name
Test status
Simulation time 8727631272 ps
CPU time 18.38 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:58 PM PDT 24
Peak memory 199780 kb
Host smart-bf78f4bf-78bb-4cf7-a2da-77e960b65882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593811241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1593811241
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.974422210
Short name T574
Test name
Test status
Simulation time 177794324709 ps
CPU time 74.04 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 208328 kb
Host smart-cc9f9bbf-d26c-40cd-aaed-cfdc63a36a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974422210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.974422210
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.175619447
Short name T372
Test name
Test status
Simulation time 11748185290 ps
CPU time 196.04 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:29:43 PM PDT 24
Peak memory 199904 kb
Host smart-0a5730c7-56a1-4d94-ace2-1ff961e9448d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175619447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.175619447
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1639482486
Short name T846
Test name
Test status
Simulation time 4611866646 ps
CPU time 9.55 seconds
Started Jul 24 04:26:34 PM PDT 24
Finished Jul 24 04:26:44 PM PDT 24
Peak memory 198204 kb
Host smart-3c4b4684-0ce1-4f82-9e17-2a2a5ba4e73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1639482486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1639482486
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2732327453
Short name T1145
Test name
Test status
Simulation time 184347151086 ps
CPU time 284.6 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:31:20 PM PDT 24
Peak memory 199920 kb
Host smart-de9326ea-7a8c-46ce-99e3-6d3ddceccc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732327453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2732327453
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2748388282
Short name T460
Test name
Test status
Simulation time 27214825566 ps
CPU time 19.21 seconds
Started Jul 24 04:26:26 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 195696 kb
Host smart-1f557605-41e6-4b50-a9c5-79be70e63da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748388282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2748388282
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1940592279
Short name T1044
Test name
Test status
Simulation time 537640390 ps
CPU time 1.6 seconds
Started Jul 24 04:26:26 PM PDT 24
Finished Jul 24 04:26:28 PM PDT 24
Peak memory 198164 kb
Host smart-55797b22-b153-4a4d-a136-972ac6262f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940592279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1940592279
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2137280193
Short name T66
Test name
Test status
Simulation time 114975717276 ps
CPU time 1587.5 seconds
Started Jul 24 04:26:28 PM PDT 24
Finished Jul 24 04:52:56 PM PDT 24
Peak memory 226096 kb
Host smart-c58d168c-309d-4095-914d-ae2170b399b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137280193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2137280193
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3177856751
Short name T4
Test name
Test status
Simulation time 2206842251 ps
CPU time 2.33 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:26:32 PM PDT 24
Peak memory 199768 kb
Host smart-708c08b8-9ac8-4c7b-9627-632962129509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177856751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3177856751
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3119316734
Short name T1030
Test name
Test status
Simulation time 38393732026 ps
CPU time 14.03 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:26:41 PM PDT 24
Peak memory 199860 kb
Host smart-fbe355c1-f052-45a9-821d-d60cfe11dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119316734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3119316734
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3564405105
Short name T382
Test name
Test status
Simulation time 5152384084 ps
CPU time 3.05 seconds
Started Jul 24 04:29:55 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 199796 kb
Host smart-b7d5cdac-7f85-44b4-be54-884c35d8756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564405105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3564405105
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2013528761
Short name T1049
Test name
Test status
Simulation time 202691890576 ps
CPU time 558.53 seconds
Started Jul 24 04:29:52 PM PDT 24
Finished Jul 24 04:39:11 PM PDT 24
Peak memory 216356 kb
Host smart-978dc721-525d-444c-a919-9d46f3e5cb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013528761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2013528761
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1060110469
Short name T564
Test name
Test status
Simulation time 9439076603 ps
CPU time 12.71 seconds
Started Jul 24 04:29:53 PM PDT 24
Finished Jul 24 04:30:06 PM PDT 24
Peak memory 199896 kb
Host smart-5bd6cbaf-4b27-4da9-9d6d-3b4ccd7ebecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060110469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1060110469
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2036351007
Short name T147
Test name
Test status
Simulation time 456528714913 ps
CPU time 697.59 seconds
Started Jul 24 04:29:54 PM PDT 24
Finished Jul 24 04:41:32 PM PDT 24
Peak memory 224844 kb
Host smart-a3bf6fc6-6aa9-4ba8-a23b-9877f9f1c7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036351007 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2036351007
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2015793164
Short name T1122
Test name
Test status
Simulation time 82723472650 ps
CPU time 32.75 seconds
Started Jul 24 04:29:54 PM PDT 24
Finished Jul 24 04:30:27 PM PDT 24
Peak memory 199796 kb
Host smart-22bcad55-c000-4a9d-8cb7-730b9e676674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015793164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2015793164
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1815907436
Short name T747
Test name
Test status
Simulation time 43389739238 ps
CPU time 187.46 seconds
Started Jul 24 04:29:55 PM PDT 24
Finished Jul 24 04:33:03 PM PDT 24
Peak memory 216400 kb
Host smart-adacccc9-28f9-4c22-8cf0-9cedc549e64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815907436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1815907436
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2406733597
Short name T920
Test name
Test status
Simulation time 94031965621 ps
CPU time 72.61 seconds
Started Jul 24 04:29:56 PM PDT 24
Finished Jul 24 04:31:09 PM PDT 24
Peak memory 200060 kb
Host smart-96925c12-2719-4a11-a6e3-c6a2f831da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406733597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2406733597
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2288790964
Short name T567
Test name
Test status
Simulation time 411793665377 ps
CPU time 241.27 seconds
Started Jul 24 04:29:54 PM PDT 24
Finished Jul 24 04:33:55 PM PDT 24
Peak memory 209344 kb
Host smart-8c76c3a8-912f-4a99-bea4-168af826d3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288790964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2288790964
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3074914085
Short name T652
Test name
Test status
Simulation time 93778197734 ps
CPU time 71.02 seconds
Started Jul 24 04:29:53 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 199972 kb
Host smart-d6a17871-0467-428b-b226-382aad7d60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074914085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3074914085
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.376504772
Short name T552
Test name
Test status
Simulation time 182349561159 ps
CPU time 651.15 seconds
Started Jul 24 04:29:53 PM PDT 24
Finished Jul 24 04:40:44 PM PDT 24
Peak memory 216504 kb
Host smart-7eef9e08-5aa0-49ea-a8f8-b0ff4e827eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376504772 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.376504772
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1232493778
Short name T369
Test name
Test status
Simulation time 141609636135 ps
CPU time 103.82 seconds
Started Jul 24 04:29:53 PM PDT 24
Finished Jul 24 04:31:37 PM PDT 24
Peak memory 199980 kb
Host smart-5c0a5429-5160-4430-8b13-05123e683ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232493778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1232493778
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.62572856
Short name T97
Test name
Test status
Simulation time 24223162171 ps
CPU time 236.16 seconds
Started Jul 24 04:29:57 PM PDT 24
Finished Jul 24 04:33:53 PM PDT 24
Peak memory 215620 kb
Host smart-255bbb4d-37f6-4317-bb38-b1ea17da950e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62572856 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.62572856
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1520221782
Short name T760
Test name
Test status
Simulation time 74001244484 ps
CPU time 212.43 seconds
Started Jul 24 04:29:55 PM PDT 24
Finished Jul 24 04:33:28 PM PDT 24
Peak memory 199956 kb
Host smart-71b067f4-6ae3-4114-a0dc-dc79d08f169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520221782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1520221782
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2833919131
Short name T100
Test name
Test status
Simulation time 154666917472 ps
CPU time 543.07 seconds
Started Jul 24 04:29:54 PM PDT 24
Finished Jul 24 04:38:57 PM PDT 24
Peak memory 224928 kb
Host smart-c57274bc-921e-45a9-bd6e-79328caa0d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833919131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2833919131
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2883969192
Short name T688
Test name
Test status
Simulation time 94320735091 ps
CPU time 84.46 seconds
Started Jul 24 04:29:57 PM PDT 24
Finished Jul 24 04:31:21 PM PDT 24
Peak memory 200000 kb
Host smart-9cc2eaec-7d1b-4bd0-9220-8a2fe56656fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883969192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2883969192
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2884966369
Short name T1058
Test name
Test status
Simulation time 67787496404 ps
CPU time 1473.68 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:54:34 PM PDT 24
Peak memory 216476 kb
Host smart-f3b6e299-09f0-48ea-a4e8-321566075cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884966369 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2884966369
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1498780324
Short name T520
Test name
Test status
Simulation time 21796208918 ps
CPU time 234.07 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:34:06 PM PDT 24
Peak memory 208140 kb
Host smart-062465d4-0461-415a-9c0f-0e01654beae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498780324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1498780324
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1639271005
Short name T553
Test name
Test status
Simulation time 41935632489 ps
CPU time 12.5 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:30:14 PM PDT 24
Peak memory 200340 kb
Host smart-a00d4e78-e57b-463d-ad13-fa11ee96fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639271005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1639271005
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3209895785
Short name T31
Test name
Test status
Simulation time 31237766854 ps
CPU time 187.2 seconds
Started Jul 24 04:29:59 PM PDT 24
Finished Jul 24 04:33:07 PM PDT 24
Peak memory 215688 kb
Host smart-f15623cd-1fe2-41b4-ac44-0d3a9e0fae7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209895785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3209895785
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3136634137
Short name T1073
Test name
Test status
Simulation time 12483196 ps
CPU time 0.56 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:26:33 PM PDT 24
Peak memory 195728 kb
Host smart-230721fa-7438-4906-943a-ccdbbf669bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136634137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3136634137
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3196761733
Short name T733
Test name
Test status
Simulation time 142816090670 ps
CPU time 213.22 seconds
Started Jul 24 04:26:28 PM PDT 24
Finished Jul 24 04:30:01 PM PDT 24
Peak memory 199912 kb
Host smart-65b68fab-d977-4a3b-814c-8962a75af065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196761733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3196761733
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2987955776
Short name T617
Test name
Test status
Simulation time 88912494373 ps
CPU time 27.66 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:27:08 PM PDT 24
Peak memory 199936 kb
Host smart-57b7133d-006f-452a-ab2a-c8d67c1e5034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987955776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2987955776
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.875811640
Short name T105
Test name
Test status
Simulation time 54087065245 ps
CPU time 20.39 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:26:53 PM PDT 24
Peak memory 199972 kb
Host smart-94b7a0ee-0ff5-40a3-b8b3-b5eccb45d3f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875811640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.875811640
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.516432098
Short name T344
Test name
Test status
Simulation time 115808783986 ps
CPU time 251.38 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 199916 kb
Host smart-4f75e302-2e7f-49df-a418-07af723f52f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516432098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.516432098
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.670763026
Short name T397
Test name
Test status
Simulation time 2891739128 ps
CPU time 4.06 seconds
Started Jul 24 04:26:27 PM PDT 24
Finished Jul 24 04:26:32 PM PDT 24
Peak memory 197260 kb
Host smart-ad59f0dc-dcff-4233-8c4b-85766c0a2702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670763026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.670763026
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2051795538
Short name T791
Test name
Test status
Simulation time 125657385728 ps
CPU time 989.97 seconds
Started Jul 24 04:26:30 PM PDT 24
Finished Jul 24 04:43:00 PM PDT 24
Peak memory 215732 kb
Host smart-04266c90-402c-456d-8575-189226e01d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051795538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2051795538
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1451023892
Short name T437
Test name
Test status
Simulation time 11180882590 ps
CPU time 522.88 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:35:15 PM PDT 24
Peak memory 199916 kb
Host smart-f9f4b1da-f58b-4792-a075-84c4df9709ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451023892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1451023892
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.654056933
Short name T705
Test name
Test status
Simulation time 1494685464 ps
CPU time 1.12 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 195584 kb
Host smart-587331d1-b0e4-4915-9c62-99c57f0c5015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654056933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.654056933
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1491924684
Short name T1160
Test name
Test status
Simulation time 73106596053 ps
CPU time 48.06 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:27:24 PM PDT 24
Peak memory 199960 kb
Host smart-37ec9412-f4e9-4805-a657-f00f2dbfc4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491924684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1491924684
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4149942401
Short name T47
Test name
Test status
Simulation time 6296497001 ps
CPU time 5.6 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:26:41 PM PDT 24
Peak memory 196716 kb
Host smart-62836b22-ec0b-4f4f-a32f-f248a63017c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149942401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4149942401
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2094764021
Short name T537
Test name
Test status
Simulation time 763894266 ps
CPU time 1.17 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:26:40 PM PDT 24
Peak memory 198680 kb
Host smart-7d4eb30c-516b-4ead-a6a7-7ee69955306b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094764021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2094764021
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1053517461
Short name T1162
Test name
Test status
Simulation time 395682044240 ps
CPU time 840.49 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:40:41 PM PDT 24
Peak memory 199936 kb
Host smart-4d798081-be71-45ef-9ca6-0f75a802d6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053517461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1053517461
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2271689935
Short name T58
Test name
Test status
Simulation time 250313753453 ps
CPU time 959.82 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:42:36 PM PDT 24
Peak memory 214124 kb
Host smart-8da5d755-5083-4e0c-ae05-609411be737d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271689935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2271689935
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3849014613
Short name T280
Test name
Test status
Simulation time 7385842797 ps
CPU time 17.9 seconds
Started Jul 24 04:26:28 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 199868 kb
Host smart-c780cf1b-6612-4ac9-9514-083b897f5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849014613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3849014613
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2077262275
Short name T983
Test name
Test status
Simulation time 20664598412 ps
CPU time 16.17 seconds
Started Jul 24 04:26:30 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 197004 kb
Host smart-102e15a8-5eab-458a-b433-6f660ff1ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077262275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2077262275
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1673683918
Short name T229
Test name
Test status
Simulation time 125218072144 ps
CPU time 112.55 seconds
Started Jul 24 04:30:03 PM PDT 24
Finished Jul 24 04:31:55 PM PDT 24
Peak memory 199964 kb
Host smart-fc0ef60d-4a58-465f-8701-9e2b1739e30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673683918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1673683918
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4181446380
Short name T838
Test name
Test status
Simulation time 248161948675 ps
CPU time 734.01 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:42:16 PM PDT 24
Peak memory 224844 kb
Host smart-b1e237e6-ef8d-4b6a-abd2-8ee5d731c8ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181446380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4181446380
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1939990433
Short name T918
Test name
Test status
Simulation time 51860689761 ps
CPU time 84.67 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:31:26 PM PDT 24
Peak memory 200032 kb
Host smart-a013c7e6-3fbc-4a57-9411-33e8de270e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939990433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1939990433
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1829150927
Short name T127
Test name
Test status
Simulation time 34753773383 ps
CPU time 70.38 seconds
Started Jul 24 04:30:02 PM PDT 24
Finished Jul 24 04:31:13 PM PDT 24
Peak memory 199908 kb
Host smart-7f95963e-35fb-45bd-918b-03af8df1492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829150927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1829150927
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1190299320
Short name T708
Test name
Test status
Simulation time 52638818143 ps
CPU time 1056.93 seconds
Started Jul 24 04:30:02 PM PDT 24
Finished Jul 24 04:47:39 PM PDT 24
Peak memory 216536 kb
Host smart-71a51705-0a0c-428a-9fbd-f99e3c23f1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190299320 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1190299320
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1598663438
Short name T204
Test name
Test status
Simulation time 59183282596 ps
CPU time 82.8 seconds
Started Jul 24 04:29:59 PM PDT 24
Finished Jul 24 04:31:22 PM PDT 24
Peak memory 199908 kb
Host smart-b71b157e-08c7-4764-bd56-34f3c87fedf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598663438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1598663438
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2980076960
Short name T466
Test name
Test status
Simulation time 40823028608 ps
CPU time 927.69 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:45:40 PM PDT 24
Peak memory 216508 kb
Host smart-87952f69-b18e-413f-b92f-e296986552a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980076960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2980076960
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.4159293208
Short name T183
Test name
Test status
Simulation time 102255972703 ps
CPU time 162.95 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:32:55 PM PDT 24
Peak memory 199968 kb
Host smart-6530c796-5fd1-425e-bd94-2653e417467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159293208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4159293208
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.70217063
Short name T1051
Test name
Test status
Simulation time 22554151489 ps
CPU time 331.14 seconds
Started Jul 24 04:31:02 PM PDT 24
Finished Jul 24 04:36:35 PM PDT 24
Peak memory 207672 kb
Host smart-c2abc7f3-e765-4d62-ad69-8a7bd34d60f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70217063 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.70217063
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3236449853
Short name T202
Test name
Test status
Simulation time 161870797548 ps
CPU time 109.29 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:31:49 PM PDT 24
Peak memory 199896 kb
Host smart-75d7d826-f315-4f6c-bd92-c87c1b2e8e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236449853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3236449853
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3575162159
Short name T1102
Test name
Test status
Simulation time 132467253004 ps
CPU time 118.58 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 213620 kb
Host smart-1cf2ca28-f937-4b78-814b-3852292e9921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575162159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3575162159
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.204411469
Short name T230
Test name
Test status
Simulation time 60106220200 ps
CPU time 25.34 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:30:37 PM PDT 24
Peak memory 199908 kb
Host smart-f7aecda1-d8ca-412e-aa0f-591e8c6ec754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204411469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.204411469
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2780140815
Short name T101
Test name
Test status
Simulation time 135074949516 ps
CPU time 694.47 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:41:36 PM PDT 24
Peak memory 224868 kb
Host smart-0ffb72a0-a00b-4dad-b2f0-69c33e994c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780140815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2780140815
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.677811118
Short name T992
Test name
Test status
Simulation time 178328020218 ps
CPU time 50.49 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 199968 kb
Host smart-b7c591f1-f10c-48de-a65f-c8e547d07154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677811118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.677811118
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3708322664
Short name T559
Test name
Test status
Simulation time 42217890059 ps
CPU time 766.23 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:42:48 PM PDT 24
Peak memory 216320 kb
Host smart-6d880e45-76f1-4085-a90c-86dc71cd4993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708322664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3708322664
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.302404138
Short name T1064
Test name
Test status
Simulation time 61190716572 ps
CPU time 63.54 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 199980 kb
Host smart-c5e4548a-f0be-4907-ae08-cc507ac59406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302404138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.302404138
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3956949406
Short name T1133
Test name
Test status
Simulation time 53811770037 ps
CPU time 1265.22 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:51:07 PM PDT 24
Peak memory 216640 kb
Host smart-d6af22ee-d3f6-4fb2-9967-664a50ee6b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956949406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3956949406
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2185659200
Short name T1136
Test name
Test status
Simulation time 16801926782 ps
CPU time 15.44 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:30:17 PM PDT 24
Peak memory 200328 kb
Host smart-1e018048-70c6-4933-a081-e017289f71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185659200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2185659200
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3187795866
Short name T65
Test name
Test status
Simulation time 89642531011 ps
CPU time 1760.99 seconds
Started Jul 24 04:29:59 PM PDT 24
Finished Jul 24 04:59:21 PM PDT 24
Peak memory 224860 kb
Host smart-e0abcb61-b7b5-4ab7-be58-514e7a12f6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187795866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3187795866
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.450717961
Short name T365
Test name
Test status
Simulation time 26170888 ps
CPU time 0.55 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:26:32 PM PDT 24
Peak memory 195368 kb
Host smart-dea92391-af74-41dc-8c35-a7c96a266ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450717961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.450717961
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.593158349
Short name T134
Test name
Test status
Simulation time 46509333529 ps
CPU time 19.17 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:26:55 PM PDT 24
Peak memory 199972 kb
Host smart-0308d5cb-9faa-49d4-8618-62a80ef3150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593158349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.593158349
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1278239285
Short name T935
Test name
Test status
Simulation time 57175148209 ps
CPU time 177.15 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 200012 kb
Host smart-5a3d0fbf-807c-45fb-85ac-e852ca9bc0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278239285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1278239285
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2407054679
Short name T470
Test name
Test status
Simulation time 14210579375 ps
CPU time 24.59 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:27:00 PM PDT 24
Peak memory 199912 kb
Host smart-90401d87-e783-4065-9842-d09731cf0b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407054679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2407054679
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1240848065
Short name T399
Test name
Test status
Simulation time 13014587652 ps
CPU time 4.59 seconds
Started Jul 24 04:26:28 PM PDT 24
Finished Jul 24 04:26:33 PM PDT 24
Peak memory 196948 kb
Host smart-9cfab8eb-b0cd-40c2-a3c2-c26154a0d514
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240848065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1240848065
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4040897639
Short name T729
Test name
Test status
Simulation time 80390645977 ps
CPU time 96.85 seconds
Started Jul 24 04:26:34 PM PDT 24
Finished Jul 24 04:28:11 PM PDT 24
Peak memory 199948 kb
Host smart-6a1c3dd3-85f2-4483-9507-24142b820411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040897639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4040897639
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2075141617
Short name T471
Test name
Test status
Simulation time 5300479222 ps
CPU time 9.97 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:26:41 PM PDT 24
Peak memory 198292 kb
Host smart-c6e847a8-a76c-4d03-afa7-fd887f28ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075141617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2075141617
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.4274872603
Short name T591
Test name
Test status
Simulation time 60006025928 ps
CPU time 123.06 seconds
Started Jul 24 04:26:31 PM PDT 24
Finished Jul 24 04:28:34 PM PDT 24
Peak memory 200064 kb
Host smart-942e7310-e75e-4689-9294-9ed8301c9c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274872603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4274872603
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1289084207
Short name T745
Test name
Test status
Simulation time 15572232418 ps
CPU time 901.92 seconds
Started Jul 24 04:26:38 PM PDT 24
Finished Jul 24 04:41:40 PM PDT 24
Peak memory 199908 kb
Host smart-2d0dd8bb-cf60-4ef6-8353-48d14b48c3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289084207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1289084207
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1841367763
Short name T931
Test name
Test status
Simulation time 5256631795 ps
CPU time 10.92 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:26:46 PM PDT 24
Peak memory 199168 kb
Host smart-d830386c-d6c1-4913-a926-96cfd0f1bf8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841367763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1841367763
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3857354814
Short name T1137
Test name
Test status
Simulation time 216351049929 ps
CPU time 431.99 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:33:53 PM PDT 24
Peak memory 199976 kb
Host smart-53bceec0-6d33-4e41-b359-fb13d0559599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857354814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3857354814
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.4049598929
Short name T290
Test name
Test status
Simulation time 54077628878 ps
CPU time 75.82 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:27:57 PM PDT 24
Peak memory 196460 kb
Host smart-0b7cd972-68f7-45ae-8c94-722f65294048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049598929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4049598929
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.934001884
Short name T352
Test name
Test status
Simulation time 450110906 ps
CPU time 1.96 seconds
Started Jul 24 04:26:29 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 198344 kb
Host smart-e7f9e1a7-af14-46bd-81d5-ec3d63ea7bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934001884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.934001884
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2442860992
Short name T150
Test name
Test status
Simulation time 132864506212 ps
CPU time 774.78 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:39:31 PM PDT 24
Peak memory 216412 kb
Host smart-89a13360-bbb3-47e7-93b6-4b03345424c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442860992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2442860992
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2862333055
Short name T848
Test name
Test status
Simulation time 832617722 ps
CPU time 2.56 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:43 PM PDT 24
Peak memory 198436 kb
Host smart-d6a5f1ef-c9dd-48d2-bffa-27d8c0a1eba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862333055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2862333055
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.850823669
Short name T388
Test name
Test status
Simulation time 27617454080 ps
CPU time 38.85 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:27:15 PM PDT 24
Peak memory 199968 kb
Host smart-d3fc0eff-2382-4040-8cbe-12c2170023f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850823669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.850823669
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2582349268
Short name T135
Test name
Test status
Simulation time 16140741041 ps
CPU time 19.28 seconds
Started Jul 24 04:30:00 PM PDT 24
Finished Jul 24 04:30:20 PM PDT 24
Peak memory 199964 kb
Host smart-49bcbd1d-8fc0-465c-b856-cf5b775e0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582349268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2582349268
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2808042703
Short name T266
Test name
Test status
Simulation time 46319271117 ps
CPU time 234.28 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:33:55 PM PDT 24
Peak memory 216976 kb
Host smart-41d51436-a5d1-47bf-ba44-60a7e26d73a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808042703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2808042703
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3525594943
Short name T551
Test name
Test status
Simulation time 42929963570 ps
CPU time 62.08 seconds
Started Jul 24 04:29:59 PM PDT 24
Finished Jul 24 04:31:02 PM PDT 24
Peak memory 200016 kb
Host smart-d8dc8676-7626-44c5-94b4-786ff059bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525594943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3525594943
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.758697326
Short name T322
Test name
Test status
Simulation time 61197772637 ps
CPU time 995.26 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:46:37 PM PDT 24
Peak memory 216508 kb
Host smart-a56815c2-bfff-4d59-9535-6b7aa168fdd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758697326 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.758697326
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3169636937
Short name T951
Test name
Test status
Simulation time 3130881651 ps
CPU time 6.3 seconds
Started Jul 24 04:31:16 PM PDT 24
Finished Jul 24 04:31:23 PM PDT 24
Peak memory 199648 kb
Host smart-0d03bd1a-eada-488b-a6c9-efe07de4fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169636937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3169636937
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3404901093
Short name T626
Test name
Test status
Simulation time 83504017682 ps
CPU time 260.77 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:34:33 PM PDT 24
Peak memory 216448 kb
Host smart-beabdb84-031f-4c1a-adef-678718e26580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404901093 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3404901093
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3748641605
Short name T748
Test name
Test status
Simulation time 99834396298 ps
CPU time 948.52 seconds
Started Jul 24 04:30:01 PM PDT 24
Finished Jul 24 04:45:50 PM PDT 24
Peak memory 224848 kb
Host smart-4ae868bd-85f3-457d-90a1-8037dda70f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748641605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3748641605
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3627230035
Short name T573
Test name
Test status
Simulation time 129649981836 ps
CPU time 187.49 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:33:19 PM PDT 24
Peak memory 199808 kb
Host smart-507e4ab0-8a58-479b-bd1f-623512575977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627230035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3627230035
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3431206073
Short name T28
Test name
Test status
Simulation time 11738097739 ps
CPU time 138.41 seconds
Started Jul 24 04:30:07 PM PDT 24
Finished Jul 24 04:32:25 PM PDT 24
Peak memory 208428 kb
Host smart-42a173a9-8004-402d-b8fe-42a23d53d1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431206073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3431206073
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.4277309153
Short name T707
Test name
Test status
Simulation time 16718914182 ps
CPU time 36.27 seconds
Started Jul 24 04:30:03 PM PDT 24
Finished Jul 24 04:30:40 PM PDT 24
Peak memory 199968 kb
Host smart-05f54584-8e6c-4ba7-a633-a6cb59ee1470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277309153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4277309153
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1838788121
Short name T1065
Test name
Test status
Simulation time 348747954650 ps
CPU time 957.98 seconds
Started Jul 24 04:30:08 PM PDT 24
Finished Jul 24 04:46:06 PM PDT 24
Peak memory 216624 kb
Host smart-6d0d74f3-b1ba-4f9f-80b3-448591eb0fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838788121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1838788121
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1157878832
Short name T496
Test name
Test status
Simulation time 83101822444 ps
CPU time 136.32 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:32:22 PM PDT 24
Peak memory 199976 kb
Host smart-489f4fbb-9719-4691-9c07-006f6065da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157878832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1157878832
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.67893096
Short name T646
Test name
Test status
Simulation time 211042175206 ps
CPU time 440.67 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:37:26 PM PDT 24
Peak memory 216504 kb
Host smart-aed37aa2-907a-408e-b239-5f0230c4050d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67893096 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.67893096
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2034299781
Short name T875
Test name
Test status
Simulation time 79186961610 ps
CPU time 30.46 seconds
Started Jul 24 04:30:08 PM PDT 24
Finished Jul 24 04:30:38 PM PDT 24
Peak memory 199964 kb
Host smart-e884ee72-f1c0-44c1-87d5-c164f53a6da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034299781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2034299781
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2973517185
Short name T806
Test name
Test status
Simulation time 45605794223 ps
CPU time 565.85 seconds
Started Jul 24 04:30:06 PM PDT 24
Finished Jul 24 04:39:32 PM PDT 24
Peak memory 224976 kb
Host smart-9c08fc28-b487-4c96-90bf-8060e595034e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973517185 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2973517185
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1792720136
Short name T1097
Test name
Test status
Simulation time 101064386220 ps
CPU time 47.66 seconds
Started Jul 24 04:30:04 PM PDT 24
Finished Jul 24 04:30:52 PM PDT 24
Peak memory 199452 kb
Host smart-f65e539f-2c8f-47e1-80d2-70cf183177f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792720136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1792720136
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1957382577
Short name T32
Test name
Test status
Simulation time 35705497785 ps
CPU time 439.11 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:37:24 PM PDT 24
Peak memory 215968 kb
Host smart-5e28091e-b0cb-45b8-a5ee-87ba5e1e8265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957382577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1957382577
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.442647929
Short name T998
Test name
Test status
Simulation time 21824115 ps
CPU time 0.55 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:41 PM PDT 24
Peak memory 195364 kb
Host smart-3ffa892a-342f-4de0-87b4-b1e39719f49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442647929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.442647929
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1473788829
Short name T1033
Test name
Test status
Simulation time 94831361321 ps
CPU time 25.36 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:27:06 PM PDT 24
Peak memory 200016 kb
Host smart-c18c8b38-0b25-4bfc-af06-27b00a94e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473788829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1473788829
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1218597197
Short name T1078
Test name
Test status
Simulation time 88854841744 ps
CPU time 13.67 seconds
Started Jul 24 04:26:36 PM PDT 24
Finished Jul 24 04:26:50 PM PDT 24
Peak memory 199988 kb
Host smart-5e088a65-c671-49f6-9c98-7e857c952028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218597197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1218597197
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.328676786
Short name T212
Test name
Test status
Simulation time 19802973398 ps
CPU time 34.25 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:27:09 PM PDT 24
Peak memory 200064 kb
Host smart-b58d9c3d-a25a-48fa-b488-b6d0d57e3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328676786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.328676786
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.623332107
Short name T789
Test name
Test status
Simulation time 24420732001 ps
CPU time 22.92 seconds
Started Jul 24 04:26:32 PM PDT 24
Finished Jul 24 04:26:55 PM PDT 24
Peak memory 199520 kb
Host smart-67dfe752-85cc-4809-b81d-204fb83a3052
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623332107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.623332107
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2256584599
Short name T248
Test name
Test status
Simulation time 181261435940 ps
CPU time 204.38 seconds
Started Jul 24 04:26:39 PM PDT 24
Finished Jul 24 04:30:04 PM PDT 24
Peak memory 199928 kb
Host smart-990a9fc6-b19b-4112-b908-a1e0f20c4ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256584599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2256584599
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1804186320
Short name T742
Test name
Test status
Simulation time 3241146096 ps
CPU time 1.97 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 199188 kb
Host smart-39d40b2f-a352-41eb-b0e5-0aa9329050bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804186320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1804186320
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3138397351
Short name T258
Test name
Test status
Simulation time 129622064619 ps
CPU time 70.86 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:27:51 PM PDT 24
Peak memory 208256 kb
Host smart-b60d5614-7481-4d7f-a591-dfc8d03bc0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138397351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3138397351
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.4100526017
Short name T962
Test name
Test status
Simulation time 11975851581 ps
CPU time 715.29 seconds
Started Jul 24 04:26:38 PM PDT 24
Finished Jul 24 04:38:33 PM PDT 24
Peak memory 199908 kb
Host smart-f732947b-c4bf-43aa-9999-70f670d820a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100526017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4100526017
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2967885246
Short name T778
Test name
Test status
Simulation time 7505450817 ps
CPU time 59.79 seconds
Started Jul 24 04:26:46 PM PDT 24
Finished Jul 24 04:27:46 PM PDT 24
Peak memory 198104 kb
Host smart-41c1de6a-03ea-4cad-9cab-df9d5e6262ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967885246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2967885246
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2236632530
Short name T991
Test name
Test status
Simulation time 174736431138 ps
CPU time 76.22 seconds
Started Jul 24 04:26:44 PM PDT 24
Finished Jul 24 04:28:01 PM PDT 24
Peak memory 199904 kb
Host smart-2f12ace3-c83f-4bb4-9eeb-23e23d18759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236632530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2236632530
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.955530877
Short name T269
Test name
Test status
Simulation time 5108181980 ps
CPU time 2.39 seconds
Started Jul 24 04:26:34 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 196396 kb
Host smart-9569b4b7-6756-4464-8996-8ffe7879c1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955530877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.955530877
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.697178978
Short name T847
Test name
Test status
Simulation time 608083577 ps
CPU time 2.52 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:26:43 PM PDT 24
Peak memory 199700 kb
Host smart-3563429b-5e66-4fed-861a-1aa3200c6001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697178978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.697178978
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1422283763
Short name T55
Test name
Test status
Simulation time 79799135252 ps
CPU time 399.24 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:33:14 PM PDT 24
Peak memory 215992 kb
Host smart-5b4730e7-648b-4cca-bfc4-454867c40b1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422283763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1422283763
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4161823192
Short name T1091
Test name
Test status
Simulation time 6016469956 ps
CPU time 1.72 seconds
Started Jul 24 04:26:35 PM PDT 24
Finished Jul 24 04:26:37 PM PDT 24
Peak memory 199256 kb
Host smart-8cde404a-c480-4c4f-921c-519f07accf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161823192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4161823192
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4244412030
Short name T297
Test name
Test status
Simulation time 158007287501 ps
CPU time 123.46 seconds
Started Jul 24 04:26:41 PM PDT 24
Finished Jul 24 04:28:45 PM PDT 24
Peak memory 199864 kb
Host smart-6f3317ad-c1b8-48db-b8cb-ab58c9d7fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244412030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4244412030
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3558499362
Short name T218
Test name
Test status
Simulation time 144580312916 ps
CPU time 42.64 seconds
Started Jul 24 04:30:04 PM PDT 24
Finished Jul 24 04:30:47 PM PDT 24
Peak memory 199916 kb
Host smart-d2a3833d-f025-4662-8692-4074721c3df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558499362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3558499362
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.336911973
Short name T1062
Test name
Test status
Simulation time 69056832161 ps
CPU time 114.87 seconds
Started Jul 24 04:30:08 PM PDT 24
Finished Jul 24 04:32:03 PM PDT 24
Peak memory 199904 kb
Host smart-3882ec7d-22aa-4e35-bf41-3729547879dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336911973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.336911973
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.4170230897
Short name T1005
Test name
Test status
Simulation time 51596032803 ps
CPU time 719.38 seconds
Started Jul 24 04:30:06 PM PDT 24
Finished Jul 24 04:42:05 PM PDT 24
Peak memory 226072 kb
Host smart-b0107254-31b3-4987-8038-d224039d59b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170230897 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.4170230897
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.696315933
Short name T536
Test name
Test status
Simulation time 139785750835 ps
CPU time 55.12 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 199912 kb
Host smart-a9df6238-1ec0-4367-8bde-6e977018a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696315933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.696315933
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.842155668
Short name T323
Test name
Test status
Simulation time 30314080448 ps
CPU time 279.61 seconds
Started Jul 24 04:31:16 PM PDT 24
Finished Jul 24 04:35:56 PM PDT 24
Peak memory 213448 kb
Host smart-b832d0c5-4f52-4601-bc91-e79c7002f913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842155668 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.842155668
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3131472974
Short name T191
Test name
Test status
Simulation time 348050343161 ps
CPU time 98.2 seconds
Started Jul 24 04:30:06 PM PDT 24
Finished Jul 24 04:31:44 PM PDT 24
Peak memory 200016 kb
Host smart-569dfed9-70b8-4f1a-9684-85968a1f95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131472974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3131472974
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.553910033
Short name T722
Test name
Test status
Simulation time 82895884806 ps
CPU time 185.33 seconds
Started Jul 24 04:30:06 PM PDT 24
Finished Jul 24 04:33:11 PM PDT 24
Peak memory 216496 kb
Host smart-d44d4183-88c4-43f2-806b-0dcf0fa3f61d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553910033 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.553910033
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1366877925
Short name T130
Test name
Test status
Simulation time 174942652612 ps
CPU time 81.13 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:31:27 PM PDT 24
Peak memory 199948 kb
Host smart-9ad40600-a857-4f9e-82de-95a79e1b0289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366877925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1366877925
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2514326378
Short name T658
Test name
Test status
Simulation time 17024423472 ps
CPU time 174.45 seconds
Started Jul 24 04:30:05 PM PDT 24
Finished Jul 24 04:33:00 PM PDT 24
Peak memory 216524 kb
Host smart-f8226894-a966-425e-b723-8bbf09291092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514326378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2514326378
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2893745648
Short name T142
Test name
Test status
Simulation time 71249586782 ps
CPU time 26.34 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:30:36 PM PDT 24
Peak memory 199980 kb
Host smart-c82e0971-f003-4522-a9e0-d2fe02ed46de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893745648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2893745648
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1433089968
Short name T57
Test name
Test status
Simulation time 490058619882 ps
CPU time 718.03 seconds
Started Jul 24 04:30:11 PM PDT 24
Finished Jul 24 04:42:09 PM PDT 24
Peak memory 224840 kb
Host smart-2dbe3d13-590a-45f0-b4f9-44df58359af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433089968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1433089968
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2194482509
Short name T929
Test name
Test status
Simulation time 30059159959 ps
CPU time 33.47 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:30:43 PM PDT 24
Peak memory 199904 kb
Host smart-58307ef9-5d0f-429a-99cd-0113da261c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194482509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2194482509
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2737454923
Short name T98
Test name
Test status
Simulation time 255975841251 ps
CPU time 364.69 seconds
Started Jul 24 04:31:16 PM PDT 24
Finished Jul 24 04:37:21 PM PDT 24
Peak memory 210260 kb
Host smart-d3e24716-6cbb-4fd8-ac76-16829f89e5ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737454923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2737454923
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2659419528
Short name T979
Test name
Test status
Simulation time 33538805647 ps
CPU time 18.15 seconds
Started Jul 24 04:30:11 PM PDT 24
Finished Jul 24 04:30:29 PM PDT 24
Peak memory 199928 kb
Host smart-9f316f62-e02a-43fb-b3ec-e1c14a717f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659419528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2659419528
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1797115441
Short name T1020
Test name
Test status
Simulation time 66325681662 ps
CPU time 316.2 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:35:26 PM PDT 24
Peak memory 216496 kb
Host smart-c9be0ecd-4d19-44da-8645-9cbe2e09111b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797115441 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1797115441
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3386792501
Short name T205
Test name
Test status
Simulation time 232589136248 ps
CPU time 22.74 seconds
Started Jul 24 04:30:12 PM PDT 24
Finished Jul 24 04:30:35 PM PDT 24
Peak memory 199948 kb
Host smart-757ae2b7-808b-4cf4-90ce-2819e314e5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386792501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3386792501
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3072329660
Short name T673
Test name
Test status
Simulation time 16636985934 ps
CPU time 147.06 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:32:38 PM PDT 24
Peak memory 216636 kb
Host smart-5cb0a75b-5c9f-4cab-9283-049b4dd673c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072329660 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3072329660
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.362792756
Short name T306
Test name
Test status
Simulation time 90766424531 ps
CPU time 164.22 seconds
Started Jul 24 04:30:10 PM PDT 24
Finished Jul 24 04:32:54 PM PDT 24
Peak memory 200048 kb
Host smart-a7030ca5-b76f-4462-8dc2-9ce61311eb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362792756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.362792756
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.709017517
Short name T51
Test name
Test status
Simulation time 88912700494 ps
CPU time 402.78 seconds
Started Jul 24 04:31:16 PM PDT 24
Finished Jul 24 04:37:59 PM PDT 24
Peak memory 224600 kb
Host smart-869419c7-7356-479b-b034-1068cfdf5e7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709017517 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.709017517
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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