Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	125878	1			T1	7		T2	15		T3	46
all_values[1]	125878	1			T1	7		T2	15		T3	46
all_values[2]	125878	1			T1	7		T2	15		T3	46
all_values[3]	125878	1			T1	7		T2	15		T3	46
all_values[4]	125878	1			T1	7		T2	15		T3	46
all_values[5]	125878	1			T1	7		T2	15		T3	46
all_values[6]	125878	1			T1	7		T2	15		T3	46
all_values[7]	125878	1			T1	7		T2	15		T3	46
all_values[8]	125878	1			T1	7		T2	15		T3	46

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574904

1

T1

39

T2

52

T3

246

auto[1]

557998

1

T1

24

T2

83

T3

168

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020693

1

T1

46

T2

113

T3

392

auto[1]

112209

1

T1

17

T2

22

T3

22

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35468	1			T3	8		T4	13		T8	81
all_values[0]	auto[0]	auto[1]	30014	1			T1	7		T2	2		T3	7
all_values[0]	auto[1]	auto[0]	33343	1			T2	5		T3	27		T4	12
all_values[0]	auto[1]	auto[1]	27053	1			T2	8		T3	4		T4	2
all_values[1]	auto[0]	auto[0]	60861	1			T1	4		T2	13		T3	11
all_values[1]	auto[0]	auto[1]	1792	1			T10	8		T40	1		T11	34
all_values[1]	auto[1]	auto[0]	61212	1			T1	3		T2	2		T3	35
all_values[1]	auto[1]	auto[1]	2013	1			T8	1		T19	1		T40	8
all_values[2]	auto[0]	auto[0]	63856	1			T1	3		T3	34		T4	19
all_values[2]	auto[0]	auto[1]	2787	1			T1	1		T4	6		T5	1
all_values[2]	auto[1]	auto[0]	56681	1			T1	2		T2	13		T3	11
all_values[2]	auto[1]	auto[1]	2554	1			T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[0]	60346	1			T1	1		T2	2		T3	39
all_values[3]	auto[0]	auto[1]	314	1			T1	3		T11	3		T88	1
all_values[3]	auto[1]	auto[0]	64895	1			T1	2		T2	13		T3	7
all_values[3]	auto[1]	auto[1]	323	1			T1	1		T12	1		T15	3
all_values[4]	auto[0]	auto[0]	64156	1			T1	4		T2	13		T3	38
all_values[4]	auto[0]	auto[1]	480	1			T13	13		T15	4		T16	2
all_values[4]	auto[1]	auto[0]	60762	1			T1	3		T2	2		T3	8
all_values[4]	auto[1]	auto[1]	480	1			T16	3		T45	1		T247	5
all_values[5]	auto[0]	auto[0]	65580	1			T1	1		T2	15		T3	15
all_values[5]	auto[0]	auto[1]	171	1			T16	1		T45	2		T38	5
all_values[5]	auto[1]	auto[0]	59937	1			T1	6		T3	31		T4	20
all_values[5]	auto[1]	auto[1]	190	1			T16	4		T45	4		T39	3
all_values[6]	auto[0]	auto[0]	68822	1			T1	4		T2	4		T3	45
all_values[6]	auto[0]	auto[1]	184	1			T16	3		T34	2		T38	2
all_values[6]	auto[1]	auto[0]	56681	1			T1	3		T2	11		T3	1
all_values[6]	auto[1]	auto[1]	191	1			T45	1		T33	3		T38	4
all_values[7]	auto[0]	auto[0]	62215	1			T1	7		T2	2		T3	34
all_values[7]	auto[0]	auto[1]	357	1			T15	1		T23	1		T44	1
all_values[7]	auto[1]	auto[0]	62912	1			T2	13		T3	12		T4	18
all_values[7]	auto[1]	auto[1]	394	1			T16	1		T128	2		T129	1
all_values[8]	auto[0]	auto[0]	35478	1			T3	12		T4	30		T8	117
all_values[8]	auto[0]	auto[1]	22023	1			T1	4		T2	1		T3	3
all_values[8]	auto[1]	auto[0]	47488	1			T1	3		T2	5		T3	24
all_values[8]	auto[1]	auto[1]	20889	1			T2	9		T3	7		T8	16