Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2545

1

T1

1

T2

1

T3

6

auto[UartRx]

2545

1

T1

1

T2

1

T3

6

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4500	1			T1	2		T2	2		T3	8
values[1]	52	1			T3	1		T24	1		T34	1
values[2]	42	1			T24	1		T34	1		T35	1
values[3]	47	1			T33	1		T37	2		T39	1
values[4]	59	1			T33	2		T36	2		T37	1
values[5]	47	1			T24	1		T34	2		T36	1
values[6]	53	1			T37	2		T38	1		T39	1
values[7]	50	1			T24	1		T34	1		T37	2
values[8]	67	1			T3	2		T24	2		T34	3
values[9]	69	1			T33	1		T36	1		T38	1
values[10]	71	1			T3	1		T23	1		T34	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2336	1			T1	1		T2	1		T3	4
auto[UartTx]	values[1]	21	1			T38	1		T47	1		T114	1
auto[UartTx]	values[2]	13	1			T24	1		T300	1		T308	1
auto[UartTx]	values[3]	17	1			T47	1		T110	1		T157	1
auto[UartTx]	values[4]	21	1			T33	1		T37	1		T39	1
auto[UartTx]	values[5]	15	1			T34	1		T180	1		T312	1
auto[UartTx]	values[6]	18	1			T37	1		T313	1		T111	1
auto[UartTx]	values[7]	17	1			T37	1		T113	1		T314	1
auto[UartTx]	values[8]	27	1			T3	1		T24	1		T34	1
auto[UartTx]	values[9]	16	1			T38	1		T47	1		T157	1
auto[UartTx]	values[10]	30	1			T3	1		T34	1		T35	1
auto[UartRx]	values[0]	2164	1			T1	1		T2	1		T3	4
auto[UartRx]	values[1]	31	1			T3	1		T24	1		T34	1
auto[UartRx]	values[2]	29	1			T34	1		T35	1		T38	1
auto[UartRx]	values[3]	30	1			T33	1		T37	2		T39	1
auto[UartRx]	values[4]	38	1			T33	1		T36	2		T39	1
auto[UartRx]	values[5]	32	1			T24	1		T34	1		T36	1
auto[UartRx]	values[6]	35	1			T37	1		T38	1		T39	1
auto[UartRx]	values[7]	33	1			T24	1		T34	1		T37	1
auto[UartRx]	values[8]	40	1			T3	1		T24	1		T34	2
auto[UartRx]	values[9]	53	1			T33	1		T36	1		T315	1
auto[UartRx]	values[10]	41	1			T23	1		T35	1		T36	1