Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2214	1			T2	4		T3	2		T4	3
auto[BaudRate115200]	1955	1			T1	1		T2	3		T3	1
auto[BaudRate230400]	2014	1			T1	4		T2	2		T3	1
auto[BaudRate128Kbps]	1863	1			T1	2		T2	2		T3	1
auto[BaudRate256Kbps]	2194	1			T1	1		T2	4		T3	2
auto[BaudRate1Mbps]	1809	1			T1	1		T3	3		T4	1
auto[BaudRate1p5Mbps]	1311	1			T3	4		T4	1		T7	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1692	1			T87	6		T14	16		T253	13
freqs[25]	1324	1			T3	14		T15	1		T270	5
freqs[48]	893	1			T11	9		T21	54		T254	4
freqs[50]	536	1			T255	13		T102	2		T38	45
freqs[100]	1027	1			T25	2		T26	2		T88	7

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	307	1			T14	16		T253	3		T248	1
auto[BaudRate9600]	freqs[25]	229	1			T3	2		T301	2		T316	9
auto[BaudRate9600]	freqs[48]	141	1			T21	18		T130	1		T159	1
auto[BaudRate9600]	freqs[50]	98	1			T255	1		T38	6		T117	3
auto[BaudRate9600]	freqs[100]	162	1			T120	2		T24	5		T33	3
auto[BaudRate115200]	freqs[24]	262	1			T253	2		T248	1		T23	7
auto[BaudRate115200]	freqs[25]	207	1			T3	1		T270	1		T266	2
auto[BaudRate115200]	freqs[48]	139	1			T11	2		T21	9		T254	1
auto[BaudRate115200]	freqs[50]	75	1			T38	9		T117	7		T317	1
auto[BaudRate115200]	freqs[100]	131	1			T120	1		T24	5		T33	2
auto[BaudRate230400]	freqs[24]	250	1			T248	1		T23	9		T250	1
auto[BaudRate230400]	freqs[25]	229	1			T3	1		T270	2		T266	3
auto[BaudRate230400]	freqs[48]	103	1			T11	1		T21	6		T254	1
auto[BaudRate230400]	freqs[50]	57	1			T255	2		T102	1		T38	4
auto[BaudRate230400]	freqs[100]	150	1			T88	2		T120	2		T24	6
auto[BaudRate128Kbps]	freqs[24]	242	1			T253	2		T23	9		T268	3
auto[BaudRate128Kbps]	freqs[25]	160	1			T3	1		T15	1		T266	1
auto[BaudRate128Kbps]	freqs[48]	112	1			T21	3		T254	1		T130	2
auto[BaudRate128Kbps]	freqs[50]	63	1			T255	1		T102	1		T38	7
auto[BaudRate128Kbps]	freqs[100]	157	1			T120	1		T24	4		T33	2
auto[BaudRate256Kbps]	freqs[24]	253	1			T87	2		T253	1		T23	11
auto[BaudRate256Kbps]	freqs[25]	207	1			T3	2		T270	2		T318	2
auto[BaudRate256Kbps]	freqs[48]	143	1			T11	4		T21	9		T254	1
auto[BaudRate256Kbps]	freqs[50]	74	1			T255	3		T38	9		T48	2
auto[BaudRate256Kbps]	freqs[100]	154	1			T25	2		T26	2		T88	1
auto[BaudRate1Mbps]	freqs[24]	236	1			T87	1		T253	2		T248	2
auto[BaudRate1Mbps]	freqs[25]	196	1			T3	3		T266	1		T301	1
auto[BaudRate1Mbps]	freqs[48]	116	1			T11	2		T21	3		T159	1
auto[BaudRate1Mbps]	freqs[50]	76	1			T255	5		T38	5		T117	4
auto[BaudRate1Mbps]	freqs[100]	140	1			T88	1		T24	5		T135	1
auto[BaudRate1p5Mbps]	freqs[25]	96	1			T3	4		T108	2		T316	6
auto[BaudRate1p5Mbps]	freqs[48]	139	1			T21	6		T128	1		T130	2
auto[BaudRate1p5Mbps]	freqs[50]	93	1			T255	1		T38	5		T117	5
auto[BaudRate1p5Mbps]	freqs[100]	133	1			T88	3		T18	1		T24	8

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded