Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	38284377	1			T1	16		T2	192		T3	11073
all_levels[1]	191859	1			T2	11		T3	1764		T4	18
all_levels[2]	2694	1			T2	1		T3	23		T4	6
all_levels[3]	1238	1			T2	1		T4	4		T8	11
all_levels[4]	860	1			T1	2		T2	2		T3	1
all_levels[5]	590	1			T4	2		T8	8		T19	1
all_levels[6]	447	1			T2	1		T3	1		T4	1
all_levels[7]	407	1			T2	1		T3	1		T4	2
all_levels[8]	270	1			T3	1		T8	2		T10	1
all_levels[9]	277	1			T8	4		T19	1		T42	2
all_levels[10]	233	1			T2	1		T8	2		T10	1
all_levels[11]	182	1			T2	1		T8	1		T10	1
all_levels[12]	177	1			T2	1		T8	2		T10	1
all_levels[13]	128	1			T8	3		T10	1		T19	1
all_levels[14]	130	1			T2	1		T12	2		T42	1
all_levels[15]	113	1			T3	1		T19	1		T88	1
all_levels[16]	121	1			T127	2		T128	1		T89	2
all_levels[17]	83	1			T1	1		T19	1		T16	1
all_levels[18]	85	1			T19	1		T129	1		T130	1
all_levels[19]	94	1			T11	3		T130	1		T131	1
all_levels[20]	88	1			T3	1		T127	1		T128	2
all_levels[21]	70	1			T10	1		T127	2		T44	1
all_levels[22]	55	1			T8	1		T128	1		T132	1
all_levels[23]	65	1			T3	1		T44	1		T89	2
all_levels[24]	51	1			T10	1		T120	1		T131	1
all_levels[25]	50	1			T19	1		T16	1		T128	1
all_levels[26]	44	1			T129	1		T133	2		T120	1
all_levels[27]	57	1			T1	1		T3	1		T8	1
all_levels[28]	56	1			T44	1		T134	1		T135	1
all_levels[29]	41	1			T136	1		T89	1		T120	1
all_levels[30]	24	1			T19	1		T137	1		T138	2
all_levels[31]	32	1			T119	5		T24	1		T139	1
all_levels[32]	22	1			T140	1		T89	1		T141	1
all_levels[33]	17	1			T43	1		T105	1		T35	3
all_levels[34]	20	1			T142	1		T143	1		T116	1
all_levels[35]	15	1			T23	1		T144	1		T38	1
all_levels[36]	28	1			T43	2		T89	1		T141	1
all_levels[37]	25	1			T145	1		T146	2		T147	1
all_levels[38]	19	1			T8	1		T23	1		T128	1
all_levels[39]	19	1			T3	1		T148	1		T149	1
all_levels[40]	18	1			T109	1		T150	1		T149	1
all_levels[41]	20	1			T140	1		T151	3		T152	1
all_levels[42]	16	1			T35	2		T137	1		T153	2
all_levels[43]	22	1			T154	3		T155	1		T156	1
all_levels[44]	23	1			T42	1		T44	1		T36	1
all_levels[45]	16	1			T54	1		T157	1		T158	1
all_levels[46]	12	1			T42	1		T16	2		T142	2
all_levels[47]	17	1			T109	1		T34	3		T148	1
all_levels[48]	13	1			T10	1		T159	1		T160	1
all_levels[49]	10	1			T155	1		T109	1		T138	3
all_levels[50]	16	1			T119	1		T137	1		T161	2
all_levels[51]	13	1			T150	1		T153	1		T162	1
all_levels[52]	7	1			T154	2		T138	1		T163	1
all_levels[53]	14	1			T148	1		T146	1		T164	1
all_levels[54]	16	1			T1	1		T109	1		T34	1
all_levels[55]	6	1			T165	1		T166	1		T167	2
all_levels[56]	8	1			T115	1		T168	1		T169	1
all_levels[57]	9	1			T170	1		T171	1		T162	3
all_levels[58]	6	1			T172	1		T58	1		T173	1
all_levels[59]	3	1			T119	1		T54	1		T174	1
all_levels[60]	3	1			T172	1		T175	1		T174	1
all_levels[61]	8	1			T176	1		T177	1		T178	1
all_levels[62]	6	1			T179	1		T180	1		T181	1
all_levels[63]	7	1			T122	1		T139	1		T182	1
all_levels[64]	91	1			T1	1		T11	3		T88	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38480637

1

T1

15

T2

213

T3

12869

auto[1]

4906

1

T1

7

T10

4

T19

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[38] , all_levels[39]]	[auto[1]]	--	--	2
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59] , all_levels[60]]	[auto[1]]	--	--	3
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	38279936	1			T1	10		T2	192		T3	11073
all_levels[0]	auto[1]	4441	1			T1	6		T10	3		T19	6
all_levels[1]	auto[0]	191784	1			T2	11		T3	1764		T4	18
all_levels[1]	auto[1]	75	1			T10	1		T43	1		T154	1
all_levels[2]	auto[0]	2664	1			T2	1		T3	23		T4	6
all_levels[2]	auto[1]	30	1			T12	1		T183	1		T184	1
all_levels[3]	auto[0]	1226	1			T2	1		T4	4		T8	11
all_levels[3]	auto[1]	12	1			T122	1		T141	1		T185	1
all_levels[4]	auto[0]	835	1			T1	1		T2	2		T3	1
all_levels[4]	auto[1]	25	1			T1	1		T11	1		T186	3
all_levels[5]	auto[0]	568	1			T4	2		T8	8		T19	1
all_levels[5]	auto[1]	22	1			T43	1		T23	1		T187	1
all_levels[6]	auto[0]	423	1			T2	1		T3	1		T4	1
all_levels[6]	auto[1]	24	1			T24	1		T152	1		T188	1
all_levels[7]	auto[0]	393	1			T2	1		T3	1		T4	2
all_levels[7]	auto[1]	14	1			T135	1		T189	1		T190	1
all_levels[8]	auto[0]	258	1			T3	1		T8	2		T10	1
all_levels[8]	auto[1]	12	1			T144	1		T191	1		T152	1
all_levels[9]	auto[0]	253	1			T8	4		T19	1		T42	2
all_levels[9]	auto[1]	24	1			T192	2		T35	1		T193	1
all_levels[10]	auto[0]	221	1			T2	1		T8	2		T10	1
all_levels[10]	auto[1]	12	1			T194	2		T195	2		T196	1
all_levels[11]	auto[0]	169	1			T2	1		T8	1		T10	1
all_levels[11]	auto[1]	13	1			T141	1		T197	2		T198	2
all_levels[12]	auto[0]	156	1			T2	1		T8	2		T10	1
all_levels[12]	auto[1]	21	1			T160	1		T199	2		T200	3
all_levels[13]	auto[0]	119	1			T8	3		T10	1		T19	1
all_levels[13]	auto[1]	9	1			T105	2		T201	1		T202	1
all_levels[14]	auto[0]	116	1			T2	1		T12	1		T42	1
all_levels[14]	auto[1]	14	1			T12	1		T203	2		T144	1
all_levels[15]	auto[0]	103	1			T3	1		T19	1		T88	1
all_levels[15]	auto[1]	10	1			T134	1		T199	1		T204	2
all_levels[16]	auto[0]	110	1			T127	2		T128	1		T89	2
all_levels[16]	auto[1]	11	1			T205	2		T54	1		T206	1
all_levels[17]	auto[0]	76	1			T1	1		T19	1		T16	1
all_levels[17]	auto[1]	7	1			T191	2		T207	1		T208	1
all_levels[18]	auto[0]	78	1			T19	1		T129	1		T130	1
all_levels[18]	auto[1]	7	1			T209	2		T162	1		T210	1
all_levels[19]	auto[0]	85	1			T11	1		T130	1		T131	1
all_levels[19]	auto[1]	9	1			T11	2		T189	1		T211	1
all_levels[20]	auto[0]	82	1			T3	1		T127	1		T128	2
all_levels[20]	auto[1]	6	1			T152	2		T209	1		T212	1
all_levels[21]	auto[0]	67	1			T10	1		T127	1		T44	1
all_levels[21]	auto[1]	3	1			T127	1		T150	1		T213	1
all_levels[22]	auto[0]	51	1			T8	1		T128	1		T132	1
all_levels[22]	auto[1]	4	1			T214	1		T147	2		T215	1
all_levels[23]	auto[0]	58	1			T3	1		T44	1		T89	2
all_levels[23]	auto[1]	7	1			T201	1		T216	1		T217	1
all_levels[24]	auto[0]	47	1			T10	1		T120	1		T131	1
all_levels[24]	auto[1]	4	1			T218	1		T219	1		T58	1
all_levels[25]	auto[0]	46	1			T19	1		T16	1		T128	1
all_levels[25]	auto[1]	4	1			T220	1		T221	1		T222	1
all_levels[26]	auto[0]	42	1			T129	1		T133	2		T120	1
all_levels[26]	auto[1]	2	1			T131	1		T182	1		-	-
all_levels[27]	auto[0]	51	1			T1	1		T3	1		T8	1
all_levels[27]	auto[1]	6	1			T138	1		T223	2		T224	1
all_levels[28]	auto[0]	47	1			T44	1		T134	1		T135	1
all_levels[28]	auto[1]	9	1			T225	1		T226	2		T227	1
all_levels[29]	auto[0]	39	1			T136	1		T89	1		T120	1
all_levels[29]	auto[1]	2	1			T220	1		T228	1		-	-
all_levels[30]	auto[0]	24	1			T19	1		T137	1		T138	2
all_levels[31]	auto[0]	27	1			T119	1		T24	1		T139	1
all_levels[31]	auto[1]	5	1			T119	4		T229	1		-	-
all_levels[32]	auto[0]	20	1			T140	1		T89	1		T141	1
all_levels[32]	auto[1]	2	1			T144	1		T212	1		-	-
all_levels[33]	auto[0]	15	1			T43	1		T105	1		T35	1
all_levels[33]	auto[1]	2	1			T35	2		-	-		-	-
all_levels[34]	auto[0]	17	1			T142	1		T143	1		T116	1
all_levels[34]	auto[1]	3	1			T230	3		-	-		-	-
all_levels[35]	auto[0]	15	1			T23	1		T144	1		T38	1
all_levels[36]	auto[0]	26	1			T43	1		T89	1		T141	1
all_levels[36]	auto[1]	2	1			T43	1		T209	1		-	-
all_levels[37]	auto[0]	22	1			T145	1		T146	1		T147	1
all_levels[37]	auto[1]	3	1			T146	1		T231	1		T232	1
all_levels[38]	auto[0]	19	1			T8	1		T23	1		T128	1
all_levels[39]	auto[0]	19	1			T3	1		T148	1		T149	1
all_levels[40]	auto[0]	16	1			T109	1		T150	1		T149	1
all_levels[40]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[41]	auto[0]	17	1			T140	1		T151	1		T152	1
all_levels[41]	auto[1]	3	1			T151	2		T234	1		-	-
all_levels[42]	auto[0]	14	1			T35	2		T137	1		T153	1
all_levels[42]	auto[1]	2	1			T153	1		T235	1		-	-
all_levels[43]	auto[0]	18	1			T154	1		T155	1		T156	1
all_levels[43]	auto[1]	4	1			T154	2		T236	1		T237	1
all_levels[44]	auto[0]	20	1			T42	1		T44	1		T36	1
all_levels[44]	auto[1]	3	1			T182	1		T238	1		T239	1
all_levels[45]	auto[0]	14	1			T54	1		T157	1		T158	1
all_levels[45]	auto[1]	2	1			T240	1		T241	1		-	-
all_levels[46]	auto[0]	12	1			T42	1		T16	2		T142	2
all_levels[47]	auto[0]	14	1			T109	1		T34	1		T148	1
all_levels[47]	auto[1]	3	1			T34	2		T242	1		-	-
all_levels[48]	auto[0]	13	1			T10	1		T159	1		T160	1
all_levels[49]	auto[0]	7	1			T155	1		T109	1		T138	1
all_levels[49]	auto[1]	3	1			T138	2		T243	1		-	-
all_levels[50]	auto[0]	9	1			T119	1		T137	1		T161	1
all_levels[50]	auto[1]	7	1			T161	1		T244	3		T232	3
all_levels[51]	auto[0]	12	1			T150	1		T153	1		T162	1
all_levels[51]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[52]	auto[0]	6	1			T154	1		T138	1		T163	1
all_levels[52]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[53]	auto[0]	14	1			T148	1		T146	1		T164	1
all_levels[54]	auto[0]	11	1			T1	1		T109	1		T34	1
all_levels[54]	auto[1]	5	1			T246	5		-	-		-	-
all_levels[55]	auto[0]	5	1			T165	1		T166	1		T167	1
all_levels[55]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[56]	auto[0]	8	1			T115	1		T168	1		T169	1
all_levels[57]	auto[0]	7	1			T170	1		T171	1		T162	1
all_levels[57]	auto[1]	2	1			T162	2		-	-		-	-
all_levels[58]	auto[0]	6	1			T172	1		T58	1		T173	1
all_levels[59]	auto[0]	3	1			T119	1		T54	1		T174	1
all_levels[60]	auto[0]	3	1			T172	1		T175	1		T174	1
all_levels[61]	auto[0]	6	1			T176	1		T177	1		T178	1
all_levels[61]	auto[1]	2	1			T195	2		-	-		-	-
all_levels[62]	auto[0]	6	1			T179	1		T180	1		T181	1
all_levels[63]	auto[0]	7	1			T122	1		T139	1		T182	1
all_levels[64]	auto[0]	82	1			T1	1		T11	2		T88	1
all_levels[64]	auto[1]	9	1			T11	1		T122	2		T54	1