Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	125878	1			T1	7		T2	15		T3	46
all_pins[1]	125878	1			T1	7		T2	15		T3	46
all_pins[2]	125878	1			T1	7		T2	15		T3	46
all_pins[3]	125878	1			T1	7		T2	15		T3	46
all_pins[4]	125878	1			T1	7		T2	15		T3	46
all_pins[5]	125878	1			T1	7		T2	15		T3	46
all_pins[6]	125878	1			T1	7		T2	15		T3	46
all_pins[7]	125878	1			T1	7		T2	15		T3	46
all_pins[8]	125878	1			T1	7		T2	15		T3	46

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1077810	1			T1	61		T2	115		T3	402
values[0x1]	55092	1			T1	2		T2	20		T3	12
transitions[0x0=>0x1]	44602	1			T1	2		T2	13		T3	10
transitions[0x1=>0x0]	44383	1			T1	2		T2	13		T3	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98747	1			T1	7		T2	7		T3	42
all_pins[0]	values[0x1]	27131	1			T2	8		T3	4		T4	2
all_pins[0]	transitions[0x0=>0x1]	26478	1			T2	8		T3	4		T4	2
all_pins[0]	transitions[0x1=>0x0]	1359	1			T8	1		T40	3		T13	2
all_pins[1]	values[0x0]	123866	1			T1	7		T2	15		T3	46
all_pins[1]	values[0x1]	2012	1			T8	1		T19	1		T40	8
all_pins[1]	transitions[0x0=>0x1]	1886	1			T40	8		T13	2		T42	2
all_pins[1]	transitions[0x1=>0x0]	2487	1			T1	1		T2	2		T3	1
all_pins[2]	values[0x0]	123265	1			T1	6		T2	13		T3	45
all_pins[2]	values[0x1]	2613	1			T1	1		T2	2		T3	1
all_pins[2]	transitions[0x0=>0x1]	2535	1			T1	1		T2	2		T3	1
all_pins[2]	transitions[0x1=>0x0]	245	1			T1	1		T15	3		T16	3
all_pins[3]	values[0x0]	125555	1			T1	6		T2	15		T3	46
all_pins[3]	values[0x1]	323	1			T1	1		T12	1		T15	3
all_pins[3]	transitions[0x0=>0x1]	287	1			T1	1		T12	1		T15	3
all_pins[3]	transitions[0x1=>0x0]	444	1			T16	1		T247	5		T141	3
all_pins[4]	values[0x0]	125398	1			T1	7		T2	15		T3	46
all_pins[4]	values[0x1]	480	1			T16	3		T45	1		T247	5
all_pins[4]	transitions[0x0=>0x1]	415	1			T16	1		T45	1		T247	4
all_pins[4]	transitions[0x1=>0x0]	182	1			T16	2		T45	4		T89	2
all_pins[5]	values[0x0]	125631	1			T1	7		T2	15		T3	46
all_pins[5]	values[0x1]	247	1			T16	4		T45	4		T89	2
all_pins[5]	transitions[0x0=>0x1]	190	1			T16	4		T45	3		T89	2
all_pins[5]	transitions[0x1=>0x0]	867	1			T2	1		T8	6		T11	1
all_pins[6]	values[0x0]	124954	1			T1	7		T2	14		T3	46
all_pins[6]	values[0x1]	924	1			T2	1		T8	6		T11	1
all_pins[6]	transitions[0x0=>0x1]	862	1			T2	1		T8	6		T11	1
all_pins[6]	transitions[0x1=>0x0]	332	1			T16	1		T129	1		T136	1
all_pins[7]	values[0x0]	125484	1			T1	7		T2	15		T3	46
all_pins[7]	values[0x1]	394	1			T16	1		T128	2		T129	1
all_pins[7]	transitions[0x0=>0x1]	228	1			T16	1		T128	2		T129	1
all_pins[7]	transitions[0x1=>0x0]	20802	1			T2	9		T3	7		T8	16
all_pins[8]	values[0x0]	104910	1			T1	7		T2	6		T3	39
all_pins[8]	values[0x1]	20968	1			T2	9		T3	7		T8	16
all_pins[8]	transitions[0x0=>0x1]	11721	1			T2	2		T3	5		T8	6
all_pins[8]	transitions[0x1=>0x0]	17665	1			T2	1		T3	2		T4	2