Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	11736529	1			T1	8		T2	41		T3	1741
all_levels[1]	2092698	1			T1	9		T3	16		T4	1
all_levels[2]	515203	1			T3	15		T4	7		T8	121
all_levels[3]	739712	1			T1	3		T2	1		T3	16
all_levels[4]	666236	1			T2	2		T3	13		T4	7
all_levels[5]	277193	1			T2	28		T3	22		T4	15
all_levels[6]	603141	1			T2	66		T3	18		T4	10
all_levels[7]	243348	1			T3	13		T4	5		T8	106
all_levels[8]	494633	1			T3	19		T4	15		T8	112
all_levels[9]	279965	1			T3	13		T4	11		T8	103
all_levels[10]	361428	1			T3	14		T4	25		T8	102
all_levels[11]	227796	1			T1	3		T3	14		T4	31
all_levels[12]	435720	1			T3	17		T4	8		T8	102
all_levels[13]	431844	1			T3	15		T4	5		T8	102
all_levels[14]	649470	1			T3	16		T4	7		T8	119
all_levels[15]	410232	1			T3	12		T8	94		T9	32
all_levels[16]	379149	1			T3	14		T8	106		T9	38
all_levels[17]	362351	1			T2	10		T3	10		T8	99
all_levels[18]	211374	1			T3	15		T4	179		T8	106
all_levels[19]	217955	1			T3	14		T8	94		T9	39
all_levels[20]	443717	1			T3	12		T8	117		T9	36
all_levels[21]	217838	1			T2	22		T3	13		T8	104
all_levels[22]	221950	1			T3	10		T8	101		T9	51
all_levels[23]	258635	1			T2	1		T3	9		T8	109
all_levels[24]	556872	1			T3	10		T8	101		T9	43
all_levels[25]	225107	1			T3	12		T8	104		T9	36
all_levels[26]	207148	1			T2	8		T3	11		T8	104
all_levels[27]	199990	1			T2	2		T3	15		T8	95
all_levels[28]	181509	1			T3	15		T8	110		T9	36
all_levels[29]	204969	1			T2	7		T3	20		T8	115
all_levels[30]	439531	1			T3	11		T8	117		T9	42
all_levels[31]	589113	1			T2	1		T3	361		T8	2551
all_levels[32]	13402861	1			T2	25		T3	10343		T8	134149

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38480637

1

T1

15

T2

213

T3

12869

auto[1]

4580

1

T1

8

T2

1

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	11734019	1			T1	4		T2	41		T3	1741
all_levels[0]	auto[1]	2510	1			T1	4		T10	1		T19	6
all_levels[1]	auto[0]	2092367	1			T1	6		T3	16		T4	1
all_levels[1]	auto[1]	331	1			T1	3		T8	1		T23	2
all_levels[2]	auto[0]	515161	1			T3	15		T4	7		T8	121
all_levels[2]	auto[1]	42	1			T19	1		T129	1		T121	1
all_levels[3]	auto[0]	739537	1			T1	3		T2	1		T3	16
all_levels[3]	auto[1]	175	1			T13	23		T44	1		T122	2
all_levels[4]	auto[0]	666199	1			T2	2		T3	13		T4	7
all_levels[4]	auto[1]	37	1			T192	1		T105	2		T320	1
all_levels[5]	auto[0]	277173	1			T2	28		T3	22		T4	15
all_levels[5]	auto[1]	20	1			T160	1		T205	2		T171	1
all_levels[6]	auto[0]	603126	1			T2	66		T3	18		T4	10
all_levels[6]	auto[1]	15	1			T254	1		T189	1		T321	1
all_levels[7]	auto[0]	243178	1			T3	13		T4	5		T8	106
all_levels[7]	auto[1]	170	1			T12	1		T102	17		T123	34
all_levels[8]	auto[0]	494615	1			T3	19		T4	15		T8	112
all_levels[8]	auto[1]	18	1			T266	1		T322	1		T323	2
all_levels[9]	auto[0]	279939	1			T3	13		T4	11		T8	103
all_levels[9]	auto[1]	26	1			T12	1		T324	2		T325	2
all_levels[10]	auto[0]	361404	1			T3	14		T4	25		T8	102
all_levels[10]	auto[1]	24	1			T19	1		T154	1		T34	1
all_levels[11]	auto[0]	227769	1			T1	2		T3	14		T4	31
all_levels[11]	auto[1]	27	1			T1	1		T205	1		T123	1
all_levels[12]	auto[0]	435685	1			T3	17		T4	8		T8	102
all_levels[12]	auto[1]	35	1			T45	1		T211	1		T188	2
all_levels[13]	auto[0]	431821	1			T3	15		T4	5		T8	102
all_levels[13]	auto[1]	23	1			T16	1		T123	1		T138	3
all_levels[14]	auto[0]	649431	1			T3	16		T4	7		T8	119
all_levels[14]	auto[1]	39	1			T11	1		T127	1		T134	2
all_levels[15]	auto[0]	410068	1			T3	12		T8	94		T9	32
all_levels[15]	auto[1]	164	1			T139	1		T191	1		T317	3
all_levels[16]	auto[0]	379123	1			T3	14		T8	106		T9	38
all_levels[16]	auto[1]	26	1			T160	1		T149	1		T54	1
all_levels[17]	auto[0]	362336	1			T2	10		T3	10		T8	99
all_levels[17]	auto[1]	15	1			T134	1		T292	1		T326	1
all_levels[18]	auto[0]	211346	1			T3	15		T4	178		T8	106
all_levels[18]	auto[1]	28	1			T4	1		T141	1		T323	2
all_levels[19]	auto[0]	217932	1			T3	14		T8	94		T9	39
all_levels[19]	auto[1]	23	1			T197	1		T327	1		T328	1
all_levels[20]	auto[0]	443703	1			T3	12		T8	117		T9	36
all_levels[20]	auto[1]	14	1			T199	1		T225	1		T329	1
all_levels[21]	auto[0]	217817	1			T2	22		T3	13		T8	104
all_levels[21]	auto[1]	21	1			T88	1		T266	2		T330	1
all_levels[22]	auto[0]	221917	1			T3	10		T8	101		T9	51
all_levels[22]	auto[1]	33	1			T35	3		T179	1		T331	1
all_levels[23]	auto[0]	258615	1			T2	1		T3	9		T8	109
all_levels[23]	auto[1]	20	1			T128	1		T45	1		T35	1
all_levels[24]	auto[0]	556859	1			T3	10		T8	101		T9	43
all_levels[24]	auto[1]	13	1			T154	1		T332	1		T333	1
all_levels[25]	auto[0]	225084	1			T3	12		T8	104		T9	36
all_levels[25]	auto[1]	23	1			T43	1		T197	1		T187	1
all_levels[26]	auto[0]	207138	1			T2	8		T3	11		T8	104
all_levels[26]	auto[1]	10	1			T54	1		T223	1		T320	2
all_levels[27]	auto[0]	199979	1			T2	2		T3	15		T8	95
all_levels[27]	auto[1]	11	1			T43	1		T137	1		T144	1
all_levels[28]	auto[0]	181492	1			T3	15		T8	110		T9	36
all_levels[28]	auto[1]	17	1			T122	3		T157	2		T334	1
all_levels[29]	auto[0]	204953	1			T2	6		T3	20		T8	115
all_levels[29]	auto[1]	16	1			T2	1		T154	1		T335	1
all_levels[30]	auto[0]	439512	1			T3	11		T8	117		T9	42
all_levels[30]	auto[1]	19	1			T24	1		T209	1		T336	1
all_levels[31]	auto[0]	589093	1			T2	1		T3	361		T8	2551
all_levels[31]	auto[1]	20	1			T154	2		T23	2		T337	1
all_levels[32]	auto[0]	13402246	1			T2	25		T3	10343		T8	134148
all_levels[32]	auto[1]	615	1			T8	1		T10	2		T87	1