Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	783	1			T16	7		T45	7		T33	4
all_values[1]	783	1			T16	7		T45	7		T33	4
all_values[2]	783	1			T16	7		T45	7		T33	4
all_values[3]	783	1			T16	7		T45	7		T33	4
all_values[4]	783	1			T16	7		T45	7		T33	4
all_values[5]	783	1			T16	7		T45	7		T33	4
all_values[6]	783	1			T16	7		T45	7		T33	4
all_values[7]	783	1			T16	7		T45	7		T33	4
all_values[8]	783	1			T16	7		T45	7		T33	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3757

1

T16

29

T45

33

T33

22

auto[1]

3290

1

T16

34

T45

30

T33

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307

1

T16

16

T45

18

T33

15

auto[1]

4740

1

T16

47

T45

45

T33

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4191

1

T16

34

T45

34

T33

24

auto[1]

2856

1

T16

29

T45

29

T33

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	243	1			T16	2		T45	2		T38	2
all_values[0]	auto[0]	auto[1]	auto[1]	220	1			T16	2		T45	1		T33	2
all_values[0]	auto[1]	auto[0]	auto[1]	165	1			T16	2		T45	2		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	155	1			T16	1		T45	2		T38	6
all_values[1]	auto[0]	auto[0]	auto[0]	261	1			T16	1		T45	3		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	224	1			T16	4		T45	1		T33	2
all_values[1]	auto[1]	auto[0]	auto[1]	168	1			T45	3		T33	1		T34	2
all_values[1]	auto[1]	auto[1]	auto[1]	130	1			T16	2		T38	3		T39	3
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T16	1		T45	1		T33	2
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T16	2		T33	1		T38	1
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T45	1		T34	1		T38	4
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T45	2		T38	2		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T16	3		T45	2		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T16	1		T45	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T16	2		T45	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T33	1		T34	1		T38	3
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T38	3		T39	1		T117	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T16	1		T45	1		T38	2
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T16	2		T45	3		T34	2
all_values[3]	auto[1]	auto[1]	auto[1]	137	1			T16	2		T45	2		T33	2
all_values[4]	auto[0]	auto[0]	auto[0]	180	1			T45	1		T33	2		T34	2
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T16	2		T45	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	131	1			T45	1		T33	2		T38	2
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T16	1		T38	1		T39	1
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T16	2		T45	2		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	127	1			T16	2		T45	2		T38	2
all_values[5]	auto[0]	auto[0]	auto[0]	173	1			T45	1		T33	2		T34	2
all_values[5]	auto[0]	auto[0]	auto[1]	70	1			T45	1		T38	2		T39	2
all_values[5]	auto[0]	auto[1]	auto[0]	129	1			T16	1		T33	2		T38	4
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T16	3		T45	3		T38	1
all_values[5]	auto[1]	auto[0]	auto[1]	182	1			T16	1		T45	1		T34	1
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T16	2		T45	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T16	2		T45	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T16	2		T34	1		T38	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T16	2		T45	4		T38	1
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T33	2		T38	2		T39	2
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T45	1		T33	1		T34	1
all_values[6]	auto[1]	auto[1]	auto[1]	154	1			T16	1		T45	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	155	1			T45	2		T38	2		T39	3
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T33	1		T34	1		T38	2
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T16	3		T45	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T45	1		T39	2		T117	1
all_values[7]	auto[1]	auto[0]	auto[1]	181	1			T16	2		T45	2		T33	3
all_values[7]	auto[1]	auto[1]	auto[1]	168	1			T16	2		T45	1		T34	1
all_values[8]	auto[0]	auto[0]	auto[1]	237	1			T16	1		T45	2		T33	2
all_values[8]	auto[0]	auto[1]	auto[1]	245	1			T16	2		T45	2		T34	1
all_values[8]	auto[1]	auto[0]	auto[1]	155	1			T16	2		T45	1		T33	1
all_values[8]	auto[1]	auto[1]	auto[1]	146	1			T16	2		T45	2		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal