Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1317
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T1252 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1509888954 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:29 PM PDT 24 49578802 ps
T1253 /workspace/coverage/cover_reg_top/5.uart_csr_rw.4164208688 Jul 25 06:25:11 PM PDT 24 Jul 25 06:25:12 PM PDT 24 51681847 ps
T1254 /workspace/coverage/cover_reg_top/18.uart_intr_test.4172890067 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:28 PM PDT 24 23053964 ps
T1255 /workspace/coverage/cover_reg_top/41.uart_intr_test.1444375825 Jul 25 06:25:39 PM PDT 24 Jul 25 06:25:39 PM PDT 24 15598119 ps
T1256 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1327281500 Jul 25 06:25:11 PM PDT 24 Jul 25 06:25:12 PM PDT 24 43185533 ps
T1257 /workspace/coverage/cover_reg_top/11.uart_intr_test.2918472675 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:26 PM PDT 24 14306852 ps
T1258 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3716288358 Jul 25 06:25:09 PM PDT 24 Jul 25 06:25:11 PM PDT 24 133521494 ps
T1259 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1087022094 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:26 PM PDT 24 41529680 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3799262683 Jul 25 06:25:17 PM PDT 24 Jul 25 06:25:18 PM PDT 24 156006410 ps
T1261 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3283201412 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:29 PM PDT 24 18413321 ps
T1262 /workspace/coverage/cover_reg_top/26.uart_intr_test.777227492 Jul 25 06:25:30 PM PDT 24 Jul 25 06:25:31 PM PDT 24 13990475 ps
T1263 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.977454430 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:28 PM PDT 24 170488369 ps
T1264 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2401069358 Jul 25 06:25:12 PM PDT 24 Jul 25 06:25:14 PM PDT 24 114349750 ps
T1265 /workspace/coverage/cover_reg_top/37.uart_intr_test.75038384 Jul 25 06:25:33 PM PDT 24 Jul 25 06:25:33 PM PDT 24 23195095 ps
T1266 /workspace/coverage/cover_reg_top/23.uart_intr_test.4133995101 Jul 25 06:25:30 PM PDT 24 Jul 25 06:25:30 PM PDT 24 11626832 ps
T1267 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2001210619 Jul 25 06:25:23 PM PDT 24 Jul 25 06:25:24 PM PDT 24 79210513 ps
T1268 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.399751003 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:26 PM PDT 24 25383212 ps
T1269 /workspace/coverage/cover_reg_top/17.uart_intr_test.2670373921 Jul 25 06:25:29 PM PDT 24 Jul 25 06:25:30 PM PDT 24 18262031 ps
T1270 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2235124765 Jul 25 06:25:13 PM PDT 24 Jul 25 06:25:14 PM PDT 24 21465249 ps
T1271 /workspace/coverage/cover_reg_top/34.uart_intr_test.768088022 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 46896850 ps
T1272 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3397256676 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:10 PM PDT 24 15324555 ps
T1273 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3638582744 Jul 25 06:25:23 PM PDT 24 Jul 25 06:25:24 PM PDT 24 15627555 ps
T1274 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2803199111 Jul 25 06:25:14 PM PDT 24 Jul 25 06:25:15 PM PDT 24 36397803 ps
T1275 /workspace/coverage/cover_reg_top/3.uart_intr_test.342198329 Jul 25 06:25:11 PM PDT 24 Jul 25 06:25:12 PM PDT 24 23399191 ps
T1276 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2611944418 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:27 PM PDT 24 143973332 ps
T1277 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1197262923 Jul 25 06:25:16 PM PDT 24 Jul 25 06:25:17 PM PDT 24 59021517 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.529262901 Jul 25 06:25:11 PM PDT 24 Jul 25 06:25:12 PM PDT 24 68122222 ps
T1279 /workspace/coverage/cover_reg_top/45.uart_intr_test.1191111718 Jul 25 06:25:34 PM PDT 24 Jul 25 06:25:34 PM PDT 24 11521922 ps
T1280 /workspace/coverage/cover_reg_top/36.uart_intr_test.3035067013 Jul 25 06:25:30 PM PDT 24 Jul 25 06:25:31 PM PDT 24 16868791 ps
T1281 /workspace/coverage/cover_reg_top/42.uart_intr_test.3010690987 Jul 25 06:25:36 PM PDT 24 Jul 25 06:25:36 PM PDT 24 12965805 ps
T1282 /workspace/coverage/cover_reg_top/32.uart_intr_test.4282937688 Jul 25 06:25:33 PM PDT 24 Jul 25 06:25:34 PM PDT 24 15757665 ps
T1283 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2303834510 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 28682849 ps
T1284 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3603403240 Jul 25 06:25:24 PM PDT 24 Jul 25 06:25:25 PM PDT 24 174776705 ps
T1285 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2594522480 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:26 PM PDT 24 306255971 ps
T1286 /workspace/coverage/cover_reg_top/47.uart_intr_test.3649593300 Jul 25 06:25:35 PM PDT 24 Jul 25 06:25:35 PM PDT 24 12179754 ps
T1287 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2240051976 Jul 25 06:25:11 PM PDT 24 Jul 25 06:25:12 PM PDT 24 145714765 ps
T1288 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1627675125 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 24317344 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3326870616 Jul 25 06:25:08 PM PDT 24 Jul 25 06:25:09 PM PDT 24 28612436 ps
T1290 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2796784358 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 57027647 ps
T1291 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1833144274 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:12 PM PDT 24 28772500 ps
T1292 /workspace/coverage/cover_reg_top/27.uart_intr_test.3237282121 Jul 25 06:25:29 PM PDT 24 Jul 25 06:25:30 PM PDT 24 13656417 ps
T98 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.841534529 Jul 25 06:25:24 PM PDT 24 Jul 25 06:25:25 PM PDT 24 138707217 ps
T1293 /workspace/coverage/cover_reg_top/4.uart_csr_rw.859640662 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 129515056 ps
T1294 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2297350151 Jul 25 06:25:23 PM PDT 24 Jul 25 06:25:25 PM PDT 24 127344500 ps
T1295 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1227332526 Jul 25 06:25:24 PM PDT 24 Jul 25 06:25:25 PM PDT 24 76603372 ps
T1296 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2936773213 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 39016822 ps
T1297 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.706651443 Jul 25 06:25:12 PM PDT 24 Jul 25 06:25:13 PM PDT 24 13948751 ps
T1298 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.992239837 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:28 PM PDT 24 22494258 ps
T1299 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1591291934 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:27 PM PDT 24 19884966 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.773138176 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:10 PM PDT 24 24715628 ps
T1301 /workspace/coverage/cover_reg_top/7.uart_intr_test.1154861297 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 20954009 ps
T1302 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1455775273 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:27 PM PDT 24 23347364 ps
T1303 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3130708145 Jul 25 06:25:23 PM PDT 24 Jul 25 06:25:24 PM PDT 24 55706226 ps
T1304 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1838753196 Jul 25 06:25:25 PM PDT 24 Jul 25 06:25:27 PM PDT 24 73867287 ps
T1305 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3180886345 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:27 PM PDT 24 39545379 ps
T1306 /workspace/coverage/cover_reg_top/1.uart_csr_rw.56470844 Jul 25 06:25:10 PM PDT 24 Jul 25 06:25:11 PM PDT 24 10863069 ps
T1307 /workspace/coverage/cover_reg_top/30.uart_intr_test.3928161686 Jul 25 06:25:29 PM PDT 24 Jul 25 06:25:30 PM PDT 24 50474775 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_intr_test.899242646 Jul 25 06:25:28 PM PDT 24 Jul 25 06:25:29 PM PDT 24 13857492 ps
T1309 /workspace/coverage/cover_reg_top/10.uart_tl_errors.301502975 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:27 PM PDT 24 192027768 ps
T1310 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3205902787 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 34124386 ps
T1311 /workspace/coverage/cover_reg_top/19.uart_intr_test.1574840126 Jul 25 06:25:27 PM PDT 24 Jul 25 06:25:29 PM PDT 24 13237117 ps
T1312 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3451963146 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 386778253 ps
T1313 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.100235843 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 62507791 ps
T1314 /workspace/coverage/cover_reg_top/10.uart_csr_rw.210504237 Jul 25 06:25:24 PM PDT 24 Jul 25 06:25:24 PM PDT 24 15068942 ps
T1315 /workspace/coverage/cover_reg_top/33.uart_intr_test.4043613502 Jul 25 06:25:31 PM PDT 24 Jul 25 06:25:32 PM PDT 24 41083661 ps
T1316 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1217395293 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:28 PM PDT 24 49438010 ps
T1317 /workspace/coverage/cover_reg_top/14.uart_intr_test.669094732 Jul 25 06:25:26 PM PDT 24 Jul 25 06:25:27 PM PDT 24 34038424 ps

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.769272379
Short name T3
Test name
Test status
Simulation time 89887546337 ps
CPU time 297.52 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:14:49 PM PDT 24
Peak memory 216780 kb
Host smart-77cd6d95-282d-4f32-b463-ec8843b8893e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769272379 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.769272379
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.693920986
Short name T16
Test name
Test status
Simulation time 233338131513 ps
CPU time 186.82 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 200196 kb
Host smart-0d714214-339c-4349-9b1f-15ae5c3d7776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693920986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.693920986
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.2911139238
Short name T8
Test name
Test status
Simulation time 202682681734 ps
CPU time 846.35 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:25:17 PM PDT 24
Peak memory 200164 kb
Host smart-a2ea298d-dc17-418e-8fe7-d411b3d27ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911139238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2911139238
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all.1323450192
Short name T89
Test name
Test status
Simulation time 490619106148 ps
CPU time 795.78 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:22:59 PM PDT 24
Peak memory 200244 kb
Host smart-d8f5e155-e521-4353-bd33-7a0c0d1a128e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323450192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1323450192
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1728211271
Short name T34
Test name
Test status
Simulation time 185499586708 ps
CPU time 754.7 seconds
Started Jul 25 07:10:23 PM PDT 24
Finished Jul 25 07:22:58 PM PDT 24
Peak memory 221208 kb
Host smart-056b0435-68ac-4e5e-a42b-99ca9056eaea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728211271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1728211271
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.618852906
Short name T109
Test name
Test status
Simulation time 473503694569 ps
CPU time 472 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:18:05 PM PDT 24
Peak memory 215892 kb
Host smart-782d56c9-2672-4451-bb92-55dd9474fca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618852906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.618852906
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.141450160
Short name T33
Test name
Test status
Simulation time 25286706079 ps
CPU time 272.12 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:14:19 PM PDT 24
Peak memory 216712 kb
Host smart-eeb70192-8c91-4638-9c72-2b2f47d0ca66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141450160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.141450160
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.1530598062
Short name T148
Test name
Test status
Simulation time 327985253644 ps
CPU time 810.55 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:24:32 PM PDT 24
Peak memory 200176 kb
Host smart-7f1afb60-b273-4d7d-8595-77dec80672c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530598062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1530598062
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.423513410
Short name T30
Test name
Test status
Simulation time 137251154 ps
CPU time 0.74 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:09:33 PM PDT 24
Peak memory 218404 kb
Host smart-5b858390-1b6d-4707-994f-0e003b262c0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423513410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.423513410
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3419537603
Short name T1
Test name
Test status
Simulation time 67471904603 ps
CPU time 28.3 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:12:30 PM PDT 24
Peak memory 200144 kb
Host smart-1673d2de-be24-438b-bf72-dc89b0fcc4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419537603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3419537603
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4262359581
Short name T36
Test name
Test status
Simulation time 403234554474 ps
CPU time 967.72 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:26:35 PM PDT 24
Peak memory 216688 kb
Host smart-ee40f8a7-dca3-4184-84a9-533821096579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262359581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4262359581
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.240262670
Short name T35
Test name
Test status
Simulation time 259878041295 ps
CPU time 797.1 seconds
Started Jul 25 07:10:26 PM PDT 24
Finished Jul 25 07:23:43 PM PDT 24
Peak memory 225024 kb
Host smart-f0349940-515f-4b91-bd9b-357bf3943734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240262670 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.240262670
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.627229843
Short name T47
Test name
Test status
Simulation time 42471409700 ps
CPU time 432.16 seconds
Started Jul 25 07:12:00 PM PDT 24
Finished Jul 25 07:19:13 PM PDT 24
Peak memory 216056 kb
Host smart-90ce137a-568b-407e-b512-855e799e2b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627229843 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.627229843
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2650619836
Short name T135
Test name
Test status
Simulation time 67479850223 ps
CPU time 147.81 seconds
Started Jul 25 07:11:24 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200248 kb
Host smart-bc33c6d7-92cd-495a-bb18-bc64c942bf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650619836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2650619836
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.941438052
Short name T23
Test name
Test status
Simulation time 101182469273 ps
CPU time 293.19 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:17:03 PM PDT 24
Peak memory 224956 kb
Host smart-7540229f-c39a-4aa5-8f81-25e94d164743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941438052 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.941438052
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.455180673
Short name T24
Test name
Test status
Simulation time 70615854541 ps
CPU time 1835.48 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:40:49 PM PDT 24
Peak memory 216752 kb
Host smart-b5b9b498-3bab-450e-ac79-eaf5b036cb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455180673 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.455180673
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1605534910
Short name T40
Test name
Test status
Simulation time 136113749047 ps
CPU time 124.92 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:12:43 PM PDT 24
Peak memory 200400 kb
Host smart-59e4e7a1-da1f-4500-a1d3-764b484c3c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605534910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1605534910
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2284274713
Short name T38
Test name
Test status
Simulation time 134397139096 ps
CPU time 1452.48 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:33:59 PM PDT 24
Peak memory 225064 kb
Host smart-375cb349-4f88-422e-b9db-6f441ac705da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284274713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2284274713
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2753865199
Short name T94
Test name
Test status
Simulation time 39982406 ps
CPU time 0.97 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 199828 kb
Host smart-50e3c4e7-899d-48f1-a04d-a2d4407e92aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753865199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2753865199
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/2.uart_stress_all.158301416
Short name T151
Test name
Test status
Simulation time 217136618025 ps
CPU time 337.03 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200276 kb
Host smart-60e4e131-0e9f-463c-ba69-b8a034402fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158301416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.158301416
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all.2345779797
Short name T149
Test name
Test status
Simulation time 258393821965 ps
CPU time 513.04 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:19:05 PM PDT 24
Peak memory 200384 kb
Host smart-eec69dcf-0e38-4828-8ee2-2a8da8a1485e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345779797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2345779797
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_alert_test.2601831584
Short name T348
Test name
Test status
Simulation time 39992057 ps
CPU time 0.58 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 195628 kb
Host smart-4203e55b-4c02-49eb-a4a9-042541cebc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601831584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2601831584
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1117791725
Short name T71
Test name
Test status
Simulation time 32074096 ps
CPU time 0.61 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 196320 kb
Host smart-531bb2a0-458c-4f0f-86f7-30935f2d2722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117791725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1117791725
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/default/43.uart_stress_all.3043868223
Short name T141
Test name
Test status
Simulation time 287375441114 ps
CPU time 207.98 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:14:56 PM PDT 24
Peak memory 200412 kb
Host smart-2434387b-e000-4501-abf5-3447232b7510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043868223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3043868223
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.66339220
Short name T251
Test name
Test status
Simulation time 164397482630 ps
CPU time 1477.16 seconds
Started Jul 25 07:10:03 PM PDT 24
Finished Jul 25 07:34:41 PM PDT 24
Peak memory 200248 kb
Host smart-bfc83305-dd6a-4038-8577-8733608b804c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66339220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.66339220
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_fifo_full.583454060
Short name T42
Test name
Test status
Simulation time 92704143175 ps
CPU time 31.29 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:10:01 PM PDT 24
Peak memory 200196 kb
Host smart-336f304e-2a2b-460c-8bf1-c9f5317a2c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583454060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.583454060
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2081613774
Short name T160
Test name
Test status
Simulation time 173361504577 ps
CPU time 23.17 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:12:42 PM PDT 24
Peak memory 200172 kb
Host smart-8341274c-9f1c-42e0-b495-9aca0fe78e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081613774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2081613774
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2841044791
Short name T158
Test name
Test status
Simulation time 388118642332 ps
CPU time 1105.22 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:28:42 PM PDT 24
Peak memory 200256 kb
Host smart-39a7718b-3809-4eab-9dca-52686109fcd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841044791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2841044791
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1138226653
Short name T116
Test name
Test status
Simulation time 180150691085 ps
CPU time 577.11 seconds
Started Jul 25 07:10:46 PM PDT 24
Finished Jul 25 07:20:24 PM PDT 24
Peak memory 225012 kb
Host smart-594003eb-3acd-428e-8821-b3dff63f397e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138226653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1138226653
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.1052812065
Short name T54
Test name
Test status
Simulation time 262476274308 ps
CPU time 826.76 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:24:09 PM PDT 24
Peak memory 200240 kb
Host smart-3018183e-a8bd-4e97-a20b-2cfcd61e96be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052812065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1052812065
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3257861128
Short name T58
Test name
Test status
Simulation time 442504249226 ps
CPU time 1159.35 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:29:51 PM PDT 24
Peak memory 232276 kb
Host smart-bd8d386b-89a6-4a24-b76d-a9eef5f1e6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257861128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3257861128
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2166367907
Short name T209
Test name
Test status
Simulation time 126713759299 ps
CPU time 198.08 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200160 kb
Host smart-b451d7b0-b2b8-4ac8-a303-8fbb50b6672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166367907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2166367907
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3424240472
Short name T189
Test name
Test status
Simulation time 80656196881 ps
CPU time 53.61 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:13:05 PM PDT 24
Peak memory 200236 kb
Host smart-82ae7a67-dc19-44b5-a1df-aea0e0fb89f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424240472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3424240472
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1733547052
Short name T90
Test name
Test status
Simulation time 274598988 ps
CPU time 1.36 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200332 kb
Host smart-586bcaa7-3023-417a-b715-f52be2485dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733547052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1733547052
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4076276753
Short name T266
Test name
Test status
Simulation time 19205113949 ps
CPU time 10.09 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 200264 kb
Host smart-a6918c6d-e4de-4522-a0d2-f38820aae142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076276753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4076276753
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3941792131
Short name T157
Test name
Test status
Simulation time 142439864012 ps
CPU time 1994.84 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:45:01 PM PDT 24
Peak memory 223868 kb
Host smart-bef70129-f515-4e59-8a9c-f9c67118dcda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941792131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3941792131
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.466698029
Short name T154
Test name
Test status
Simulation time 234603943893 ps
CPU time 76.88 seconds
Started Jul 25 07:12:35 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200104 kb
Host smart-f946073f-d677-4927-889b-02baba96241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466698029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.466698029
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_perf.1892638558
Short name T41
Test name
Test status
Simulation time 34084026104 ps
CPU time 105.9 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:13:05 PM PDT 24
Peak memory 200256 kb
Host smart-ac86352c-a8f2-4c37-b002-ed50e0256a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892638558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1892638558
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.325763946
Short name T925
Test name
Test status
Simulation time 92447445642 ps
CPU time 77.76 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:13:36 PM PDT 24
Peak memory 200160 kb
Host smart-f64b7a1a-ff69-4ffa-8304-962705e95df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325763946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.325763946
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.816629390
Short name T211
Test name
Test status
Simulation time 96283624497 ps
CPU time 308.9 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:16:55 PM PDT 24
Peak memory 200344 kb
Host smart-0410da45-f9c8-4df7-87ec-d738042f12e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816629390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.816629390
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3177114942
Short name T162
Test name
Test status
Simulation time 23025544960 ps
CPU time 30.46 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:48 PM PDT 24
Peak memory 200244 kb
Host smart-c662528e-4a96-485f-a48f-7e8c20f61ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177114942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3177114942
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2344298311
Short name T199
Test name
Test status
Simulation time 203744324744 ps
CPU time 159.86 seconds
Started Jul 25 07:12:42 PM PDT 24
Finished Jul 25 07:15:23 PM PDT 24
Peak memory 200188 kb
Host smart-ad177473-ddcc-4d7c-8e77-ece50facfb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344298311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2344298311
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.249399136
Short name T201
Test name
Test status
Simulation time 70712581519 ps
CPU time 57.47 seconds
Started Jul 25 07:13:00 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 200180 kb
Host smart-0d2333de-b870-4b12-b2b7-b69fa4b890e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249399136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.249399136
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.4221979076
Short name T182
Test name
Test status
Simulation time 458577513877 ps
CPU time 499.3 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:19:57 PM PDT 24
Peak memory 200184 kb
Host smart-6ff7ba06-cc1f-49f7-8161-bf9b36c63c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221979076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4221979076
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.398806525
Short name T195
Test name
Test status
Simulation time 74214726048 ps
CPU time 77.52 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 200168 kb
Host smart-60158210-2f49-4c90-826d-0c729a811d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398806525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.398806525
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1985641434
Short name T224
Test name
Test status
Simulation time 132828478567 ps
CPU time 158.11 seconds
Started Jul 25 07:12:34 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200180 kb
Host smart-ff3c3411-f132-4c53-986a-3e080f29f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985641434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1985641434
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4191563976
Short name T243
Test name
Test status
Simulation time 32411257620 ps
CPU time 26.6 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:13:13 PM PDT 24
Peak memory 200200 kb
Host smart-66035b9a-69c7-482b-a02b-c1e65822af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191563976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4191563976
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3072661282
Short name T172
Test name
Test status
Simulation time 136740215621 ps
CPU time 386.94 seconds
Started Jul 25 07:11:56 PM PDT 24
Finished Jul 25 07:18:23 PM PDT 24
Peak memory 216744 kb
Host smart-540019ba-7d65-4fc4-ae9a-13b87a9dbe51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072661282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3072661282
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2344197237
Short name T144
Test name
Test status
Simulation time 69907257199 ps
CPU time 48.04 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:12:51 PM PDT 24
Peak memory 200196 kb
Host smart-dd6b3736-608f-4521-91a8-2fa7265bc0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344197237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2344197237
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2594522480
Short name T1285
Test name
Test status
Simulation time 306255971 ps
CPU time 1.31 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200484 kb
Host smart-3724df17-799a-4022-bd39-ca82d4856e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594522480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2594522480
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.745059453
Short name T200
Test name
Test status
Simulation time 133321697200 ps
CPU time 58.59 seconds
Started Jul 25 07:12:23 PM PDT 24
Finished Jul 25 07:13:22 PM PDT 24
Peak memory 200228 kb
Host smart-5ae16e8d-5f80-424f-8192-ab43e9abb40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745059453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.745059453
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3683286248
Short name T232
Test name
Test status
Simulation time 50639340906 ps
CPU time 19.96 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:13:18 PM PDT 24
Peak memory 200104 kb
Host smart-6153d112-4098-44cd-aba9-b5d8caed1e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683286248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3683286248
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2486817448
Short name T121
Test name
Test status
Simulation time 82478706772 ps
CPU time 117.24 seconds
Started Jul 25 07:10:35 PM PDT 24
Finished Jul 25 07:12:32 PM PDT 24
Peak memory 200072 kb
Host smart-600c0a27-58b9-42b9-8725-80b6a68a4195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486817448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2486817448
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4273414950
Short name T220
Test name
Test status
Simulation time 69207689543 ps
CPU time 94.53 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200264 kb
Host smart-def9057a-add3-4bf1-9f68-60edb1246a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273414950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4273414950
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2238150442
Short name T579
Test name
Test status
Simulation time 37677119425 ps
CPU time 23.49 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 200200 kb
Host smart-e8b546e7-8a3b-45f2-9193-afe4045d0914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238150442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2238150442
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3059450705
Short name T241
Test name
Test status
Simulation time 19950294217 ps
CPU time 31.53 seconds
Started Jul 25 07:10:00 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 200192 kb
Host smart-c57dc52e-1820-48e4-be3e-e96c87a4e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059450705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3059450705
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3278832840
Short name T227
Test name
Test status
Simulation time 10346238308 ps
CPU time 5.16 seconds
Started Jul 25 07:12:17 PM PDT 24
Finished Jul 25 07:12:22 PM PDT 24
Peak memory 200176 kb
Host smart-d90b899c-bf94-4221-aaef-75d48703bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278832840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3278832840
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4020419119
Short name T191
Test name
Test status
Simulation time 126266458374 ps
CPU time 52.11 seconds
Started Jul 25 07:12:23 PM PDT 24
Finished Jul 25 07:13:15 PM PDT 24
Peak memory 200224 kb
Host smart-857a875e-53fd-404d-b636-2e9051dc75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020419119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4020419119
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.162705568
Short name T235
Test name
Test status
Simulation time 29815588092 ps
CPU time 46.44 seconds
Started Jul 25 07:12:22 PM PDT 24
Finished Jul 25 07:13:08 PM PDT 24
Peak memory 200184 kb
Host smart-35c74874-8fa4-464b-97ca-eac8f54bcf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162705568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.162705568
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1807647597
Short name T246
Test name
Test status
Simulation time 73906677586 ps
CPU time 31.85 seconds
Started Jul 25 07:12:20 PM PDT 24
Finished Jul 25 07:12:52 PM PDT 24
Peak memory 200168 kb
Host smart-af1758c5-d2c6-44b5-9187-eb48a25eee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807647597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1807647597
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1441726099
Short name T507
Test name
Test status
Simulation time 17364752575 ps
CPU time 45.45 seconds
Started Jul 25 07:12:23 PM PDT 24
Finished Jul 25 07:13:08 PM PDT 24
Peak memory 200212 kb
Host smart-24fd7f43-d892-4037-9d67-3941632a8ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441726099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1441726099
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2811452639
Short name T147
Test name
Test status
Simulation time 27369479187 ps
CPU time 49.7 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:13:27 PM PDT 24
Peak memory 200160 kb
Host smart-f0a09a6c-a068-466a-a6fc-fa98932259b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811452639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2811452639
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2380089867
Short name T245
Test name
Test status
Simulation time 42231653105 ps
CPU time 17.03 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:12:56 PM PDT 24
Peak memory 200252 kb
Host smart-7c944958-3438-4c8f-ac54-73e5028d2bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380089867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2380089867
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1984865141
Short name T119
Test name
Test status
Simulation time 28082854036 ps
CPU time 15.58 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 200248 kb
Host smart-e493a4fb-3a51-43a8-a3d3-6ba4ca9f2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984865141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1984865141
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3476442176
Short name T167
Test name
Test status
Simulation time 36716044272 ps
CPU time 41.83 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200180 kb
Host smart-218b6188-96d6-4ecd-812c-e6c54fa2c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476442176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3476442176
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.137116377
Short name T127
Test name
Test status
Simulation time 61716259841 ps
CPU time 98.18 seconds
Started Jul 25 07:13:13 PM PDT 24
Finished Jul 25 07:14:51 PM PDT 24
Peak memory 200180 kb
Host smart-aa79f47c-197b-4e9e-968f-1d84d86e274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137116377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.137116377
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.950431516
Short name T233
Test name
Test status
Simulation time 178538038395 ps
CPU time 17.36 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:27 PM PDT 24
Peak memory 200228 kb
Host smart-3c43e71f-8dd1-40c2-adc9-a5b6a159f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950431516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.950431516
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.381580078
Short name T230
Test name
Test status
Simulation time 170520858972 ps
CPU time 58.37 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:12:08 PM PDT 24
Peak memory 200180 kb
Host smart-d18956d2-4759-4090-9032-caed8dcfa02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381580078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.381580078
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3748158187
Short name T1220
Test name
Test status
Simulation time 20650317 ps
CPU time 0.7 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 195932 kb
Host smart-409e750a-bb1c-4b4f-a590-e8bbd43819a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748158187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3748158187
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2283745435
Short name T1238
Test name
Test status
Simulation time 3370775740 ps
CPU time 2.46 seconds
Started Jul 25 06:25:17 PM PDT 24
Finished Jul 25 06:25:19 PM PDT 24
Peak memory 198996 kb
Host smart-cc5caa6b-2b98-4de4-872b-7e0082b25d7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283745435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2283745435
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2599373074
Short name T70
Test name
Test status
Simulation time 45790097 ps
CPU time 0.62 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196308 kb
Host smart-95256c4b-01d4-4e60-b5de-900ff347d957
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599373074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2599373074
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2019838887
Short name T1231
Test name
Test status
Simulation time 22990011 ps
CPU time 1.16 seconds
Started Jul 25 06:25:16 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 200888 kb
Host smart-dc53bf79-3c80-4261-a32c-c0a3a16df3e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019838887 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2019838887
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3397256676
Short name T1272
Test name
Test status
Simulation time 15324555 ps
CPU time 0.65 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:10 PM PDT 24
Peak memory 196328 kb
Host smart-4a72f0f9-fae4-4f20-9b07-ced1dcba8dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397256676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3397256676
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.637082326
Short name T1240
Test name
Test status
Simulation time 15231119 ps
CPU time 0.57 seconds
Started Jul 25 06:25:09 PM PDT 24
Finished Jul 25 06:25:10 PM PDT 24
Peak memory 195256 kb
Host smart-cebdaf9a-594f-41ef-8a72-6fae470a0dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637082326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.637082326
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.617157681
Short name T1244
Test name
Test status
Simulation time 19920583 ps
CPU time 0.64 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 196568 kb
Host smart-ab677f17-3513-4465-9f91-9eed6999a716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617157681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.617157681
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4463822
Short name T1190
Test name
Test status
Simulation time 28696727 ps
CPU time 1.28 seconds
Started Jul 25 06:25:09 PM PDT 24
Finished Jul 25 06:25:10 PM PDT 24
Peak memory 200952 kb
Host smart-31746aca-22df-4d81-8437-c96ec5a4a988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4463822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4463822
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2896310130
Short name T92
Test name
Test status
Simulation time 246506143 ps
CPU time 1.27 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:10 PM PDT 24
Peak memory 200260 kb
Host smart-c90423a5-9898-4269-8e45-a9866e5ffb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896310130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2896310130
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2596114177
Short name T1248
Test name
Test status
Simulation time 25699057 ps
CPU time 0.7 seconds
Started Jul 25 06:25:16 PM PDT 24
Finished Jul 25 06:25:17 PM PDT 24
Peak memory 195656 kb
Host smart-7c0a681f-84bb-43e4-a585-fea625ed9ab0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596114177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2596114177
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3282259853
Short name T73
Test name
Test status
Simulation time 136202289 ps
CPU time 1.61 seconds
Started Jul 25 06:25:07 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 198540 kb
Host smart-5ef31f8f-aa13-48a0-8442-adeacc79bc99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282259853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3282259853
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2796784358
Short name T1290
Test name
Test status
Simulation time 57027647 ps
CPU time 0.64 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196308 kb
Host smart-710b17bf-cce1-41a1-8c05-ea072c9523fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796784358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2796784358
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.291895096
Short name T1209
Test name
Test status
Simulation time 66766508 ps
CPU time 1.04 seconds
Started Jul 25 06:25:17 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 200776 kb
Host smart-c84c1558-93b0-47de-9bad-af51b5dd76f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291895096 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.291895096
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.56470844
Short name T1306
Test name
Test status
Simulation time 10863069 ps
CPU time 0.64 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196328 kb
Host smart-fc168091-a7ba-4a99-ac4e-5fbca76a1256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56470844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.56470844
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1096926616
Short name T1185
Test name
Test status
Simulation time 14255764 ps
CPU time 0.62 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:08 PM PDT 24
Peak memory 195224 kb
Host smart-49876b29-79a7-412b-9ee1-6c7e20d9d738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096926616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1096926616
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2984238688
Short name T1236
Test name
Test status
Simulation time 97565301 ps
CPU time 0.75 seconds
Started Jul 25 06:25:07 PM PDT 24
Finished Jul 25 06:25:08 PM PDT 24
Peak memory 197832 kb
Host smart-b4a59d50-9b24-4486-b5a3-d576b6099d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984238688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2984238688
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2401069358
Short name T1264
Test name
Test status
Simulation time 114349750 ps
CPU time 2.36 seconds
Started Jul 25 06:25:12 PM PDT 24
Finished Jul 25 06:25:14 PM PDT 24
Peak memory 200956 kb
Host smart-5c9faaa0-a7b0-44cf-b0bf-db8b114a0330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401069358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2401069358
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.728701984
Short name T93
Test name
Test status
Simulation time 175780778 ps
CPU time 0.93 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 199676 kb
Host smart-b52f255a-94c0-4c1d-8169-d4d598ee0084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728701984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.728701984
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.717711853
Short name T1233
Test name
Test status
Simulation time 314525492 ps
CPU time 1.35 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 201020 kb
Host smart-e0eb4bf6-9625-4724-a5d0-db7e274dc834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717711853 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.717711853
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.210504237
Short name T1314
Test name
Test status
Simulation time 15068942 ps
CPU time 0.62 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 196428 kb
Host smart-091c7eaf-4597-4b94-b085-1500fb5708bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210504237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.210504237
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.175838318
Short name T1193
Test name
Test status
Simulation time 36508611 ps
CPU time 0.56 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:23 PM PDT 24
Peak memory 195284 kb
Host smart-84045740-1adf-44ba-a871-0799dc78627a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175838318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.175838318
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1455775273
Short name T1302
Test name
Test status
Simulation time 23347364 ps
CPU time 0.63 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 196556 kb
Host smart-d569475c-c559-4f24-902c-9110dacaa1a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455775273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1455775273
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.301502975
Short name T1309
Test name
Test status
Simulation time 192027768 ps
CPU time 1.21 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200980 kb
Host smart-7d89c21b-dd83-4392-b971-e4e0635f7a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301502975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.301502975
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.880130288
Short name T1216
Test name
Test status
Simulation time 81495105 ps
CPU time 0.74 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 199144 kb
Host smart-084cbc61-6bb5-43fa-bf8b-19f79023c2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880130288 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.880130288
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2851152240
Short name T1207
Test name
Test status
Simulation time 123269544 ps
CPU time 0.59 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 196352 kb
Host smart-ec77d175-f2d7-4fc3-a0a0-c83b750283db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851152240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2851152240
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2918472675
Short name T1257
Test name
Test status
Simulation time 14306852 ps
CPU time 0.58 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 195352 kb
Host smart-04ebcb90-b3cc-4866-b13a-297ceeb3d28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918472675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2918472675
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3205902787
Short name T1310
Test name
Test status
Simulation time 34124386 ps
CPU time 0.79 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 198384 kb
Host smart-6010482b-a19b-41cf-9200-7ef510d97260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205902787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3205902787
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2019386605
Short name T1227
Test name
Test status
Simulation time 87740574 ps
CPU time 1.63 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200928 kb
Host smart-123a505f-6589-4d61-b567-8f85948480c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019386605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2019386605
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1087022094
Short name T1259
Test name
Test status
Simulation time 41529680 ps
CPU time 0.94 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 199748 kb
Host smart-e397bc5e-4683-4957-a15a-7dfbabd6f3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087022094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1087022094
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.908741873
Short name T1222
Test name
Test status
Simulation time 85765204 ps
CPU time 1.16 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 201004 kb
Host smart-aea7981d-bec4-4619-a47a-a4fd7b7f3a10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908741873 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.908741873
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3777028662
Short name T75
Test name
Test status
Simulation time 21690312 ps
CPU time 0.62 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 196316 kb
Host smart-bd9ca749-ab81-4457-b18b-e3940ad86b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777028662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3777028662
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1210724394
Short name T1225
Test name
Test status
Simulation time 39985379 ps
CPU time 0.54 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 195300 kb
Host smart-c17fe16e-8fb5-4bf0-bd00-fc5ebb16e823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210724394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1210724394
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2208666573
Short name T78
Test name
Test status
Simulation time 26608049 ps
CPU time 0.71 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 197740 kb
Host smart-42b25c1a-a23b-4fbe-a130-50f994605ce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208666573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2208666573
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2611944418
Short name T1276
Test name
Test status
Simulation time 143973332 ps
CPU time 1.47 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200964 kb
Host smart-db6b9419-fb98-402d-bc64-a8549e7c2b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611944418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2611944418
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3603403240
Short name T1284
Test name
Test status
Simulation time 174776705 ps
CPU time 0.96 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 199888 kb
Host smart-24675a68-e922-4fd9-aa69-0feb7ed4969e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603403240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3603403240
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3459891375
Short name T1230
Test name
Test status
Simulation time 92313280 ps
CPU time 0.77 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 199252 kb
Host smart-f36e40b1-e5aa-4226-8523-597c6e86a0d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459891375 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3459891375
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2667190663
Short name T72
Test name
Test status
Simulation time 65425391 ps
CPU time 0.58 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 196328 kb
Host smart-b7337a45-0601-4aa3-b7cf-58f795d0f747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667190663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2667190663
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3383205679
Short name T1200
Test name
Test status
Simulation time 11121237 ps
CPU time 0.56 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 195300 kb
Host smart-8a8e50b9-7cad-40ec-85e2-8ca700811515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383205679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3383205679
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1591291934
Short name T1299
Test name
Test status
Simulation time 19884966 ps
CPU time 0.65 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 196472 kb
Host smart-663bba5a-67a5-4e64-80c3-68c73b69cd48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591291934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1591291934
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3597431901
Short name T1182
Test name
Test status
Simulation time 181617336 ps
CPU time 1.82 seconds
Started Jul 25 06:25:22 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 200972 kb
Host smart-07e63267-7354-4371-9493-14dd59b46339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597431901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3597431901
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.284194633
Short name T91
Test name
Test status
Simulation time 177448998 ps
CPU time 0.93 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 199872 kb
Host smart-bd1c5931-0ed5-4cde-a9ac-bee59de9a137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284194633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.284194633
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1140396298
Short name T1250
Test name
Test status
Simulation time 24704679 ps
CPU time 0.77 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 199636 kb
Host smart-b6a7d1dc-672f-46a8-846c-a5dd5e1a0fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140396298 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1140396298
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.669094732
Short name T1317
Test name
Test status
Simulation time 34038424 ps
CPU time 0.59 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 195264 kb
Host smart-37299ce4-6c8a-488a-99f7-f788057bfc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669094732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.669094732
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1017327369
Short name T85
Test name
Test status
Simulation time 113738890 ps
CPU time 0.71 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 197936 kb
Host smart-89524e1e-0672-4be3-94bc-156b16b5ac00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017327369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1017327369
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2460486261
Short name T1219
Test name
Test status
Simulation time 78531139 ps
CPU time 1.77 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200984 kb
Host smart-2325d303-cedb-42a4-9f6b-bb4bca813c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460486261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2460486261
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1509888954
Short name T1252
Test name
Test status
Simulation time 49578802 ps
CPU time 0.93 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 199936 kb
Host smart-d580b097-6f75-4618-8bcc-4801c7e58811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509888954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1509888954
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2297350151
Short name T1294
Test name
Test status
Simulation time 127344500 ps
CPU time 0.9 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 200688 kb
Host smart-565ee03f-2c0a-455a-8bcf-78a605153516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297350151 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2297350151
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3180886345
Short name T1305
Test name
Test status
Simulation time 39545379 ps
CPU time 0.58 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 196292 kb
Host smart-e000436f-c955-4f2e-a2b2-3bc1f17a9904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180886345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3180886345
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.601028832
Short name T1223
Test name
Test status
Simulation time 31288444 ps
CPU time 0.58 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 195356 kb
Host smart-f9d70de0-bd37-403b-b155-440039880a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601028832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.601028832
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1520827139
Short name T80
Test name
Test status
Simulation time 78295237 ps
CPU time 0.67 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 195640 kb
Host smart-ad4a7566-01dd-4695-b58f-3dea48a4380c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520827139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1520827139
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2022356703
Short name T1246
Test name
Test status
Simulation time 26599537 ps
CPU time 1.24 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200940 kb
Host smart-207fd9cd-dbc2-4b19-bdb0-feca036338f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022356703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2022356703
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3799086791
Short name T95
Test name
Test status
Simulation time 352661749 ps
CPU time 1.34 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 200228 kb
Host smart-4aaeaed3-0f0d-4de4-beab-2f539a8166ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799086791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3799086791
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2650674588
Short name T1226
Test name
Test status
Simulation time 31866893 ps
CPU time 0.87 seconds
Started Jul 25 06:25:28 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 200772 kb
Host smart-14cc41da-97f6-4f0a-a02f-26c323bc7cf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650674588 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2650674588
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3036192133
Short name T1224
Test name
Test status
Simulation time 41097792 ps
CPU time 0.64 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 196304 kb
Host smart-3dd9723d-6c16-4b2e-83cd-b82867c8dba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036192133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3036192133
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.899242646
Short name T1308
Test name
Test status
Simulation time 13857492 ps
CPU time 0.61 seconds
Started Jul 25 06:25:28 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 195344 kb
Host smart-f1398b87-7a5e-4fc6-b369-33d11eacdded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899242646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.899242646
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1217395293
Short name T1316
Test name
Test status
Simulation time 49438010 ps
CPU time 0.73 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 198016 kb
Host smart-6697d29b-66bd-4c26-a08c-7083d1449ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217395293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1217395293
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.507071403
Short name T1187
Test name
Test status
Simulation time 24066443 ps
CPU time 1.29 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200940 kb
Host smart-c9ffb975-96d0-4ac3-ac04-0abd0698d23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507071403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.507071403
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.841534529
Short name T98
Test name
Test status
Simulation time 138707217 ps
CPU time 0.94 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 199812 kb
Host smart-24e54140-26bf-4e97-8036-3b3be51a903e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841534529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.841534529
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3283201412
Short name T1261
Test name
Test status
Simulation time 18413321 ps
CPU time 0.92 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 200696 kb
Host smart-1e2dc463-8a6e-40f3-b12b-b399f39fe980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283201412 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3283201412
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.664921439
Short name T76
Test name
Test status
Simulation time 53952741 ps
CPU time 0.66 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 196496 kb
Host smart-a34d3898-f0e6-4fa8-bda3-3d967dc91c51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664921439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.664921439
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2670373921
Short name T1269
Test name
Test status
Simulation time 18262031 ps
CPU time 0.61 seconds
Started Jul 25 06:25:29 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 195332 kb
Host smart-590ac4c9-6af6-43ff-a74c-13b165d48f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670373921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2670373921
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.647522271
Short name T84
Test name
Test status
Simulation time 22653320 ps
CPU time 0.72 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 196564 kb
Host smart-100c4dd3-8d5b-4411-8045-8a9a70d71438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647522271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.647522271
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.791309175
Short name T1211
Test name
Test status
Simulation time 43280130 ps
CPU time 1.78 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200972 kb
Host smart-e980e315-a7ee-46c5-b3da-ed2c0212adb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791309175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.791309175
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.977454430
Short name T1263
Test name
Test status
Simulation time 170488369 ps
CPU time 0.93 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 199988 kb
Host smart-dbfa9980-e30f-4d48-870e-6c5c93f2513b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977454430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.977454430
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.399751003
Short name T1268
Test name
Test status
Simulation time 25383212 ps
CPU time 0.8 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200680 kb
Host smart-59aa662d-80d1-4883-a8f3-5bf088f0585b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399751003 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.399751003
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4126719348
Short name T77
Test name
Test status
Simulation time 14690260 ps
CPU time 0.61 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 196468 kb
Host smart-aef0e07f-96c3-44f7-a1f8-9df0016fec1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126719348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4126719348
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4172890067
Short name T1254
Test name
Test status
Simulation time 23053964 ps
CPU time 0.59 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 195208 kb
Host smart-06ffcc0d-6db3-4ecf-a0bb-43df84042973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172890067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4172890067
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2303834510
Short name T1283
Test name
Test status
Simulation time 28682849 ps
CPU time 0.65 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 195480 kb
Host smart-3d96480f-4f98-4fca-aaf3-d70f4743e446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303834510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2303834510
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3451963146
Short name T1312
Test name
Test status
Simulation time 386778253 ps
CPU time 1.73 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 200980 kb
Host smart-7d57d810-b1bf-4217-a1e3-ffdc812b6097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451963146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3451963146
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.411351877
Short name T96
Test name
Test status
Simulation time 50321932 ps
CPU time 0.96 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 199896 kb
Host smart-50c1f890-f67a-4e0d-9a88-c8feccac25a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411351877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.411351877
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2001210619
Short name T1267
Test name
Test status
Simulation time 79210513 ps
CPU time 0.93 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 200776 kb
Host smart-2e423bb7-bed0-4049-b897-142d03d83589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001210619 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2001210619
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2970743333
Short name T79
Test name
Test status
Simulation time 19542390 ps
CPU time 0.68 seconds
Started Jul 25 06:25:28 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 196328 kb
Host smart-e4899d8b-ea62-4274-ad8f-e299dd419d1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970743333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2970743333
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1574840126
Short name T1311
Test name
Test status
Simulation time 13237117 ps
CPU time 0.61 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 195276 kb
Host smart-5cc5f1b8-e477-474b-af14-b77538a0cc4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574840126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1574840126
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1933982982
Short name T82
Test name
Test status
Simulation time 53476352 ps
CPU time 0.79 seconds
Started Jul 25 06:25:30 PM PDT 24
Finished Jul 25 06:25:31 PM PDT 24
Peak memory 198572 kb
Host smart-30cf3dd1-31f3-463c-859d-0e824bc3d5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933982982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1933982982
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3671893465
Short name T1249
Test name
Test status
Simulation time 129625129 ps
CPU time 2.21 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200952 kb
Host smart-946d27e9-4abb-4165-b4a3-826886735376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671893465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3671893465
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1838753196
Short name T1304
Test name
Test status
Simulation time 73867287 ps
CPU time 1.21 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200168 kb
Host smart-29f3e370-55d4-472f-8478-2951bd225593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838753196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1838753196
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.773138176
Short name T1300
Test name
Test status
Simulation time 24715628 ps
CPU time 0.76 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:10 PM PDT 24
Peak memory 197272 kb
Host smart-92a20391-6d75-4a02-a067-f24f14c68281
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773138176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.773138176
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2475346938
Short name T68
Test name
Test status
Simulation time 643835129 ps
CPU time 2.3 seconds
Started Jul 25 06:25:09 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 199032 kb
Host smart-275bb649-8040-43b0-9025-579a6e937320
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475346938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2475346938
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.706651443
Short name T1297
Test name
Test status
Simulation time 13948751 ps
CPU time 0.64 seconds
Started Jul 25 06:25:12 PM PDT 24
Finished Jul 25 06:25:13 PM PDT 24
Peak memory 196228 kb
Host smart-718a9235-6ea9-4f3d-b11b-3ed81b2aa46a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706651443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.706651443
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.195213238
Short name T1184
Test name
Test status
Simulation time 31446304 ps
CPU time 0.89 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 200748 kb
Host smart-af02f9ac-936a-49dd-b877-d6d228ef7dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195213238 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.195213238
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1197262923
Short name T1277
Test name
Test status
Simulation time 59021517 ps
CPU time 0.64 seconds
Started Jul 25 06:25:16 PM PDT 24
Finished Jul 25 06:25:17 PM PDT 24
Peak memory 196376 kb
Host smart-493dd4ee-a797-4211-9e69-856993961001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197262923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1197262923
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1198814153
Short name T1214
Test name
Test status
Simulation time 48096275 ps
CPU time 0.6 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 195204 kb
Host smart-16fe29dc-a684-4b8e-acae-a4b83364b424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198814153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1198814153
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3326870616
Short name T1289
Test name
Test status
Simulation time 28612436 ps
CPU time 0.72 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 197660 kb
Host smart-beac8b88-a6cb-4e07-8c0c-9cf31d62cb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326870616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3326870616
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4004962131
Short name T1239
Test name
Test status
Simulation time 137720616 ps
CPU time 2.38 seconds
Started Jul 25 06:25:13 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 200964 kb
Host smart-fa224176-b200-4683-800e-f769efd15f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004962131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4004962131
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3799262683
Short name T1260
Test name
Test status
Simulation time 156006410 ps
CPU time 1.33 seconds
Started Jul 25 06:25:17 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 200440 kb
Host smart-6ec0aecb-5895-422e-901d-c6de64be1fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799262683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3799262683
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3594000161
Short name T1213
Test name
Test status
Simulation time 31108323 ps
CPU time 0.56 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 195224 kb
Host smart-d706094a-7810-42af-b809-07a960cd055c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594000161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3594000161
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.583149465
Short name T1217
Test name
Test status
Simulation time 13840946 ps
CPU time 0.58 seconds
Started Jul 25 06:25:28 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 195248 kb
Host smart-26ab0093-6234-43c7-9c87-7f93061e0657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583149465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.583149465
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3771244272
Short name T1228
Test name
Test status
Simulation time 17563277 ps
CPU time 0.58 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 195256 kb
Host smart-5cd61288-6878-42f4-8f35-872d59116912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771244272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3771244272
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4133995101
Short name T1266
Test name
Test status
Simulation time 11626832 ps
CPU time 0.58 seconds
Started Jul 25 06:25:30 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 195232 kb
Host smart-de3ef7f1-46eb-449c-82d5-3760ca80da14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133995101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4133995101
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2191291652
Short name T1186
Test name
Test status
Simulation time 149202755 ps
CPU time 0.6 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 195344 kb
Host smart-a7df25f6-da11-445c-9ec6-5851beb92c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191291652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2191291652
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1086136305
Short name T1247
Test name
Test status
Simulation time 13046580 ps
CPU time 0.62 seconds
Started Jul 25 06:25:30 PM PDT 24
Finished Jul 25 06:25:31 PM PDT 24
Peak memory 195308 kb
Host smart-015a57d3-d801-4ed5-94b1-5c795a5a55b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086136305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1086136305
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.777227492
Short name T1262
Test name
Test status
Simulation time 13990475 ps
CPU time 0.58 seconds
Started Jul 25 06:25:30 PM PDT 24
Finished Jul 25 06:25:31 PM PDT 24
Peak memory 195280 kb
Host smart-396ddb2f-f3d3-4f5b-b00a-42fc2f203496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777227492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.777227492
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3237282121
Short name T1292
Test name
Test status
Simulation time 13656417 ps
CPU time 0.56 seconds
Started Jul 25 06:25:29 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 195304 kb
Host smart-59bf8ab8-635d-411e-8611-3fffb4b8dc47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237282121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3237282121
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3393734883
Short name T1234
Test name
Test status
Simulation time 51160592 ps
CPU time 0.57 seconds
Started Jul 25 06:25:34 PM PDT 24
Finished Jul 25 06:25:35 PM PDT 24
Peak memory 195308 kb
Host smart-3fccdabf-44cb-4f10-a05e-d8cb17c62f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393734883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3393734883
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.735861089
Short name T1188
Test name
Test status
Simulation time 156703796 ps
CPU time 0.59 seconds
Started Jul 25 06:25:29 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 195232 kb
Host smart-f850e7ef-9eb7-4bbd-af11-0abd3a9f8cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735861089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.735861089
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1608689573
Short name T69
Test name
Test status
Simulation time 160907529 ps
CPU time 0.81 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 197688 kb
Host smart-445f663e-e5b3-4ce1-a40d-b5cf92ba97c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608689573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1608689573
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1687906799
Short name T1201
Test name
Test status
Simulation time 703295682 ps
CPU time 2.45 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:14 PM PDT 24
Peak memory 198720 kb
Host smart-a0afabf6-b347-4877-9d0e-5d3b31a1f88a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687906799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1687906799
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1360911216
Short name T1199
Test name
Test status
Simulation time 13029686 ps
CPU time 0.63 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196324 kb
Host smart-0504fb4a-e024-4896-b967-b207187eeb7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360911216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1360911216
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3743191917
Short name T1221
Test name
Test status
Simulation time 33796039 ps
CPU time 0.72 seconds
Started Jul 25 06:25:18 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 199400 kb
Host smart-c24d0b98-7b05-4a18-b5df-7c4b3c59bd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743191917 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3743191917
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.930228260
Short name T1235
Test name
Test status
Simulation time 44433373 ps
CPU time 0.62 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 196336 kb
Host smart-cfa90576-1c26-4f2e-9c3d-37acea7cf358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930228260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.930228260
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.342198329
Short name T1275
Test name
Test status
Simulation time 23399191 ps
CPU time 0.57 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 195308 kb
Host smart-0c2be26d-6e67-4b85-805e-625df6ac869b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342198329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.342198329
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3727918580
Short name T81
Test name
Test status
Simulation time 59995499 ps
CPU time 0.76 seconds
Started Jul 25 06:25:14 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 197992 kb
Host smart-01b831ca-2aa2-4bf6-80a7-9382a220b5e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727918580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3727918580
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2936773213
Short name T1296
Test name
Test status
Simulation time 39016822 ps
CPU time 1 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 200704 kb
Host smart-6066b62f-49bd-442f-b8a0-c90b6b9a6675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936773213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2936773213
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2240051976
Short name T1287
Test name
Test status
Simulation time 145714765 ps
CPU time 0.96 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 199872 kb
Host smart-bc59922e-8652-409a-b91b-cfec43f5e33c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240051976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2240051976
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3928161686
Short name T1307
Test name
Test status
Simulation time 50474775 ps
CPU time 0.58 seconds
Started Jul 25 06:25:29 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 195320 kb
Host smart-a9e17b22-005f-4c26-a41e-05c1e97e1146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928161686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3928161686
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1731376715
Short name T1218
Test name
Test status
Simulation time 35663608 ps
CPU time 0.56 seconds
Started Jul 25 06:25:29 PM PDT 24
Finished Jul 25 06:25:29 PM PDT 24
Peak memory 195264 kb
Host smart-0eb08b61-5081-4126-863d-c0355db45b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731376715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1731376715
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4282937688
Short name T1282
Test name
Test status
Simulation time 15757665 ps
CPU time 0.6 seconds
Started Jul 25 06:25:33 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 195320 kb
Host smart-e633e63d-d185-4b9a-9357-a0eb2a02f60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282937688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4282937688
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4043613502
Short name T1315
Test name
Test status
Simulation time 41083661 ps
CPU time 0.56 seconds
Started Jul 25 06:25:31 PM PDT 24
Finished Jul 25 06:25:32 PM PDT 24
Peak memory 195244 kb
Host smart-eca9a4a0-6a30-4c43-be70-d39f3afd0bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043613502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4043613502
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.768088022
Short name T1271
Test name
Test status
Simulation time 46896850 ps
CPU time 0.56 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 195284 kb
Host smart-39b745b1-37b7-4d0c-9eb0-d1fa82620768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768088022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.768088022
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2946056974
Short name T1191
Test name
Test status
Simulation time 13734812 ps
CPU time 0.56 seconds
Started Jul 25 06:25:34 PM PDT 24
Finished Jul 25 06:25:35 PM PDT 24
Peak memory 195244 kb
Host smart-7053b8f2-f2d3-42f0-8c42-661ebe27794a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946056974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2946056974
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3035067013
Short name T1280
Test name
Test status
Simulation time 16868791 ps
CPU time 0.56 seconds
Started Jul 25 06:25:30 PM PDT 24
Finished Jul 25 06:25:31 PM PDT 24
Peak memory 195324 kb
Host smart-9bd7a14a-0bd1-4fd0-981f-3e35cf5bddad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035067013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3035067013
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.75038384
Short name T1265
Test name
Test status
Simulation time 23195095 ps
CPU time 0.55 seconds
Started Jul 25 06:25:33 PM PDT 24
Finished Jul 25 06:25:33 PM PDT 24
Peak memory 195240 kb
Host smart-707a3ced-d5c6-47e2-baf8-0acfc3477423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75038384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.75038384
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3873387511
Short name T1192
Test name
Test status
Simulation time 47325188 ps
CPU time 0.57 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 195300 kb
Host smart-89242ba1-bc1a-42a4-9c25-e0a0288be006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873387511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3873387511
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3333643655
Short name T1241
Test name
Test status
Simulation time 45884873 ps
CPU time 0.62 seconds
Started Jul 25 06:25:35 PM PDT 24
Finished Jul 25 06:25:35 PM PDT 24
Peak memory 195280 kb
Host smart-58edde11-5de0-4494-a966-a57d292f2670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333643655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3333643655
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.497740908
Short name T1205
Test name
Test status
Simulation time 48921702 ps
CPU time 0.66 seconds
Started Jul 25 06:25:08 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 195828 kb
Host smart-bccc3564-529c-4b36-9111-d509acf79daf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497740908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.497740908
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3716288358
Short name T1258
Test name
Test status
Simulation time 133521494 ps
CPU time 1.58 seconds
Started Jul 25 06:25:09 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 198536 kb
Host smart-d123daf8-6d9e-45a8-8c0e-54d82d10f77d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716288358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3716288358
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1627675125
Short name T1288
Test name
Test status
Simulation time 24317344 ps
CPU time 0.64 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196332 kb
Host smart-c4aa97fe-baa7-464e-b82a-cc796084a3da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627675125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1627675125
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1833144274
Short name T1291
Test name
Test status
Simulation time 28772500 ps
CPU time 1.28 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 200856 kb
Host smart-3e70ca3f-0a64-44b1-8d7a-2d3463e5fd1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833144274 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1833144274
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.859640662
Short name T1293
Test name
Test status
Simulation time 129515056 ps
CPU time 0.57 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 196320 kb
Host smart-e0a5a654-88f1-4a89-8b48-ec3356af10c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859640662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.859640662
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.801266360
Short name T1197
Test name
Test status
Simulation time 59762903 ps
CPU time 0.56 seconds
Started Jul 25 06:25:09 PM PDT 24
Finished Jul 25 06:25:09 PM PDT 24
Peak memory 195336 kb
Host smart-ce9c12b4-f2f2-4397-a830-02926cbbe5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801266360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.801266360
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.529262901
Short name T1278
Test name
Test status
Simulation time 68122222 ps
CPU time 0.67 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 195720 kb
Host smart-48b8d373-74af-4071-8614-509907f3e9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529262901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.529262901
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1897685300
Short name T1189
Test name
Test status
Simulation time 119222150 ps
CPU time 2.13 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:13 PM PDT 24
Peak memory 200936 kb
Host smart-cb8f992e-cce9-4a8f-9d3e-a23ca62a0b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897685300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1897685300
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2977432600
Short name T125
Test name
Test status
Simulation time 322658902 ps
CPU time 1.34 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 200416 kb
Host smart-c0dcd585-395b-42e6-84ab-6a96feaab421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977432600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2977432600
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.530390949
Short name T1215
Test name
Test status
Simulation time 16175490 ps
CPU time 0.59 seconds
Started Jul 25 06:25:33 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 195328 kb
Host smart-5546ef16-be6f-4530-ae3e-2d83d2811857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530390949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.530390949
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1444375825
Short name T1255
Test name
Test status
Simulation time 15598119 ps
CPU time 0.58 seconds
Started Jul 25 06:25:39 PM PDT 24
Finished Jul 25 06:25:39 PM PDT 24
Peak memory 195316 kb
Host smart-6d9dcadd-c8ae-4228-a9cd-c84719d2cd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444375825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1444375825
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3010690987
Short name T1281
Test name
Test status
Simulation time 12965805 ps
CPU time 0.58 seconds
Started Jul 25 06:25:36 PM PDT 24
Finished Jul 25 06:25:36 PM PDT 24
Peak memory 195236 kb
Host smart-87b39158-574c-436c-9d68-a00206b12741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010690987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3010690987
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1370113973
Short name T1202
Test name
Test status
Simulation time 46784377 ps
CPU time 0.55 seconds
Started Jul 25 06:25:34 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 195308 kb
Host smart-642c5f13-4817-4864-8158-5a80984e6678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370113973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1370113973
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.890219601
Short name T1203
Test name
Test status
Simulation time 17199559 ps
CPU time 0.58 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 195216 kb
Host smart-721401f4-3672-4009-b5aa-d2b93e443811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890219601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.890219601
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1191111718
Short name T1279
Test name
Test status
Simulation time 11521922 ps
CPU time 0.58 seconds
Started Jul 25 06:25:34 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 195316 kb
Host smart-05028e45-6d7a-41d7-a960-dea524bb9675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191111718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1191111718
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3952637363
Short name T1195
Test name
Test status
Simulation time 15274369 ps
CPU time 0.56 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 195316 kb
Host smart-bcb4fd8e-55cc-4c10-be05-3e8cafdcb071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952637363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3952637363
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3649593300
Short name T1286
Test name
Test status
Simulation time 12179754 ps
CPU time 0.6 seconds
Started Jul 25 06:25:35 PM PDT 24
Finished Jul 25 06:25:35 PM PDT 24
Peak memory 195288 kb
Host smart-ec41e4ea-12d8-4318-bae9-ba2f865899e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649593300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3649593300
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.611523782
Short name T1245
Test name
Test status
Simulation time 15938494 ps
CPU time 0.57 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 195280 kb
Host smart-ac1ef5dc-2f32-4958-ad5c-038531e8019a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611523782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.611523782
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2283489019
Short name T1196
Test name
Test status
Simulation time 25244052 ps
CPU time 0.58 seconds
Started Jul 25 06:25:36 PM PDT 24
Finished Jul 25 06:25:37 PM PDT 24
Peak memory 195324 kb
Host smart-3373fb0b-9c70-460a-8418-e012d47c8a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283489019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2283489019
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2803199111
Short name T1274
Test name
Test status
Simulation time 36397803 ps
CPU time 1.04 seconds
Started Jul 25 06:25:14 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 200744 kb
Host smart-1806f40e-3134-451f-80cc-37ac52fa4a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803199111 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2803199111
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4164208688
Short name T1253
Test name
Test status
Simulation time 51681847 ps
CPU time 0.65 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 196484 kb
Host smart-4377094f-b5d7-448d-b4e4-aaf76e171b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164208688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4164208688
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2836134809
Short name T1237
Test name
Test status
Simulation time 64531703 ps
CPU time 0.61 seconds
Started Jul 25 06:25:16 PM PDT 24
Finished Jul 25 06:25:17 PM PDT 24
Peak memory 195256 kb
Host smart-2e63a5ab-9d43-4191-b74f-229ca8cf5eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836134809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2836134809
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2235124765
Short name T1270
Test name
Test status
Simulation time 21465249 ps
CPU time 0.7 seconds
Started Jul 25 06:25:13 PM PDT 24
Finished Jul 25 06:25:14 PM PDT 24
Peak memory 196748 kb
Host smart-a24752fb-96c9-4294-85c2-dc3cce5dbcce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235124765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2235124765
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3241541754
Short name T1204
Test name
Test status
Simulation time 89603282 ps
CPU time 1.96 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 200952 kb
Host smart-895b1678-a5bb-4fdb-b05d-65d32dd96cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241541754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3241541754
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3554767
Short name T1206
Test name
Test status
Simulation time 65875855 ps
CPU time 0.95 seconds
Started Jul 25 06:25:14 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 200732 kb
Host smart-203a7cdc-774e-4e9e-ae23-ab1eeeec525d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554767 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3554767
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3563772364
Short name T1183
Test name
Test status
Simulation time 14116605 ps
CPU time 0.59 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 196320 kb
Host smart-e0d07bb8-394c-4521-a59c-4306d3bd8b44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563772364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3563772364
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3566203250
Short name T1232
Test name
Test status
Simulation time 49478406 ps
CPU time 0.63 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 195296 kb
Host smart-85dc16bc-813f-4bd8-8495-e643bea30181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566203250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3566203250
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1327281500
Short name T1256
Test name
Test status
Simulation time 43185533 ps
CPU time 0.73 seconds
Started Jul 25 06:25:11 PM PDT 24
Finished Jul 25 06:25:12 PM PDT 24
Peak memory 198800 kb
Host smart-9a2c9d61-89e9-4605-9b8f-7b8321b8b7cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327281500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1327281500
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1025794863
Short name T1208
Test name
Test status
Simulation time 60271696 ps
CPU time 1.32 seconds
Started Jul 25 06:25:14 PM PDT 24
Finished Jul 25 06:25:16 PM PDT 24
Peak memory 200960 kb
Host smart-1f287567-9d88-41a9-a81d-f4c9a1c60bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025794863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1025794863
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3309577456
Short name T1251
Test name
Test status
Simulation time 56693848 ps
CPU time 1.02 seconds
Started Jul 25 06:25:07 PM PDT 24
Finished Jul 25 06:25:08 PM PDT 24
Peak memory 199904 kb
Host smart-9f6d6643-a3b2-4715-99e0-72011c133f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309577456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3309577456
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.100235843
Short name T1313
Test name
Test status
Simulation time 62507791 ps
CPU time 0.87 seconds
Started Jul 25 06:25:26 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 200680 kb
Host smart-71929b3e-2fc8-4017-9a2e-c2efa2e4ce15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100235843 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.100235843
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.477798365
Short name T86
Test name
Test status
Simulation time 13715605 ps
CPU time 0.6 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 196268 kb
Host smart-f337a208-a163-4526-8f36-5f87109d07b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477798365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.477798365
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1154861297
Short name T1301
Test name
Test status
Simulation time 20954009 ps
CPU time 0.57 seconds
Started Jul 25 06:25:10 PM PDT 24
Finished Jul 25 06:25:11 PM PDT 24
Peak memory 195296 kb
Host smart-7a07fcc1-8ece-4ce4-8b32-1d0ad78bb6df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154861297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1154861297
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.992239837
Short name T1298
Test name
Test status
Simulation time 22494258 ps
CPU time 0.67 seconds
Started Jul 25 06:25:27 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 196432 kb
Host smart-33762056-092f-49a4-96a1-0ba9a29c001b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992239837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.992239837
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1445312181
Short name T1194
Test name
Test status
Simulation time 87228905 ps
CPU time 2.46 seconds
Started Jul 25 06:25:15 PM PDT 24
Finished Jul 25 06:25:17 PM PDT 24
Peak memory 200884 kb
Host smart-de5e1046-855d-4bf7-986e-a659afe56439
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445312181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1445312181
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.201855466
Short name T1242
Test name
Test status
Simulation time 31695719 ps
CPU time 0.83 seconds
Started Jul 25 06:25:28 PM PDT 24
Finished Jul 25 06:25:30 PM PDT 24
Peak memory 200588 kb
Host smart-d41bca7e-3424-414c-8c6e-c2582814d51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201855466 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.201855466
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3638582744
Short name T1273
Test name
Test status
Simulation time 15627555 ps
CPU time 0.6 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 196416 kb
Host smart-28be0583-cb80-4e36-989c-f00dcbb29337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638582744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3638582744
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.258743480
Short name T1210
Test name
Test status
Simulation time 23544629 ps
CPU time 0.56 seconds
Started Jul 25 06:25:22 PM PDT 24
Finished Jul 25 06:25:22 PM PDT 24
Peak memory 195296 kb
Host smart-1c66ba94-abb1-4aaf-ab9a-24a932991212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258743480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.258743480
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1271462635
Short name T1243
Test name
Test status
Simulation time 93759397 ps
CPU time 0.76 seconds
Started Jul 25 06:25:22 PM PDT 24
Finished Jul 25 06:25:23 PM PDT 24
Peak memory 197868 kb
Host smart-6e9700ae-e867-4cfe-8a1d-b5ddec2adf04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271462635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1271462635
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.424099383
Short name T1198
Test name
Test status
Simulation time 259480749 ps
CPU time 2.22 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200912 kb
Host smart-6390bf4a-5048-4cc2-8a35-229205286eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424099383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.424099383
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3522713078
Short name T97
Test name
Test status
Simulation time 338693414 ps
CPU time 1.27 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 200208 kb
Host smart-a2705b5a-1205-4ebf-b34f-00bdcb17b669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522713078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3522713078
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1227332526
Short name T1295
Test name
Test status
Simulation time 76603372 ps
CPU time 0.7 seconds
Started Jul 25 06:25:24 PM PDT 24
Finished Jul 25 06:25:25 PM PDT 24
Peak memory 199240 kb
Host smart-a61042b2-33b8-42dd-93cc-fcea66123877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227332526 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1227332526
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4218344308
Short name T1229
Test name
Test status
Simulation time 27350428 ps
CPU time 0.63 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:26 PM PDT 24
Peak memory 196364 kb
Host smart-b33ec32b-9434-4e25-8ecf-8a6134cdf61a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218344308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4218344308
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.986548461
Short name T1212
Test name
Test status
Simulation time 43807753 ps
CPU time 0.59 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 195312 kb
Host smart-4113d6ca-b474-4ff2-b0fe-5241d8bf21de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986548461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.986548461
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.398493971
Short name T83
Test name
Test status
Simulation time 24287937 ps
CPU time 0.65 seconds
Started Jul 25 06:25:17 PM PDT 24
Finished Jul 25 06:25:18 PM PDT 24
Peak memory 196516 kb
Host smart-a0a3ce37-2d0f-4fee-87b2-7b8442574f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398493971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.398493971
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3130708145
Short name T1303
Test name
Test status
Simulation time 55706226 ps
CPU time 1.17 seconds
Started Jul 25 06:25:23 PM PDT 24
Finished Jul 25 06:25:24 PM PDT 24
Peak memory 200968 kb
Host smart-960806b1-87cb-41a3-9da0-363915fb9a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130708145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3130708145
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.645145884
Short name T126
Test name
Test status
Simulation time 373446345 ps
CPU time 1.32 seconds
Started Jul 25 06:25:25 PM PDT 24
Finished Jul 25 06:25:27 PM PDT 24
Peak memory 200352 kb
Host smart-032b111c-ef6a-4bca-943b-4a5405ce2de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645145884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.645145884
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.778112986
Short name T770
Test name
Test status
Simulation time 26591104 ps
CPU time 0.59 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 195624 kb
Host smart-73a6d146-3854-4c99-9d0a-145c25348552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778112986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.778112986
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2821875767
Short name T1102
Test name
Test status
Simulation time 129873190494 ps
CPU time 187.19 seconds
Started Jul 25 07:09:26 PM PDT 24
Finished Jul 25 07:12:34 PM PDT 24
Peak memory 200252 kb
Host smart-aa60d4f3-8d6d-4846-9c5e-6e5aa6104491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821875767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2821875767
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3657342463
Short name T1022
Test name
Test status
Simulation time 102136870438 ps
CPU time 723.4 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:21:33 PM PDT 24
Peak memory 200272 kb
Host smart-b48e460d-93ec-44af-a581-940382cb3fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657342463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3657342463
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3451761120
Short name T143
Test name
Test status
Simulation time 135919479407 ps
CPU time 121.4 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:11:33 PM PDT 24
Peak memory 200148 kb
Host smart-31a82442-24eb-48a0-87bb-fbb312be34cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451761120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3451761120
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1722550829
Short name T15
Test name
Test status
Simulation time 18433342444 ps
CPU time 10.2 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 200156 kb
Host smart-9230fe78-77a7-4140-aa12-0603d4b71ac0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722550829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1722550829
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3452592693
Short name T594
Test name
Test status
Simulation time 136696653807 ps
CPU time 558.2 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:18:56 PM PDT 24
Peak memory 200236 kb
Host smart-1c6720fc-54b5-45bf-9ce6-42e78234c4cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452592693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3452592693
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1643431965
Short name T368
Test name
Test status
Simulation time 6224305955 ps
CPU time 10.36 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:09:48 PM PDT 24
Peak memory 199852 kb
Host smart-d92c8a0e-d775-4b05-b693-cf66335f8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643431965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1643431965
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1047764065
Short name T868
Test name
Test status
Simulation time 137469162776 ps
CPU time 26.51 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:56 PM PDT 24
Peak memory 200044 kb
Host smart-605bba5b-dc84-4ad9-aff1-840b90663a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047764065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1047764065
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2434531294
Short name T832
Test name
Test status
Simulation time 28271558037 ps
CPU time 249.25 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:13:42 PM PDT 24
Peak memory 200004 kb
Host smart-f2403e4e-9ad9-45d6-a1ae-6866f4778c68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434531294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2434531294
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2437326896
Short name T884
Test name
Test status
Simulation time 2938782826 ps
CPU time 21.27 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:56 PM PDT 24
Peak memory 198296 kb
Host smart-b7efea0a-75b3-46f7-a69a-58baa670afb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437326896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2437326896
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3733727793
Short name T170
Test name
Test status
Simulation time 49768016049 ps
CPU time 19.23 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:52 PM PDT 24
Peak memory 200212 kb
Host smart-f7dde2c2-0a2c-437f-8e28-b7c787a9d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733727793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3733727793
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3435691114
Short name T941
Test name
Test status
Simulation time 3812616708 ps
CPU time 3.63 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 197040 kb
Host smart-d06cbec5-9b31-49f3-b71e-7426a65050c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435691114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3435691114
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.362130875
Short name T532
Test name
Test status
Simulation time 543551505 ps
CPU time 1.36 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 199732 kb
Host smart-91e99caa-3bc6-4cd1-8578-4ee9c7414c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362130875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.362130875
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3513446295
Short name T508
Test name
Test status
Simulation time 321422788381 ps
CPU time 1707.97 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:38:04 PM PDT 24
Peak memory 200208 kb
Host smart-f5f98ea1-0bbc-4908-b07d-7853f3588cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513446295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3513446295
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.687383078
Short name T66
Test name
Test status
Simulation time 76063661548 ps
CPU time 615.27 seconds
Started Jul 25 07:09:26 PM PDT 24
Finished Jul 25 07:19:42 PM PDT 24
Peak memory 216884 kb
Host smart-8caf90fc-fc9a-40d7-9143-05c2b09f2929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687383078 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.687383078
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.467792773
Short name T1132
Test name
Test status
Simulation time 916941526 ps
CPU time 2.96 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:34 PM PDT 24
Peak memory 198776 kb
Host smart-7a9ef91e-7751-43e6-9315-3518bc5c474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467792773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.467792773
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.925955494
Short name T658
Test name
Test status
Simulation time 19082918681 ps
CPU time 16.22 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 200196 kb
Host smart-6bed0e69-9fb8-463a-97d0-1620ec727d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925955494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.925955494
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2040957875
Short name T447
Test name
Test status
Simulation time 41150520 ps
CPU time 0.57 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:09:39 PM PDT 24
Peak memory 195620 kb
Host smart-07b15c64-e65b-4c50-b211-851ebe3c9650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040957875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2040957875
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3841816275
Short name T278
Test name
Test status
Simulation time 19331130174 ps
CPU time 28.76 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:10:08 PM PDT 24
Peak memory 200180 kb
Host smart-1d4beaa4-396c-4e67-9448-d1be818cf61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841816275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3841816275
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.281258992
Short name T13
Test name
Test status
Simulation time 28214346421 ps
CPU time 6.71 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 200008 kb
Host smart-07a2cc8f-fa5b-4271-80c2-de949feb93fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281258992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.281258992
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3624778792
Short name T376
Test name
Test status
Simulation time 259367356364 ps
CPU time 410.7 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:16:27 PM PDT 24
Peak memory 200256 kb
Host smart-af5e325c-919f-4c37-b7e2-ea7ec8f41b1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624778792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3624778792
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.596762230
Short name T655
Test name
Test status
Simulation time 1571065835 ps
CPU time 0.93 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:09:33 PM PDT 24
Peak memory 195932 kb
Host smart-67c3372f-1d0d-436c-8120-916b30505fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596762230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.596762230
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.155973322
Short name T255
Test name
Test status
Simulation time 93906871656 ps
CPU time 66.37 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 200376 kb
Host smart-43202ec5-9e90-4545-9ff9-b48d3f2eb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155973322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.155973322
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1704584419
Short name T257
Test name
Test status
Simulation time 18060726181 ps
CPU time 176.66 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:12:27 PM PDT 24
Peak memory 200252 kb
Host smart-b290cfd7-34a3-4f94-a680-317ed18edfb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704584419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1704584419
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.649094668
Short name T347
Test name
Test status
Simulation time 3875802938 ps
CPU time 30.26 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:10:01 PM PDT 24
Peak memory 198692 kb
Host smart-0565cc6a-7039-40d0-9e1c-19a94bb43801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649094668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.649094668
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2013853344
Short name T496
Test name
Test status
Simulation time 62201920214 ps
CPU time 44.43 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:10:15 PM PDT 24
Peak memory 200232 kb
Host smart-db895dce-4053-4204-98a2-19e4e3dc482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013853344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2013853344
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.621928531
Short name T1056
Test name
Test status
Simulation time 2104179738 ps
CPU time 3.89 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:09:42 PM PDT 24
Peak memory 195760 kb
Host smart-fd21d556-fe70-4948-b2df-15a6592aa4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621928531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.621928531
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3688666333
Short name T32
Test name
Test status
Simulation time 80288153 ps
CPU time 0.79 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 218472 kb
Host smart-7c7fceac-ccdb-4865-b7d6-51fba83a4acc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688666333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3688666333
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.89839055
Short name T293
Test name
Test status
Simulation time 549643115 ps
CPU time 2.71 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:37 PM PDT 24
Peak memory 199768 kb
Host smart-de5b5b1f-b78b-46d0-b8ac-0fb42650adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89839055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.89839055
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1825678714
Short name T602
Test name
Test status
Simulation time 182529507722 ps
CPU time 1112.41 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:28:09 PM PDT 24
Peak memory 215768 kb
Host smart-c6ff5a69-a6cd-4c97-a09e-7339e9ff5d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825678714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1825678714
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1792316558
Short name T65
Test name
Test status
Simulation time 133849089251 ps
CPU time 752.69 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:22:05 PM PDT 24
Peak memory 216716 kb
Host smart-57369ae1-a4d0-48df-b85c-4e8f78856295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792316558 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1792316558
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.451382348
Short name T384
Test name
Test status
Simulation time 6662464633 ps
CPU time 12.79 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:09:48 PM PDT 24
Peak memory 200072 kb
Host smart-7e72ac57-0ce7-4183-bcd7-b767afd02e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451382348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.451382348
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.473911663
Short name T929
Test name
Test status
Simulation time 54668490850 ps
CPU time 83.16 seconds
Started Jul 25 07:09:31 PM PDT 24
Finished Jul 25 07:10:54 PM PDT 24
Peak memory 200232 kb
Host smart-e18508e0-ae6c-4576-9b1f-a9d5726f6863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473911663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.473911663
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.459708197
Short name T476
Test name
Test status
Simulation time 22803124 ps
CPU time 0.57 seconds
Started Jul 25 07:09:49 PM PDT 24
Finished Jul 25 07:09:49 PM PDT 24
Peak memory 195636 kb
Host smart-937071c0-1da0-4a05-8073-a7dea0a54d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459708197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.459708197
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1060091033
Short name T670
Test name
Test status
Simulation time 60745879129 ps
CPU time 27.09 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 200176 kb
Host smart-b2c7a3be-108f-42fb-b547-06f36fdc4457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060091033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1060091033
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4092285542
Short name T768
Test name
Test status
Simulation time 62525693061 ps
CPU time 32.6 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 200176 kb
Host smart-d4f92a8c-e0c0-4288-81ce-fc2f63c9c605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092285542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4092285542
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2813017882
Short name T887
Test name
Test status
Simulation time 45264810780 ps
CPU time 10.69 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:01 PM PDT 24
Peak memory 198956 kb
Host smart-38cbef69-1cb7-4bb6-b635-4f6a6c1d88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813017882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2813017882
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.240766334
Short name T56
Test name
Test status
Simulation time 35772621668 ps
CPU time 56.58 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:47 PM PDT 24
Peak memory 199996 kb
Host smart-f87dafb6-1279-4948-921e-1b3a5b163c8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240766334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.240766334
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.402938664
Short name T1144
Test name
Test status
Simulation time 151262805849 ps
CPU time 317.88 seconds
Started Jul 25 07:09:53 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200204 kb
Host smart-ee0a56d9-2f07-4591-b1ce-641c1b5bd346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402938664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.402938664
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.327443021
Short name T824
Test name
Test status
Simulation time 3820677560 ps
CPU time 10.6 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:09:59 PM PDT 24
Peak memory 199860 kb
Host smart-e5194aae-5cdd-414a-b0c9-8f63639cf1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327443021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.327443021
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1789887206
Short name T1029
Test name
Test status
Simulation time 169321780697 ps
CPU time 83.03 seconds
Started Jul 25 07:09:58 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 200404 kb
Host smart-bd68f6ae-271d-46c9-bf66-3927dba59cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789887206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1789887206
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3266557705
Short name T1094
Test name
Test status
Simulation time 16809638052 ps
CPU time 63.93 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:10:55 PM PDT 24
Peak memory 200196 kb
Host smart-773d5dde-1dea-4722-a4dc-689891765cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266557705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3266557705
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2541779982
Short name T1116
Test name
Test status
Simulation time 4638326777 ps
CPU time 36.23 seconds
Started Jul 25 07:09:49 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 199476 kb
Host smart-bf86783e-489e-4152-950e-40d6411d68f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541779982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2541779982
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3627506742
Short name T714
Test name
Test status
Simulation time 77845887553 ps
CPU time 78.2 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:11:07 PM PDT 24
Peak memory 200148 kb
Host smart-06eb093b-731c-42f0-b475-0d3eab7693ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627506742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3627506742
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2329862348
Short name T1081
Test name
Test status
Simulation time 6286494242 ps
CPU time 1.4 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:09:56 PM PDT 24
Peak memory 196292 kb
Host smart-890ebda6-43b6-4fea-a74d-6dd3d971873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329862348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2329862348
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1263816178
Short name T1109
Test name
Test status
Simulation time 904190100 ps
CPU time 1.7 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 198760 kb
Host smart-a0998d58-8d2c-4a47-9ac7-7ddc15effac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263816178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1263816178
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2558138101
Short name T117
Test name
Test status
Simulation time 197538925216 ps
CPU time 148.12 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:12:17 PM PDT 24
Peak memory 216408 kb
Host smart-a7ab15aa-e062-4ad3-8ea6-f5c057d44d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558138101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2558138101
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1088203529
Short name T577
Test name
Test status
Simulation time 1851742976 ps
CPU time 2.27 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:09:56 PM PDT 24
Peak memory 199660 kb
Host smart-7b4cbf09-58ec-419c-bc2b-e0e79e5b4460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088203529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1088203529
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1335569759
Short name T815
Test name
Test status
Simulation time 61384608838 ps
CPU time 47.91 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 200188 kb
Host smart-87924053-e313-4678-8809-2e86a85e3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335569759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1335569759
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3732284547
Short name T1096
Test name
Test status
Simulation time 202125012186 ps
CPU time 83.4 seconds
Started Jul 25 07:12:21 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 200120 kb
Host smart-44f2c497-977a-4acb-8558-cca7f52a54a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732284547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3732284547
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3706030054
Short name T1178
Test name
Test status
Simulation time 57238384575 ps
CPU time 29.09 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 200196 kb
Host smart-6c35c5a4-59b2-4b79-81fc-0c1a603c6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706030054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3706030054
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1465771705
Short name T194
Test name
Test status
Simulation time 23873984083 ps
CPU time 10.89 seconds
Started Jul 25 07:12:20 PM PDT 24
Finished Jul 25 07:12:31 PM PDT 24
Peak memory 199172 kb
Host smart-33e9773b-cb3c-42b5-bc65-b4914a47441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465771705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1465771705
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1268192943
Short name T898
Test name
Test status
Simulation time 34603607469 ps
CPU time 48.94 seconds
Started Jul 25 07:12:20 PM PDT 24
Finished Jul 25 07:13:09 PM PDT 24
Peak memory 200272 kb
Host smart-50680ce8-4da3-4209-b088-6ab7c3f6805d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268192943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1268192943
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3338754525
Short name T1155
Test name
Test status
Simulation time 63174373635 ps
CPU time 38.63 seconds
Started Jul 25 07:12:16 PM PDT 24
Finished Jul 25 07:12:55 PM PDT 24
Peak memory 200180 kb
Host smart-39ef2956-f861-48ef-8632-4aff68691b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338754525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3338754525
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.102913656
Short name T366
Test name
Test status
Simulation time 29914541183 ps
CPU time 45.64 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 200032 kb
Host smart-87427978-ad1e-4a5a-a737-3c1799f36d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102913656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.102913656
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1251739837
Short name T322
Test name
Test status
Simulation time 88814269000 ps
CPU time 12.98 seconds
Started Jul 25 07:12:17 PM PDT 24
Finished Jul 25 07:12:30 PM PDT 24
Peak memory 200188 kb
Host smart-32e7877c-62ab-4696-9736-5bd3127f5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251739837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1251739837
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1691843282
Short name T1010
Test name
Test status
Simulation time 15875707629 ps
CPU time 24.79 seconds
Started Jul 25 07:12:20 PM PDT 24
Finished Jul 25 07:12:45 PM PDT 24
Peak memory 200048 kb
Host smart-8daa05de-0327-4320-9364-5b5e30041134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691843282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1691843282
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3690357586
Short name T307
Test name
Test status
Simulation time 22780940034 ps
CPU time 9.53 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:12:29 PM PDT 24
Peak memory 200216 kb
Host smart-0725c56c-9d53-4ff0-b80e-fc86207e707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690357586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3690357586
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.330431784
Short name T1040
Test name
Test status
Simulation time 13344923 ps
CPU time 0.55 seconds
Started Jul 25 07:09:53 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 195568 kb
Host smart-09ad798e-953d-4194-9598-f37fe9f3edae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330431784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.330431784
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.53502438
Short name T258
Test name
Test status
Simulation time 261648098853 ps
CPU time 536.03 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:18:47 PM PDT 24
Peak memory 200276 kb
Host smart-7ae3fbb7-1e33-455b-a379-0b76a3435f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53502438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.53502438
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3341060283
Short name T1069
Test name
Test status
Simulation time 118467898188 ps
CPU time 18.05 seconds
Started Jul 25 07:10:00 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 200264 kb
Host smart-29a10165-29c4-472f-b181-f953c4c407a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341060283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3341060283
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.1789075841
Short name T550
Test name
Test status
Simulation time 29024585977 ps
CPU time 14.21 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 200220 kb
Host smart-807e1eab-6137-4c9f-9dce-11119b465cff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789075841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1789075841
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1826028202
Short name T1021
Test name
Test status
Simulation time 211888110369 ps
CPU time 554.74 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:19:09 PM PDT 24
Peak memory 200252 kb
Host smart-daaa8d8c-0e39-4d19-9836-7cd60ae8391a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826028202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1826028202
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4103788559
Short name T993
Test name
Test status
Simulation time 2035078891 ps
CPU time 1.81 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 197972 kb
Host smart-eb32dcfb-e25a-4485-8eda-e823cf2c6d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103788559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4103788559
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1981549601
Short name T563
Test name
Test status
Simulation time 138107590679 ps
CPU time 49.08 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:10:41 PM PDT 24
Peak memory 200200 kb
Host smart-cf95f03f-9bd9-4c8f-b1c1-de1f330a0bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981549601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1981549601
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1160345226
Short name T746
Test name
Test status
Simulation time 12850991737 ps
CPU time 758.86 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:22:29 PM PDT 24
Peak memory 200128 kb
Host smart-77e3a858-06bd-4097-8a4d-784f95d4fb54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160345226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1160345226
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.993597303
Short name T1047
Test name
Test status
Simulation time 2645233930 ps
CPU time 21.99 seconds
Started Jul 25 07:10:01 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 198484 kb
Host smart-3bcb62ad-c34d-4139-99f2-86a5461f29b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993597303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.993597303
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1260100112
Short name T863
Test name
Test status
Simulation time 49197255190 ps
CPU time 18.49 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 198792 kb
Host smart-d6d970d4-763e-4b40-8a2d-a6f31d37b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260100112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1260100112
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1801340022
Short name T50
Test name
Test status
Simulation time 1760741189 ps
CPU time 1.24 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:53 PM PDT 24
Peak memory 195736 kb
Host smart-b12ab316-6a7a-4b3d-b007-cfa5754855d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801340022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1801340022
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2871801849
Short name T954
Test name
Test status
Simulation time 503712700 ps
CPU time 1.96 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 198496 kb
Host smart-67ad4a50-cd4d-4e35-8dbc-c06e18eb24b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871801849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2871801849
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2889262024
Short name T677
Test name
Test status
Simulation time 75934048376 ps
CPU time 60.82 seconds
Started Jul 25 07:10:01 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 200176 kb
Host smart-fba5fff9-6065-4899-a75a-a7034031f37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889262024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2889262024
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3323994250
Short name T1115
Test name
Test status
Simulation time 990905031981 ps
CPU time 851.7 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:24:25 PM PDT 24
Peak memory 227292 kb
Host smart-cc239c74-41e8-4e45-874b-4654d13e01d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323994250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3323994250
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2612449658
Short name T892
Test name
Test status
Simulation time 6878752518 ps
CPU time 19.69 seconds
Started Jul 25 07:10:05 PM PDT 24
Finished Jul 25 07:10:25 PM PDT 24
Peak memory 200176 kb
Host smart-93ff24b5-585e-40f5-bb2f-729d59f6d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612449658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2612449658
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4056265385
Short name T551
Test name
Test status
Simulation time 50289457028 ps
CPU time 55.88 seconds
Started Jul 25 07:09:53 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200212 kb
Host smart-f0911af6-9293-4258-8389-772b3ce03d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056265385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4056265385
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3731203550
Short name T858
Test name
Test status
Simulation time 49352273846 ps
CPU time 68.21 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200240 kb
Host smart-432884b1-1627-4fa7-ba53-97f2b07f7d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731203550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3731203550
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2606245746
Short name T1071
Test name
Test status
Simulation time 13037991735 ps
CPU time 24.12 seconds
Started Jul 25 07:12:22 PM PDT 24
Finished Jul 25 07:12:46 PM PDT 24
Peak memory 200248 kb
Host smart-6a0a5e49-dda5-4366-878f-5733a2c9f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606245746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2606245746
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2023511037
Short name T747
Test name
Test status
Simulation time 64641418474 ps
CPU time 25.64 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:44 PM PDT 24
Peak memory 200228 kb
Host smart-25c4bffc-d32a-4847-99a3-40d65697baf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023511037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2023511037
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.289041932
Short name T345
Test name
Test status
Simulation time 6458295259 ps
CPU time 9.46 seconds
Started Jul 25 07:12:20 PM PDT 24
Finished Jul 25 07:12:30 PM PDT 24
Peak memory 198152 kb
Host smart-9de62730-c724-4f69-b8ee-51f298663de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289041932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.289041932
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2078852609
Short name T1006
Test name
Test status
Simulation time 36723785034 ps
CPU time 54.08 seconds
Started Jul 25 07:12:17 PM PDT 24
Finished Jul 25 07:13:11 PM PDT 24
Peak memory 200192 kb
Host smart-782c4f8d-d026-443b-8760-f9fc136ca2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078852609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2078852609
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3934570118
Short name T207
Test name
Test status
Simulation time 90477807418 ps
CPU time 71.1 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 200224 kb
Host smart-ad3c569a-6f3b-4b67-82be-2522e1d4dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934570118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3934570118
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3071940028
Short name T1088
Test name
Test status
Simulation time 43356258 ps
CPU time 0.57 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 195628 kb
Host smart-912d96d8-9342-459e-905e-6d60f2d6d67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071940028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3071940028
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3121689839
Short name T698
Test name
Test status
Simulation time 45219929779 ps
CPU time 66.85 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200220 kb
Host smart-d9f41bc6-9f16-4344-a40f-4a65aeb4afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121689839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3121689839
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.462465957
Short name T120
Test name
Test status
Simulation time 143506197499 ps
CPU time 193.63 seconds
Started Jul 25 07:10:03 PM PDT 24
Finished Jul 25 07:13:16 PM PDT 24
Peak memory 200176 kb
Host smart-4edebf03-3d76-4973-9f05-d8555dfa6682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462465957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.462465957
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.93825015
Short name T218
Test name
Test status
Simulation time 143433492012 ps
CPU time 120.61 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:11:43 PM PDT 24
Peak memory 200256 kb
Host smart-7849760e-10aa-4be7-bea6-de512b0612d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93825015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.93825015
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.654559764
Short name T603
Test name
Test status
Simulation time 53551074805 ps
CPU time 100.97 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:11:27 PM PDT 24
Peak memory 200256 kb
Host smart-ba13cd7d-e1c6-4494-a8d7-beb58b267627
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654559764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.654559764
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1901815505
Short name T269
Test name
Test status
Simulation time 97419391382 ps
CPU time 400.43 seconds
Started Jul 25 07:10:11 PM PDT 24
Finished Jul 25 07:16:52 PM PDT 24
Peak memory 200208 kb
Host smart-3dcc1aff-b55f-4845-b8cd-d326f4a5b116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901815505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1901815505
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3212596677
Short name T360
Test name
Test status
Simulation time 6219898102 ps
CPU time 6.55 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:52 PM PDT 24
Peak memory 200120 kb
Host smart-863e1de4-ae3c-4547-8c00-3563208e9d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212596677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3212596677
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.30698533
Short name T514
Test name
Test status
Simulation time 197413807828 ps
CPU time 84.57 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 200360 kb
Host smart-a76cfada-f55e-4ca5-80a7-ee02054bc3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30698533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.30698533
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1958013325
Short name T1139
Test name
Test status
Simulation time 20904842616 ps
CPU time 1113.33 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:28:18 PM PDT 24
Peak memory 200164 kb
Host smart-8c130d11-a474-4676-b619-b41a61e5e643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958013325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1958013325
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1535356321
Short name T1095
Test name
Test status
Simulation time 4584629090 ps
CPU time 9.18 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:10:01 PM PDT 24
Peak memory 198376 kb
Host smart-b4c49fa3-9f38-4467-b7d7-cf18fac118f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535356321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1535356321
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1222519069
Short name T434
Test name
Test status
Simulation time 45451719667 ps
CPU time 79.61 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 200228 kb
Host smart-2819699d-ee99-44d8-a226-4e31c578c1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222519069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1222519069
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2491219987
Short name T298
Test name
Test status
Simulation time 44952533982 ps
CPU time 18.46 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 196600 kb
Host smart-5e8b309c-6f7b-4096-8f50-86f520ba1a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491219987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2491219987
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2058625330
Short name T657
Test name
Test status
Simulation time 558121546 ps
CPU time 1.2 seconds
Started Jul 25 07:10:05 PM PDT 24
Finished Jul 25 07:10:06 PM PDT 24
Peak memory 198948 kb
Host smart-33d533da-8864-40f7-9799-bc5b15115838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058625330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2058625330
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1177706114
Short name T775
Test name
Test status
Simulation time 555761282049 ps
CPU time 408.49 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:16:34 PM PDT 24
Peak memory 216312 kb
Host smart-00d44b9f-d7e0-4f4b-902c-5d0f460115a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177706114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1177706114
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2502823780
Short name T300
Test name
Test status
Simulation time 116526064027 ps
CPU time 2725.9 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:55:11 PM PDT 24
Peak memory 228100 kb
Host smart-1e4376c6-baec-41b9-9d9f-4fdfbef26e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502823780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2502823780
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1788861782
Short name T988
Test name
Test status
Simulation time 382202790 ps
CPU time 1.4 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:09:56 PM PDT 24
Peak memory 198484 kb
Host smart-cc5348f4-37d2-46a6-8328-60e0a74b937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788861782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1788861782
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1344739865
Short name T1062
Test name
Test status
Simulation time 94430363551 ps
CPU time 80.46 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:11:06 PM PDT 24
Peak memory 200208 kb
Host smart-ff3daa17-4389-4d7b-981a-f15029248a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344739865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1344739865
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4000636035
Short name T244
Test name
Test status
Simulation time 295726256160 ps
CPU time 28.47 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:46 PM PDT 24
Peak memory 200268 kb
Host smart-04a537d6-3cd4-40b5-896a-bc29085a73de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000636035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4000636035
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3528902117
Short name T634
Test name
Test status
Simulation time 13481026353 ps
CPU time 28.17 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 200268 kb
Host smart-c3119c96-bcbd-46a1-b444-7cc28ff990bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528902117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3528902117
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3814976086
Short name T515
Test name
Test status
Simulation time 41370970486 ps
CPU time 12.69 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:31 PM PDT 24
Peak memory 200244 kb
Host smart-b7a3138c-d45f-4679-97e5-87df09911dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814976086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3814976086
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3989752537
Short name T131
Test name
Test status
Simulation time 29466296134 ps
CPU time 35.9 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:12:54 PM PDT 24
Peak memory 200260 kb
Host smart-adc8a675-5511-4c44-a5de-b44657ffb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989752537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3989752537
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.796095690
Short name T921
Test name
Test status
Simulation time 128524040512 ps
CPU time 122.76 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200236 kb
Host smart-7e081f6a-3845-4876-a933-04a423bc52e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796095690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.796095690
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2959234485
Short name T437
Test name
Test status
Simulation time 35189904254 ps
CPU time 69.52 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200240 kb
Host smart-5a928898-f261-41b2-9914-b180001c4d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959234485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2959234485
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2541084929
Short name T982
Test name
Test status
Simulation time 36882323 ps
CPU time 0.54 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:10:07 PM PDT 24
Peak memory 194552 kb
Host smart-653c78df-3115-4479-8a02-e3b7031d915c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541084929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2541084929
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2506792194
Short name T970
Test name
Test status
Simulation time 118294680497 ps
CPU time 80.02 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 200176 kb
Host smart-29e40c74-50ce-4a50-ad2a-31655f9b8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506792194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2506792194
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3293271120
Short name T1072
Test name
Test status
Simulation time 29817963541 ps
CPU time 45.6 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:28 PM PDT 24
Peak memory 200176 kb
Host smart-cb5271b2-e237-4229-9613-8afd2a2bad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293271120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3293271120
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.359157545
Short name T440
Test name
Test status
Simulation time 9290169963 ps
CPU time 9.72 seconds
Started Jul 25 07:10:07 PM PDT 24
Finished Jul 25 07:10:16 PM PDT 24
Peak memory 200076 kb
Host smart-2d658df2-6cdf-4ca4-8bca-261c39d84d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359157545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.359157545
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1663770651
Short name T317
Test name
Test status
Simulation time 22904264895 ps
CPU time 19.12 seconds
Started Jul 25 07:10:03 PM PDT 24
Finished Jul 25 07:10:22 PM PDT 24
Peak memory 200228 kb
Host smart-7e632324-70e9-4b8b-b090-b0ed4b3ab21e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663770651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1663770651
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3412026729
Short name T889
Test name
Test status
Simulation time 80472562877 ps
CPU time 306.93 seconds
Started Jul 25 07:10:05 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200240 kb
Host smart-1fc8bb2d-7695-4001-8b0b-9e8e5a4aedf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412026729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3412026729
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1747028214
Short name T1038
Test name
Test status
Simulation time 2245847574 ps
CPU time 1.32 seconds
Started Jul 25 07:10:09 PM PDT 24
Finished Jul 25 07:10:10 PM PDT 24
Peak memory 198840 kb
Host smart-7649dc91-cdce-40ec-a942-f66bc1bc14c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747028214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1747028214
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1001456448
Short name T329
Test name
Test status
Simulation time 69966458039 ps
CPU time 22.49 seconds
Started Jul 25 07:09:49 PM PDT 24
Finished Jul 25 07:10:12 PM PDT 24
Peak memory 200376 kb
Host smart-85802943-c300-42bf-8a4b-189f9fa7ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001456448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1001456448
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1128773482
Short name T382
Test name
Test status
Simulation time 13548134892 ps
CPU time 120.23 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 200248 kb
Host smart-188c83f7-de9a-482f-8e7f-2b0cc1fcfa8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128773482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1128773482
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3426305053
Short name T354
Test name
Test status
Simulation time 2703130976 ps
CPU time 18.06 seconds
Started Jul 25 07:09:55 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 199308 kb
Host smart-b82805e7-8037-4ca4-9108-67fbb852707a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426305053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3426305053
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.592966721
Short name T129
Test name
Test status
Simulation time 60123999376 ps
CPU time 105.48 seconds
Started Jul 25 07:09:56 PM PDT 24
Finished Jul 25 07:11:42 PM PDT 24
Peak memory 200248 kb
Host smart-4c62e890-159e-4da1-b2f9-1789c6d8aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592966721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.592966721
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.76730470
Short name T1166
Test name
Test status
Simulation time 3150870380 ps
CPU time 1.93 seconds
Started Jul 25 07:09:58 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 196296 kb
Host smart-885f753e-96d1-4832-a21e-1a0a832cd2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76730470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.76730470
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3684212172
Short name T377
Test name
Test status
Simulation time 298807947 ps
CPU time 1.04 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:44 PM PDT 24
Peak memory 198424 kb
Host smart-2ad09a12-0978-4d28-ab36-f10e0b018297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684212172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3684212172
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.4193676800
Short name T986
Test name
Test status
Simulation time 191445597127 ps
CPU time 347.38 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:15:38 PM PDT 24
Peak memory 208748 kb
Host smart-6f9c908b-d947-44d6-b363-9ac9438883ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193676800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4193676800
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4236256159
Short name T1083
Test name
Test status
Simulation time 694266627 ps
CPU time 3.7 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:09:57 PM PDT 24
Peak memory 198568 kb
Host smart-4815e8a3-6360-4d9b-a821-92d4fcf32a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236256159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4236256159
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2792977424
Short name T816
Test name
Test status
Simulation time 67503219184 ps
CPU time 19.4 seconds
Started Jul 25 07:09:56 PM PDT 24
Finished Jul 25 07:10:16 PM PDT 24
Peak memory 200268 kb
Host smart-d93e283b-6915-46d9-b244-c88aea45db85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792977424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2792977424
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2338215797
Short name T622
Test name
Test status
Simulation time 23944375960 ps
CPU time 51.03 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:13:10 PM PDT 24
Peak memory 200256 kb
Host smart-f841d9eb-8099-48d4-8a66-736059aeec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338215797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2338215797
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4145449935
Short name T204
Test name
Test status
Simulation time 44558302140 ps
CPU time 14.77 seconds
Started Jul 25 07:12:21 PM PDT 24
Finished Jul 25 07:12:36 PM PDT 24
Peak memory 200120 kb
Host smart-5ac45d59-86fb-4c5b-a67d-2bd063ecaf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145449935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4145449935
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2971559796
Short name T912
Test name
Test status
Simulation time 174630623202 ps
CPU time 68.56 seconds
Started Jul 25 07:12:35 PM PDT 24
Finished Jul 25 07:13:43 PM PDT 24
Peak memory 200176 kb
Host smart-e84f5a4c-503f-41ed-bf60-3b40778f0a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971559796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2971559796
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2667083030
Short name T203
Test name
Test status
Simulation time 89729319763 ps
CPU time 136.11 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:15:01 PM PDT 24
Peak memory 200176 kb
Host smart-8aa183ab-41fd-45e5-b62f-f02f20490bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667083030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2667083030
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3190804136
Short name T1113
Test name
Test status
Simulation time 165229177790 ps
CPU time 602.78 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:22:33 PM PDT 24
Peak memory 200220 kb
Host smart-25891345-dae0-4061-a77e-f9d0aade71c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190804136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3190804136
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4130065551
Short name T310
Test name
Test status
Simulation time 129535335094 ps
CPU time 199.46 seconds
Started Jul 25 07:12:31 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200212 kb
Host smart-7de18871-ac7f-443f-b157-101c0d891a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130065551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4130065551
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4289129261
Short name T88
Test name
Test status
Simulation time 17520808252 ps
CPU time 27.05 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:12:57 PM PDT 24
Peak memory 200196 kb
Host smart-d13140be-8378-4f9a-8b5a-a9e2357c7884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289129261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4289129261
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2029370155
Short name T469
Test name
Test status
Simulation time 263953632309 ps
CPU time 52.12 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:13:25 PM PDT 24
Peak memory 200204 kb
Host smart-2043d406-b7ee-4986-8a15-97289405fd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029370155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2029370155
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3316184172
Short name T688
Test name
Test status
Simulation time 117190715121 ps
CPU time 45.83 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:13:16 PM PDT 24
Peak memory 200228 kb
Host smart-d7181c86-fa04-4618-b452-42b9dd6bb1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316184172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3316184172
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4091600524
Short name T483
Test name
Test status
Simulation time 11397091 ps
CPU time 0.54 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:09:51 PM PDT 24
Peak memory 195636 kb
Host smart-881dde49-b994-4579-88c5-c06e05b97b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091600524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4091600524
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.131213781
Short name T337
Test name
Test status
Simulation time 109005025715 ps
CPU time 138.15 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:12:04 PM PDT 24
Peak memory 200184 kb
Host smart-9617777f-56b8-44c3-b58e-fc70d45d7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131213781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.131213781
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1819278318
Short name T905
Test name
Test status
Simulation time 204304646637 ps
CPU time 59.84 seconds
Started Jul 25 07:09:55 PM PDT 24
Finished Jul 25 07:10:55 PM PDT 24
Peak memory 200188 kb
Host smart-9fbfbedc-9dcb-40b5-a066-508f3eba43df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819278318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1819278318
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2167066220
Short name T841
Test name
Test status
Simulation time 86440159695 ps
CPU time 67.17 seconds
Started Jul 25 07:13:55 PM PDT 24
Finished Jul 25 07:15:02 PM PDT 24
Peak memory 200264 kb
Host smart-81d26dd0-cb41-4ff7-a873-34e4104ef412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167066220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2167066220
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1262900563
Short name T789
Test name
Test status
Simulation time 31639204574 ps
CPU time 28.17 seconds
Started Jul 25 07:09:58 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 200212 kb
Host smart-4a703dab-108a-47bb-b069-d08423681494
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262900563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1262900563
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.736104625
Short name T893
Test name
Test status
Simulation time 102025105418 ps
CPU time 285.76 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:14:36 PM PDT 24
Peak memory 200252 kb
Host smart-bfa4385d-f4fd-4936-972e-b753c627df7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736104625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.736104625
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.767607793
Short name T106
Test name
Test status
Simulation time 3329716634 ps
CPU time 4.43 seconds
Started Jul 25 07:09:57 PM PDT 24
Finished Jul 25 07:10:06 PM PDT 24
Peak memory 199896 kb
Host smart-48457f5c-d50f-4a4f-808a-d22589a59153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767607793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.767607793
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.756658927
Short name T294
Test name
Test status
Simulation time 178231040779 ps
CPU time 20.45 seconds
Started Jul 25 07:09:56 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 199168 kb
Host smart-9d22274b-7a44-4825-9f3b-2771772eec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756658927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.756658927
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1085882259
Short name T277
Test name
Test status
Simulation time 15228173345 ps
CPU time 203.15 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:13:23 PM PDT 24
Peak memory 200256 kb
Host smart-4291de3e-e2d3-4bab-836c-dbba05178776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085882259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1085882259
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1254271560
Short name T936
Test name
Test status
Simulation time 3424613849 ps
CPU time 19.2 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:02 PM PDT 24
Peak memory 198276 kb
Host smart-75d7c689-11c1-4111-8c88-94cef0130347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254271560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1254271560
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3833542936
Short name T659
Test name
Test status
Simulation time 68178105512 ps
CPU time 61.67 seconds
Started Jul 25 07:10:00 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 200228 kb
Host smart-7acd88d4-4299-41d6-9303-4b0572fbc0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833542936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3833542936
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.57886225
Short name T633
Test name
Test status
Simulation time 4778280514 ps
CPU time 5.5 seconds
Started Jul 25 07:10:05 PM PDT 24
Finished Jul 25 07:10:10 PM PDT 24
Peak memory 196820 kb
Host smart-426c9479-7323-4e0b-ab13-643ebbc08074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57886225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.57886225
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2878127093
Short name T475
Test name
Test status
Simulation time 641325977 ps
CPU time 2.18 seconds
Started Jul 25 07:09:58 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 198648 kb
Host smart-96e4d8b2-da5a-4543-9577-d8568f51ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878127093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2878127093
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2171126391
Short name T557
Test name
Test status
Simulation time 26933154985 ps
CPU time 12.08 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 200324 kb
Host smart-9da410b5-f2bc-4acc-83ac-d9b5e824886a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171126391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2171126391
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3019528469
Short name T67
Test name
Test status
Simulation time 327955222434 ps
CPU time 666.21 seconds
Started Jul 25 07:09:57 PM PDT 24
Finished Jul 25 07:21:03 PM PDT 24
Peak memory 217076 kb
Host smart-ab321743-0be4-4236-b4f0-c96d38e76858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019528469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3019528469
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4248606492
Short name T717
Test name
Test status
Simulation time 745036033 ps
CPU time 1.41 seconds
Started Jul 25 07:10:04 PM PDT 24
Finished Jul 25 07:10:05 PM PDT 24
Peak memory 198756 kb
Host smart-a8c65b9d-a144-4f61-b2aa-48fb48bf22a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248606492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4248606492
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3391157066
Short name T964
Test name
Test status
Simulation time 43545924144 ps
CPU time 63.35 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 200256 kb
Host smart-28544601-643d-4e4f-8e1c-7a2e2ddfc280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391157066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3391157066
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3845794396
Short name T183
Test name
Test status
Simulation time 62894136171 ps
CPU time 45.05 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:13:18 PM PDT 24
Peak memory 200160 kb
Host smart-1c1f96ec-b8d7-48bc-a53f-2febcfd82dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845794396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3845794396
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2303294717
Short name T853
Test name
Test status
Simulation time 223514899241 ps
CPU time 152.49 seconds
Started Jul 25 07:12:33 PM PDT 24
Finished Jul 25 07:15:06 PM PDT 24
Peak memory 200260 kb
Host smart-bcc0ddf0-e81f-4534-9ccf-81c43b8316bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303294717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2303294717
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1013212902
Short name T422
Test name
Test status
Simulation time 149230451571 ps
CPU time 214.83 seconds
Started Jul 25 07:12:29 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 200212 kb
Host smart-609dfd70-fab6-458f-9172-db9b9ef985ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013212902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1013212902
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1170587671
Short name T1052
Test name
Test status
Simulation time 200336525306 ps
CPU time 135.72 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200240 kb
Host smart-36b2a44e-ef34-4535-ae03-c1328b2d27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170587671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1170587671
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1521350756
Short name T188
Test name
Test status
Simulation time 63970284199 ps
CPU time 91.21 seconds
Started Jul 25 07:12:31 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 200212 kb
Host smart-cee7f094-56e3-4477-aad6-5df70f4203ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521350756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1521350756
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3908045636
Short name T12
Test name
Test status
Simulation time 19308023584 ps
CPU time 47.36 seconds
Started Jul 25 07:12:28 PM PDT 24
Finished Jul 25 07:13:15 PM PDT 24
Peak memory 200244 kb
Host smart-4b70c536-ca65-418d-8354-bbc526bd4b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908045636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3908045636
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2362220584
Short name T270
Test name
Test status
Simulation time 23916076872 ps
CPU time 10.77 seconds
Started Jul 25 07:12:36 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 200168 kb
Host smart-ffa3380c-6879-4c35-8162-a4bac9b332b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362220584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2362220584
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1117512003
Short name T807
Test name
Test status
Simulation time 76037260442 ps
CPU time 26.91 seconds
Started Jul 25 07:12:29 PM PDT 24
Finished Jul 25 07:12:56 PM PDT 24
Peak memory 200252 kb
Host smart-11cb5890-1761-4c32-ba91-4af46d081ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117512003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1117512003
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2737862140
Short name T610
Test name
Test status
Simulation time 24276272592 ps
CPU time 19.29 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:12:50 PM PDT 24
Peak memory 200180 kb
Host smart-845e2dc4-52be-4196-9c66-7ac239033f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737862140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2737862140
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2536724105
Short name T764
Test name
Test status
Simulation time 26403173268 ps
CPU time 19.98 seconds
Started Jul 25 07:12:36 PM PDT 24
Finished Jul 25 07:12:56 PM PDT 24
Peak memory 200228 kb
Host smart-ea2f6850-f4d6-46d8-84df-2297e3868e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536724105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2536724105
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1081723596
Short name T644
Test name
Test status
Simulation time 125310605 ps
CPU time 0.6 seconds
Started Jul 25 07:10:11 PM PDT 24
Finished Jul 25 07:10:12 PM PDT 24
Peak memory 194576 kb
Host smart-4f37db46-194c-45e4-8605-5300d9b5e5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081723596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1081723596
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.795708550
Short name T911
Test name
Test status
Simulation time 129826407962 ps
CPU time 21.24 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:21 PM PDT 24
Peak memory 200100 kb
Host smart-4ebf7961-0ff6-4ebc-817d-13dc145d8390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795708550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.795708550
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3886870628
Short name T627
Test name
Test status
Simulation time 16409507039 ps
CPU time 24.05 seconds
Started Jul 25 07:10:08 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 200188 kb
Host smart-a85b8bb4-d030-4dd1-8a29-f9d7ec4fa325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886870628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3886870628
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2920225514
Short name T1171
Test name
Test status
Simulation time 52848256493 ps
CPU time 88.58 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 200244 kb
Host smart-b8532a82-1555-4c7f-b1e2-e9b2957d51f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920225514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2920225514
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.203806016
Short name T882
Test name
Test status
Simulation time 10009137186 ps
CPU time 9.19 seconds
Started Jul 25 07:09:51 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 198096 kb
Host smart-595f196f-eabc-493c-8170-b543390a742d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203806016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.203806016
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_loopback.3444740244
Short name T1154
Test name
Test status
Simulation time 355338903 ps
CPU time 1.04 seconds
Started Jul 25 07:10:04 PM PDT 24
Finished Jul 25 07:10:05 PM PDT 24
Peak memory 196460 kb
Host smart-72eefb0c-6897-4055-8d73-3b5af74efad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444740244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3444740244
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3135805142
Short name T466
Test name
Test status
Simulation time 10302088558 ps
CPU time 17.25 seconds
Started Jul 25 07:09:56 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 200180 kb
Host smart-b5a90d3f-2cda-479c-91b7-a7aaf1cf0505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135805142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3135805142
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1750311318
Short name T249
Test name
Test status
Simulation time 10023312680 ps
CPU time 112.99 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:12:06 PM PDT 24
Peak memory 200216 kb
Host smart-db61d3c1-ae60-4c5b-a80a-fb956c3c83cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750311318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1750311318
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.523588327
Short name T554
Test name
Test status
Simulation time 4092226011 ps
CPU time 31.11 seconds
Started Jul 25 07:10:01 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 199112 kb
Host smart-56ef3277-c8c2-4f35-a89b-3137d4bb8e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523588327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.523588327
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2714588040
Short name T1017
Test name
Test status
Simulation time 20557622872 ps
CPU time 28.87 seconds
Started Jul 25 07:10:11 PM PDT 24
Finished Jul 25 07:10:40 PM PDT 24
Peak memory 198816 kb
Host smart-f05f3a36-f515-47f1-a3e6-15e95f4513d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714588040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2714588040
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.705803315
Short name T814
Test name
Test status
Simulation time 2969098049 ps
CPU time 1.82 seconds
Started Jul 25 07:10:02 PM PDT 24
Finished Jul 25 07:10:04 PM PDT 24
Peak memory 196724 kb
Host smart-ba47d27a-e9f9-45ca-a795-b8e0a7ee6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705803315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.705803315
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1671037433
Short name T738
Test name
Test status
Simulation time 6097498695 ps
CPU time 9.48 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 200184 kb
Host smart-b89ba61e-6c7d-46dc-98c1-ceaca9681551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671037433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1671037433
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.502702604
Short name T396
Test name
Test status
Simulation time 185309789208 ps
CPU time 1708.83 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:38:28 PM PDT 24
Peak memory 225004 kb
Host smart-9ab6e17e-3065-4d6f-83ac-704d90b5a977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502702604 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.502702604
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1670259603
Short name T671
Test name
Test status
Simulation time 1412096860 ps
CPU time 2.21 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 199928 kb
Host smart-bbbdf255-2563-40dc-b3b3-84d20bdec3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670259603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1670259603
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.416571263
Short name T779
Test name
Test status
Simulation time 4693900233 ps
CPU time 7.73 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:07 PM PDT 24
Peak memory 197140 kb
Host smart-53559dac-2ca3-4b86-bc3b-4870717bb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416571263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.416571263
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1735628636
Short name T516
Test name
Test status
Simulation time 68457947465 ps
CPU time 121.54 seconds
Started Jul 25 07:12:27 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 200192 kb
Host smart-0aa08a25-f0ce-4263-89ce-a41245c089c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735628636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1735628636
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.327233681
Short name T649
Test name
Test status
Simulation time 13792439642 ps
CPU time 21.63 seconds
Started Jul 25 07:12:31 PM PDT 24
Finished Jul 25 07:12:53 PM PDT 24
Peak memory 200244 kb
Host smart-2513a159-2045-4591-98fa-f9f06c67f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327233681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.327233681
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3381773633
Short name T1043
Test name
Test status
Simulation time 28766953150 ps
CPU time 41.31 seconds
Started Jul 25 07:12:29 PM PDT 24
Finished Jul 25 07:13:10 PM PDT 24
Peak memory 200188 kb
Host smart-4db5bece-ba79-405a-baa1-96f652506f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381773633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3381773633
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.913178616
Short name T11
Test name
Test status
Simulation time 42394963127 ps
CPU time 36.61 seconds
Started Jul 25 07:12:49 PM PDT 24
Finished Jul 25 07:13:26 PM PDT 24
Peak memory 200240 kb
Host smart-cd7cd467-b68a-40d0-adf9-bc8934fa7e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913178616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.913178616
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1249625403
Short name T527
Test name
Test status
Simulation time 96546015103 ps
CPU time 129.59 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 200272 kb
Host smart-c7945f68-db17-4f07-8538-2ffd4c9dbba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249625403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1249625403
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3457334044
Short name T1098
Test name
Test status
Simulation time 30245015044 ps
CPU time 49.26 seconds
Started Jul 25 07:12:29 PM PDT 24
Finished Jul 25 07:13:18 PM PDT 24
Peak memory 200256 kb
Host smart-3f185c3e-3a59-49fa-a5ed-4dd36fdfded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457334044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3457334044
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2185088070
Short name T1075
Test name
Test status
Simulation time 50037396401 ps
CPU time 74.47 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 200260 kb
Host smart-97ed3403-9276-4b10-891f-da5489bcbe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185088070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2185088070
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2235247838
Short name T931
Test name
Test status
Simulation time 119257363868 ps
CPU time 31.82 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:13:02 PM PDT 24
Peak memory 200240 kb
Host smart-48a7c93f-48f0-4f74-b5ee-ae4426ebc5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235247838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2235247838
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2355226070
Short name T949
Test name
Test status
Simulation time 79001960190 ps
CPU time 31.1 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:13:02 PM PDT 24
Peak memory 200152 kb
Host smart-78eb702f-d8c7-4a36-a44b-0efbb8fc0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355226070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2355226070
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4228966406
Short name T977
Test name
Test status
Simulation time 31076747 ps
CPU time 0.59 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:10:15 PM PDT 24
Peak memory 195852 kb
Host smart-c7d8849a-2c05-44e7-a72a-1baa8ccd12e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228966406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4228966406
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3665141649
Short name T142
Test name
Test status
Simulation time 37576935383 ps
CPU time 18.68 seconds
Started Jul 25 07:10:02 PM PDT 24
Finished Jul 25 07:10:21 PM PDT 24
Peak memory 200240 kb
Host smart-3421175e-5e09-4cf1-9f5d-55c7953c036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665141649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3665141649
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2352005872
Short name T155
Test name
Test status
Simulation time 44042633161 ps
CPU time 15.84 seconds
Started Jul 25 07:09:53 PM PDT 24
Finished Jul 25 07:10:09 PM PDT 24
Peak memory 200244 kb
Host smart-e173454a-12f9-4f50-9ca9-b5138a8804f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352005872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2352005872
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1014227825
Short name T520
Test name
Test status
Simulation time 30048126417 ps
CPU time 43.04 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:11:01 PM PDT 24
Peak memory 200256 kb
Host smart-9914b58d-ab4f-4848-be2c-84fa587c67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014227825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1014227825
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2551790455
Short name T676
Test name
Test status
Simulation time 18041888331 ps
CPU time 5.97 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 200144 kb
Host smart-c06ab0ba-9f26-4687-ba3c-54f6a8775dbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551790455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2551790455
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1120080726
Short name T9
Test name
Test status
Simulation time 42781146826 ps
CPU time 258.77 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 200180 kb
Host smart-2568b469-4434-41a8-9585-0b6144d4ada0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120080726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1120080726
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.711311095
Short name T875
Test name
Test status
Simulation time 7437785352 ps
CPU time 7.16 seconds
Started Jul 25 07:10:02 PM PDT 24
Finished Jul 25 07:10:09 PM PDT 24
Peak memory 199052 kb
Host smart-a051ab8e-3c67-4069-b12a-e16368704980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711311095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.711311095
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3579757632
Short name T681
Test name
Test status
Simulation time 19238402907 ps
CPU time 27.84 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 200320 kb
Host smart-428da884-1686-4618-ae5c-7ac23a70cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579757632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3579757632
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1952908208
Short name T703
Test name
Test status
Simulation time 14182107562 ps
CPU time 655.94 seconds
Started Jul 25 07:10:07 PM PDT 24
Finished Jul 25 07:21:03 PM PDT 24
Peak memory 200216 kb
Host smart-5773de69-5fb7-40ed-857b-ca05d28b646c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952908208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1952908208
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.333301366
Short name T1011
Test name
Test status
Simulation time 5710644184 ps
CPU time 46.92 seconds
Started Jul 25 07:10:09 PM PDT 24
Finished Jul 25 07:10:56 PM PDT 24
Peak memory 199336 kb
Host smart-49cc83b5-adf6-49e3-b881-b38654010914
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333301366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.333301366
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2083153438
Short name T837
Test name
Test status
Simulation time 334482299098 ps
CPU time 28.45 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:45 PM PDT 24
Peak memory 198908 kb
Host smart-5ce219c0-c55a-4659-b0a6-41c91a1afdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083153438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2083153438
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.259573057
Short name T1025
Test name
Test status
Simulation time 3549267628 ps
CPU time 2.13 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:10:14 PM PDT 24
Peak memory 196620 kb
Host smart-896c90c3-2807-4d68-ad9c-337c05bfcbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259573057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.259573057
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2200029732
Short name T523
Test name
Test status
Simulation time 499205919 ps
CPU time 1.99 seconds
Started Jul 25 07:10:08 PM PDT 24
Finished Jul 25 07:10:10 PM PDT 24
Peak memory 199100 kb
Host smart-52fd9b32-18cd-460a-9e19-10e0e19aaaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200029732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2200029732
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.867455616
Short name T304
Test name
Test status
Simulation time 193931212032 ps
CPU time 1074.68 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:28:11 PM PDT 24
Peak memory 208552 kb
Host smart-0ac6eacf-5999-4e8a-b078-5833522d19b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867455616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.867455616
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.499586864
Short name T37
Test name
Test status
Simulation time 83983679737 ps
CPU time 1467.3 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:34:42 PM PDT 24
Peak memory 225052 kb
Host smart-6d52a544-946a-44ec-afe9-f8a2c7b59e58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499586864 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.499586864
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1543217972
Short name T910
Test name
Test status
Simulation time 558988965 ps
CPU time 2.01 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:10:09 PM PDT 24
Peak memory 199784 kb
Host smart-463fa86f-9672-4f11-b853-bbea601a09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543217972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1543217972
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2335528543
Short name T583
Test name
Test status
Simulation time 107556773174 ps
CPU time 25.97 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:10:40 PM PDT 24
Peak memory 200188 kb
Host smart-3123b212-7f99-46a4-94f8-bea436071a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335528543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2335528543
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3409925916
Short name T206
Test name
Test status
Simulation time 23089790532 ps
CPU time 43.85 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 200204 kb
Host smart-f86153e0-9141-484b-ad1a-b7861f08c129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409925916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3409925916
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1260660418
Short name T771
Test name
Test status
Simulation time 22438221081 ps
CPU time 33.46 seconds
Started Jul 25 07:12:30 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 200044 kb
Host smart-507dc008-e8ad-4e80-aa4b-d701c1d448bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260660418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1260660418
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2166198969
Short name T950
Test name
Test status
Simulation time 10217785793 ps
CPU time 11.42 seconds
Started Jul 25 07:12:28 PM PDT 24
Finished Jul 25 07:12:39 PM PDT 24
Peak memory 200188 kb
Host smart-6a80b357-bf0f-4f19-8964-a89bacc9a7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166198969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2166198969
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1606519391
Short name T997
Test name
Test status
Simulation time 5373168235 ps
CPU time 8.62 seconds
Started Jul 25 07:12:32 PM PDT 24
Finished Jul 25 07:12:41 PM PDT 24
Peak memory 199872 kb
Host smart-b1be00c8-523e-4b98-9b78-334b89a20483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606519391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1606519391
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1375039964
Short name T1118
Test name
Test status
Simulation time 256130523569 ps
CPU time 39.25 seconds
Started Jul 25 07:12:40 PM PDT 24
Finished Jul 25 07:13:19 PM PDT 24
Peak memory 200112 kb
Host smart-0edb2d28-1d4b-49d3-be12-cdfb2111032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375039964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1375039964
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3001503521
Short name T608
Test name
Test status
Simulation time 206336447089 ps
CPU time 86.9 seconds
Started Jul 25 07:12:44 PM PDT 24
Finished Jul 25 07:14:11 PM PDT 24
Peak memory 200084 kb
Host smart-11f4c8c0-4458-4022-888d-39b5c3761f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001503521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3001503521
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1286200713
Short name T1121
Test name
Test status
Simulation time 138383612864 ps
CPU time 77.03 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 200148 kb
Host smart-fef11a79-a209-4647-a0d2-6c6582b32662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286200713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1286200713
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2058376900
Short name T482
Test name
Test status
Simulation time 26270775976 ps
CPU time 22.08 seconds
Started Jul 25 07:12:39 PM PDT 24
Finished Jul 25 07:13:02 PM PDT 24
Peak memory 200148 kb
Host smart-3e348e75-0c11-4312-84e7-298c0a2af4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058376900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2058376900
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2691119936
Short name T292
Test name
Test status
Simulation time 32747124749 ps
CPU time 11.76 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:12:50 PM PDT 24
Peak memory 200216 kb
Host smart-5d60f0f0-a983-44cd-aba6-8f7005ad069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691119936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2691119936
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3555550217
Short name T544
Test name
Test status
Simulation time 12057698 ps
CPU time 0.55 seconds
Started Jul 25 07:10:21 PM PDT 24
Finished Jul 25 07:10:22 PM PDT 24
Peak memory 195620 kb
Host smart-a287ca00-5ceb-4906-a7a6-9bf8c6527d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555550217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3555550217
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3701964300
Short name T673
Test name
Test status
Simulation time 61631245057 ps
CPU time 45.21 seconds
Started Jul 25 07:10:21 PM PDT 24
Finished Jul 25 07:11:07 PM PDT 24
Peak memory 200124 kb
Host smart-c990b7f9-5c82-4705-b599-b096a4ed21b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701964300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3701964300
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.619451024
Short name T547
Test name
Test status
Simulation time 258432227436 ps
CPU time 153.44 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:12:49 PM PDT 24
Peak memory 200236 kb
Host smart-3bfdaced-3db2-4742-95aa-9f970434ec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619451024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.619451024
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.4078626774
Short name T472
Test name
Test status
Simulation time 96064821188 ps
CPU time 143.73 seconds
Started Jul 25 07:10:04 PM PDT 24
Finished Jul 25 07:12:28 PM PDT 24
Peak memory 200180 kb
Host smart-6779e292-ed0d-4a09-af82-73eb755e6447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078626774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4078626774
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1417056106
Short name T667
Test name
Test status
Simulation time 36432197128 ps
CPU time 21.56 seconds
Started Jul 25 07:09:57 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 200404 kb
Host smart-9519a9ae-ce1f-4cb3-bf48-3d698982a01e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417056106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1417056106
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.76954424
Short name T723
Test name
Test status
Simulation time 113177003517 ps
CPU time 311.38 seconds
Started Jul 25 07:09:57 PM PDT 24
Finished Jul 25 07:15:08 PM PDT 24
Peak memory 200348 kb
Host smart-a731d6a6-388e-40c4-9710-92e65563afea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76954424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.76954424
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3277286694
Short name T731
Test name
Test status
Simulation time 8690959214 ps
CPU time 3.43 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:03 PM PDT 24
Peak memory 200180 kb
Host smart-5a04f513-6548-4240-bdb4-fd3f3fc1300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277286694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3277286694
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4279779887
Short name T619
Test name
Test status
Simulation time 53365809262 ps
CPU time 38.72 seconds
Started Jul 25 07:10:20 PM PDT 24
Finished Jul 25 07:10:58 PM PDT 24
Peak memory 200320 kb
Host smart-39a80826-f6ab-4548-a10f-f95e488fcac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279779887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4279779887
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3476883688
Short name T967
Test name
Test status
Simulation time 15054694040 ps
CPU time 313.22 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:15:27 PM PDT 24
Peak memory 200224 kb
Host smart-922bf518-36f0-4c45-8622-3539761ca7e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476883688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3476883688
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.185986208
Short name T592
Test name
Test status
Simulation time 5986518247 ps
CPU time 25.99 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 198436 kb
Host smart-b358b0b6-c729-453c-9549-f27bb2225b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185986208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.185986208
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.677078953
Short name T136
Test name
Test status
Simulation time 64527330075 ps
CPU time 124.93 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:12:11 PM PDT 24
Peak memory 200180 kb
Host smart-536f3f16-5048-43a5-bb66-e2a2ff0177db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677078953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.677078953
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.638779327
Short name T662
Test name
Test status
Simulation time 41933787045 ps
CPU time 57.59 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:57 PM PDT 24
Peak memory 196568 kb
Host smart-02777506-da35-48c9-8b64-e3fb7e653a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638779327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.638779327
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.138220867
Short name T631
Test name
Test status
Simulation time 90890939 ps
CPU time 0.82 seconds
Started Jul 25 07:09:57 PM PDT 24
Finished Jul 25 07:09:58 PM PDT 24
Peak memory 197376 kb
Host smart-5c0c07a8-0728-4fa4-a86a-7ab59b8e0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138220867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.138220867
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1516635104
Short name T416
Test name
Test status
Simulation time 230109079946 ps
CPU time 108.02 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:11:58 PM PDT 24
Peak memory 216536 kb
Host smart-50d0c64c-6d14-4742-ade4-54e0b56eb3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516635104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1516635104
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.750710656
Short name T1180
Test name
Test status
Simulation time 1174133638 ps
CPU time 4.03 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 198900 kb
Host smart-ed57004d-b756-463e-8c1c-26a8197a99fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750710656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.750710656
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.470274660
Short name T355
Test name
Test status
Simulation time 1414833548 ps
CPU time 1.2 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 197276 kb
Host smart-3df2a227-bcef-43c8-a175-74c703cac664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470274660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.470274660
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.630752701
Short name T991
Test name
Test status
Simulation time 73043614025 ps
CPU time 195.1 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:15:53 PM PDT 24
Peak memory 200180 kb
Host smart-43a4e63e-9366-4348-a595-943454685d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630752701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.630752701
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.269044930
Short name T980
Test name
Test status
Simulation time 9178768000 ps
CPU time 20.35 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:12:58 PM PDT 24
Peak memory 200156 kb
Host smart-fd6b4284-e044-4d24-8dd1-c2a725b1f69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269044930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.269044930
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3097837290
Short name T933
Test name
Test status
Simulation time 183703613901 ps
CPU time 30.93 seconds
Started Jul 25 07:12:43 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 200192 kb
Host smart-bb94c9b5-816c-4f73-8293-f642df3f053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097837290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3097837290
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3231036737
Short name T467
Test name
Test status
Simulation time 278657318940 ps
CPU time 102.91 seconds
Started Jul 25 07:12:36 PM PDT 24
Finished Jul 25 07:14:19 PM PDT 24
Peak memory 200364 kb
Host smart-0585626e-7445-4824-b3ec-3c7bf7048487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231036737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3231036737
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3613297765
Short name T1167
Test name
Test status
Simulation time 122916897492 ps
CPU time 158.39 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:15:17 PM PDT 24
Peak memory 199960 kb
Host smart-6421fd3d-d4c2-419b-bb86-4cedac6216c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613297765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3613297765
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3655091870
Short name T1179
Test name
Test status
Simulation time 9990689959 ps
CPU time 25.31 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 200240 kb
Host smart-2dbda6b1-478a-4310-b105-a50a541ded2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655091870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3655091870
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.363276579
Short name T198
Test name
Test status
Simulation time 107411776785 ps
CPU time 235.91 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:16:35 PM PDT 24
Peak memory 200184 kb
Host smart-ba914687-a957-4601-8de6-76989dee9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363276579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.363276579
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1519610258
Short name T1110
Test name
Test status
Simulation time 48352879941 ps
CPU time 18.32 seconds
Started Jul 25 07:12:37 PM PDT 24
Finished Jul 25 07:12:55 PM PDT 24
Peak memory 200248 kb
Host smart-7e055500-b4f2-4a35-a04f-fc1b3db07de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519610258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1519610258
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4015925085
Short name T987
Test name
Test status
Simulation time 97634277048 ps
CPU time 77.47 seconds
Started Jul 25 07:12:39 PM PDT 24
Finished Jul 25 07:13:57 PM PDT 24
Peak memory 200208 kb
Host smart-2b61d1e2-06ea-45e9-962c-c700736d91a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015925085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4015925085
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3938079060
Short name T856
Test name
Test status
Simulation time 12047715 ps
CPU time 0.54 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 195684 kb
Host smart-33d4efa3-711e-4066-9c03-d4c5f4f0d727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938079060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3938079060
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.744293935
Short name T951
Test name
Test status
Simulation time 55983278877 ps
CPU time 100.6 seconds
Started Jul 25 07:10:00 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200260 kb
Host smart-41ae3d3f-ac5b-47c5-9f5d-ac3f59da4871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744293935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.744293935
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3786261088
Short name T830
Test name
Test status
Simulation time 33439304768 ps
CPU time 14.94 seconds
Started Jul 25 07:10:08 PM PDT 24
Finished Jul 25 07:10:24 PM PDT 24
Peak memory 200268 kb
Host smart-4b443f28-6ed6-4a34-a8e6-2a3895782233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786261088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3786261088
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2173517590
Short name T690
Test name
Test status
Simulation time 123474724408 ps
CPU time 54.64 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:11:09 PM PDT 24
Peak memory 200180 kb
Host smart-874e941e-8955-4e22-b98a-77c9bc4b173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173517590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2173517590
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2598242800
Short name T247
Test name
Test status
Simulation time 93367512729 ps
CPU time 134.91 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:12:27 PM PDT 24
Peak memory 200256 kb
Host smart-f568a920-7dce-4e42-9789-4adf2dcea964
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598242800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2598242800
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4264979336
Short name T842
Test name
Test status
Simulation time 87144998151 ps
CPU time 439.57 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:17:31 PM PDT 24
Peak memory 200244 kb
Host smart-f8cff00b-bd5d-4873-9a8b-a9751f970773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264979336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4264979336
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1888514214
Short name T736
Test name
Test status
Simulation time 9168935394 ps
CPU time 22.1 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 199868 kb
Host smart-e3ccb20c-d4f1-40da-8a72-7b4c0aa4d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888514214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1888514214
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1814873007
Short name T253
Test name
Test status
Simulation time 158020334671 ps
CPU time 67.93 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 200344 kb
Host smart-1699adbe-c412-44a6-ac62-2eea5cc21a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814873007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1814873007
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2624202731
Short name T1028
Test name
Test status
Simulation time 12987530735 ps
CPU time 202.05 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 200192 kb
Host smart-dcb70d16-b84e-46be-84c7-0efa658b9617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624202731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2624202731
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2371554135
Short name T778
Test name
Test status
Simulation time 6974221088 ps
CPU time 17.62 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:10:28 PM PDT 24
Peak memory 198632 kb
Host smart-6e89ab6d-3953-448a-a054-af3b484fbc3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371554135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2371554135
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.426370116
Short name T695
Test name
Test status
Simulation time 118301140274 ps
CPU time 237.28 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:14:12 PM PDT 24
Peak memory 200244 kb
Host smart-fbdec1fb-a595-420c-8f47-837a0811c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426370116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.426370116
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3224710456
Short name T908
Test name
Test status
Simulation time 3482541530 ps
CPU time 3.48 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:26 PM PDT 24
Peak memory 196548 kb
Host smart-21ade015-9287-45b7-ab6e-2bf4aa7d63a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224710456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3224710456
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.360388756
Short name T715
Test name
Test status
Simulation time 484295813 ps
CPU time 1.21 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 199612 kb
Host smart-5e5abe79-854c-496d-9150-6021e407e473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360388756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.360388756
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.4035984272
Short name T517
Test name
Test status
Simulation time 336181874261 ps
CPU time 223.08 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 216620 kb
Host smart-abd83b60-d887-4a98-baad-30ac596fe596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035984272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4035984272
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.71594850
Short name T463
Test name
Test status
Simulation time 110003652681 ps
CPU time 341.86 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:16:00 PM PDT 24
Peak memory 216896 kb
Host smart-5fece47b-92a2-4d2f-beff-adbb6eb4e93b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71594850 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.71594850
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.227025095
Short name T309
Test name
Test status
Simulation time 6972232131 ps
CPU time 39.52 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 199972 kb
Host smart-4a6564b4-d22a-470c-b518-8e1c43c9ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227025095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.227025095
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3572543613
Short name T335
Test name
Test status
Simulation time 8038202693 ps
CPU time 8.05 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 198992 kb
Host smart-c4e20fd6-650e-438e-9c9a-97e995863a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572543613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3572543613
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3378319226
Short name T205
Test name
Test status
Simulation time 94537342246 ps
CPU time 132.21 seconds
Started Jul 25 07:12:43 PM PDT 24
Finished Jul 25 07:14:55 PM PDT 24
Peak memory 200164 kb
Host smart-662820ba-33db-44a7-85c1-de975ac3db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378319226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3378319226
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2387317139
Short name T242
Test name
Test status
Simulation time 21858564657 ps
CPU time 12.32 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:12:50 PM PDT 24
Peak memory 200240 kb
Host smart-055de264-7504-4128-a1f6-699cf2e6b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387317139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2387317139
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2462189827
Short name T946
Test name
Test status
Simulation time 53107599118 ps
CPU time 149.05 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:15:07 PM PDT 24
Peak memory 200240 kb
Host smart-eaae5739-3848-4ca1-9d7b-2414348b8d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462189827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2462189827
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.150222501
Short name T705
Test name
Test status
Simulation time 162771996946 ps
CPU time 62.77 seconds
Started Jul 25 07:12:36 PM PDT 24
Finished Jul 25 07:13:39 PM PDT 24
Peak memory 200224 kb
Host smart-1f16956a-106c-4e3a-a234-59a0e5251fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150222501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.150222501
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3285009042
Short name T833
Test name
Test status
Simulation time 69374812591 ps
CPU time 14.19 seconds
Started Jul 25 07:12:37 PM PDT 24
Finished Jul 25 07:12:51 PM PDT 24
Peak memory 200220 kb
Host smart-c882434a-cf81-48ac-9802-1ae9021b969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285009042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3285009042
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3514354879
Short name T1105
Test name
Test status
Simulation time 43763944000 ps
CPU time 33.65 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 200176 kb
Host smart-f92c3491-0ddc-4187-82db-9d2dbc085fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514354879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3514354879
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.616504207
Short name T210
Test name
Test status
Simulation time 169383016873 ps
CPU time 42.83 seconds
Started Jul 25 07:12:36 PM PDT 24
Finished Jul 25 07:13:19 PM PDT 24
Peak memory 200240 kb
Host smart-c91ac3cb-4a9d-404e-9f9e-aae0a651a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616504207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.616504207
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.489457054
Short name T528
Test name
Test status
Simulation time 140624202873 ps
CPU time 249.8 seconds
Started Jul 25 07:12:44 PM PDT 24
Finished Jul 25 07:16:54 PM PDT 24
Peak memory 200156 kb
Host smart-cf031fa5-1a97-46e6-8869-9d1f6227f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489457054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.489457054
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1798317469
Short name T751
Test name
Test status
Simulation time 9185646855 ps
CPU time 14.94 seconds
Started Jul 25 07:12:42 PM PDT 24
Finished Jul 25 07:12:58 PM PDT 24
Peak memory 199136 kb
Host smart-8bc929ae-91b1-46ec-8678-ec5f2c6de933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798317469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1798317469
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4093755028
Short name T938
Test name
Test status
Simulation time 215645371422 ps
CPU time 47.75 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:11:01 PM PDT 24
Peak memory 200216 kb
Host smart-16fbe7bd-3b70-455e-8bad-2b442d4612a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093755028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4093755028
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.261893748
Short name T506
Test name
Test status
Simulation time 30945301860 ps
CPU time 38.37 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:10:56 PM PDT 24
Peak memory 200212 kb
Host smart-ecf91003-4a58-42f6-af14-7b696aa22df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261893748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.261893748
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2519945145
Short name T934
Test name
Test status
Simulation time 92642807150 ps
CPU time 132.47 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:12:27 PM PDT 24
Peak memory 200080 kb
Host smart-5935f22a-c8f9-4106-8b90-0216da250316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519945145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2519945145
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3006050218
Short name T974
Test name
Test status
Simulation time 21030215117 ps
CPU time 8.72 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:10:24 PM PDT 24
Peak memory 200252 kb
Host smart-00d4bada-5b46-4545-829f-28855c30c24f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006050218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3006050218
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1844297174
Short name T735
Test name
Test status
Simulation time 94163034539 ps
CPU time 241.83 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:14:30 PM PDT 24
Peak memory 200248 kb
Host smart-3d5e218a-153e-44d8-b4e3-0cd608b22fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844297174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1844297174
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.723168152
Short name T1090
Test name
Test status
Simulation time 3018640278 ps
CPU time 1.96 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 198516 kb
Host smart-a66fb63a-d090-4a0c-bad4-b36164295182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723168152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.723168152
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.197735041
Short name T2
Test name
Test status
Simulation time 121879462116 ps
CPU time 36 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 200388 kb
Host smart-6bc6430a-ebfd-441a-b697-0c718b4bdbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197735041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.197735041
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1818095534
Short name T441
Test name
Test status
Simulation time 11082514055 ps
CPU time 298.89 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:15:16 PM PDT 24
Peak memory 199988 kb
Host smart-f18bbf30-4208-4992-8c12-a934f3db3609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818095534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1818095534
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2797778677
Short name T823
Test name
Test status
Simulation time 6518803621 ps
CPU time 28.95 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 199308 kb
Host smart-c9f569c0-58d6-489a-9afd-02e3bc13eb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797778677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2797778677
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2796945933
Short name T1077
Test name
Test status
Simulation time 19005675934 ps
CPU time 16.74 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 199584 kb
Host smart-ae36935b-8b18-4cec-9494-f922cf17c1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796945933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2796945933
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.430530965
Short name T499
Test name
Test status
Simulation time 31490210324 ps
CPU time 4.57 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 196136 kb
Host smart-8ececd77-9b77-4a1a-8f91-97b9c7399722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430530965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.430530965
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2140360418
Short name T534
Test name
Test status
Simulation time 935904672 ps
CPU time 6.66 seconds
Started Jul 25 07:10:06 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 199128 kb
Host smart-66a290f2-ad05-4cec-a664-40b6a95c47e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140360418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2140360418
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1534610615
Short name T493
Test name
Test status
Simulation time 440037871681 ps
CPU time 464.49 seconds
Started Jul 25 07:10:09 PM PDT 24
Finished Jul 25 07:17:54 PM PDT 24
Peak memory 216684 kb
Host smart-623d8614-8b74-412b-a166-13c84777c56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534610615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1534610615
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2132175950
Short name T308
Test name
Test status
Simulation time 47936881759 ps
CPU time 875.75 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:24:54 PM PDT 24
Peak memory 228188 kb
Host smart-f9650d51-af8c-4a07-b835-c750f91e6b97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132175950 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2132175950
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1081683860
Short name T803
Test name
Test status
Simulation time 1810657575 ps
CPU time 2.32 seconds
Started Jul 25 07:10:43 PM PDT 24
Finished Jul 25 07:10:45 PM PDT 24
Peak memory 198732 kb
Host smart-d2f33beb-e93e-4e5b-a30c-512a22e4bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081683860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1081683860
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2742915063
Short name T332
Test name
Test status
Simulation time 30268055492 ps
CPU time 32.45 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:10:47 PM PDT 24
Peak memory 200164 kb
Host smart-5f4f6721-3c35-44a8-a4da-97d7292282a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742915063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2742915063
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1946093199
Short name T10
Test name
Test status
Simulation time 121734123166 ps
CPU time 26.1 seconds
Started Jul 25 07:12:39 PM PDT 24
Finished Jul 25 07:13:06 PM PDT 24
Peak memory 200236 kb
Host smart-3ae6aa7e-c4c3-476c-ae78-b21927440068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946093199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1946093199
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2737110794
Short name T530
Test name
Test status
Simulation time 18816760401 ps
CPU time 27.67 seconds
Started Jul 25 07:12:38 PM PDT 24
Finished Jul 25 07:13:06 PM PDT 24
Peak memory 200212 kb
Host smart-db5a73b7-b609-40b3-906f-e485e392843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737110794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2737110794
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3817645652
Short name T492
Test name
Test status
Simulation time 93701295123 ps
CPU time 38.19 seconds
Started Jul 25 07:12:40 PM PDT 24
Finished Jul 25 07:13:18 PM PDT 24
Peak memory 200064 kb
Host smart-2de1bdb1-c00c-4306-a422-97f0aea6be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817645652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3817645652
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3233245495
Short name T1117
Test name
Test status
Simulation time 109650894445 ps
CPU time 176.87 seconds
Started Jul 25 07:12:43 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200252 kb
Host smart-c1fed964-d741-477d-85ac-7d11c63aa372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233245495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3233245495
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.904630374
Short name T798
Test name
Test status
Simulation time 6615942526 ps
CPU time 6.26 seconds
Started Jul 25 07:20:06 PM PDT 24
Finished Jul 25 07:20:12 PM PDT 24
Peak memory 200244 kb
Host smart-6fd2ae5c-04a7-4971-a4d1-5165f4800cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904630374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.904630374
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1353339275
Short name T122
Test name
Test status
Simulation time 132330901421 ps
CPU time 61 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 200248 kb
Host smart-7a4476cf-1d65-4a65-bdbd-dae3cfbc84a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353339275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1353339275
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3557049061
Short name T585
Test name
Test status
Simulation time 68979245231 ps
CPU time 58.51 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 200260 kb
Host smart-d32f8b6a-6db9-4584-9ed3-55298fe5b698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557049061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3557049061
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2973091992
Short name T836
Test name
Test status
Simulation time 98600238902 ps
CPU time 47 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:13:34 PM PDT 24
Peak memory 200256 kb
Host smart-f85ee63f-949c-408a-9f4f-20b5c33da9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973091992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2973091992
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.296467651
Short name T906
Test name
Test status
Simulation time 355385915047 ps
CPU time 126.16 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:14:51 PM PDT 24
Peak memory 200252 kb
Host smart-dd94350c-b241-42c8-adc4-61c370d84d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296467651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.296467651
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4010619334
Short name T917
Test name
Test status
Simulation time 101128069607 ps
CPU time 152.14 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:15:19 PM PDT 24
Peak memory 200212 kb
Host smart-67bd1b9d-3d84-4854-8bd4-1de9471acc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010619334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4010619334
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3188709583
Short name T27
Test name
Test status
Simulation time 14227895 ps
CPU time 0.55 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 194560 kb
Host smart-3c864827-e0a0-489b-bd63-9c1d099b5b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188709583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3188709583
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.849911571
Short name T867
Test name
Test status
Simulation time 245872530613 ps
CPU time 103.17 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:11:16 PM PDT 24
Peak memory 200200 kb
Host smart-1f14d551-677b-4236-989e-5abab84da39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849911571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.849911571
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1409504361
Short name T958
Test name
Test status
Simulation time 141413273379 ps
CPU time 171.12 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:12:27 PM PDT 24
Peak memory 200184 kb
Host smart-92236483-6751-4ab4-9c47-a3d5b4c0ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409504361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1409504361
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2403741202
Short name T1150
Test name
Test status
Simulation time 142400680035 ps
CPU time 41.64 seconds
Started Jul 25 07:09:30 PM PDT 24
Finished Jul 25 07:10:12 PM PDT 24
Peak memory 200100 kb
Host smart-50b28933-fb0d-464e-a53b-c4f3ca14483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403741202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2403741202
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.241154431
Short name T387
Test name
Test status
Simulation time 6900819312 ps
CPU time 8.06 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:44 PM PDT 24
Peak memory 197216 kb
Host smart-c4a8e94c-a9e2-4b2b-9b9e-afb754fc17b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241154431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.241154431
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1103105416
Short name T1176
Test name
Test status
Simulation time 118688441563 ps
CPU time 298.73 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:14:41 PM PDT 24
Peak memory 200232 kb
Host smart-c20ac424-e646-4e30-8f83-280b16e721e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103105416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1103105416
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3323984925
Short name T642
Test name
Test status
Simulation time 712550676 ps
CPU time 2.06 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:09:42 PM PDT 24
Peak memory 198592 kb
Host smart-e3c61035-2bd6-481e-8346-e2750539a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323984925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3323984925
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.327049928
Short name T1061
Test name
Test status
Simulation time 23861757339 ps
CPU time 34.84 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:10:09 PM PDT 24
Peak memory 199264 kb
Host smart-8cf9c302-a900-4241-9c62-affafcec30e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327049928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.327049928
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3228850864
Short name T1079
Test name
Test status
Simulation time 8964683882 ps
CPU time 507.7 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:18:04 PM PDT 24
Peak memory 200216 kb
Host smart-378d8eff-e354-440f-86c1-e098afc58f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228850864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3228850864
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.648315480
Short name T1129
Test name
Test status
Simulation time 3173740829 ps
CPU time 16.42 seconds
Started Jul 25 07:09:29 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 199308 kb
Host smart-541ac616-636f-47d2-87f5-3fa4e1b15ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648315480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.648315480
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1438328603
Short name T1175
Test name
Test status
Simulation time 49163705910 ps
CPU time 17.38 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:59 PM PDT 24
Peak memory 200244 kb
Host smart-13874107-4b59-472b-a195-b4649f881aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438328603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1438328603
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1125481248
Short name T359
Test name
Test status
Simulation time 1812421124 ps
CPU time 1.94 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:39 PM PDT 24
Peak memory 195948 kb
Host smart-c4511238-973b-45f8-9f13-793a68dd1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125481248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1125481248
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2360659255
Short name T31
Test name
Test status
Simulation time 110624404 ps
CPU time 0.81 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 218436 kb
Host smart-292e9058-c976-4604-babe-170b9b370f3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360659255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2360659255
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2748895204
Short name T640
Test name
Test status
Simulation time 762665358 ps
CPU time 1.67 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:34 PM PDT 24
Peak memory 198712 kb
Host smart-7e01330a-5b5b-4689-a2ff-25961c2b9865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748895204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2748895204
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1612740391
Short name T873
Test name
Test status
Simulation time 19991931148 ps
CPU time 137.09 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:11:58 PM PDT 24
Peak memory 216592 kb
Host smart-cfc98885-4b3d-46b7-8a74-fe35e1b35f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612740391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1612740391
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1220060172
Short name T295
Test name
Test status
Simulation time 1954748265 ps
CPU time 2.05 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:09:39 PM PDT 24
Peak memory 200148 kb
Host smart-23865d5f-7c77-44aa-b9a7-001902ee3ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220060172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1220060172
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2736230728
Short name T425
Test name
Test status
Simulation time 10402737439 ps
CPU time 15.26 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:49 PM PDT 24
Peak memory 197876 kb
Host smart-9aac89e4-28f8-4b7b-8e44-43aadd34c37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736230728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2736230728
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1066386653
Short name T28
Test name
Test status
Simulation time 13288459 ps
CPU time 0.59 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 195272 kb
Host smart-47fc564e-b8f1-4f62-a937-0a8d97881f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066386653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1066386653
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.549954542
Short name T581
Test name
Test status
Simulation time 68965413748 ps
CPU time 55.25 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:55 PM PDT 24
Peak memory 200188 kb
Host smart-3c327e61-d837-4738-be00-aab151896270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549954542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.549954542
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.430260524
Short name T460
Test name
Test status
Simulation time 10102437673 ps
CPU time 17.14 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:10:35 PM PDT 24
Peak memory 199992 kb
Host smart-e2e4cd23-e363-485d-90fe-e69abf217bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430260524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.430260524
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2922075079
Short name T1106
Test name
Test status
Simulation time 26450382326 ps
CPU time 41.95 seconds
Started Jul 25 07:10:20 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 200196 kb
Host smart-fbb36daf-310c-4ead-a75b-d9cac6a616fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922075079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2922075079
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4258729410
Short name T487
Test name
Test status
Simulation time 18779183945 ps
CPU time 31.2 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:10:41 PM PDT 24
Peak memory 200228 kb
Host smart-24de1501-771c-4c9b-802a-3f0cbbbac1c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258729410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4258729410
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2082197346
Short name T994
Test name
Test status
Simulation time 60613448183 ps
CPU time 433.83 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:17:38 PM PDT 24
Peak memory 199940 kb
Host smart-3b1c52e7-06f7-4621-a0ee-2687338955d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082197346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2082197346
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1616791871
Short name T919
Test name
Test status
Simulation time 8373906177 ps
CPU time 5.69 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 200196 kb
Host smart-c635fc2a-f83b-4b33-84f3-50502c68abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616791871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1616791871
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.73531584
Short name T697
Test name
Test status
Simulation time 12985400647 ps
CPU time 10.45 seconds
Started Jul 25 07:10:10 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 197296 kb
Host smart-3ae21d8c-33c6-4cce-94df-19c07de64b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73531584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.73531584
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4235048223
Short name T766
Test name
Test status
Simulation time 6119345845 ps
CPU time 312.36 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 199992 kb
Host smart-2e4822be-3c02-46ba-9c98-53102ff1d505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235048223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4235048223
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3526372957
Short name T339
Test name
Test status
Simulation time 7646232918 ps
CPU time 4.94 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 198588 kb
Host smart-23fefdde-ab36-4d91-b8ca-436de964f16c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526372957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3526372957
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2613819885
Short name T44
Test name
Test status
Simulation time 148838238036 ps
CPU time 31.73 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:10:46 PM PDT 24
Peak memory 200208 kb
Host smart-8b3036e4-5a59-478a-b119-5f7c12d1bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613819885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2613819885
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3892092671
Short name T404
Test name
Test status
Simulation time 34220341803 ps
CPU time 48.73 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 196344 kb
Host smart-8f0527dd-4c83-4a23-907c-0fa36b2cb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892092671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3892092671
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.461377021
Short name T750
Test name
Test status
Simulation time 499611623 ps
CPU time 2.2 seconds
Started Jul 25 07:10:12 PM PDT 24
Finished Jul 25 07:10:14 PM PDT 24
Peak memory 199484 kb
Host smart-678fa4b1-d18e-4f5a-b7c8-0cd8788c08dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461377021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.461377021
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3837442159
Short name T64
Test name
Test status
Simulation time 435027047114 ps
CPU time 1542.16 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:36:02 PM PDT 24
Peak memory 228240 kb
Host smart-933aa901-9398-483d-b151-1ff44b324bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837442159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3837442159
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.775040189
Short name T5
Test name
Test status
Simulation time 979690955 ps
CPU time 2.86 seconds
Started Jul 25 07:10:13 PM PDT 24
Finished Jul 25 07:10:16 PM PDT 24
Peak memory 199448 kb
Host smart-f559a007-b5c4-454d-ab0c-eca7783548a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775040189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.775040189
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2275678848
Short name T787
Test name
Test status
Simulation time 40036279835 ps
CPU time 17.19 seconds
Started Jul 25 07:10:21 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 199996 kb
Host smart-b1370c21-2ab0-4ebb-b6c0-773f2a94de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275678848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2275678848
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1824022473
Short name T1046
Test name
Test status
Simulation time 139870244197 ps
CPU time 32.1 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200016 kb
Host smart-91835208-c98d-4a00-9b63-f4ba7f6ba375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824022473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1824022473
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3077896202
Short name T580
Test name
Test status
Simulation time 12278702810 ps
CPU time 17.53 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 199224 kb
Host smart-2e0be224-cdf0-424c-b978-24f9d4463c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077896202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3077896202
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3667522460
Short name T860
Test name
Test status
Simulation time 57649955211 ps
CPU time 143.19 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:15:09 PM PDT 24
Peak memory 200192 kb
Host smart-c561c21e-ed9e-4322-8874-7d7810c9b0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667522460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3667522460
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3166814187
Short name T221
Test name
Test status
Simulation time 44580539132 ps
CPU time 85.08 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:14:21 PM PDT 24
Peak memory 200188 kb
Host smart-90af490f-0d14-4cd8-b52a-cd16dc8a70f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166814187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3166814187
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4134413431
Short name T185
Test name
Test status
Simulation time 141535913564 ps
CPU time 220.68 seconds
Started Jul 25 07:13:18 PM PDT 24
Finished Jul 25 07:16:59 PM PDT 24
Peak memory 200184 kb
Host smart-8d3dcd82-2cbb-4564-af20-fdd7cfd53767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134413431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4134413431
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3180688871
Short name T234
Test name
Test status
Simulation time 108334248851 ps
CPU time 212.31 seconds
Started Jul 25 07:12:47 PM PDT 24
Finished Jul 25 07:16:19 PM PDT 24
Peak memory 200216 kb
Host smart-356ceea4-0045-477a-a9a9-5f8640da7545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180688871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3180688871
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.889759750
Short name T827
Test name
Test status
Simulation time 70168922696 ps
CPU time 46.02 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:13:33 PM PDT 24
Peak memory 199944 kb
Host smart-f6f9ec8e-530d-43c8-9b2c-28c675a80a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889759750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.889759750
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2085540879
Short name T641
Test name
Test status
Simulation time 26041425720 ps
CPU time 13.16 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:09 PM PDT 24
Peak memory 200188 kb
Host smart-85766192-98a6-4f65-a73d-113b3d680acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085540879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2085540879
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.142445556
Short name T808
Test name
Test status
Simulation time 40813523361 ps
CPU time 65.82 seconds
Started Jul 25 07:22:15 PM PDT 24
Finished Jul 25 07:23:22 PM PDT 24
Peak memory 200184 kb
Host smart-c1c13463-2d81-4063-84c0-71d4243b5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142445556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.142445556
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3337824026
Short name T744
Test name
Test status
Simulation time 153705927613 ps
CPU time 101.46 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:14:37 PM PDT 24
Peak memory 200256 kb
Host smart-9674a5d8-dcdb-4127-957c-278e3339caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337824026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3337824026
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.204927405
Short name T1008
Test name
Test status
Simulation time 35892834 ps
CPU time 0.54 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:10:29 PM PDT 24
Peak memory 195576 kb
Host smart-b2fb848e-2a52-437e-87a5-f5963c66f651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204927405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.204927405
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.304877375
Short name T590
Test name
Test status
Simulation time 61711614603 ps
CPU time 34.04 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200280 kb
Host smart-87be04fd-6de2-4bc3-aefe-a7e5b7f23bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304877375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.304877375
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2539425727
Short name T1148
Test name
Test status
Simulation time 141650214927 ps
CPU time 21.32 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:10:45 PM PDT 24
Peak memory 200248 kb
Host smart-11bce4d5-5503-4d53-ad98-0fb7c8333a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539425727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2539425727
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3108001289
Short name T124
Test name
Test status
Simulation time 52691294485 ps
CPU time 19.73 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:45 PM PDT 24
Peak memory 200272 kb
Host smart-930cddb5-6eb4-4cce-b379-d4cc2813782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108001289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3108001289
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3893355041
Short name T965
Test name
Test status
Simulation time 337975732364 ps
CPU time 478.87 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:18:24 PM PDT 24
Peak memory 200244 kb
Host smart-ff78c000-3d06-4a1c-a276-78533275c876
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893355041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3893355041
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3922170130
Short name T272
Test name
Test status
Simulation time 242105282962 ps
CPU time 1305.96 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:32:04 PM PDT 24
Peak memory 200244 kb
Host smart-bd1ec32e-96af-4c99-bccd-6cfa054a5d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922170130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3922170130
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2750234584
Short name T471
Test name
Test status
Simulation time 5334058909 ps
CPU time 10.74 seconds
Started Jul 25 07:10:26 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 199384 kb
Host smart-b2979192-8783-4fe3-a001-fded52178bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750234584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2750234584
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1731116280
Short name T572
Test name
Test status
Simulation time 100645596791 ps
CPU time 37.45 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:11:00 PM PDT 24
Peak memory 208308 kb
Host smart-b0515509-5f85-40b5-986a-317529376a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731116280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1731116280
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3663888606
Short name T861
Test name
Test status
Simulation time 10578815226 ps
CPU time 639.38 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:20:56 PM PDT 24
Peak memory 200248 kb
Host smart-ca6eb36b-6be0-433b-869b-771720e6074a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663888606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3663888606
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.339091638
Short name T1136
Test name
Test status
Simulation time 3903579341 ps
CPU time 15.15 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 198688 kb
Host smart-0b8c3c00-ad5c-4ff9-be82-f373eb6ee8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339091638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.339091638
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.914595447
Short name T587
Test name
Test status
Simulation time 7114291515 ps
CPU time 16.31 seconds
Started Jul 25 07:10:20 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 200248 kb
Host smart-ba0e6804-7ed1-4348-89c4-a93361c8efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914595447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.914595447
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1882516255
Short name T450
Test name
Test status
Simulation time 3651884534 ps
CPU time 3.3 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:10:23 PM PDT 24
Peak memory 196580 kb
Host smart-afba5aea-e099-4714-b420-8f3ccadf4d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882516255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1882516255
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3161246982
Short name T420
Test name
Test status
Simulation time 5621467256 ps
CPU time 4.59 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:21 PM PDT 24
Peak memory 200204 kb
Host smart-23257750-ad39-4359-9478-c09e1ead7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161246982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3161246982
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.724091742
Short name T1092
Test name
Test status
Simulation time 45501979460 ps
CPU time 78.3 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:11:38 PM PDT 24
Peak memory 200416 kb
Host smart-3e9d7656-3310-403b-8b25-4e7e2ca5e658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724091742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.724091742
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1492645737
Short name T556
Test name
Test status
Simulation time 19569355357 ps
CPU time 209.53 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 208608 kb
Host smart-3588ed39-9954-4452-a1d3-8657aad5afcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492645737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1492645737
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2130066505
Short name T342
Test name
Test status
Simulation time 813290356 ps
CPU time 2.54 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:10:22 PM PDT 24
Peak memory 199064 kb
Host smart-3454e57f-8ba2-4166-8cdb-0bca809676df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130066505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2130066505
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1917946211
Short name T596
Test name
Test status
Simulation time 77819464433 ps
CPU time 180.49 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:13:19 PM PDT 24
Peak memory 200256 kb
Host smart-59f284cb-9e34-4484-9736-1e3095233793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917946211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1917946211
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.613026133
Short name T971
Test name
Test status
Simulation time 110711279758 ps
CPU time 40.38 seconds
Started Jul 25 07:12:48 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200252 kb
Host smart-6b1a92b8-fa99-49b3-bda8-d0462d1e8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613026133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.613026133
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3652419471
Short name T518
Test name
Test status
Simulation time 78952356711 ps
CPU time 63.57 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:13:49 PM PDT 24
Peak memory 200172 kb
Host smart-c553f632-3860-4581-9c0c-50e81465a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652419471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3652419471
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1436722351
Short name T1019
Test name
Test status
Simulation time 19524542365 ps
CPU time 7.9 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:12:54 PM PDT 24
Peak memory 199572 kb
Host smart-071cac2f-eb66-4903-905d-ed1cc51b75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436722351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1436722351
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1024272042
Short name T320
Test name
Test status
Simulation time 10032650020 ps
CPU time 28.49 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:24 PM PDT 24
Peak memory 200248 kb
Host smart-3bbe2580-8e97-4179-994a-b4f742e82987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024272042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1024272042
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2765384740
Short name T797
Test name
Test status
Simulation time 51210905830 ps
CPU time 21.09 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200184 kb
Host smart-f4edeaaf-bb6c-4c52-b13d-b65b65ae12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765384740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2765384740
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1105101956
Short name T459
Test name
Test status
Simulation time 4252927074 ps
CPU time 7.63 seconds
Started Jul 25 07:12:47 PM PDT 24
Finished Jul 25 07:12:55 PM PDT 24
Peak memory 200096 kb
Host smart-ed7f01c7-7838-4ac7-aead-3f4b5091af92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105101956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1105101956
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.531623657
Short name T669
Test name
Test status
Simulation time 35443003395 ps
CPU time 17.22 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 200216 kb
Host smart-afac8a24-1455-465b-b92f-eb2b0e495818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531623657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.531623657
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1262681318
Short name T238
Test name
Test status
Simulation time 12482978728 ps
CPU time 8.49 seconds
Started Jul 25 07:12:48 PM PDT 24
Finished Jul 25 07:12:57 PM PDT 24
Peak memory 200188 kb
Host smart-48a40387-564a-49a5-8392-1bf1ad9b0e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262681318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1262681318
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2414828216
Short name T574
Test name
Test status
Simulation time 45886817365 ps
CPU time 38.28 seconds
Started Jul 25 07:12:49 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200228 kb
Host smart-37fe751f-0775-49ab-93c8-52247d3f49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414828216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2414828216
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.208619018
Short name T899
Test name
Test status
Simulation time 64163725 ps
CPU time 0.53 seconds
Started Jul 25 07:10:18 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 195876 kb
Host smart-40740aae-2aea-4c06-a394-a040e2aabb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208619018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.208619018
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3205292681
Short name T287
Test name
Test status
Simulation time 145445424688 ps
CPU time 102.94 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:12:12 PM PDT 24
Peak memory 200220 kb
Host smart-0cb02977-b89b-4eea-b184-59b501acf254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205292681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3205292681
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2827964764
Short name T140
Test name
Test status
Simulation time 83984213324 ps
CPU time 39.41 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 200204 kb
Host smart-35f8e2f2-8ccb-413d-abd1-12065319f6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827964764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2827964764
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3162678926
Short name T215
Test name
Test status
Simulation time 95360287727 ps
CPU time 118.27 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:12:14 PM PDT 24
Peak memory 200260 kb
Host smart-b30d14e6-b882-4c8e-97d7-3b19a536801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162678926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3162678926
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.378851465
Short name T704
Test name
Test status
Simulation time 40477369141 ps
CPU time 47.34 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200252 kb
Host smart-884291ab-2df7-45cc-bf4f-2f913f076b95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378851465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.378851465
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1198476034
Short name T576
Test name
Test status
Simulation time 74099293884 ps
CPU time 312.22 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200216 kb
Host smart-9565920b-96d1-449f-9568-cb0d7f671735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198476034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1198476034
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.518132902
Short name T962
Test name
Test status
Simulation time 8319810444 ps
CPU time 16.68 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 199264 kb
Host smart-4d56e192-90f0-4bd8-b792-ff4fc36a0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518132902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.518132902
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2818451669
Short name T822
Test name
Test status
Simulation time 145265878410 ps
CPU time 47.42 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:11:16 PM PDT 24
Peak memory 200180 kb
Host smart-21f91354-9cc0-4926-94aa-b626f239b917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818451669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2818451669
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1326467288
Short name T536
Test name
Test status
Simulation time 7019564448 ps
CPU time 431.63 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:17:39 PM PDT 24
Peak memory 200256 kb
Host smart-8d6a06b0-bd6e-442e-8385-d5a1ccb5301a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326467288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1326467288
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1796109858
Short name T615
Test name
Test status
Simulation time 5542154255 ps
CPU time 29.93 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 199668 kb
Host smart-5ee2971a-0c5e-4f4b-ab10-6791e6e13e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796109858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1796109858
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1513122785
Short name T613
Test name
Test status
Simulation time 184987765823 ps
CPU time 76.56 seconds
Started Jul 25 07:10:17 PM PDT 24
Finished Jul 25 07:11:34 PM PDT 24
Peak memory 200244 kb
Host smart-3810772f-bb48-4a31-b9b4-638cec9192f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513122785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1513122785
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2458827854
Short name T279
Test name
Test status
Simulation time 45172932083 ps
CPU time 13.23 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 196088 kb
Host smart-b26e6e9f-36de-44fc-9430-09fd4b3c4d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458827854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2458827854
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2076612719
Short name T491
Test name
Test status
Simulation time 244688591 ps
CPU time 1.64 seconds
Started Jul 25 07:10:16 PM PDT 24
Finished Jul 25 07:10:17 PM PDT 24
Peak memory 198720 kb
Host smart-a05fe601-b657-46f0-b959-4d2c3d039ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076612719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2076612719
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3567657186
Short name T123
Test name
Test status
Simulation time 310025551898 ps
CPU time 1176.11 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:29:56 PM PDT 24
Peak memory 208576 kb
Host smart-172d4295-0052-46f1-9cee-938d65ee3406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567657186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3567657186
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2758764990
Short name T711
Test name
Test status
Simulation time 1150557630 ps
CPU time 2.02 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:10:22 PM PDT 24
Peak memory 198508 kb
Host smart-ebe67785-df18-4196-8a11-e10eb827cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758764990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2758764990
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2114934623
Short name T495
Test name
Test status
Simulation time 50790733637 ps
CPU time 118.62 seconds
Started Jul 25 07:10:19 PM PDT 24
Finished Jul 25 07:12:18 PM PDT 24
Peak memory 200252 kb
Host smart-0f0dd1a2-3763-457c-8415-afecf28dbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114934623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2114934623
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.970702023
Short name T818
Test name
Test status
Simulation time 18640729136 ps
CPU time 13.33 seconds
Started Jul 25 07:12:45 PM PDT 24
Finished Jul 25 07:12:59 PM PDT 24
Peak memory 199964 kb
Host smart-f72989f1-8130-4fd3-9fe2-36bd5b689892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970702023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.970702023
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.53697431
Short name T519
Test name
Test status
Simulation time 5809979039 ps
CPU time 20.96 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200232 kb
Host smart-7fe47a9d-bd42-4680-8148-d73407399cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53697431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.53697431
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.378931284
Short name T179
Test name
Test status
Simulation time 157306725794 ps
CPU time 96.87 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:14:33 PM PDT 24
Peak memory 200208 kb
Host smart-e188c243-b80d-4040-befd-0b11134fd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378931284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.378931284
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3764755017
Short name T1059
Test name
Test status
Simulation time 33087539386 ps
CPU time 19.64 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200244 kb
Host smart-1d752a3a-3b4b-4991-870a-1b479b7d5f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764755017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3764755017
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2876889371
Short name T139
Test name
Test status
Simulation time 145949861743 ps
CPU time 71.38 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:14:09 PM PDT 24
Peak memory 200248 kb
Host smart-1a913d1e-2ece-4ba7-88e4-63dcf6126406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876889371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2876889371
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.586454987
Short name T208
Test name
Test status
Simulation time 241827995948 ps
CPU time 48.74 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 200188 kb
Host smart-0a07c9ca-8de1-4070-913e-41fa6daf4d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586454987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.586454987
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.568697879
Short name T1143
Test name
Test status
Simulation time 130088810456 ps
CPU time 15.47 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:13 PM PDT 24
Peak memory 200220 kb
Host smart-3ada524b-d40e-440e-a891-05aa75f06bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568697879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.568697879
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1224155331
Short name T397
Test name
Test status
Simulation time 33179304919 ps
CPU time 54.06 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 199876 kb
Host smart-a365b262-b3b9-4064-8269-fff79c6273ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224155331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1224155331
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1580558106
Short name T1074
Test name
Test status
Simulation time 100905952356 ps
CPU time 179.32 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:15:55 PM PDT 24
Peak memory 200248 kb
Host smart-c53f28e7-596c-42d5-94eb-36b69b6af640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580558106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1580558106
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1667819768
Short name T1159
Test name
Test status
Simulation time 17847372 ps
CPU time 0.6 seconds
Started Jul 25 07:10:35 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 195932 kb
Host smart-eec285c5-7923-45af-8c10-453fbf267f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667819768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1667819768
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2282894560
Short name T171
Test name
Test status
Simulation time 75478887829 ps
CPU time 98.35 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:12:06 PM PDT 24
Peak memory 200232 kb
Host smart-d0e8c807-0176-40de-99fa-0997532e6a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282894560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2282894560
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3171934520
Short name T710
Test name
Test status
Simulation time 80727618263 ps
CPU time 27.22 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:10:51 PM PDT 24
Peak memory 200184 kb
Host smart-946b9cae-ff40-4292-929a-9d9355aa2af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171934520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3171934520
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.356768915
Short name T1099
Test name
Test status
Simulation time 10371547807 ps
CPU time 9.83 seconds
Started Jul 25 07:10:14 PM PDT 24
Finished Jul 25 07:10:24 PM PDT 24
Peak memory 200240 kb
Host smart-0964b258-ce57-4e58-8abb-3b0558eaac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356768915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.356768915
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1114604428
Short name T401
Test name
Test status
Simulation time 121262777054 ps
CPU time 154.81 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:12:50 PM PDT 24
Peak memory 197224 kb
Host smart-823d2fa1-0c41-4f0e-af3d-28bc5d193c04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114604428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1114604428
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3072336490
Short name T834
Test name
Test status
Simulation time 70203969937 ps
CPU time 730.53 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:22:46 PM PDT 24
Peak memory 200244 kb
Host smart-5f20b089-4cfc-4b96-92e8-3becd20eb1d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072336490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3072336490
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1352383031
Short name T341
Test name
Test status
Simulation time 6814797382 ps
CPU time 4.57 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 199940 kb
Host smart-fcdadcc6-0e95-4112-8c6c-da0cc8810b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352383031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1352383031
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2315621515
Short name T874
Test name
Test status
Simulation time 152340863762 ps
CPU time 20.65 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:51 PM PDT 24
Peak memory 200244 kb
Host smart-77feb282-9f59-4e8e-beb0-3323ec065d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315621515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2315621515
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3935968396
Short name T1162
Test name
Test status
Simulation time 3397001678 ps
CPU time 166.57 seconds
Started Jul 25 07:10:20 PM PDT 24
Finished Jul 25 07:13:07 PM PDT 24
Peak memory 200152 kb
Host smart-ec574974-286f-4890-bb50-133ef8080e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935968396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3935968396
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2669457581
Short name T804
Test name
Test status
Simulation time 2989993228 ps
CPU time 4.99 seconds
Started Jul 25 07:10:15 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 198508 kb
Host smart-eecc62fb-79e0-4c8e-b38b-c9ad7b30610f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669457581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2669457581
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.21310552
Short name T685
Test name
Test status
Simulation time 186745951642 ps
CPU time 285.91 seconds
Started Jul 25 07:10:26 PM PDT 24
Finished Jul 25 07:15:12 PM PDT 24
Peak memory 200212 kb
Host smart-48fd5f22-6858-400d-8d5d-1fd71d8ed6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21310552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.21310552
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2842213750
Short name T728
Test name
Test status
Simulation time 1374827053 ps
CPU time 1.71 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 195940 kb
Host smart-b51a309f-5f4b-4102-b6da-1c4683c98e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842213750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2842213750
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4170251853
Short name T926
Test name
Test status
Simulation time 675053984 ps
CPU time 3.57 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:31 PM PDT 24
Peak memory 198580 kb
Host smart-35497357-adc8-4530-a2e0-34e20937eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170251853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4170251853
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2193426145
Short name T939
Test name
Test status
Simulation time 741253993 ps
CPU time 5.45 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 198696 kb
Host smart-e6dd5d45-e50b-4f63-a820-f6bb2989ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193426145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2193426145
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3241014719
Short name T479
Test name
Test status
Simulation time 62338313478 ps
CPU time 23.26 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200204 kb
Host smart-79d2a1e6-7006-4136-9d23-043690bf0f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241014719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3241014719
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2069666290
Short name T691
Test name
Test status
Simulation time 183632936604 ps
CPU time 254.16 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:17:10 PM PDT 24
Peak memory 200268 kb
Host smart-fa66143f-5aa2-4db8-9b25-2c7741137e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069666290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2069666290
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2208602801
Short name T336
Test name
Test status
Simulation time 8626058927 ps
CPU time 11.69 seconds
Started Jul 25 07:13:00 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 199588 kb
Host smart-82ba9886-a258-4357-ae1e-775a4a3d7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208602801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2208602801
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2373967567
Short name T629
Test name
Test status
Simulation time 162227985132 ps
CPU time 111.41 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 199972 kb
Host smart-5321a622-6172-48d9-97af-5a3c1e116da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373967567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2373967567
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3766229396
Short name T1161
Test name
Test status
Simulation time 71671884929 ps
CPU time 167.52 seconds
Started Jul 25 07:12:54 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200248 kb
Host smart-cdd3caaf-5285-4307-8a1a-a16aa43816f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766229396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3766229396
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2303575888
Short name T178
Test name
Test status
Simulation time 52276353407 ps
CPU time 24.65 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:13:22 PM PDT 24
Peak memory 200124 kb
Host smart-c4f290fa-15b4-45cb-9ad1-a38ceba02010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303575888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2303575888
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1640868912
Short name T166
Test name
Test status
Simulation time 21408340047 ps
CPU time 36.67 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:33 PM PDT 24
Peak memory 200240 kb
Host smart-543cf7bd-5ea2-454e-ab10-d23ea13ec79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640868912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1640868912
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.905395138
Short name T430
Test name
Test status
Simulation time 130576344991 ps
CPU time 140.19 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200180 kb
Host smart-83346e8c-8f0f-49b9-a9a9-758c3f3600db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905395138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.905395138
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3521798690
Short name T236
Test name
Test status
Simulation time 33613428345 ps
CPU time 16.8 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 200212 kb
Host smart-be8ddd12-fdb8-42c8-834e-a8bbdc9dead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521798690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3521798690
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4140952183
Short name T1111
Test name
Test status
Simulation time 15610268143 ps
CPU time 14.42 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:11 PM PDT 24
Peak memory 200120 kb
Host smart-7afb9554-c3b8-457c-a7d4-b73d10d55ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140952183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4140952183
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.319067223
Short name T381
Test name
Test status
Simulation time 40836060 ps
CPU time 0.56 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 195632 kb
Host smart-3a35816f-28dd-4887-a469-100ee04c7114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319067223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.319067223
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3171065024
Short name T674
Test name
Test status
Simulation time 177188430310 ps
CPU time 13.24 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:10:50 PM PDT 24
Peak memory 200172 kb
Host smart-75aa3a29-e81e-4992-a01f-e769992208da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171065024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3171065024
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.269499842
Short name T701
Test name
Test status
Simulation time 18333239534 ps
CPU time 35.36 seconds
Started Jul 25 07:10:22 PM PDT 24
Finished Jul 25 07:10:57 PM PDT 24
Peak memory 200196 kb
Host smart-c0ff4cfc-e5c2-46a3-9b24-6454b8533df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269499842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.269499842
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.382584565
Short name T915
Test name
Test status
Simulation time 46490940496 ps
CPU time 77.82 seconds
Started Jul 25 07:10:23 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200160 kb
Host smart-d5b7e5c4-7b7e-4985-b143-42b656ef2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382584565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.382584565
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2914212412
Short name T733
Test name
Test status
Simulation time 58333091135 ps
CPU time 37.12 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 200248 kb
Host smart-cd65a558-76a2-48ee-89ce-834b168880ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914212412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2914212412
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1822074552
Short name T859
Test name
Test status
Simulation time 183789025538 ps
CPU time 749.37 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:22:54 PM PDT 24
Peak memory 200188 kb
Host smart-6e055add-f7fb-4ce3-a5d2-035ec576968b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822074552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1822074552
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1466883034
Short name T976
Test name
Test status
Simulation time 4911759229 ps
CPU time 2.67 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:10:43 PM PDT 24
Peak memory 198336 kb
Host smart-b8f8fe14-6ea0-4199-92e0-b16625317b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466883034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1466883034
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4183307709
Short name T1108
Test name
Test status
Simulation time 27780864637 ps
CPU time 41.18 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:11:08 PM PDT 24
Peak memory 199340 kb
Host smart-343f67c8-c168-4db8-bf90-b9564ad5cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183307709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4183307709
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1243022089
Short name T683
Test name
Test status
Simulation time 13438689255 ps
CPU time 642.1 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:21:07 PM PDT 24
Peak memory 200264 kb
Host smart-87cfb7a4-5d78-499f-a245-52294bd16b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243022089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1243022089
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1318000231
Short name T346
Test name
Test status
Simulation time 4835438707 ps
CPU time 9.84 seconds
Started Jul 25 07:10:20 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 199476 kb
Host smart-ac689d53-dcc1-471a-b65a-6bfb4349aa00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318000231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1318000231
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1379125433
Short name T886
Test name
Test status
Simulation time 28077580343 ps
CPU time 12.24 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:45 PM PDT 24
Peak memory 199488 kb
Host smart-ddf7fdf9-b0c6-4404-b7f8-8efea5c31c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379125433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1379125433
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1490117970
Short name T776
Test name
Test status
Simulation time 4577068861 ps
CPU time 1.7 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:29 PM PDT 24
Peak memory 196588 kb
Host smart-3d7f4a98-8827-46f6-8310-4b598603a7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490117970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1490117970
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.648332373
Short name T288
Test name
Test status
Simulation time 6083672467 ps
CPU time 18.75 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:10:43 PM PDT 24
Peak memory 200240 kb
Host smart-86bb2042-e178-4f94-9717-8918dda5b801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648332373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.648332373
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.866127273
Short name T1058
Test name
Test status
Simulation time 196760710403 ps
CPU time 224.01 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:14:10 PM PDT 24
Peak memory 200260 kb
Host smart-d9e85517-04db-4966-bc14-347ee86a0a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866127273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.866127273
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1626723108
Short name T575
Test name
Test status
Simulation time 142990012093 ps
CPU time 821.5 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:24:09 PM PDT 24
Peak memory 225064 kb
Host smart-33cc4fee-c2c0-4bd9-9c3d-e2f76c0e0465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626723108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1626723108
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.664702101
Short name T413
Test name
Test status
Simulation time 894542970 ps
CPU time 1.6 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 198940 kb
Host smart-6b170ff9-2c05-458f-9e9e-62c129b7ec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664702101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.664702101
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1134362993
Short name T282
Test name
Test status
Simulation time 28619876709 ps
CPU time 48.01 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200252 kb
Host smart-a5502637-c2f6-45da-b357-5989ac5d7162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134362993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1134362993
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.925237700
Short name T621
Test name
Test status
Simulation time 12042539568 ps
CPU time 23.93 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:13:22 PM PDT 24
Peak memory 200228 kb
Host smart-d1b2a34e-a26f-4b4b-9155-3ce47a568d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925237700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.925237700
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3427726158
Short name T850
Test name
Test status
Simulation time 51659106184 ps
CPU time 42.87 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:13:38 PM PDT 24
Peak memory 200204 kb
Host smart-c8b72c12-fa22-48ed-bc4b-17288fa40a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427726158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3427726158
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2803175688
Short name T959
Test name
Test status
Simulation time 184990334378 ps
CPU time 17.77 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 200248 kb
Host smart-90f98955-49d6-435d-9881-d346d69b631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803175688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2803175688
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2529789818
Short name T1051
Test name
Test status
Simulation time 13641435120 ps
CPU time 34.17 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 200148 kb
Host smart-bd011693-e8b4-454d-a7c4-ab246eeb5c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529789818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2529789818
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2381053489
Short name T1169
Test name
Test status
Simulation time 8587676035 ps
CPU time 12.5 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:09 PM PDT 24
Peak memory 200144 kb
Host smart-72ac0c23-613e-4281-b46b-2bf62a7c3114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381053489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2381053489
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2435777267
Short name T565
Test name
Test status
Simulation time 11468108449 ps
CPU time 21.78 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:19 PM PDT 24
Peak memory 200188 kb
Host smart-2c91dbe7-931b-49e5-acb9-c6ab3860c247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435777267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2435777267
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3038593628
Short name T935
Test name
Test status
Simulation time 23960453949 ps
CPU time 40.54 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:38 PM PDT 24
Peak memory 200252 kb
Host smart-2d24485a-d4dd-42f2-ba14-c97191fe7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038593628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3038593628
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.691112687
Short name T902
Test name
Test status
Simulation time 90902026746 ps
CPU time 33.32 seconds
Started Jul 25 07:12:58 PM PDT 24
Finished Jul 25 07:13:31 PM PDT 24
Peak memory 200032 kb
Host smart-53453da4-13fd-4a7f-86be-29b834bdfc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691112687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.691112687
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2976578805
Short name T680
Test name
Test status
Simulation time 43010617497 ps
CPU time 15.84 seconds
Started Jul 25 07:12:57 PM PDT 24
Finished Jul 25 07:13:13 PM PDT 24
Peak memory 200212 kb
Host smart-502183e8-199a-4370-bb23-efa1372666b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976578805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2976578805
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3583744538
Short name T477
Test name
Test status
Simulation time 34561939 ps
CPU time 0.55 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 195916 kb
Host smart-bede9455-830f-4954-a66e-eb506b169148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583744538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3583744538
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4272510107
Short name T250
Test name
Test status
Simulation time 60734230866 ps
CPU time 21.65 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:10:52 PM PDT 24
Peak memory 200176 kb
Host smart-f88172dd-454b-44d5-9330-3275888ffd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272510107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4272510107
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2675641361
Short name T996
Test name
Test status
Simulation time 26984063011 ps
CPU time 39.86 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:11:05 PM PDT 24
Peak memory 199468 kb
Host smart-6fbde622-5cf8-4ecd-a079-964a82281fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675641361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2675641361
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2609215264
Short name T226
Test name
Test status
Simulation time 69334846939 ps
CPU time 33.35 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:11:00 PM PDT 24
Peak memory 200272 kb
Host smart-b94cce0c-b036-437f-ab7e-80f25492c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609215264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2609215264
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3004723470
Short name T648
Test name
Test status
Simulation time 84043566313 ps
CPU time 46.4 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 200276 kb
Host smart-a29a770c-1cb7-4da8-a129-21309203f9ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004723470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3004723470
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.33983206
Short name T724
Test name
Test status
Simulation time 284187312082 ps
CPU time 549.46 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:19:41 PM PDT 24
Peak memory 200248 kb
Host smart-580ab112-a151-441f-a898-e0e4cadb6891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33983206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.33983206
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1277867410
Short name T668
Test name
Test status
Simulation time 3107818813 ps
CPU time 5.57 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 198600 kb
Host smart-a521725b-402e-46f6-848e-d3c95c590f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277867410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1277867410
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1902834643
Short name T923
Test name
Test status
Simulation time 144413438497 ps
CPU time 86.61 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:12:00 PM PDT 24
Peak memory 199476 kb
Host smart-ce9b09d5-f0c7-4975-8ac0-57b48e32fe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902834643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1902834643
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4024577919
Short name T880
Test name
Test status
Simulation time 8006233567 ps
CPU time 183.78 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:13:32 PM PDT 24
Peak memory 200240 kb
Host smart-104a9f75-54ed-4a8d-b80d-43e28ff10eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024577919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4024577919
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.679413361
Short name T552
Test name
Test status
Simulation time 3297434280 ps
CPU time 10.69 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 199280 kb
Host smart-c28c18f3-be1e-4f51-a6dd-d8233fd03d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679413361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.679413361
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3036102382
Short name T752
Test name
Test status
Simulation time 4065531410 ps
CPU time 2.45 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 196528 kb
Host smart-160d0046-3e66-4067-9460-894123d10ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036102382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3036102382
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.559243031
Short name T737
Test name
Test status
Simulation time 501004786 ps
CPU time 1.99 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:29 PM PDT 24
Peak memory 199888 kb
Host smart-240c10f2-f285-4d22-861e-e3be07bd8f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559243031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.559243031
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2632831602
Short name T480
Test name
Test status
Simulation time 268089594757 ps
CPU time 466.92 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:18:11 PM PDT 24
Peak memory 200184 kb
Host smart-78b80299-5da9-4328-a243-cb9d3da4739c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632831602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2632831602
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2068841881
Short name T604
Test name
Test status
Simulation time 2212944245 ps
CPU time 1.7 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:27 PM PDT 24
Peak memory 197240 kb
Host smart-0a58a781-b1c1-44b5-b968-9e58b55470d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068841881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2068841881
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.725635918
Short name T334
Test name
Test status
Simulation time 17502175599 ps
CPU time 21.97 seconds
Started Jul 25 07:10:24 PM PDT 24
Finished Jul 25 07:10:46 PM PDT 24
Peak memory 200124 kb
Host smart-969fb599-0bd4-4bf3-bda2-5b1ca8bf177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725635918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.725635918
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.303357007
Short name T907
Test name
Test status
Simulation time 71174730313 ps
CPU time 10.5 seconds
Started Jul 25 07:12:55 PM PDT 24
Finished Jul 25 07:13:06 PM PDT 24
Peak memory 200208 kb
Host smart-b7e2c6d6-b38b-4b47-af85-e6dde89eb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303357007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.303357007
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2934920367
Short name T500
Test name
Test status
Simulation time 12439318114 ps
CPU time 20.35 seconds
Started Jul 25 07:12:56 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200188 kb
Host smart-2807ae6a-1c2d-4942-8664-6104984bd1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934920367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2934920367
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3011376947
Short name T231
Test name
Test status
Simulation time 112415651293 ps
CPU time 78.01 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 200252 kb
Host smart-b33bb34e-7f40-4361-ad85-88576cdd1864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011376947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3011376947
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2791560003
Short name T152
Test name
Test status
Simulation time 36063687058 ps
CPU time 59.23 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:14:04 PM PDT 24
Peak memory 200252 kb
Host smart-15e7c52f-2c2a-4ac0-a175-b201f58a47e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791560003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2791560003
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1859776081
Short name T276
Test name
Test status
Simulation time 180156185633 ps
CPU time 144.98 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 200212 kb
Host smart-4dd698d5-7ddb-48f1-b103-2b393b840611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859776081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1859776081
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3843520910
Short name T274
Test name
Test status
Simulation time 122180195507 ps
CPU time 194.01 seconds
Started Jul 25 07:13:06 PM PDT 24
Finished Jul 25 07:16:20 PM PDT 24
Peak memory 200248 kb
Host smart-df4d3fb9-7ecc-4893-92da-089ed9c496b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843520910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3843520910
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2887636256
Short name T196
Test name
Test status
Simulation time 61732446519 ps
CPU time 22.65 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200248 kb
Host smart-895e2036-3144-4e16-b21d-e0e0e5b2ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887636256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2887636256
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2150552888
Short name T145
Test name
Test status
Simulation time 65060614465 ps
CPU time 45.39 seconds
Started Jul 25 07:13:06 PM PDT 24
Finished Jul 25 07:13:51 PM PDT 24
Peak memory 200224 kb
Host smart-009cf901-a76f-45e9-91b0-e8763813a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150552888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2150552888
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2011337551
Short name T879
Test name
Test status
Simulation time 26320409 ps
CPU time 0.54 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:10:32 PM PDT 24
Peak memory 195080 kb
Host smart-d742359e-0e36-477c-abf1-cee30ccd3666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011337551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2011337551
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3076065273
Short name T800
Test name
Test status
Simulation time 47892035312 ps
CPU time 25.17 seconds
Started Jul 25 07:10:26 PM PDT 24
Finished Jul 25 07:10:51 PM PDT 24
Peak memory 200176 kb
Host smart-32044eb4-5aa4-44a3-8be8-8455216d2af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076065273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3076065273
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1322006821
Short name T786
Test name
Test status
Simulation time 35617315384 ps
CPU time 16.56 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 200244 kb
Host smart-fce20597-05f3-4d87-adc8-197427ce5394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322006821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1322006821
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3203508367
Short name T725
Test name
Test status
Simulation time 51195761038 ps
CPU time 14.16 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 200204 kb
Host smart-6d289185-2099-4f22-a2b5-0b1d4d39dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203508367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3203508367
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2833660428
Short name T606
Test name
Test status
Simulation time 37274587013 ps
CPU time 14.95 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 199528 kb
Host smart-94f753e1-e750-4ed4-ae08-69298714c897
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833660428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2833660428
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4117571568
Short name T784
Test name
Test status
Simulation time 73196399061 ps
CPU time 427.1 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:17:36 PM PDT 24
Peak memory 200244 kb
Host smart-895b594e-12e5-45d7-a53c-934217eb2ea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117571568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4117571568
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1214043574
Short name T591
Test name
Test status
Simulation time 332127252 ps
CPU time 0.8 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:10:31 PM PDT 24
Peak memory 195664 kb
Host smart-eb6281e1-a65f-4b05-b863-ebf9a2650df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214043574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1214043574
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.828572433
Short name T432
Test name
Test status
Simulation time 119002681849 ps
CPU time 23.49 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:52 PM PDT 24
Peak memory 208388 kb
Host smart-c914cea2-cf9b-4c96-91b3-9718e1416c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828572433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.828572433
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3999353382
Short name T1004
Test name
Test status
Simulation time 18868515339 ps
CPU time 234.79 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:14:31 PM PDT 24
Peak memory 200224 kb
Host smart-5af25935-44af-4bd0-bde6-8e2904f3c6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999353382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3999353382
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3159875857
Short name T609
Test name
Test status
Simulation time 1463478060 ps
CPU time 8.37 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 198336 kb
Host smart-1b40ec0c-1f10-46d0-b876-4ceacb5fe50a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159875857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3159875857
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.768012326
Short name T454
Test name
Test status
Simulation time 14505437028 ps
CPU time 22.64 seconds
Started Jul 25 07:10:26 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200160 kb
Host smart-77c1e5d7-c9f9-4b8d-8ef6-ad8c7bf16c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768012326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.768012326
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.198129316
Short name T395
Test name
Test status
Simulation time 3136145077 ps
CPU time 1.97 seconds
Started Jul 25 07:10:27 PM PDT 24
Finished Jul 25 07:10:30 PM PDT 24
Peak memory 196820 kb
Host smart-33641dec-6d70-45a6-910b-38075c8260ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198129316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.198129316
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.935680246
Short name T280
Test name
Test status
Simulation time 429482281 ps
CPU time 2.3 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 198440 kb
Host smart-0ea322b9-632a-42a9-a3bf-b2438a6f64e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935680246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.935680246
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1368487298
Short name T57
Test name
Test status
Simulation time 47086620006 ps
CPU time 334.56 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:16:05 PM PDT 24
Peak memory 208524 kb
Host smart-1b7141f4-ffae-4239-80c8-f416de8535ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368487298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1368487298
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2582835606
Short name T799
Test name
Test status
Simulation time 5134502032 ps
CPU time 2.15 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:10:35 PM PDT 24
Peak memory 199340 kb
Host smart-8674dda6-e92f-410b-b0f0-9c2b168231e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582835606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2582835606
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3053453415
Short name T734
Test name
Test status
Simulation time 13281707478 ps
CPU time 11.62 seconds
Started Jul 25 07:10:25 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 200040 kb
Host smart-ef776b23-96bf-49d3-a2c6-5e25dc320a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053453415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3053453415
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1085174022
Short name T542
Test name
Test status
Simulation time 5675047069 ps
CPU time 8.76 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:13:13 PM PDT 24
Peak memory 199844 kb
Host smart-d489af44-412b-4dc6-ae05-54896c64798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085174022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1085174022
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1435026068
Short name T497
Test name
Test status
Simulation time 92786873219 ps
CPU time 39.86 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 200180 kb
Host smart-562f03cb-c70f-4e29-aa06-2190c83aaadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435026068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1435026068
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1186595299
Short name T894
Test name
Test status
Simulation time 112936205400 ps
CPU time 52.43 seconds
Started Jul 25 07:13:08 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 200236 kb
Host smart-afbe043c-408d-4235-a326-1eb4b51b9387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186595299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1186595299
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1253711026
Short name T239
Test name
Test status
Simulation time 45305257220 ps
CPU time 47.08 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200216 kb
Host smart-e633e112-64bc-4f0a-891b-28825774cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253711026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1253711026
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3976989063
Short name T765
Test name
Test status
Simulation time 19199665191 ps
CPU time 29.75 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 200180 kb
Host smart-f37fc157-156f-4f41-9841-4fd7bdf230b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976989063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3976989063
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.208247798
Short name T1005
Test name
Test status
Simulation time 41193029896 ps
CPU time 28.01 seconds
Started Jul 25 07:13:03 PM PDT 24
Finished Jul 25 07:13:31 PM PDT 24
Peak memory 200220 kb
Host smart-09733b72-d9fa-4cc4-a014-e8e7d6808303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208247798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.208247798
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4118468797
Short name T391
Test name
Test status
Simulation time 38829281023 ps
CPU time 15.94 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:13:20 PM PDT 24
Peak memory 199948 kb
Host smart-f7ad9e13-460d-482d-a562-c9f557f9a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118468797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4118468797
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.8145826
Short name T1048
Test name
Test status
Simulation time 32298271089 ps
CPU time 14.31 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:20 PM PDT 24
Peak memory 200252 kb
Host smart-4f99e742-75d5-47be-b4f3-272e475640ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8145826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.8145826
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2314402327
Short name T1073
Test name
Test status
Simulation time 25634554031 ps
CPU time 23.64 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:29 PM PDT 24
Peak memory 200144 kb
Host smart-f7adc009-81ac-4535-a213-0495c5a03fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314402327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2314402327
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2878174029
Short name T146
Test name
Test status
Simulation time 51289203801 ps
CPU time 24.04 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 200256 kb
Host smart-615c6a2d-5907-4419-81ae-28289525944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878174029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2878174029
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1560025955
Short name T357
Test name
Test status
Simulation time 37593844 ps
CPU time 0.54 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 195888 kb
Host smart-f1d6a75d-5a73-49fa-baad-abba9c5e9113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560025955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1560025955
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.789445046
Short name T436
Test name
Test status
Simulation time 269544182315 ps
CPU time 180.41 seconds
Started Jul 25 07:10:35 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 200272 kb
Host smart-48894c8e-36ea-44fa-b3e1-11e6e145c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789445046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.789445046
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1727571514
Short name T455
Test name
Test status
Simulation time 48631464534 ps
CPU time 42.88 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:11:14 PM PDT 24
Peak memory 200244 kb
Host smart-afd89f1f-9d10-4ce1-963e-c2ea8667770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727571514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1727571514
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2816696783
Short name T979
Test name
Test status
Simulation time 116830697223 ps
CPU time 317.02 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:15:51 PM PDT 24
Peak memory 200188 kb
Host smart-ae7851e2-2e41-4d2a-848b-e77003ab7c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816696783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2816696783
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3137816349
Short name T755
Test name
Test status
Simulation time 30682855921 ps
CPU time 44.99 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 200240 kb
Host smart-a66b97f3-bc6f-4bbc-ac55-8675531f2587
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137816349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3137816349
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1436405291
Short name T897
Test name
Test status
Simulation time 70961832869 ps
CPU time 306.56 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:15:40 PM PDT 24
Peak memory 200276 kb
Host smart-9f13068c-ce85-4a9c-8bae-1fb38aad691a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436405291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1436405291
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.4095943086
Short name T338
Test name
Test status
Simulation time 9772122685 ps
CPU time 3.94 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:33 PM PDT 24
Peak memory 199976 kb
Host smart-167bff7b-4dfa-41a5-9938-611628ffa885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095943086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4095943086
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.578863354
Short name T810
Test name
Test status
Simulation time 238524956781 ps
CPU time 89.95 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:12:02 PM PDT 24
Peak memory 200060 kb
Host smart-06aa1199-b761-4fc8-99d0-9944812dbab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578863354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.578863354
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2441177057
Short name T284
Test name
Test status
Simulation time 10305051733 ps
CPU time 586.98 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:20:18 PM PDT 24
Peak memory 200192 kb
Host smart-c4e36bd3-d388-4381-8c57-ccfb31bf9262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441177057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2441177057
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1729207592
Short name T14
Test name
Test status
Simulation time 6175665301 ps
CPU time 12.94 seconds
Started Jul 25 07:10:28 PM PDT 24
Finished Jul 25 07:10:41 PM PDT 24
Peak memory 199064 kb
Host smart-1d4379eb-1961-4b29-a4c0-65a7e943c928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729207592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1729207592
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.4115301449
Short name T558
Test name
Test status
Simulation time 87328572611 ps
CPU time 33.15 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 199740 kb
Host smart-dac577de-6100-46fe-b4c2-d011d955ba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115301449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4115301449
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.252871339
Short name T6
Test name
Test status
Simulation time 4399840003 ps
CPU time 2.88 seconds
Started Jul 25 07:10:35 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 196496 kb
Host smart-f4da8625-dc60-46d1-910e-a4da395ffd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252871339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.252871339
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3910954374
Short name T285
Test name
Test status
Simulation time 5325817890 ps
CPU time 8.01 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 199836 kb
Host smart-85767d2a-748d-45ed-b5ce-1147ce2bcb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910954374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3910954374
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2166006092
Short name T1089
Test name
Test status
Simulation time 452889109868 ps
CPU time 599.81 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:20:32 PM PDT 24
Peak memory 216768 kb
Host smart-e592d217-c9d8-4f4b-a86a-18a9a68b0d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166006092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2166006092
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.111873896
Short name T782
Test name
Test status
Simulation time 198686386723 ps
CPU time 606.99 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:20:38 PM PDT 24
Peak memory 216884 kb
Host smart-bdb8e77a-cb98-4530-aa6b-6560d73eff9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111873896 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.111873896
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2137034486
Short name T900
Test name
Test status
Simulation time 1906304546 ps
CPU time 2.19 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 198880 kb
Host smart-5a3a5dc3-7742-4a7b-9676-5457e4db3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137034486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2137034486
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.941297574
Short name T940
Test name
Test status
Simulation time 65206925501 ps
CPU time 60.15 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:11:31 PM PDT 24
Peak memory 200348 kb
Host smart-a832255e-e0df-40dc-a50d-64d6fc65899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941297574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.941297574
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2240617206
Short name T453
Test name
Test status
Simulation time 35585873301 ps
CPU time 24.06 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:29 PM PDT 24
Peak memory 200112 kb
Host smart-25bc0c57-ac84-4f36-bd74-46bcf0654235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240617206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2240617206
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2001942337
Short name T324
Test name
Test status
Simulation time 184418550863 ps
CPU time 145.31 seconds
Started Jul 25 07:13:04 PM PDT 24
Finished Jul 25 07:15:29 PM PDT 24
Peak memory 200228 kb
Host smart-5d54426b-cea2-4833-b686-ebe789005d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001942337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2001942337
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3385356471
Short name T501
Test name
Test status
Simulation time 69333563554 ps
CPU time 28.88 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:34 PM PDT 24
Peak memory 200244 kb
Host smart-9024a892-f97c-4933-a7ee-1b739b3fd453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385356471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3385356471
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1818552128
Short name T1164
Test name
Test status
Simulation time 116161762650 ps
CPU time 163.69 seconds
Started Jul 25 07:13:06 PM PDT 24
Finished Jul 25 07:15:50 PM PDT 24
Peak memory 200244 kb
Host smart-8539fe97-0f20-4f8b-ad06-8ac15b3d71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818552128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1818552128
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1745631796
Short name T1172
Test name
Test status
Simulation time 16638621857 ps
CPU time 24.07 seconds
Started Jul 25 07:13:06 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 200156 kb
Host smart-51e2ee31-daa7-4655-8bf4-868fe675d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745631796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1745631796
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.912133261
Short name T1114
Test name
Test status
Simulation time 32619144752 ps
CPU time 31.93 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:37 PM PDT 24
Peak memory 200220 kb
Host smart-ef08d9e5-9506-4fc6-a8f8-94bac91b7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912133261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.912133261
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3005737320
Short name T186
Test name
Test status
Simulation time 29193591235 ps
CPU time 41.99 seconds
Started Jul 25 07:13:08 PM PDT 24
Finished Jul 25 07:13:51 PM PDT 24
Peak memory 200260 kb
Host smart-13820953-714c-47fc-acd0-c4d33010f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005737320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3005737320
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2064385711
Short name T1082
Test name
Test status
Simulation time 115075785797 ps
CPU time 49.67 seconds
Started Jul 25 07:13:09 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 200248 kb
Host smart-195b31c7-7072-4311-8c67-30bd450a4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064385711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2064385711
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3888848213
Short name T237
Test name
Test status
Simulation time 26041403071 ps
CPU time 47.59 seconds
Started Jul 25 07:13:05 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200260 kb
Host smart-c38cc819-2082-425d-b420-16f3f6ee1647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888848213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3888848213
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.493967606
Short name T1140
Test name
Test status
Simulation time 45720061241 ps
CPU time 78.03 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:14:33 PM PDT 24
Peak memory 200240 kb
Host smart-9916eb71-d45a-4344-be38-6d311dd3d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493967606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.493967606
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2069909
Short name T597
Test name
Test status
Simulation time 71972161 ps
CPU time 0.55 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 195628 kb
Host smart-820686f4-00b6-4a4c-8d3f-67c456dd001d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2069909
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.973886150
Short name T373
Test name
Test status
Simulation time 19050179097 ps
CPU time 27.18 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:11:00 PM PDT 24
Peak memory 200232 kb
Host smart-e8350765-442c-4bdd-abe2-8036ba614a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973886150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.973886150
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.973410883
Short name T456
Test name
Test status
Simulation time 122743822675 ps
CPU time 169.8 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:13:26 PM PDT 24
Peak memory 200244 kb
Host smart-1af2664e-959e-4a68-a21f-802d28dbd7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973410883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.973410883
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.1647853464
Short name T774
Test name
Test status
Simulation time 54190884687 ps
CPU time 42.36 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:11:16 PM PDT 24
Peak memory 200252 kb
Host smart-569835cd-e9ce-4889-b1dc-d7dc40ce394d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647853464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1647853464
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.21674690
Short name T256
Test name
Test status
Simulation time 104867683365 ps
CPU time 583.74 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:20:20 PM PDT 24
Peak memory 200248 kb
Host smart-bf3b27e4-c1f2-4b12-b627-ae8539397125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21674690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.21674690
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2867836395
Short name T851
Test name
Test status
Simulation time 11903412894 ps
CPU time 11.61 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 200136 kb
Host smart-6c0434ba-0cfa-4c7c-afcc-6f28d70453ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867836395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2867836395
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1647040006
Short name T914
Test name
Test status
Simulation time 45658210561 ps
CPU time 6.55 seconds
Started Jul 25 07:10:30 PM PDT 24
Finished Jul 25 07:10:37 PM PDT 24
Peak memory 200376 kb
Host smart-673b8e22-2385-413b-8bab-4a001689b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647040006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1647040006
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.402135371
Short name T1153
Test name
Test status
Simulation time 21073417093 ps
CPU time 1154.59 seconds
Started Jul 25 07:10:34 PM PDT 24
Finished Jul 25 07:29:49 PM PDT 24
Peak memory 200400 kb
Host smart-8b6bc35a-6709-401c-ade0-867b3293ed70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402135371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.402135371
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1760868368
Short name T494
Test name
Test status
Simulation time 5348323248 ps
CPU time 47.68 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 198444 kb
Host smart-b415fd31-cafe-4a8d-afcf-2c7f0522b6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760868368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1760868368
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1398046049
Short name T720
Test name
Test status
Simulation time 33344303937 ps
CPU time 31.34 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 200196 kb
Host smart-01c07e9a-d032-46ea-a48d-11fd5d275e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398046049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1398046049
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4160356711
Short name T586
Test name
Test status
Simulation time 2967450961 ps
CPU time 1.83 seconds
Started Jul 25 07:10:33 PM PDT 24
Finished Jul 25 07:10:35 PM PDT 24
Peak memory 196756 kb
Host smart-b8da7b91-1ba8-45fe-a9d6-fe8d30a786ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160356711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4160356711
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.447008674
Short name T538
Test name
Test status
Simulation time 5552642955 ps
CPU time 17.03 seconds
Started Jul 25 07:10:29 PM PDT 24
Finished Jul 25 07:10:46 PM PDT 24
Peak memory 200268 kb
Host smart-fd3044ce-dbb7-4599-b83e-82b58d322dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447008674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.447008674
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3335585587
Short name T137
Test name
Test status
Simulation time 342235865536 ps
CPU time 530.32 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:19:22 PM PDT 24
Peak memory 208612 kb
Host smart-9a59a3c8-f969-44a2-b441-65b3ab25fbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335585587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3335585587
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1851890984
Short name T352
Test name
Test status
Simulation time 826067964 ps
CPU time 1.37 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:10:33 PM PDT 24
Peak memory 198592 kb
Host smart-56653be1-2564-40e8-a453-e5638d103775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851890984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1851890984
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.497632006
Short name T978
Test name
Test status
Simulation time 50566217509 ps
CPU time 27.43 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:59 PM PDT 24
Peak memory 200256 kb
Host smart-c46119aa-8c8d-4ad2-af53-c02310db5778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497632006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.497632006
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1054451057
Short name T1120
Test name
Test status
Simulation time 25444527476 ps
CPU time 35.34 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:13:50 PM PDT 24
Peak memory 200236 kb
Host smart-21698db0-1aa7-453f-92d6-76ef50ab5e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054451057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1054451057
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.940471889
Short name T992
Test name
Test status
Simulation time 128121612448 ps
CPU time 204.88 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:16:39 PM PDT 24
Peak memory 200108 kb
Host smart-a4c1c6cc-681e-4c4f-8273-6d0888778dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940471889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.940471889
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.829726036
Short name T1170
Test name
Test status
Simulation time 86833464705 ps
CPU time 26.27 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:13:40 PM PDT 24
Peak memory 200236 kb
Host smart-83589684-8b07-49f2-a152-8569f53c3428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829726036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.829726036
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2587089556
Short name T570
Test name
Test status
Simulation time 196411846149 ps
CPU time 20.9 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 200184 kb
Host smart-5fb67631-5614-4aa7-8373-2270d72b7387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587089556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2587089556
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4025607512
Short name T161
Test name
Test status
Simulation time 262412443659 ps
CPU time 31.31 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 200248 kb
Host smart-c50dd137-0789-4c76-9b67-a36970f4110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025607512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4025607512
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3306195277
Short name T675
Test name
Test status
Simulation time 93343516660 ps
CPU time 51.06 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 200152 kb
Host smart-0769a44b-9d23-469a-9866-ca12c2597d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306195277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3306195277
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1083090577
Short name T105
Test name
Test status
Simulation time 28422509211 ps
CPU time 14.58 seconds
Started Jul 25 07:13:13 PM PDT 24
Finished Jul 25 07:13:27 PM PDT 24
Peak memory 200252 kb
Host smart-25cbbf58-40db-42dd-8f13-e8e8b927a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083090577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1083090577
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3106768627
Short name T442
Test name
Test status
Simulation time 247546010426 ps
CPU time 47.93 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 200248 kb
Host smart-a307eefc-cbac-4fd3-b24f-b9921abc7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106768627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3106768627
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3554172286
Short name T281
Test name
Test status
Simulation time 46397705984 ps
CPU time 36.4 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200236 kb
Host smart-a4cbd2f0-cda6-4cfd-a164-89d550c8c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554172286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3554172286
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.551756352
Short name T134
Test name
Test status
Simulation time 177270403693 ps
CPU time 36.34 seconds
Started Jul 25 07:13:16 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 200192 kb
Host smart-ccf8965b-fd0e-45d5-be66-eb1e74a1b575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551756352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.551756352
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1854956807
Short name T343
Test name
Test status
Simulation time 45692820 ps
CPU time 0.55 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:10:38 PM PDT 24
Peak memory 195628 kb
Host smart-95ad84b0-4d27-4709-bbd3-6d87dd3032a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854956807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1854956807
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1511027080
Short name T457
Test name
Test status
Simulation time 217175890272 ps
CPU time 85.28 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:12:05 PM PDT 24
Peak memory 200220 kb
Host smart-f2c9a545-2da7-405a-b3ef-30717b172a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511027080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1511027080
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3624218080
Short name T524
Test name
Test status
Simulation time 244101721417 ps
CPU time 102.88 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:12:19 PM PDT 24
Peak memory 200232 kb
Host smart-5201f27f-c0a2-4cf3-aec0-7cf77f79073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624218080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3624218080
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.3007080151
Short name T636
Test name
Test status
Simulation time 125547460543 ps
CPU time 161.6 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:13:21 PM PDT 24
Peak memory 198364 kb
Host smart-7aa1b486-41a7-4482-8768-089eb0001f4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007080151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3007080151
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1276521690
Short name T793
Test name
Test status
Simulation time 154757892080 ps
CPU time 234.02 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:14:34 PM PDT 24
Peak memory 200204 kb
Host smart-9c712367-854a-4613-9ae1-289e58666b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276521690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1276521690
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1854449009
Short name T878
Test name
Test status
Simulation time 8789467815 ps
CPU time 7.24 seconds
Started Jul 25 07:10:43 PM PDT 24
Finished Jul 25 07:10:50 PM PDT 24
Peak memory 200176 kb
Host smart-f11dc117-543c-4fcf-8c92-b4b6c63a7f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854449009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1854449009
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.2160059127
Short name T263
Test name
Test status
Simulation time 10180836084 ps
CPU time 200.91 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 200296 kb
Host smart-9536eae1-cc1d-4f84-a495-e5dc2df1cfbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160059127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2160059127
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.106438796
Short name T760
Test name
Test status
Simulation time 5539381853 ps
CPU time 11.1 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 198440 kb
Host smart-f544f650-3ab4-4b7e-867b-86dd17987fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106438796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.106438796
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4035614057
Short name T502
Test name
Test status
Simulation time 44715324995 ps
CPU time 62.99 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:11:40 PM PDT 24
Peak memory 200036 kb
Host smart-0ae6c04c-7fd5-4ba4-88cf-2cce98e8fd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035614057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4035614057
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.365144985
Short name T1124
Test name
Test status
Simulation time 4279769469 ps
CPU time 2.31 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 196568 kb
Host smart-5eb8f3c1-25f7-4168-90ad-57d23755fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365144985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.365144985
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1088696287
Short name T386
Test name
Test status
Simulation time 554823641 ps
CPU time 2.11 seconds
Started Jul 25 07:10:32 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 198776 kb
Host smart-fa876d0d-b2ec-42e2-9503-c67275457dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088696287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1088696287
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.96209663
Short name T163
Test name
Test status
Simulation time 109756432104 ps
CPU time 955.26 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:26:33 PM PDT 24
Peak memory 225096 kb
Host smart-51467910-f141-4307-aa71-e4299f387501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96209663 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.96209663
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.502868570
Short name T18
Test name
Test status
Simulation time 297838829 ps
CPU time 1.54 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 200144 kb
Host smart-ae72fb39-bb1a-4086-9ad0-1e0f3f95272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502868570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.502868570
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1670751467
Short name T605
Test name
Test status
Simulation time 69904259226 ps
CPU time 55.9 seconds
Started Jul 25 07:10:31 PM PDT 24
Finished Jul 25 07:11:27 PM PDT 24
Peak memory 200280 kb
Host smart-d00022cf-e98c-4571-a566-a2c1ba833020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670751467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1670751467
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2914928469
Short name T1018
Test name
Test status
Simulation time 141656228002 ps
CPU time 102 seconds
Started Jul 25 07:13:16 PM PDT 24
Finished Jul 25 07:14:58 PM PDT 24
Peak memory 200160 kb
Host smart-70c66da4-f3ac-4d4e-84e3-6e6fada2bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914928469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2914928469
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1002605623
Short name T686
Test name
Test status
Simulation time 41207294187 ps
CPU time 94.28 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:14:49 PM PDT 24
Peak memory 200224 kb
Host smart-146e0b69-8d9e-402f-9872-b8c95d134e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002605623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1002605623
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2848578699
Short name T153
Test name
Test status
Simulation time 46806120053 ps
CPU time 78.4 seconds
Started Jul 25 07:13:13 PM PDT 24
Finished Jul 25 07:14:32 PM PDT 24
Peak memory 200272 kb
Host smart-e9731809-90cf-492a-b4b6-e70142a3f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848578699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2848578699
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.220065778
Short name T1016
Test name
Test status
Simulation time 45367337949 ps
CPU time 37.18 seconds
Started Jul 25 07:13:13 PM PDT 24
Finished Jul 25 07:13:50 PM PDT 24
Peak memory 200220 kb
Host smart-d1fae51f-92cc-442d-9971-544f124aed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220065778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.220065778
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.532379441
Short name T390
Test name
Test status
Simulation time 48384047066 ps
CPU time 21.91 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:38 PM PDT 24
Peak memory 200196 kb
Host smart-2db421fd-44a0-4ac6-b600-5d4146ca785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532379441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.532379441
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2594070539
Short name T193
Test name
Test status
Simulation time 161950774035 ps
CPU time 79.92 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:14:34 PM PDT 24
Peak memory 200188 kb
Host smart-c099de4f-8f07-45f7-9791-88c798a45b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594070539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2594070539
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1783612151
Short name T229
Test name
Test status
Simulation time 106114382708 ps
CPU time 35.71 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:51 PM PDT 24
Peak memory 200180 kb
Host smart-b4bd976e-f6a7-471b-b792-4ce8f465d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783612151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1783612151
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1540032522
Short name T190
Test name
Test status
Simulation time 148152654549 ps
CPU time 51.04 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 200248 kb
Host smart-067e3f49-a316-4ac5-83d5-3601b4f717e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540032522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1540032522
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4240694078
Short name T214
Test name
Test status
Simulation time 67124338485 ps
CPU time 13.74 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:29 PM PDT 24
Peak memory 200248 kb
Host smart-89699888-59f6-4480-9d55-f56ff4f4b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240694078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4240694078
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.835944972
Short name T1130
Test name
Test status
Simulation time 18830568 ps
CPU time 0.54 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:35 PM PDT 24
Peak memory 195628 kb
Host smart-f0fd436f-57da-45ec-b3ab-d4e4aa5d61f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835944972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.835944972
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3411446329
Short name T895
Test name
Test status
Simulation time 100862267600 ps
CPU time 42.45 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:10:15 PM PDT 24
Peak memory 200132 kb
Host smart-34574b95-38ad-4156-b807-effc31cf4648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411446329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3411446329
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2803011323
Short name T646
Test name
Test status
Simulation time 97486100075 ps
CPU time 320.61 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:14:54 PM PDT 24
Peak memory 199988 kb
Host smart-da03527f-766e-4a54-a24d-a03836fcb033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803011323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2803011323
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2705821215
Short name T424
Test name
Test status
Simulation time 106939044859 ps
CPU time 73.11 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:10:50 PM PDT 24
Peak memory 200232 kb
Host smart-a35c5925-54f8-489e-9a1a-fdafeec4e3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705821215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2705821215
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4155223393
Short name T719
Test name
Test status
Simulation time 36001164543 ps
CPU time 52.56 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 199096 kb
Host smart-d459742b-fa3e-4b09-ad1a-4af3977aa200
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155223393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4155223393
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2815810333
Short name T865
Test name
Test status
Simulation time 60472472895 ps
CPU time 198.6 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:12:56 PM PDT 24
Peak memory 200256 kb
Host smart-1b488527-8e39-479a-991e-594d8e6989cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815810333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2815810333
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1040850710
Short name T316
Test name
Test status
Simulation time 9330253508 ps
CPU time 8.32 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 199360 kb
Host smart-b402f847-9364-47ef-afa3-a2e1fd8fc3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040850710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1040850710
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.106915156
Short name T275
Test name
Test status
Simulation time 96374916865 ps
CPU time 76.69 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:10:57 PM PDT 24
Peak memory 200176 kb
Host smart-fd4f1b86-6978-461c-b61c-c0d88ff98f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106915156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.106915156
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2529537197
Short name T1107
Test name
Test status
Simulation time 15197677223 ps
CPU time 953.2 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:25:40 PM PDT 24
Peak memory 200284 kb
Host smart-3316ed0a-feb9-44c2-a9b2-52c9d935d788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529537197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2529537197
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3150036228
Short name T1173
Test name
Test status
Simulation time 3401617787 ps
CPU time 18.57 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:09:53 PM PDT 24
Peak memory 198724 kb
Host smart-4c0fb8f1-2ab0-4787-883d-e875f55ff381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150036228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3150036228
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3658628437
Short name T388
Test name
Test status
Simulation time 22436595703 ps
CPU time 11.43 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:48 PM PDT 24
Peak memory 200272 kb
Host smart-49636a28-5508-48d3-921f-f6bbdc275b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658628437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3658628437
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.940089598
Short name T663
Test name
Test status
Simulation time 4758986569 ps
CPU time 4.49 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:09:42 PM PDT 24
Peak memory 196420 kb
Host smart-9a18ba03-9515-4305-992a-65cd41bcb321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940089598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.940089598
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3588044799
Short name T99
Test name
Test status
Simulation time 511375821 ps
CPU time 0.84 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:09:44 PM PDT 24
Peak memory 218456 kb
Host smart-e9d20a01-d26a-4831-adaa-2749472937ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588044799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3588044799
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4211338926
Short name T283
Test name
Test status
Simulation time 6014112177 ps
CPU time 17.1 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:51 PM PDT 24
Peak memory 199532 kb
Host smart-cba4a30b-81c0-40c9-87f7-6832156fc322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211338926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4211338926
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2256092113
Short name T1037
Test name
Test status
Simulation time 33089631610 ps
CPU time 377.85 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 216728 kb
Host smart-cb55a3c9-8750-4332-ac31-902eb0f5c0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256092113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2256092113
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4128025948
Short name T616
Test name
Test status
Simulation time 8347238456 ps
CPU time 12.85 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:46 PM PDT 24
Peak memory 200120 kb
Host smart-15e3ed9a-d3a9-47e6-9a5e-5b520e4fec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128025948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4128025948
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.4267975627
Short name T4
Test name
Test status
Simulation time 97905683789 ps
CPU time 118.84 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:11:39 PM PDT 24
Peak memory 200172 kb
Host smart-ef470d3b-2ccf-43bd-867b-aedf9c117cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267975627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.4267975627
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1482331090
Short name T421
Test name
Test status
Simulation time 12261315 ps
CPU time 0.56 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 195604 kb
Host smart-6230c976-a4a3-44d9-a3c5-df7097370ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482331090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1482331090
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1971290959
Short name T503
Test name
Test status
Simulation time 9214089889 ps
CPU time 4.95 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:10:44 PM PDT 24
Peak memory 200248 kb
Host smart-562ee4a2-3a36-4398-8de4-356b961d7a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971290959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1971290959
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.853118166
Short name T1027
Test name
Test status
Simulation time 41275371524 ps
CPU time 74.53 seconds
Started Jul 25 07:10:41 PM PDT 24
Finished Jul 25 07:11:56 PM PDT 24
Peak memory 200176 kb
Host smart-a94847dd-c5ab-495c-b2d7-789ac7981313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853118166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.853118166
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3352893335
Short name T754
Test name
Test status
Simulation time 123273972674 ps
CPU time 90.34 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:12:09 PM PDT 24
Peak memory 200036 kb
Host smart-b9bc6e65-cf05-49cb-9342-b3bde813e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352893335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3352893335
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4252098544
Short name T972
Test name
Test status
Simulation time 148984201471 ps
CPU time 246.74 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 198052 kb
Host smart-cd46a54e-8628-436c-a339-fa2864810b9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252098544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4252098544
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1541370869
Short name T1014
Test name
Test status
Simulation time 61474826095 ps
CPU time 542.28 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:19:42 PM PDT 24
Peak memory 200244 kb
Host smart-df450fc2-8ba2-4df5-b92f-af2f03df68a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541370869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1541370869
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3440758306
Short name T473
Test name
Test status
Simulation time 871505141 ps
CPU time 0.92 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 196408 kb
Host smart-e28e6fac-d9e9-403a-a664-8495b3964dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440758306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3440758306
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.67894137
Short name T584
Test name
Test status
Simulation time 172478389956 ps
CPU time 128.75 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 208492 kb
Host smart-7c9b94fe-ffb6-424f-b4bb-e3e53a5ecd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67894137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.67894137
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.164448732
Short name T356
Test name
Test status
Simulation time 15922471242 ps
CPU time 46.64 seconds
Started Jul 25 07:10:41 PM PDT 24
Finished Jul 25 07:11:28 PM PDT 24
Peak memory 200240 kb
Host smart-e1f2317c-f427-44b2-a7da-d8505327dc2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164448732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.164448732
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.887646973
Short name T831
Test name
Test status
Simulation time 4423873316 ps
CPU time 17.45 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:10:54 PM PDT 24
Peak memory 198428 kb
Host smart-c01b5daf-c69d-4f18-bf1e-21c178d932b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887646973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.887646973
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2945691308
Short name T930
Test name
Test status
Simulation time 138473527067 ps
CPU time 273.35 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:15:10 PM PDT 24
Peak memory 200180 kb
Host smart-261fb593-d8cd-4675-9d88-858cd8bce635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945691308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2945691308
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2212601361
Short name T730
Test name
Test status
Simulation time 2583664718 ps
CPU time 4.42 seconds
Started Jul 25 07:10:42 PM PDT 24
Finished Jul 25 07:10:47 PM PDT 24
Peak memory 196080 kb
Host smart-3c9de719-64df-4992-b42e-ac534141b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212601361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2212601361
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4178380780
Short name T414
Test name
Test status
Simulation time 512423689 ps
CPU time 1.63 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:10:40 PM PDT 24
Peak memory 199068 kb
Host smart-0bc9ce20-a222-428f-8de5-bab48cde1a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178380780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4178380780
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.4244621569
Short name T638
Test name
Test status
Simulation time 67824850710 ps
CPU time 118.64 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:12:39 PM PDT 24
Peak memory 200196 kb
Host smart-bc29a025-3caf-4f1c-aae1-4f169c07dda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244621569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4244621569
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3688265398
Short name T589
Test name
Test status
Simulation time 38234303695 ps
CPU time 294.68 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 214068 kb
Host smart-3b70f2ee-4139-4a6f-a806-c6c68993580a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688265398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3688265398
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3619310740
Short name T349
Test name
Test status
Simulation time 2589021849 ps
CPU time 2.52 seconds
Started Jul 25 07:10:36 PM PDT 24
Finished Jul 25 07:10:39 PM PDT 24
Peak memory 199260 kb
Host smart-edd702b4-cf4b-43c8-a4c3-0edeb839ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619310740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3619310740
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3824600925
Short name T448
Test name
Test status
Simulation time 38892073058 ps
CPU time 59.58 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:11:39 PM PDT 24
Peak memory 200260 kb
Host smart-2e5fa8d8-6382-4bf1-85ee-94b498e9608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824600925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3824600925
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.792804988
Short name T839
Test name
Test status
Simulation time 41395316 ps
CPU time 0.58 seconds
Started Jul 25 07:10:51 PM PDT 24
Finished Jul 25 07:10:51 PM PDT 24
Peak memory 195644 kb
Host smart-373ca2b7-a33b-4a13-ad68-3888e1c21fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792804988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.792804988
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.179486512
Short name T928
Test name
Test status
Simulation time 118037923476 ps
CPU time 220.71 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:14:20 PM PDT 24
Peak memory 200244 kb
Host smart-6c2a98f4-abe4-41ef-a49c-d1fd56baabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179486512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.179486512
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2104280408
Short name T645
Test name
Test status
Simulation time 18349891449 ps
CPU time 7.54 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 200272 kb
Host smart-6127f4c9-1c4b-4094-8dab-118b32f1d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104280408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2104280408
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3057257669
Short name T957
Test name
Test status
Simulation time 17918595500 ps
CPU time 55.15 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:11:33 PM PDT 24
Peak memory 200228 kb
Host smart-4ee6db2f-19eb-4c08-b2e8-3d95db8a3326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057257669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3057257669
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1469970303
Short name T661
Test name
Test status
Simulation time 100588305433 ps
CPU time 487.34 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:18:54 PM PDT 24
Peak memory 200192 kb
Host smart-143fb1ce-e5d8-43b2-a586-53c804b8c6da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469970303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1469970303
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3546474977
Short name T418
Test name
Test status
Simulation time 3719482189 ps
CPU time 2.69 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 198380 kb
Host smart-0e7a0f29-dc3b-4de2-8928-2ac5d3f44187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546474977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3546474977
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2643609817
Short name T888
Test name
Test status
Simulation time 23973905186 ps
CPU time 46.44 seconds
Started Jul 25 07:10:40 PM PDT 24
Finished Jul 25 07:11:27 PM PDT 24
Peak memory 199112 kb
Host smart-3dd6a1ea-bf1f-4368-8213-79d120ca0acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643609817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2643609817
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.137147532
Short name T811
Test name
Test status
Simulation time 19243459419 ps
CPU time 482.48 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:18:50 PM PDT 24
Peak memory 200196 kb
Host smart-89f70077-97a8-4071-9f74-f106ae62866a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137147532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.137147532
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1702043849
Short name T351
Test name
Test status
Simulation time 1480802070 ps
CPU time 5.4 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:10:43 PM PDT 24
Peak memory 198212 kb
Host smart-5755b20d-66e3-4f65-8d3a-ef3cc1885c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702043849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1702043849
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1460693414
Short name T159
Test name
Test status
Simulation time 73951320268 ps
CPU time 63.27 seconds
Started Jul 25 07:10:37 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200228 kb
Host smart-5bbad26d-980d-4857-b790-0e7839868c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460693414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1460693414
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1464557455
Short name T464
Test name
Test status
Simulation time 2181145584 ps
CPU time 2.24 seconds
Started Jul 25 07:10:38 PM PDT 24
Finished Jul 25 07:10:40 PM PDT 24
Peak memory 195800 kb
Host smart-9b6c81b5-6c57-4f80-8f20-5f50d10325ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464557455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1464557455
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1285928875
Short name T781
Test name
Test status
Simulation time 5552924702 ps
CPU time 17.79 seconds
Started Jul 25 07:10:46 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 200248 kb
Host smart-115c9a1a-a0c5-47b4-87d9-d0845e1911b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285928875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1285928875
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1330825287
Short name T881
Test name
Test status
Simulation time 372224823822 ps
CPU time 327.02 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:16:16 PM PDT 24
Peak memory 200252 kb
Host smart-bbb4723a-2fa9-445d-8b36-caeeb3036ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330825287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1330825287
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2245789132
Short name T1146
Test name
Test status
Simulation time 1094320628 ps
CPU time 2.1 seconds
Started Jul 25 07:10:39 PM PDT 24
Finished Jul 25 07:10:41 PM PDT 24
Peak memory 198544 kb
Host smart-833b3742-424d-4f60-ab98-d3c79047d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245789132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2245789132
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.437906251
Short name T438
Test name
Test status
Simulation time 136902468876 ps
CPU time 71.61 seconds
Started Jul 25 07:10:41 PM PDT 24
Finished Jul 25 07:11:52 PM PDT 24
Peak memory 200216 kb
Host smart-499f5a05-a849-4028-b104-7d234e979134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437906251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.437906251
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1559535155
Short name T706
Test name
Test status
Simulation time 11228403 ps
CPU time 0.59 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:10:50 PM PDT 24
Peak memory 195608 kb
Host smart-b2682bff-340b-407f-97a7-805ac6f4620c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559535155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1559535155
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.801321931
Short name T48
Test name
Test status
Simulation time 49037085090 ps
CPU time 36.41 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200272 kb
Host smart-c169b06c-06cb-4f8a-845c-2cd5c54078c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801321931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.801321931
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3838608347
Short name T1165
Test name
Test status
Simulation time 227264237973 ps
CPU time 68.58 seconds
Started Jul 25 07:10:51 PM PDT 24
Finished Jul 25 07:11:59 PM PDT 24
Peak memory 200164 kb
Host smart-581ffd2f-4754-4f33-9236-010ff2805c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838608347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3838608347
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.584291008
Short name T756
Test name
Test status
Simulation time 38967983474 ps
CPU time 14.75 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 198724 kb
Host smart-00727994-3d08-44c1-8873-f0aef33c3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584291008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.584291008
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1873308450
Short name T920
Test name
Test status
Simulation time 20113193602 ps
CPU time 18.21 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:11:08 PM PDT 24
Peak memory 199460 kb
Host smart-2204df2e-39e9-4e28-95aa-aa1b7ca8fe2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873308450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1873308450
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.994877664
Short name T87
Test name
Test status
Simulation time 97806359555 ps
CPU time 87.17 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:12:16 PM PDT 24
Peak memory 200260 kb
Host smart-bed7d878-3cd2-453d-9ef4-37ca3f00b318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994877664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.994877664
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.303039392
Short name T1035
Test name
Test status
Simulation time 7974277702 ps
CPU time 13.63 seconds
Started Jul 25 07:10:48 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 200276 kb
Host smart-af65b6af-39e5-48d0-914d-a4b7fea31ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303039392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.303039392
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1717229457
Short name T718
Test name
Test status
Simulation time 120562537317 ps
CPU time 90.79 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:12:20 PM PDT 24
Peak memory 200384 kb
Host smart-0b75b8fc-0e66-447d-939d-56ab094f077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717229457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1717229457
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2428986237
Short name T498
Test name
Test status
Simulation time 7780554761 ps
CPU time 359.4 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:16:49 PM PDT 24
Peak memory 200228 kb
Host smart-598b5fa2-6d9a-4e8b-9e35-894248584a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428986237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2428986237
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4121150650
Short name T405
Test name
Test status
Simulation time 4509058865 ps
CPU time 9.81 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:10:59 PM PDT 24
Peak memory 199716 kb
Host smart-e00a72a2-b8c0-4883-b7b4-86c6142834db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121150650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4121150650
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4213262369
Short name T330
Test name
Test status
Simulation time 38198271771 ps
CPU time 16.97 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 200128 kb
Host smart-d5d63d5e-1e9b-4550-b42e-d1afd4944472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213262369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4213262369
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3944167639
Short name T660
Test name
Test status
Simulation time 4757558921 ps
CPU time 4.2 seconds
Started Jul 25 07:10:51 PM PDT 24
Finished Jul 25 07:10:55 PM PDT 24
Peak memory 196676 kb
Host smart-1e4ba2ae-71ec-4717-8ea1-e303063b89e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944167639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3944167639
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2947265915
Short name T732
Test name
Test status
Simulation time 449359914 ps
CPU time 1.55 seconds
Started Jul 25 07:10:48 PM PDT 24
Finished Jul 25 07:10:50 PM PDT 24
Peak memory 199084 kb
Host smart-a4dfe9a3-354d-4782-9546-93dd3a9859e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947265915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2947265915
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2923143371
Short name T857
Test name
Test status
Simulation time 337542383868 ps
CPU time 547.05 seconds
Started Jul 25 07:10:46 PM PDT 24
Finished Jul 25 07:19:53 PM PDT 24
Peak memory 208756 kb
Host smart-2e22a836-cda2-43f0-b6cf-b90502e43ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923143371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2923143371
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3636610555
Short name T314
Test name
Test status
Simulation time 101236949368 ps
CPU time 395.39 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:17:25 PM PDT 24
Peak memory 216336 kb
Host smart-793acc11-e2b2-442a-883f-356180c5f032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636610555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3636610555
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1118253874
Short name T877
Test name
Test status
Simulation time 1198543752 ps
CPU time 1.91 seconds
Started Jul 25 07:10:52 PM PDT 24
Finished Jul 25 07:10:54 PM PDT 24
Peak memory 199404 kb
Host smart-c6a41f68-5977-4111-82a1-40ca2da8c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118253874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1118253874
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1574392389
Short name T1067
Test name
Test status
Simulation time 132367263657 ps
CPU time 37.57 seconds
Started Jul 25 07:10:49 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200148 kb
Host smart-5e3aa7f8-46da-40bb-bc63-a17c38b3d1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574392389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1574392389
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3096131702
Short name T1044
Test name
Test status
Simulation time 20086680 ps
CPU time 0.56 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:11:01 PM PDT 24
Peak memory 195912 kb
Host smart-9183d632-23b8-4743-8bf9-e9ce6976c4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096131702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3096131702
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1699056980
Short name T1001
Test name
Test status
Simulation time 40217069692 ps
CPU time 91.56 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:12:19 PM PDT 24
Peak memory 200180 kb
Host smart-acb4fcc0-1f31-41c2-b80e-8ad68ab241af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699056980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1699056980
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1870159121
Short name T1103
Test name
Test status
Simulation time 38933867822 ps
CPU time 26.32 seconds
Started Jul 25 07:10:52 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200216 kb
Host smart-5be223f2-f55b-4ab3-86ee-ac9f447122e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870159121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1870159121
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3479836786
Short name T762
Test name
Test status
Simulation time 112125839695 ps
CPU time 49.85 seconds
Started Jul 25 07:10:52 PM PDT 24
Finished Jul 25 07:11:42 PM PDT 24
Peak memory 200232 kb
Host smart-197d7a2c-daab-49d2-a0ef-81f6315273e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479836786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3479836786
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3208053881
Short name T1156
Test name
Test status
Simulation time 37716450930 ps
CPU time 60.49 seconds
Started Jul 25 07:10:52 PM PDT 24
Finished Jul 25 07:11:53 PM PDT 24
Peak memory 200156 kb
Host smart-6ab8e80d-9b09-4c88-b670-8f4b73d7e0b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208053881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3208053881
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2104889615
Short name T653
Test name
Test status
Simulation time 81396733089 ps
CPU time 360.43 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:16:58 PM PDT 24
Peak memory 200196 kb
Host smart-84355678-8222-4dca-8ca9-6ac6458f501e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104889615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2104889615
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3422472189
Short name T651
Test name
Test status
Simulation time 2822849213 ps
CPU time 8.59 seconds
Started Jul 25 07:10:57 PM PDT 24
Finished Jul 25 07:11:06 PM PDT 24
Peak memory 199784 kb
Host smart-81bdc2b5-9f37-4d1f-bc5b-6e3830cb9794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422472189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3422472189
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.584045980
Short name T716
Test name
Test status
Simulation time 110988394425 ps
CPU time 106.94 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 208492 kb
Host smart-7e2ceea8-473c-4571-a338-7beaed5e20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584045980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.584045980
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1070946695
Short name T614
Test name
Test status
Simulation time 28001769251 ps
CPU time 1502.33 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:36:04 PM PDT 24
Peak memory 200156 kb
Host smart-32b50c8b-06a9-4b28-ae92-7f1191fc78c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070946695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1070946695
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.849534999
Short name T543
Test name
Test status
Simulation time 6599290027 ps
CPU time 5.09 seconds
Started Jul 25 07:10:47 PM PDT 24
Finished Jul 25 07:10:53 PM PDT 24
Peak memory 199072 kb
Host smart-9bd968db-7ee3-44ea-990d-3f077a2407b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849534999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.849534999
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3791969505
Short name T1181
Test name
Test status
Simulation time 54707399245 ps
CPU time 75.62 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:12:16 PM PDT 24
Peak memory 200240 kb
Host smart-04961749-94fb-4b8c-b5ce-5141cd289454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791969505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3791969505
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.596801591
Short name T909
Test name
Test status
Simulation time 4700347940 ps
CPU time 2.52 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 196368 kb
Host smart-ca4bf86c-1035-45ba-9947-fded7a1c5522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596801591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.596801591
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3367086968
Short name T769
Test name
Test status
Simulation time 465594623 ps
CPU time 0.96 seconds
Started Jul 25 07:10:48 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 198672 kb
Host smart-208b2213-42a5-4a9c-bbd7-f889affcc852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367086968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3367086968
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.722401030
Short name T601
Test name
Test status
Simulation time 141840581658 ps
CPU time 258.85 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200236 kb
Host smart-e2d80827-9eac-461e-99c2-e72e1a02dd2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722401030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.722401030
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3220602213
Short name T761
Test name
Test status
Simulation time 30518608377 ps
CPU time 255.17 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 216436 kb
Host smart-a5a3aa58-9cf0-4011-946b-4dde70a0bf34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220602213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3220602213
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3626984567
Short name T820
Test name
Test status
Simulation time 1292911720 ps
CPU time 3.96 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:06 PM PDT 24
Peak memory 199236 kb
Host smart-6abd1123-19e7-4145-a8e5-bce34237f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626984567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3626984567
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3563371293
Short name T566
Test name
Test status
Simulation time 66459532207 ps
CPU time 67.31 seconds
Started Jul 25 07:10:46 PM PDT 24
Finished Jul 25 07:11:53 PM PDT 24
Peak memory 200224 kb
Host smart-f98415d9-5a41-4eb1-a4c3-ac95815f8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563371293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3563371293
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1179627682
Short name T1002
Test name
Test status
Simulation time 63558663 ps
CPU time 0.56 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:10:58 PM PDT 24
Peak memory 195896 kb
Host smart-6db744f0-ba02-4eec-bc78-dfb5a3b8c97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179627682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1179627682
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2259158344
Short name T1063
Test name
Test status
Simulation time 35817747858 ps
CPU time 18.56 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:20 PM PDT 24
Peak memory 200216 kb
Host smart-5efbde47-1e22-4ba6-b60f-02e3526cee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259158344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2259158344
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3746107491
Short name T248
Test name
Test status
Simulation time 163099366423 ps
CPU time 65.14 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:12:04 PM PDT 24
Peak memory 200176 kb
Host smart-e1742a08-a413-4f8e-8159-2f95ee18ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746107491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3746107491
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1006352191
Short name T966
Test name
Test status
Simulation time 33748487560 ps
CPU time 26.36 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200224 kb
Host smart-71c4813e-bbf2-4260-8463-adb221fddc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006352191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1006352191
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3957491752
Short name T829
Test name
Test status
Simulation time 9871253335 ps
CPU time 2.97 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 200136 kb
Host smart-7b3a0519-3497-42b0-8cc6-24cb89f6cc7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957491752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3957491752
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3757189855
Short name T541
Test name
Test status
Simulation time 92610414052 ps
CPU time 368.03 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:17:06 PM PDT 24
Peak memory 200292 kb
Host smart-5850c952-eaff-47d0-9189-7f4b9be6fd97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757189855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3757189855
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3765078218
Short name T1126
Test name
Test status
Simulation time 3775537343 ps
CPU time 4.68 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:06 PM PDT 24
Peak memory 199180 kb
Host smart-80a6411b-c996-4720-ad87-3ac6f5a45008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765078218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3765078218
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1551609892
Short name T1024
Test name
Test status
Simulation time 162495804666 ps
CPU time 84.86 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:12:26 PM PDT 24
Peak memory 208332 kb
Host smart-7a8bd6fd-244f-433b-832a-74dfd15d6049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551609892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1551609892
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2943625645
Short name T903
Test name
Test status
Simulation time 17949586125 ps
CPU time 387.13 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:17:26 PM PDT 24
Peak memory 200160 kb
Host smart-c6c12023-e69f-4278-90d3-e06215079530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943625645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2943625645
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3456384181
Short name T709
Test name
Test status
Simulation time 5525462389 ps
CPU time 12.93 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 198084 kb
Host smart-7673e09e-e69b-42e8-bb67-8d7c79a0bbb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456384181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3456384181
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3635604869
Short name T486
Test name
Test status
Simulation time 25659561367 ps
CPU time 25.64 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:11:25 PM PDT 24
Peak memory 200020 kb
Host smart-74bec2ad-4678-4a23-b372-65a32e51d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635604869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3635604869
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.306665484
Short name T509
Test name
Test status
Simulation time 4148879380 ps
CPU time 7.59 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:11:07 PM PDT 24
Peak memory 197100 kb
Host smart-a52401e2-f514-419c-bbda-27fb2afe4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306665484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.306665484
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3360094588
Short name T371
Test name
Test status
Simulation time 274854255 ps
CPU time 1.12 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 198840 kb
Host smart-c51de461-7b0a-43a8-a2dd-21b44a5ed1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360094588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3360094588
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4052633243
Short name T1034
Test name
Test status
Simulation time 324874340022 ps
CPU time 568.26 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:20:51 PM PDT 24
Peak memory 200252 kb
Host smart-f031b1a3-8eef-41db-ba08-97de5c4832d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052633243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4052633243
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1286365412
Short name T181
Test name
Test status
Simulation time 15728246206 ps
CPU time 182.05 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 215976 kb
Host smart-00b61d78-74de-403f-a505-f084dfda4fd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286365412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1286365412
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1107025544
Short name T1152
Test name
Test status
Simulation time 6347780644 ps
CPU time 21.16 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 199920 kb
Host smart-99ad954e-62ce-43d4-9c09-df3f81e39560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107025544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1107025544
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1925167016
Short name T952
Test name
Test status
Simulation time 56095463729 ps
CPU time 88.7 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:12:31 PM PDT 24
Peak memory 200264 kb
Host smart-271e6e47-f6cf-4252-b617-ba8e4d3017cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925167016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1925167016
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4155971515
Short name T1163
Test name
Test status
Simulation time 38551163 ps
CPU time 0.6 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:10:59 PM PDT 24
Peak memory 195624 kb
Host smart-67d4827c-24e2-430b-8d33-191f96ebdd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155971515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4155971515
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2071910944
Short name T864
Test name
Test status
Simulation time 41697554286 ps
CPU time 34.77 seconds
Started Jul 25 07:11:03 PM PDT 24
Finished Jul 25 07:11:38 PM PDT 24
Peak memory 200160 kb
Host smart-f6357e17-3b95-4805-82f1-5ff980b2de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071910944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2071910944
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2929431538
Short name T872
Test name
Test status
Simulation time 24035517787 ps
CPU time 28.66 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:11:29 PM PDT 24
Peak memory 200240 kb
Host smart-a3f466cb-bd36-4b7c-8b5a-3ad9b7527372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929431538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2929431538
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4237141487
Short name T712
Test name
Test status
Simulation time 48995401602 ps
CPU time 21.29 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 200268 kb
Host smart-192ce51f-5c86-41b3-838f-159b28b591da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237141487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4237141487
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.179015585
Short name T1135
Test name
Test status
Simulation time 159707921278 ps
CPU time 194.52 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:14:12 PM PDT 24
Peak memory 198220 kb
Host smart-2be4d874-d39b-4a2d-a1e1-23d98d65209e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179015585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.179015585
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.64619802
Short name T1151
Test name
Test status
Simulation time 114020755021 ps
CPU time 694.87 seconds
Started Jul 25 07:11:03 PM PDT 24
Finished Jul 25 07:22:38 PM PDT 24
Peak memory 200240 kb
Host smart-ce3b24e4-eff0-498f-bef8-20b41917b466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64619802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.64619802
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3652938864
Short name T22
Test name
Test status
Simulation time 3527923739 ps
CPU time 2.03 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:11:02 PM PDT 24
Peak memory 199120 kb
Host smart-84065b6c-cdc3-4883-9e96-a5ad20efdb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652938864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3652938864
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2839978710
Short name T740
Test name
Test status
Simulation time 135734465949 ps
CPU time 135.68 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 200172 kb
Host smart-d9edb54b-27ab-48b9-ac6a-901a1502ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839978710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2839978710
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3919085692
Short name T753
Test name
Test status
Simulation time 4450946252 ps
CPU time 226.35 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:14:48 PM PDT 24
Peak memory 200200 kb
Host smart-f11e9cad-255f-44e8-8497-37c40cbb7780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919085692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3919085692
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.977239902
Short name T626
Test name
Test status
Simulation time 4985301237 ps
CPU time 10.95 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 199488 kb
Host smart-7b879680-999f-44b7-a077-c3899ace72e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977239902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.977239902
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1824675813
Short name T854
Test name
Test status
Simulation time 22292694838 ps
CPU time 15.3 seconds
Started Jul 25 07:10:58 PM PDT 24
Finished Jul 25 07:11:14 PM PDT 24
Peak memory 200204 kb
Host smart-4d87a5f1-c526-4f89-bbcc-ce79e7a9e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824675813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1824675813
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1080160815
Short name T635
Test name
Test status
Simulation time 44588626503 ps
CPU time 34.67 seconds
Started Jul 25 07:11:00 PM PDT 24
Finished Jul 25 07:11:34 PM PDT 24
Peak memory 196408 kb
Host smart-981a91b9-2023-4398-9f95-3e4bd4f4da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080160815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1080160815
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.923257424
Short name T948
Test name
Test status
Simulation time 900561255 ps
CPU time 2.13 seconds
Started Jul 25 07:11:01 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 200096 kb
Host smart-97fd77eb-c897-47de-8af7-e596a383f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923257424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.923257424
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3964672924
Short name T531
Test name
Test status
Simulation time 82928344054 ps
CPU time 760.94 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:23:43 PM PDT 24
Peak memory 216724 kb
Host smart-13623d7a-0c46-4c6b-8310-895ea36723c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964672924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3964672924
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.126972414
Short name T358
Test name
Test status
Simulation time 2396668907 ps
CPU time 1.96 seconds
Started Jul 25 07:11:03 PM PDT 24
Finished Jul 25 07:11:05 PM PDT 24
Peak memory 198660 kb
Host smart-fff12248-0720-4f6b-ba33-e9004f994d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126972414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.126972414
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3387933065
Short name T367
Test name
Test status
Simulation time 4269212325 ps
CPU time 7.51 seconds
Started Jul 25 07:10:59 PM PDT 24
Finished Jul 25 07:11:06 PM PDT 24
Peak memory 200008 kb
Host smart-36e6d6c2-483f-473a-923f-b7be02279366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387933065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3387933065
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3568470139
Short name T813
Test name
Test status
Simulation time 35983252 ps
CPU time 0.56 seconds
Started Jul 25 07:11:15 PM PDT 24
Finished Jul 25 07:11:16 PM PDT 24
Peak memory 195884 kb
Host smart-813418fa-6c2e-44f5-ba3a-a57363fb4d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568470139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3568470139
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3594239795
Short name T1066
Test name
Test status
Simulation time 135120968705 ps
CPU time 53.9 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:12:04 PM PDT 24
Peak memory 200236 kb
Host smart-8f9edd35-8824-4638-bf15-db916000581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594239795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3594239795
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3770125768
Short name T133
Test name
Test status
Simulation time 104353819832 ps
CPU time 32.59 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:43 PM PDT 24
Peak memory 200212 kb
Host smart-11f0ac04-11ae-4a9a-a27e-190fdbfcade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770125768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3770125768
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.1373552417
Short name T299
Test name
Test status
Simulation time 50844805780 ps
CPU time 26.67 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:37 PM PDT 24
Peak memory 200172 kb
Host smart-007fc970-5304-4deb-ae26-95c3e9059330
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373552417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1373552417
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3752839857
Short name T46
Test name
Test status
Simulation time 77597885424 ps
CPU time 763.52 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:23:53 PM PDT 24
Peak memory 200256 kb
Host smart-2eb79528-6830-4d87-b703-2aac3b0b51ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752839857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3752839857
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3137745938
Short name T650
Test name
Test status
Simulation time 3574350122 ps
CPU time 3.32 seconds
Started Jul 25 07:11:11 PM PDT 24
Finished Jul 25 07:11:15 PM PDT 24
Peak memory 198724 kb
Host smart-521c10cc-5c94-490a-b4fd-d3cf77a8267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137745938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3137745938
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1312273981
Short name T254
Test name
Test status
Simulation time 20780380691 ps
CPU time 16.72 seconds
Started Jul 25 07:11:15 PM PDT 24
Finished Jul 25 07:11:32 PM PDT 24
Peak memory 200348 kb
Host smart-6074b1c1-10f9-4f8d-b3b4-f142b814b4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312273981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1312273981
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2286546946
Short name T52
Test name
Test status
Simulation time 22085122398 ps
CPU time 266.21 seconds
Started Jul 25 07:11:07 PM PDT 24
Finished Jul 25 07:15:34 PM PDT 24
Peak memory 200212 kb
Host smart-e4074067-5d6d-4c49-af78-3cf9a1a06ab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286546946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2286546946
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.616675548
Short name T1091
Test name
Test status
Simulation time 2340942285 ps
CPU time 16.39 seconds
Started Jul 25 07:11:08 PM PDT 24
Finished Jul 25 07:11:24 PM PDT 24
Peak memory 198556 kb
Host smart-4af4058c-3747-4aa4-84e4-239d058bdf75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616675548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.616675548
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.971818648
Short name T173
Test name
Test status
Simulation time 26153563443 ps
CPU time 9.49 seconds
Started Jul 25 07:11:08 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200228 kb
Host smart-9b8029db-4de2-4841-9ce1-e9e57e2a13ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971818648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.971818648
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.4078530196
Short name T378
Test name
Test status
Simulation time 40758308259 ps
CPU time 13.66 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:24 PM PDT 24
Peak memory 196128 kb
Host smart-ac7f5d8d-ad39-48f8-84ab-3a4bfdcc702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078530196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.4078530196
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1929635491
Short name T721
Test name
Test status
Simulation time 297213093 ps
CPU time 1.23 seconds
Started Jul 25 07:11:02 PM PDT 24
Finished Jul 25 07:11:03 PM PDT 24
Peak memory 198652 kb
Host smart-adf6e34c-557f-43a8-9198-77f5ebd69d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929635491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1929635491
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3631131748
Short name T916
Test name
Test status
Simulation time 149576439000 ps
CPU time 68.84 seconds
Started Jul 25 07:11:14 PM PDT 24
Finished Jul 25 07:12:23 PM PDT 24
Peak memory 200160 kb
Host smart-d875105f-7ace-4017-af16-bf5b5920898c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631131748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3631131748
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3089376934
Short name T945
Test name
Test status
Simulation time 27764396079 ps
CPU time 533.88 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:20:03 PM PDT 24
Peak memory 208740 kb
Host smart-3f49fac1-d5c1-4821-8a25-161a7888319f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089376934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3089376934
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2056129023
Short name T647
Test name
Test status
Simulation time 7161458953 ps
CPU time 11.63 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 200232 kb
Host smart-ac9fdf35-ff41-4890-b807-7cb2ed5c0e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056129023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2056129023
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.939259557
Short name T1042
Test name
Test status
Simulation time 10414321341 ps
CPU time 18.17 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:29 PM PDT 24
Peak memory 200264 kb
Host smart-18dfd242-be9e-4d87-86a8-56e2b218e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939259557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.939259557
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3818039660
Short name T1123
Test name
Test status
Simulation time 14018863 ps
CPU time 0.57 seconds
Started Jul 25 07:11:16 PM PDT 24
Finished Jul 25 07:11:17 PM PDT 24
Peak memory 195640 kb
Host smart-473ff27d-5854-4e38-8692-945a1b9ce6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818039660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3818039660
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2969494949
Short name T722
Test name
Test status
Simulation time 128258230245 ps
CPU time 56.95 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:12:09 PM PDT 24
Peak memory 199996 kb
Host smart-2673fa55-4da4-4a13-8dc1-b25abb7c9ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969494949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2969494949
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.322355430
Short name T611
Test name
Test status
Simulation time 19494031836 ps
CPU time 15.24 seconds
Started Jul 25 07:11:15 PM PDT 24
Finished Jul 25 07:11:31 PM PDT 24
Peak memory 200228 kb
Host smart-e1a667ea-0894-4ef9-9688-2a9198e13dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322355430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.322355430
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.1235432639
Short name T426
Test name
Test status
Simulation time 6011254631 ps
CPU time 9.63 seconds
Started Jul 25 07:11:08 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 200068 kb
Host smart-44b0f6b1-d4f6-49ab-b0b6-4f7906da2a7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235432639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1235432639
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1086088022
Short name T672
Test name
Test status
Simulation time 84975386781 ps
CPU time 763.8 seconds
Started Jul 25 07:11:14 PM PDT 24
Finished Jul 25 07:23:58 PM PDT 24
Peak memory 200264 kb
Host smart-05f8f1a1-e0a8-4f50-9e4b-0ff00f35e0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086088022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1086088022
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3289805986
Short name T846
Test name
Test status
Simulation time 4309802706 ps
CPU time 2.88 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 199596 kb
Host smart-7e7d4fbd-f247-4545-805a-c9c7f9d08667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289805986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3289805986
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2480353547
Short name T985
Test name
Test status
Simulation time 53959537997 ps
CPU time 46.23 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:56 PM PDT 24
Peak memory 200056 kb
Host smart-111b235e-2b61-4eef-9e0f-5ced9a65c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480353547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2480353547
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1011733799
Short name T548
Test name
Test status
Simulation time 12320167776 ps
CPU time 325.71 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:16:36 PM PDT 24
Peak memory 200248 kb
Host smart-45531067-e03d-447c-9e50-57f28283e1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011733799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1011733799
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1143429275
Short name T1015
Test name
Test status
Simulation time 4029970841 ps
CPU time 8.91 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:18 PM PDT 24
Peak memory 198672 kb
Host smart-0b0fd833-47d0-423f-b205-54e6dfe8d167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143429275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1143429275
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3610820737
Short name T286
Test name
Test status
Simulation time 29848505796 ps
CPU time 27.09 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:36 PM PDT 24
Peak memory 200268 kb
Host smart-6528d9f8-aace-461d-a9d5-be6689887c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610820737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3610820737
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3741303531
Short name T25
Test name
Test status
Simulation time 2484425922 ps
CPU time 4.3 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 196720 kb
Host smart-a8e7f7c9-4070-4c4a-b658-f0f9ca8d0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741303531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3741303531
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.265059086
Short name T369
Test name
Test status
Simulation time 157763938 ps
CPU time 0.81 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 198444 kb
Host smart-b51038cc-ce28-49cc-8cfc-17f06df7a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265059086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.265059086
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.501608500
Short name T165
Test name
Test status
Simulation time 167521900328 ps
CPU time 619.51 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:21:32 PM PDT 24
Peak memory 200272 kb
Host smart-c07edc9d-e6df-4c06-8a80-b8ae23acd68a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501608500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.501608500
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4264999478
Short name T61
Test name
Test status
Simulation time 53964211616 ps
CPU time 481.75 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:19:12 PM PDT 24
Peak memory 216924 kb
Host smart-42284060-1ebd-4578-b666-63eb3a160983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264999478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4264999478
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4026542726
Short name T713
Test name
Test status
Simulation time 1130309202 ps
CPU time 3.28 seconds
Started Jul 25 07:11:08 PM PDT 24
Finished Jul 25 07:11:11 PM PDT 24
Peak memory 198628 kb
Host smart-d31c33da-7614-45f4-8ccb-6b0a6ef56e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026542726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4026542726
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3187349335
Short name T1084
Test name
Test status
Simulation time 100799071749 ps
CPU time 56.73 seconds
Started Jul 25 07:11:15 PM PDT 24
Finished Jul 25 07:12:11 PM PDT 24
Peak memory 200164 kb
Host smart-182f8788-7f4a-49ef-a902-2bbac0ccb576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187349335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3187349335
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2338667518
Short name T409
Test name
Test status
Simulation time 24192128 ps
CPU time 0.53 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:10 PM PDT 24
Peak memory 194620 kb
Host smart-659f35ed-7456-4afe-8c22-47391fd1bdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338667518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2338667518
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2233084544
Short name T707
Test name
Test status
Simulation time 151206140787 ps
CPU time 519.79 seconds
Started Jul 25 07:11:16 PM PDT 24
Finished Jul 25 07:19:56 PM PDT 24
Peak memory 200248 kb
Host smart-8c7e7115-ec23-480f-904c-11ac0148e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233084544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2233084544
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3761178844
Short name T743
Test name
Test status
Simulation time 172759229884 ps
CPU time 280.73 seconds
Started Jul 25 07:11:11 PM PDT 24
Finished Jul 25 07:15:52 PM PDT 24
Peak memory 200228 kb
Host smart-5311fb2b-6dfd-46e4-bafe-ad58f46623eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761178844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3761178844
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1113709933
Short name T240
Test name
Test status
Simulation time 70628927776 ps
CPU time 39.19 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:49 PM PDT 24
Peak memory 200272 kb
Host smart-8bbdb3f4-9652-4904-bf5c-ac1420c6fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113709933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1113709933
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.61501208
Short name T598
Test name
Test status
Simulation time 33479078309 ps
CPU time 14.59 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200100 kb
Host smart-cb2b49e6-94f3-4740-89a3-5e69cdab30d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61501208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.61501208
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2318305833
Short name T883
Test name
Test status
Simulation time 127021939516 ps
CPU time 871.56 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:25:43 PM PDT 24
Peak memory 200192 kb
Host smart-c75ae1d5-e571-43a2-a4b9-059ca26553f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318305833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2318305833
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2286128859
Short name T407
Test name
Test status
Simulation time 7666400860 ps
CPU time 6.19 seconds
Started Jul 25 07:11:16 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 200184 kb
Host smart-92c6d083-e673-4cb2-9e97-93d5198066ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286128859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2286128859
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4228036148
Short name T311
Test name
Test status
Simulation time 36440519439 ps
CPU time 12.92 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 194804 kb
Host smart-07fbd419-e2f6-43e7-ae54-3a180af07356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228036148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4228036148
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.524175001
Short name T268
Test name
Test status
Simulation time 13387137800 ps
CPU time 197.17 seconds
Started Jul 25 07:11:11 PM PDT 24
Finished Jul 25 07:14:28 PM PDT 24
Peak memory 199948 kb
Host smart-7999528f-c9eb-494d-8ebf-ef0ad71f22a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524175001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.524175001
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3874832425
Short name T17
Test name
Test status
Simulation time 4444775453 ps
CPU time 29.4 seconds
Started Jul 25 07:11:11 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 198320 kb
Host smart-150dc0ef-df81-4a51-a9a0-9547e0a66c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874832425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3874832425
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1986362465
Short name T847
Test name
Test status
Simulation time 107513226221 ps
CPU time 148.1 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:13:38 PM PDT 24
Peak memory 200248 kb
Host smart-98cabc00-50d5-49d5-b9a2-aec8c3d25182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986362465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1986362465
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2453276830
Short name T303
Test name
Test status
Simulation time 38498049586 ps
CPU time 56.79 seconds
Started Jul 25 07:11:16 PM PDT 24
Finished Jul 25 07:12:13 PM PDT 24
Peak memory 196284 kb
Host smart-31e2be29-25b8-4d77-b87e-f8f13f1cd169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453276830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2453276830
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1957628411
Short name T1009
Test name
Test status
Simulation time 714855597 ps
CPU time 1.31 seconds
Started Jul 25 07:11:10 PM PDT 24
Finished Jul 25 07:11:12 PM PDT 24
Peak memory 198816 kb
Host smart-d1aa1d40-f01a-4c0d-b950-f3bda900a637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957628411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1957628411
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1434726522
Short name T39
Test name
Test status
Simulation time 66684409945 ps
CPU time 202.54 seconds
Started Jul 25 07:11:11 PM PDT 24
Finished Jul 25 07:14:34 PM PDT 24
Peak memory 213736 kb
Host smart-1893753f-079d-4716-9c9c-e443aaa272c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434726522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1434726522
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.4119063125
Short name T1068
Test name
Test status
Simulation time 525488230 ps
CPU time 2.25 seconds
Started Jul 25 07:11:09 PM PDT 24
Finished Jul 25 07:11:12 PM PDT 24
Peak memory 198684 kb
Host smart-6a678bcf-251d-489b-9625-adfd0b45e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119063125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4119063125
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1096614224
Short name T526
Test name
Test status
Simulation time 28555950259 ps
CPU time 45.73 seconds
Started Jul 25 07:11:16 PM PDT 24
Finished Jul 25 07:12:02 PM PDT 24
Peak memory 200196 kb
Host smart-f073c2d4-2551-4ff0-ac72-9bb47ea96c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096614224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1096614224
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1175476067
Short name T29
Test name
Test status
Simulation time 10705635 ps
CPU time 0.54 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 195056 kb
Host smart-fe4d93d9-9144-4f2a-aadf-9fb859cf8164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175476067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1175476067
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.308987881
Short name T956
Test name
Test status
Simulation time 41513072866 ps
CPU time 68.8 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:12:29 PM PDT 24
Peak memory 200244 kb
Host smart-80c9ecf5-a2e8-43bc-8d0d-8dbf9e10ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308987881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.308987881
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.276454251
Short name T702
Test name
Test status
Simulation time 74259606831 ps
CPU time 15.47 seconds
Started Jul 25 07:11:23 PM PDT 24
Finished Jul 25 07:11:38 PM PDT 24
Peak memory 200168 kb
Host smart-b648c0f7-2b8b-4db4-984f-e525c1638e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276454251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.276454251
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.2603129362
Short name T399
Test name
Test status
Simulation time 22759759608 ps
CPU time 20.49 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200212 kb
Host smart-7feaf1ee-8881-4d8a-9dd4-960213f9a02e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603129362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2603129362
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3838217846
Short name T694
Test name
Test status
Simulation time 84632515459 ps
CPU time 100.85 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:13:01 PM PDT 24
Peak memory 200268 kb
Host smart-66651b6e-db54-4f64-8a48-2e6056deb8e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838217846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3838217846
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1209400203
Short name T821
Test name
Test status
Simulation time 526945839 ps
CPU time 0.76 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 195928 kb
Host smart-3185032e-eef8-41fb-9a3f-3c9434c704ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209400203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1209400203
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.256881756
Short name T795
Test name
Test status
Simulation time 173617235171 ps
CPU time 38.53 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 208396 kb
Host smart-4ec9aed9-9cf0-405c-a288-532761284dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256881756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.256881756
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3304385008
Short name T773
Test name
Test status
Simulation time 14428435343 ps
CPU time 447.15 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:18:50 PM PDT 24
Peak memory 200240 kb
Host smart-9d20d74d-a7d7-4855-b539-3bfdf7a04da4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304385008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3304385008
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4165988373
Short name T852
Test name
Test status
Simulation time 4315363936 ps
CPU time 16.83 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:11:36 PM PDT 24
Peak memory 198360 kb
Host smart-bb4d3fb1-86cb-4799-877c-6cb42f740bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165988373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4165988373
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.753415092
Short name T1031
Test name
Test status
Simulation time 72224807852 ps
CPU time 114.61 seconds
Started Jul 25 07:11:21 PM PDT 24
Finished Jul 25 07:13:16 PM PDT 24
Peak memory 200224 kb
Host smart-6f96934a-0104-41da-98a4-447f684f74cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753415092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.753415092
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3632054786
Short name T306
Test name
Test status
Simulation time 3211626070 ps
CPU time 2.88 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 196188 kb
Host smart-ea1e7601-14f5-4341-9ca9-6e5bc7bfffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632054786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3632054786
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1150536264
Short name T408
Test name
Test status
Simulation time 470363413 ps
CPU time 1.17 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:11:13 PM PDT 24
Peak memory 199032 kb
Host smart-42dc4ec8-63b4-4071-9140-b1e1bd504f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150536264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1150536264
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2689406073
Short name T45
Test name
Test status
Simulation time 121161029529 ps
CPU time 221.38 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200136 kb
Host smart-6f926a56-9c56-4d09-b142-741635b8fe40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689406073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2689406073
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1044816113
Short name T115
Test name
Test status
Simulation time 112416613233 ps
CPU time 367.38 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:17:27 PM PDT 24
Peak memory 209596 kb
Host smart-50bc4901-bb0d-4273-ac43-aeea20aed826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044816113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1044816113
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3228563005
Short name T632
Test name
Test status
Simulation time 747513724 ps
CPU time 1.94 seconds
Started Jul 25 07:11:23 PM PDT 24
Finished Jul 25 07:11:25 PM PDT 24
Peak memory 199400 kb
Host smart-3f442ca5-eb1d-4521-85dd-af6d2b39d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228563005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3228563005
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1006914936
Short name T273
Test name
Test status
Simulation time 31093642098 ps
CPU time 49.98 seconds
Started Jul 25 07:11:12 PM PDT 24
Finished Jul 25 07:12:02 PM PDT 24
Peak memory 199988 kb
Host smart-f85a38fe-813e-4d18-9a26-5df19460bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006914936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1006914936
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1405617684
Short name T428
Test name
Test status
Simulation time 39978984 ps
CPU time 0.55 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 195628 kb
Host smart-84dd180c-397b-4044-a272-5435398eb868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405617684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1405617684
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2991145640
Short name T130
Test name
Test status
Simulation time 61425826254 ps
CPU time 45.29 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:10:18 PM PDT 24
Peak memory 200244 kb
Host smart-dc050483-d99f-4c7b-be98-00b49b4d251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991145640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2991145640
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3031390797
Short name T55
Test name
Test status
Simulation time 98838321110 ps
CPU time 28.4 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:10:08 PM PDT 24
Peak memory 200192 kb
Host smart-b0d4b7f8-d0aa-42a4-a6d1-1210505efbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031390797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3031390797
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.801873075
Short name T825
Test name
Test status
Simulation time 172009120429 ps
CPU time 106.47 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200168 kb
Host smart-e0700355-a44f-4fd8-95d8-1fb8b22eb020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801873075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.801873075
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2993414887
Short name T1138
Test name
Test status
Simulation time 55624860028 ps
CPU time 37.75 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:10:13 PM PDT 24
Peak memory 200212 kb
Host smart-8a85d946-8d5b-4590-8de5-af3c210b62c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993414887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2993414887
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2962109963
Short name T271
Test name
Test status
Simulation time 146676666914 ps
CPU time 383.37 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200208 kb
Host smart-7cb4d4c2-0853-460a-895e-b75697822106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962109963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2962109963
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2109858868
Short name T582
Test name
Test status
Simulation time 10346062035 ps
CPU time 20.73 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 199516 kb
Host smart-52317654-5238-4e34-af48-92d493dac0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109858868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2109858868
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2197233107
Short name T427
Test name
Test status
Simulation time 130547390968 ps
CPU time 49.6 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:10:27 PM PDT 24
Peak memory 199316 kb
Host smart-45d052c5-b6f9-4121-9059-cca566836208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197233107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2197233107
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1258252887
Short name T118
Test name
Test status
Simulation time 23357645416 ps
CPU time 677.75 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:20:55 PM PDT 24
Peak memory 200260 kb
Host smart-f998b63d-4e9d-4f3f-89e5-c07a66536cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258252887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1258252887
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.895630951
Short name T398
Test name
Test status
Simulation time 7549172857 ps
CPU time 33.41 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:10:12 PM PDT 24
Peak memory 198384 kb
Host smart-761abfa4-30b4-47fe-a1be-520c0dcc0822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895630951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.895630951
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.476827163
Short name T981
Test name
Test status
Simulation time 41204473118 ps
CPU time 58.47 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:10:34 PM PDT 24
Peak memory 200272 kb
Host smart-f78afa41-46ad-4e7f-8f34-67b5589d813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476827163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.476827163
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3448737019
Short name T913
Test name
Test status
Simulation time 3009201029 ps
CPU time 1.88 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 197116 kb
Host smart-51cb59a2-a73d-4a10-b7bb-4134ee6ba294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448737019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3448737019
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2186042703
Short name T100
Test name
Test status
Simulation time 119695746 ps
CPU time 0.79 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:09:36 PM PDT 24
Peak memory 218448 kb
Host smart-d91a853b-c8f0-4460-bfbc-0b700e074f76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186042703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2186042703
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3648095133
Short name T792
Test name
Test status
Simulation time 296643748 ps
CPU time 1.08 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:09:43 PM PDT 24
Peak memory 198664 kb
Host smart-cd753e5b-9026-464b-bdc7-e4aaf492b5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648095133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3648095133
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.161938364
Short name T415
Test name
Test status
Simulation time 96977849313 ps
CPU time 1684.51 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:37:46 PM PDT 24
Peak memory 200172 kb
Host smart-5514b3a5-d60f-4d24-839c-8b8935361e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161938364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.161938364
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1364257242
Short name T74
Test name
Test status
Simulation time 21640752196 ps
CPU time 168.07 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:12:28 PM PDT 24
Peak memory 208496 kb
Host smart-2e09072e-0576-4672-ba64-242940ece1d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364257242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1364257242
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.578189525
Short name T578
Test name
Test status
Simulation time 2621669493 ps
CPU time 1.41 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:09:42 PM PDT 24
Peak memory 200216 kb
Host smart-70fb9a87-f013-4d88-a6ac-84ff0e0d4c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578189525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.578189525
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2947747805
Short name T291
Test name
Test status
Simulation time 4712157348 ps
CPU time 7.73 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 197040 kb
Host smart-84c2fc30-b2a8-4e85-b367-ed6efe610cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947747805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2947747805
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1348834049
Short name T533
Test name
Test status
Simulation time 10760577 ps
CPU time 0.54 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:11:19 PM PDT 24
Peak memory 195056 kb
Host smart-e09c1bdf-bd82-4db9-9e1f-fb4dd98b2041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348834049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1348834049
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.4119749577
Short name T844
Test name
Test status
Simulation time 20594870270 ps
CPU time 34.17 seconds
Started Jul 25 07:11:23 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 200176 kb
Host smart-649db608-3f43-4064-bfb8-f205e543fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119749577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4119749577
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1456834670
Short name T700
Test name
Test status
Simulation time 26858727639 ps
CPU time 20.88 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200192 kb
Host smart-a34c308f-d741-4658-8b49-d716beb32e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456834670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1456834670
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.427882658
Short name T217
Test name
Test status
Simulation time 48180456799 ps
CPU time 43.96 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:12:06 PM PDT 24
Peak memory 200184 kb
Host smart-05472e82-64aa-44d8-9fe6-0dad61bf2b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427882658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.427882658
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1760172353
Short name T656
Test name
Test status
Simulation time 5590072753 ps
CPU time 4.14 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 200152 kb
Host smart-77a8aecb-edce-4ab6-afaa-069032e98c88
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760172353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1760172353
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.289188272
Short name T431
Test name
Test status
Simulation time 48871625585 ps
CPU time 403.91 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:18:03 PM PDT 24
Peak memory 200196 kb
Host smart-c80c3b2e-06a1-4b71-9c35-8270fd17d116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289188272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.289188272
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.584321919
Short name T344
Test name
Test status
Simulation time 1387651245 ps
CPU time 1.52 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:22 PM PDT 24
Peak memory 199988 kb
Host smart-61955cf3-fe5e-49ce-b7b3-86d2f60dc5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584321919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.584321919
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1178571208
Short name T331
Test name
Test status
Simulation time 29270934926 ps
CPU time 45.86 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:12:09 PM PDT 24
Peak memory 199420 kb
Host smart-f5a5916e-c934-4ed5-b56b-1415cd47bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178571208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1178571208
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.340185177
Short name T49
Test name
Test status
Simulation time 21797043002 ps
CPU time 260.52 seconds
Started Jul 25 07:11:21 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 200220 kb
Host smart-4707df80-78db-475c-8ba0-a5f2627a680c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340185177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.340185177
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.938131331
Short name T484
Test name
Test status
Simulation time 6881838984 ps
CPU time 14.71 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:35 PM PDT 24
Peak memory 198912 kb
Host smart-816086b4-c393-4ea2-8854-98b39180ab18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938131331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.938131331
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2954058819
Short name T637
Test name
Test status
Simulation time 19971061466 ps
CPU time 29.07 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:11:51 PM PDT 24
Peak memory 200148 kb
Host smart-40dac5df-dba0-4b64-90e9-b54e9a18ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954058819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2954058819
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.521872675
Short name T104
Test name
Test status
Simulation time 4134295997 ps
CPU time 3.94 seconds
Started Jul 25 07:11:21 PM PDT 24
Finished Jul 25 07:11:25 PM PDT 24
Peak memory 196100 kb
Host smart-0c07c8d3-656f-454a-a6bd-f57473fb97a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521872675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.521872675
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.984198631
Short name T924
Test name
Test status
Simulation time 648547796 ps
CPU time 2.51 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 199060 kb
Host smart-68727ef6-98a3-4b86-bd18-8e7f96834556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984198631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.984198631
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1868617345
Short name T783
Test name
Test status
Simulation time 261683035640 ps
CPU time 299.49 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:16:21 PM PDT 24
Peak memory 200188 kb
Host smart-ed359b5d-ee4f-4f9f-aa59-61562051f98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868617345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1868617345
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3264595189
Short name T312
Test name
Test status
Simulation time 268926421098 ps
CPU time 454.67 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:18:53 PM PDT 24
Peak memory 216892 kb
Host smart-81e3b283-2edd-4f11-919c-e0cec0d69e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264595189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3264595189
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3363758608
Short name T679
Test name
Test status
Simulation time 605004336 ps
CPU time 2.01 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:22 PM PDT 24
Peak memory 198856 kb
Host smart-4afea599-62aa-4aa1-9f5b-a0807785ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363758608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3363758608
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1627150275
Short name T470
Test name
Test status
Simulation time 85205760253 ps
CPU time 34.81 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:11:53 PM PDT 24
Peak memory 200164 kb
Host smart-4047b314-693e-4e0e-86f3-f3bb8f77f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627150275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1627150275
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.785285090
Short name T745
Test name
Test status
Simulation time 14891878 ps
CPU time 0.58 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:11:31 PM PDT 24
Peak memory 195680 kb
Host smart-ef7587de-12e9-4217-a947-29b7c294040b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785285090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.785285090
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3449953216
Short name T801
Test name
Test status
Simulation time 10490809370 ps
CPU time 20.31 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:40 PM PDT 24
Peak memory 200232 kb
Host smart-f2b6497e-c7da-4c02-8a8a-d14e3c1cdedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449953216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3449953216
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1288407845
Short name T639
Test name
Test status
Simulation time 184494213701 ps
CPU time 153.73 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 200184 kb
Host smart-25fec7c9-e216-4256-b112-45a53fae6c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288407845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1288407845
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1983973370
Short name T932
Test name
Test status
Simulation time 121256363246 ps
CPU time 52.47 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:12:11 PM PDT 24
Peak memory 200244 kb
Host smart-2d361896-08b2-4781-bdc0-f2c9140f6997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983973370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1983973370
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.822448851
Short name T433
Test name
Test status
Simulation time 252118554 ps
CPU time 0.98 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:21 PM PDT 24
Peak memory 195900 kb
Host smart-b2665af5-3213-4961-be67-923c5f2e8eb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822448851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.822448851
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1258141190
Short name T529
Test name
Test status
Simulation time 143686241992 ps
CPU time 715.79 seconds
Started Jul 25 07:11:22 PM PDT 24
Finished Jul 25 07:23:18 PM PDT 24
Peak memory 200192 kb
Host smart-4268324e-d479-4003-9bac-308c2cb0f2cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258141190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1258141190
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2636690839
Short name T1033
Test name
Test status
Simulation time 1811077430 ps
CPU time 4.03 seconds
Started Jul 25 07:11:21 PM PDT 24
Finished Jul 25 07:11:25 PM PDT 24
Peak memory 199036 kb
Host smart-f0ca5d51-916a-4f65-813e-dd75bc529311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636690839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2636690839
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3181282040
Short name T998
Test name
Test status
Simulation time 79866904256 ps
CPU time 119.74 seconds
Started Jul 25 07:11:18 PM PDT 24
Finished Jul 25 07:13:18 PM PDT 24
Peak memory 200392 kb
Host smart-9e8c915f-5424-4d72-a888-aa9d6a19c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181282040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3181282040
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4045181124
Short name T664
Test name
Test status
Simulation time 4444101995 ps
CPU time 8.31 seconds
Started Jul 25 07:11:19 PM PDT 24
Finished Jul 25 07:11:27 PM PDT 24
Peak memory 199532 kb
Host smart-56ce36f4-662f-4a9b-ab77-18ce2d497310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045181124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4045181124
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1963276011
Short name T1131
Test name
Test status
Simulation time 70693496428 ps
CPU time 58.48 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:12:18 PM PDT 24
Peak memory 200216 kb
Host smart-4eae0940-81e2-4ed4-aa46-cc85c0c87d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963276011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1963276011
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.957039900
Short name T26
Test name
Test status
Simulation time 2754926786 ps
CPU time 4.87 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:26 PM PDT 24
Peak memory 196744 kb
Host smart-03ba39e5-0336-4471-a12b-e9f4fd483bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957039900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.957039900
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3871626309
Short name T922
Test name
Test status
Simulation time 738709304 ps
CPU time 1.65 seconds
Started Jul 25 07:11:21 PM PDT 24
Finished Jul 25 07:11:23 PM PDT 24
Peak memory 198628 kb
Host smart-a7835957-a7a9-46f2-9ac6-cd76f1b7f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871626309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3871626309
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2209352789
Short name T1054
Test name
Test status
Simulation time 317874103034 ps
CPU time 144.62 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 200128 kb
Host smart-8a6423de-d6a8-4441-a558-eb8d2d48b685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209352789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2209352789
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.818565850
Short name T114
Test name
Test status
Simulation time 100757165781 ps
CPU time 139.19 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:13:40 PM PDT 24
Peak memory 216900 kb
Host smart-1c4cafff-6163-4ff5-9fa1-1a2c5417ab9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818565850 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.818565850
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2537005419
Short name T699
Test name
Test status
Simulation time 9196066927 ps
CPU time 14.37 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:34 PM PDT 24
Peak memory 200216 kb
Host smart-2c8796cf-0b21-495f-ad0e-85d5f080beed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537005419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2537005419
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3311475021
Short name T871
Test name
Test status
Simulation time 172006865173 ps
CPU time 21.41 seconds
Started Jul 25 07:11:20 PM PDT 24
Finished Jul 25 07:11:42 PM PDT 24
Peak memory 200256 kb
Host smart-e45132a3-0957-465a-8afe-f8165ddfffbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311475021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3311475021
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1941132312
Short name T984
Test name
Test status
Simulation time 95586695 ps
CPU time 0.56 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:30 PM PDT 24
Peak memory 195884 kb
Host smart-f6901644-18f5-4629-870f-35e6a63b121d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941132312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1941132312
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3925042524
Short name T439
Test name
Test status
Simulation time 1473243756 ps
CPU time 1.81 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:33 PM PDT 24
Peak memory 199172 kb
Host smart-0e3a4010-9c92-4cc3-9ff9-c8c41dad1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925042524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3925042524
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3828126196
Short name T446
Test name
Test status
Simulation time 78057995373 ps
CPU time 95.04 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:13:06 PM PDT 24
Peak memory 200240 kb
Host smart-b2700929-2c3d-4236-9cd3-afe380d62ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828126196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3828126196
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.908758284
Short name T192
Test name
Test status
Simulation time 156591008586 ps
CPU time 64.92 seconds
Started Jul 25 07:11:34 PM PDT 24
Finished Jul 25 07:12:39 PM PDT 24
Peak memory 200132 kb
Host smart-89c9fa0f-7cb1-4b7f-a914-04fc39d7c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908758284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.908758284
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3392762930
Short name T319
Test name
Test status
Simulation time 190678108907 ps
CPU time 48.6 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:12:18 PM PDT 24
Peak memory 198300 kb
Host smart-7fe8a99f-5da3-4140-b6ab-75658e0ef6a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392762930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3392762930
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3369729155
Short name T759
Test name
Test status
Simulation time 166852286491 ps
CPU time 1106.82 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:29:55 PM PDT 24
Peak memory 200244 kb
Host smart-abec065a-97d4-4d4b-8f32-e699ae5ed5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369729155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3369729155
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.722239359
Short name T652
Test name
Test status
Simulation time 3835452398 ps
CPU time 6.38 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:11:35 PM PDT 24
Peak memory 199100 kb
Host smart-3cba1af8-5644-407d-b976-4bdeddb9a757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722239359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.722239359
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.133520605
Short name T1134
Test name
Test status
Simulation time 91884491031 ps
CPU time 53.83 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:12:22 PM PDT 24
Peak memory 208584 kb
Host smart-6b80269e-64b6-4dcd-9cb0-4746029c7ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133520605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.133520605
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1386877819
Short name T521
Test name
Test status
Simulation time 9792905718 ps
CPU time 297.4 seconds
Started Jul 25 07:11:27 PM PDT 24
Finished Jul 25 07:16:24 PM PDT 24
Peak memory 200188 kb
Host smart-879737eb-c343-4eef-9a40-79ae6be84d8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386877819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1386877819
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.365024763
Short name T363
Test name
Test status
Simulation time 3811473096 ps
CPU time 30.87 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 199204 kb
Host smart-289b45ac-b0a7-4d4a-b3a0-49a024316623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365024763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.365024763
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3263568781
Short name T901
Test name
Test status
Simulation time 116812180870 ps
CPU time 53.51 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:12:23 PM PDT 24
Peak memory 199864 kb
Host smart-6ef137f9-b9e9-4267-8b3c-21f48286c396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263568781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3263568781
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.789272851
Short name T289
Test name
Test status
Simulation time 42837388225 ps
CPU time 24.88 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:56 PM PDT 24
Peak memory 196764 kb
Host smart-8ad04a05-0fb2-46b6-9165-4a27c67ec2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789272851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.789272851
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1977094238
Short name T103
Test name
Test status
Simulation time 954960480 ps
CPU time 2.26 seconds
Started Jul 25 07:11:34 PM PDT 24
Finished Jul 25 07:11:37 PM PDT 24
Peak memory 199032 kb
Host smart-79027ce7-48b6-437b-b2a0-d832e5175c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977094238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1977094238
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2447404874
Short name T252
Test name
Test status
Simulation time 158302767435 ps
CPU time 392.94 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:18:04 PM PDT 24
Peak memory 200240 kb
Host smart-29c2ea5d-ca6e-403d-918d-54933091fe2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447404874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2447404874
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3133729813
Short name T1036
Test name
Test status
Simulation time 71850558598 ps
CPU time 711.43 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:23:20 PM PDT 24
Peak memory 225144 kb
Host smart-e59297e3-5488-46f8-8590-c18d9327e009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133729813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3133729813
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.364949268
Short name T1104
Test name
Test status
Simulation time 2141265456 ps
CPU time 2.94 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:32 PM PDT 24
Peak memory 199992 kb
Host smart-e192ce42-1245-4f07-983b-303bcc83e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364949268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.364949268
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2952540923
Short name T1112
Test name
Test status
Simulation time 51380321855 ps
CPU time 19.65 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:51 PM PDT 24
Peak memory 200164 kb
Host smart-aeaa3513-659a-4cc0-b67a-9a90b80f3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952540923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2952540923
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1690891421
Short name T525
Test name
Test status
Simulation time 11052043 ps
CPU time 0.58 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:32 PM PDT 24
Peak memory 195616 kb
Host smart-7b35d305-42f0-4fc7-b932-cd631732b58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690891421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1690891421
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2433412301
Short name T943
Test name
Test status
Simulation time 118434900375 ps
CPU time 44 seconds
Started Jul 25 07:11:32 PM PDT 24
Finished Jul 25 07:12:16 PM PDT 24
Peak memory 200188 kb
Host smart-0e52ec41-2733-4a45-8c7a-1cc59f38b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433412301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2433412301
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3443547116
Short name T1174
Test name
Test status
Simulation time 29035209421 ps
CPU time 10.65 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:42 PM PDT 24
Peak memory 200056 kb
Host smart-86085961-8ac3-4735-a048-0f18323c990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443547116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3443547116
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2253857425
Short name T403
Test name
Test status
Simulation time 24068007412 ps
CPU time 10.89 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 198024 kb
Host smart-94e92604-6de8-4255-b5b0-13262b515733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253857425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2253857425
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3456307738
Short name T545
Test name
Test status
Simulation time 28967948850 ps
CPU time 30.01 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:59 PM PDT 24
Peak memory 200192 kb
Host smart-80fc4697-1f5f-4c39-a17e-dddc9bb74cb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456307738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3456307738
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.250053858
Short name T108
Test name
Test status
Simulation time 135547736205 ps
CPU time 435.51 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:18:47 PM PDT 24
Peak memory 200100 kb
Host smart-88620666-978a-4b1f-9eb2-c0ab04efe1a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250053858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.250053858
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3605089102
Short name T353
Test name
Test status
Simulation time 929106788 ps
CPU time 0.98 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:30 PM PDT 24
Peak memory 195720 kb
Host smart-03bc26a3-11d6-4200-9674-9b883faf8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605089102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3605089102
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2558264839
Short name T392
Test name
Test status
Simulation time 120350592771 ps
CPU time 103.69 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:13:15 PM PDT 24
Peak memory 208568 kb
Host smart-6f87f14d-f2f3-484d-aae3-a614f6a539cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558264839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2558264839
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1685031797
Short name T942
Test name
Test status
Simulation time 17548667252 ps
CPU time 1058.22 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:29:08 PM PDT 24
Peak memory 200188 kb
Host smart-a0caf931-c75c-43d5-8ffc-3bcdcd287561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685031797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1685031797
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2098410211
Short name T474
Test name
Test status
Simulation time 2767907796 ps
CPU time 22.11 seconds
Started Jul 25 07:11:35 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 199456 kb
Host smart-09cf2cf7-caee-46f7-a4bf-c2c75a0dcfcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098410211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2098410211
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1522400196
Short name T600
Test name
Test status
Simulation time 88696270753 ps
CPU time 31.48 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:12:03 PM PDT 24
Peak memory 200272 kb
Host smart-e3596479-a162-4e45-948d-da7417c777d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522400196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1522400196
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4021178237
Short name T809
Test name
Test status
Simulation time 2346531019 ps
CPU time 4.04 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:35 PM PDT 24
Peak memory 196764 kb
Host smart-ff574fdc-1062-40b2-bc73-669e57195223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021178237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4021178237
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2436238112
Short name T302
Test name
Test status
Simulation time 6181493013 ps
CPU time 17.94 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 199944 kb
Host smart-a6976b98-34a0-4a5e-aa8b-20eccdc16246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436238112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2436238112
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2008704519
Short name T315
Test name
Test status
Simulation time 31590146889 ps
CPU time 743.85 seconds
Started Jul 25 07:11:33 PM PDT 24
Finished Jul 25 07:23:57 PM PDT 24
Peak memory 216764 kb
Host smart-270d86f9-e492-46a9-8632-29e8a93000d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008704519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2008704519
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.606260368
Short name T260
Test name
Test status
Simulation time 6510844099 ps
CPU time 19.64 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 200012 kb
Host smart-4a9e130c-49bb-473b-ba5c-b81d7cba86d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606260368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.606260368
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3036842671
Short name T1078
Test name
Test status
Simulation time 40121372522 ps
CPU time 14.83 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 200216 kb
Host smart-218c06d1-6877-4889-939c-5435271ea00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036842671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3036842671
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.902467483
Short name T758
Test name
Test status
Simulation time 49790567 ps
CPU time 0.55 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:32 PM PDT 24
Peak memory 195284 kb
Host smart-24f10d09-1934-422c-9e66-9cdcae730d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902467483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.902467483
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3754123579
Short name T53
Test name
Test status
Simulation time 61801736768 ps
CPU time 46.22 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:12:15 PM PDT 24
Peak memory 200180 kb
Host smart-de4bd216-fc47-4136-a52a-73f62bc0cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754123579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3754123579
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2687644821
Short name T177
Test name
Test status
Simulation time 48354444366 ps
CPU time 24.03 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:53 PM PDT 24
Peak memory 200208 kb
Host smart-ff3a4b1a-e3c1-4d20-80c3-e53f6d74bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687644821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2687644821
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1145274044
Short name T510
Test name
Test status
Simulation time 38979784778 ps
CPU time 17.66 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 200240 kb
Host smart-dc1817cc-f593-4456-921f-38d7b6246df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145274044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1145274044
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1419199461
Short name T1003
Test name
Test status
Simulation time 68060620544 ps
CPU time 94 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:13:05 PM PDT 24
Peak memory 200244 kb
Host smart-6167aa86-e17b-47fd-9a93-bc50ab148915
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419199461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1419199461
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4270890140
Short name T727
Test name
Test status
Simulation time 105502103740 ps
CPU time 628.35 seconds
Started Jul 25 07:11:33 PM PDT 24
Finished Jul 25 07:22:02 PM PDT 24
Peak memory 200256 kb
Host smart-52ca8c72-4f07-4397-86bb-e22edc84fa90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270890140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4270890140
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.158104873
Short name T806
Test name
Test status
Simulation time 4156720056 ps
CPU time 4.55 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 199748 kb
Host smart-ceb000d7-eebd-4dfc-b031-b753067fa097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158104873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.158104873
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4092602297
Short name T623
Test name
Test status
Simulation time 122155090261 ps
CPU time 29.35 seconds
Started Jul 25 07:11:36 PM PDT 24
Finished Jul 25 07:12:05 PM PDT 24
Peak memory 198860 kb
Host smart-fc4ffe67-6a65-440f-a4f0-15cdb994fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092602297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4092602297
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2868263234
Short name T267
Test name
Test status
Simulation time 16423548846 ps
CPU time 869.52 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:25:59 PM PDT 24
Peak memory 200192 kb
Host smart-3a060e29-8f10-4674-96a9-ed751d7f9995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868263234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2868263234
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.626190891
Short name T763
Test name
Test status
Simulation time 5583902554 ps
CPU time 13.42 seconds
Started Jul 25 07:11:29 PM PDT 24
Finished Jul 25 07:11:43 PM PDT 24
Peak memory 199696 kb
Host smart-bb2a8d7f-cd3f-4468-9c2a-1c7396d58b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626190891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.626190891
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2322228331
Short name T296
Test name
Test status
Simulation time 21828028217 ps
CPU time 14.81 seconds
Started Jul 25 07:11:32 PM PDT 24
Finished Jul 25 07:11:47 PM PDT 24
Peak memory 200212 kb
Host smart-962d4982-b221-41f5-b1d3-e286fd6de195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322228331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2322228331
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1561527962
Short name T318
Test name
Test status
Simulation time 3215981316 ps
CPU time 1.92 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:11:32 PM PDT 24
Peak memory 196744 kb
Host smart-502ba986-7c87-4d4e-82c8-c034e92abb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561527962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1561527962
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1823078059
Short name T535
Test name
Test status
Simulation time 463646135 ps
CPU time 1.66 seconds
Started Jul 25 07:11:35 PM PDT 24
Finished Jul 25 07:11:36 PM PDT 24
Peak memory 198468 kb
Host smart-4fcf2533-6a95-4cb4-b55d-189f5dd10cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823078059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1823078059
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1961153525
Short name T539
Test name
Test status
Simulation time 524202098054 ps
CPU time 690.52 seconds
Started Jul 25 07:11:27 PM PDT 24
Finished Jul 25 07:22:58 PM PDT 24
Peak memory 208640 kb
Host smart-b52f2503-e5a5-4d5f-9515-5a6bc3a2c9e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961153525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1961153525
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4187711518
Short name T1045
Test name
Test status
Simulation time 106630786216 ps
CPU time 1648.49 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:39:10 PM PDT 24
Peak memory 233152 kb
Host smart-715acd2f-805b-437e-bbb3-6bdf100f1959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187711518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4187711518
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.290753932
Short name T1055
Test name
Test status
Simulation time 7073591771 ps
CPU time 8.6 seconds
Started Jul 25 07:11:32 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200116 kb
Host smart-d08573c6-3c71-4942-a3cb-25da39ecc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290753932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.290753932
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1172660932
Short name T505
Test name
Test status
Simulation time 45346191996 ps
CPU time 55.23 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:12:26 PM PDT 24
Peak memory 200240 kb
Host smart-d69bb8c6-d687-47c3-a4e4-9b4a2b42bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172660932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1172660932
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4176977361
Short name T362
Test name
Test status
Simulation time 24225420 ps
CPU time 0.54 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:11:37 PM PDT 24
Peak memory 195852 kb
Host smart-f5506f1a-ed2a-452c-88fe-5ab9244099cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176977361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4176977361
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1573702461
Short name T297
Test name
Test status
Simulation time 152836532736 ps
CPU time 268.9 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200244 kb
Host smart-5435dfdc-6c09-4f72-9765-198df447b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573702461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1573702461
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2893081943
Short name T555
Test name
Test status
Simulation time 173110176747 ps
CPU time 263.93 seconds
Started Jul 25 07:11:35 PM PDT 24
Finished Jul 25 07:15:59 PM PDT 24
Peak memory 200208 kb
Host smart-ee5d6a00-d8f5-4ef2-84c1-e4e46efaaf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893081943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2893081943
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.260350155
Short name T223
Test name
Test status
Simulation time 38016282893 ps
CPU time 13.87 seconds
Started Jul 25 07:11:27 PM PDT 24
Finished Jul 25 07:11:41 PM PDT 24
Peak memory 200208 kb
Host smart-3092637e-9cbd-439c-9e1a-6adcfa2c42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260350155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.260350155
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.647095968
Short name T410
Test name
Test status
Simulation time 34861607975 ps
CPU time 67.64 seconds
Started Jul 25 07:11:30 PM PDT 24
Finished Jul 25 07:12:38 PM PDT 24
Peak memory 200244 kb
Host smart-16fefc59-5b76-4bf7-a10d-16c5dae72df6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647095968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.647095968
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.233552659
Short name T458
Test name
Test status
Simulation time 149251920631 ps
CPU time 462.12 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:19:20 PM PDT 24
Peak memory 200276 kb
Host smart-fcb8fafc-dd4a-4143-803c-50e9fd193550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233552659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.233552659
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3137252822
Short name T573
Test name
Test status
Simulation time 3843494174 ps
CPU time 9.35 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:11:48 PM PDT 24
Peak memory 198732 kb
Host smart-00c5a6c3-8d40-44fb-a47f-7b9737fd7c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137252822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3137252822
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1461335873
Short name T969
Test name
Test status
Simulation time 7906992555 ps
CPU time 12.34 seconds
Started Jul 25 07:11:35 PM PDT 24
Finished Jul 25 07:11:48 PM PDT 24
Peak memory 200176 kb
Host smart-0d65a12b-91d7-4abb-81ec-87239968cfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461335873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1461335873
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3770081310
Short name T1007
Test name
Test status
Simulation time 31220263827 ps
CPU time 1517.62 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:36:56 PM PDT 24
Peak memory 200276 kb
Host smart-22674981-123d-41f5-80e9-973fea30432d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770081310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3770081310
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3856970159
Short name T374
Test name
Test status
Simulation time 2856676310 ps
CPU time 5.42 seconds
Started Jul 25 07:11:31 PM PDT 24
Finished Jul 25 07:11:37 PM PDT 24
Peak memory 198268 kb
Host smart-3cd6f753-9707-4992-bb85-d8fcd752f876
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856970159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3856970159
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.988810900
Short name T624
Test name
Test status
Simulation time 100302147756 ps
CPU time 81.48 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:13:03 PM PDT 24
Peak memory 200260 kb
Host smart-c3e0499b-8b75-4be8-b960-173df8f6d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988810900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.988810900
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3728253305
Short name T380
Test name
Test status
Simulation time 2667540377 ps
CPU time 1.6 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:11:43 PM PDT 24
Peak memory 196792 kb
Host smart-39993928-ecda-4cf1-ad7f-b8f856cd1646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728253305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3728253305
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1363717195
Short name T383
Test name
Test status
Simulation time 268190987 ps
CPU time 1.23 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:11:43 PM PDT 24
Peak memory 199440 kb
Host smart-b5c274fc-58ce-4131-bc43-2e59c52f0e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363717195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1363717195
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.317315839
Short name T175
Test name
Test status
Simulation time 1795451723311 ps
CPU time 1031.5 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:28:49 PM PDT 24
Peak memory 227088 kb
Host smart-8e754823-6335-4f60-aab6-c528b96b26fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317315839 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.317315839
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1268724828
Short name T7
Test name
Test status
Simulation time 849529854 ps
CPU time 2.89 seconds
Started Jul 25 07:11:43 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 198708 kb
Host smart-214f809a-aaf6-4f37-b71c-77e86aa632d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268724828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1268724828
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2708055580
Short name T819
Test name
Test status
Simulation time 82860698508 ps
CPU time 90.21 seconds
Started Jul 25 07:11:28 PM PDT 24
Finished Jul 25 07:12:58 PM PDT 24
Peak memory 200136 kb
Host smart-1d4b86ca-e211-4ccb-ae9f-3039fcbe54f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708055580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2708055580
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.480498811
Short name T1101
Test name
Test status
Simulation time 36697235 ps
CPU time 0.55 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:11:38 PM PDT 24
Peak memory 195620 kb
Host smart-c26134fc-2f41-4d3c-826a-77d8e2facce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480498811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.480498811
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2258350904
Short name T1177
Test name
Test status
Simulation time 23106961118 ps
CPU time 40.39 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:12:21 PM PDT 24
Peak memory 200256 kb
Host smart-2e652d92-1ec0-4da5-be1e-8dd9b260990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258350904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2258350904
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1496548392
Short name T156
Test name
Test status
Simulation time 138466638299 ps
CPU time 114.48 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:13:31 PM PDT 24
Peak memory 200180 kb
Host smart-cd024927-fae3-463d-a4ff-49648fcbde07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496548392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1496548392
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3908209712
Short name T791
Test name
Test status
Simulation time 56880173857 ps
CPU time 36.25 seconds
Started Jul 25 07:11:36 PM PDT 24
Finished Jul 25 07:12:12 PM PDT 24
Peak memory 200148 kb
Host smart-df546a6a-dfc9-4218-93d3-ac0cc595683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908209712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3908209712
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3090971746
Short name T1012
Test name
Test status
Simulation time 203388283696 ps
CPU time 62.47 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:12:40 PM PDT 24
Peak memory 200240 kb
Host smart-29818306-fd9c-4b73-9f9b-d9b4c20e87c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090971746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3090971746
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4002182568
Short name T488
Test name
Test status
Simulation time 81128639047 ps
CPU time 567.01 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:21:04 PM PDT 24
Peak memory 200244 kb
Host smart-1b43b587-c491-46b7-8399-7facc349dd4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002182568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4002182568
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3754899068
Short name T375
Test name
Test status
Simulation time 11372873213 ps
CPU time 5.49 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 200148 kb
Host smart-c0077fb3-9065-4fe2-8236-4bb3611e0964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754899068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3754899068
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.994191434
Short name T461
Test name
Test status
Simulation time 79091283595 ps
CPU time 35.67 seconds
Started Jul 25 07:11:40 PM PDT 24
Finished Jul 25 07:12:16 PM PDT 24
Peak memory 200308 kb
Host smart-5abe3d05-078e-4257-bfba-ca56821456a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994191434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.994191434
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2815548102
Short name T1087
Test name
Test status
Simulation time 23735809672 ps
CPU time 1268.76 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:32:46 PM PDT 24
Peak memory 200252 kb
Host smart-9f53565d-44c1-4abd-a289-5c4b0d090622
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815548102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2815548102
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.4168702364
Short name T522
Test name
Test status
Simulation time 3252701808 ps
CPU time 11.44 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:11:49 PM PDT 24
Peak memory 198712 kb
Host smart-dd375de0-efb4-444e-8133-20dfd1342a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168702364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4168702364
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2323442519
Short name T567
Test name
Test status
Simulation time 85199127257 ps
CPU time 92.01 seconds
Started Jul 25 07:11:40 PM PDT 24
Finished Jul 25 07:13:12 PM PDT 24
Peak memory 200156 kb
Host smart-37e373d5-2413-4676-a236-096f972a61c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323442519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2323442519
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1317455947
Short name T849
Test name
Test status
Simulation time 46441640516 ps
CPU time 75.41 seconds
Started Jul 25 07:11:36 PM PDT 24
Finished Jul 25 07:12:52 PM PDT 24
Peak memory 196752 kb
Host smart-1c6476a2-4441-4bc6-8f63-04858d673601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317455947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1317455947
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4103972046
Short name T885
Test name
Test status
Simulation time 338906755 ps
CPU time 1.14 seconds
Started Jul 25 07:11:39 PM PDT 24
Finished Jul 25 07:11:40 PM PDT 24
Peak memory 199320 kb
Host smart-216b0652-4054-4113-ace5-4fcad3a24250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103972046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4103972046
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1966171284
Short name T1122
Test name
Test status
Simulation time 469004056120 ps
CPU time 816.44 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:25:15 PM PDT 24
Peak memory 200140 kb
Host smart-b3159665-2b23-4f3e-a4b5-9bcaf909608d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966171284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1966171284
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2935644140
Short name T452
Test name
Test status
Simulation time 315082337 ps
CPU time 1.29 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:11:38 PM PDT 24
Peak memory 197412 kb
Host smart-7c85f83a-4783-4ad1-b8bc-15dadfbe4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935644140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2935644140
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3728088197
Short name T259
Test name
Test status
Simulation time 75776197372 ps
CPU time 31.65 seconds
Started Jul 25 07:11:40 PM PDT 24
Finished Jul 25 07:12:12 PM PDT 24
Peak memory 200196 kb
Host smart-7563ad7b-971e-4db3-ab51-e8f60a9f6b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728088197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3728088197
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1438251418
Short name T870
Test name
Test status
Simulation time 29785112 ps
CPU time 0.57 seconds
Started Jul 25 07:11:49 PM PDT 24
Finished Jul 25 07:11:50 PM PDT 24
Peak memory 195608 kb
Host smart-7939bba8-3688-48af-bf97-fc8b12691924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438251418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1438251418
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2735270091
Short name T1168
Test name
Test status
Simulation time 43966081860 ps
CPU time 18.62 seconds
Started Jul 25 07:11:39 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 200172 kb
Host smart-54070585-7bfe-4d1d-9c3d-59d5acaee3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735270091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2735270091
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2048286906
Short name T445
Test name
Test status
Simulation time 152013629931 ps
CPU time 63.92 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:12:41 PM PDT 24
Peak memory 199756 kb
Host smart-9a60669d-c446-4d3b-9aa4-331535b6dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048286906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2048286906
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2549582954
Short name T817
Test name
Test status
Simulation time 111315936355 ps
CPU time 24.18 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 199916 kb
Host smart-80e2180b-e86c-4d71-8e2d-48fe5477b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549582954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2549582954
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1204728241
Short name T102
Test name
Test status
Simulation time 17756546770 ps
CPU time 16.36 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 200172 kb
Host smart-875c4a1e-d865-4027-b253-2f2b2c740919
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204728241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1204728241
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1083951195
Short name T1097
Test name
Test status
Simulation time 154977725247 ps
CPU time 401.6 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:18:28 PM PDT 24
Peak memory 200180 kb
Host smart-22fe5f74-4868-4666-b77d-ac19937f8a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083951195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1083951195
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3298755825
Short name T739
Test name
Test status
Simulation time 6462755771 ps
CPU time 13.39 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:11:59 PM PDT 24
Peak memory 199088 kb
Host smart-3ca1c0f8-714c-49c0-b033-102458aef108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298755825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3298755825
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3091181552
Short name T326
Test name
Test status
Simulation time 37246481967 ps
CPU time 15.45 seconds
Started Jul 25 07:11:41 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 200372 kb
Host smart-3de564a8-b8ff-4afd-b2fc-a8c287ce07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091181552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3091181552
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1673531207
Short name T478
Test name
Test status
Simulation time 18837416658 ps
CPU time 894 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:26:40 PM PDT 24
Peak memory 200180 kb
Host smart-e781c21d-fb7b-41f2-adc9-1ab0ac5d4a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673531207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1673531207
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4173967088
Short name T855
Test name
Test status
Simulation time 3300930525 ps
CPU time 25.32 seconds
Started Jul 25 07:11:40 PM PDT 24
Finished Jul 25 07:12:05 PM PDT 24
Peak memory 198404 kb
Host smart-e45037d8-3c90-40f8-8bef-1ed0a0530a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173967088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4173967088
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3351360529
Short name T692
Test name
Test status
Simulation time 21016802923 ps
CPU time 25.41 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:12:11 PM PDT 24
Peak memory 199488 kb
Host smart-3d74f4c4-b720-4b0f-9775-875201743c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351360529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3351360529
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.322949318
Short name T393
Test name
Test status
Simulation time 4304636023 ps
CPU time 2.98 seconds
Started Jul 25 07:11:36 PM PDT 24
Finished Jul 25 07:11:39 PM PDT 24
Peak memory 197112 kb
Host smart-a7c6d7f5-cf4a-40f9-b402-d6b3c1faf801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322949318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.322949318
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3178915527
Short name T785
Test name
Test status
Simulation time 471293033 ps
CPU time 1.62 seconds
Started Jul 25 07:11:38 PM PDT 24
Finished Jul 25 07:11:39 PM PDT 24
Peak memory 198972 kb
Host smart-0983737f-490a-4ce1-ab8c-326d4f8172bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178915527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3178915527
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3514085918
Short name T164
Test name
Test status
Simulation time 244645865120 ps
CPU time 361.85 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:17:47 PM PDT 24
Peak memory 200256 kb
Host smart-8a9c1324-d03f-4664-b98a-102936a8801f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514085918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3514085918
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3086624269
Short name T927
Test name
Test status
Simulation time 48351631525 ps
CPU time 750.84 seconds
Started Jul 25 07:11:47 PM PDT 24
Finished Jul 25 07:24:18 PM PDT 24
Peak memory 225096 kb
Host smart-1cf8d129-da43-4bc0-a0c6-e138c706ec78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086624269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3086624269
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3242706730
Short name T511
Test name
Test status
Simulation time 1012059927 ps
CPU time 4.1 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:11:49 PM PDT 24
Peak memory 198636 kb
Host smart-69943157-8484-4d15-b384-dbeb2b4f4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242706730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3242706730
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3762151730
Short name T995
Test name
Test status
Simulation time 150130417296 ps
CPU time 291.13 seconds
Started Jul 25 07:11:37 PM PDT 24
Finished Jul 25 07:16:28 PM PDT 24
Peak memory 200192 kb
Host smart-75c58ca9-c462-4a50-8a1b-a959b61e2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762151730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3762151730
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.181848315
Short name T968
Test name
Test status
Simulation time 32160377 ps
CPU time 0.54 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 195072 kb
Host smart-3e8c1e8f-0a68-46ce-8b5e-7fef74341981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181848315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.181848315
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2613236531
Short name T132
Test name
Test status
Simulation time 29402724341 ps
CPU time 48.11 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:12:34 PM PDT 24
Peak memory 200156 kb
Host smart-5acec040-8b27-4641-992e-19456b4b1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613236531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2613236531
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.890555733
Short name T1000
Test name
Test status
Simulation time 53618901368 ps
CPU time 82.22 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:13:07 PM PDT 24
Peak memory 200160 kb
Host smart-cfc20b84-bf2b-4cc0-856e-401f8525586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890555733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.890555733
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3544215
Short name T947
Test name
Test status
Simulation time 13374411751 ps
CPU time 26.15 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:12:20 PM PDT 24
Peak memory 200220 kb
Host smart-801d8daf-649f-405b-b16c-973eea43282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3544215
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3068580154
Short name T682
Test name
Test status
Simulation time 53931485906 ps
CPU time 43.73 seconds
Started Jul 25 07:11:47 PM PDT 24
Finished Jul 25 07:12:31 PM PDT 24
Peak memory 200264 kb
Host smart-3d0c95ce-54d6-48ef-8b7e-d562aacdecba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068580154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3068580154
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.622848827
Short name T429
Test name
Test status
Simulation time 59061093372 ps
CPU time 324.3 seconds
Started Jul 25 07:11:47 PM PDT 24
Finished Jul 25 07:17:11 PM PDT 24
Peak memory 200184 kb
Host smart-b1521be9-f174-4266-894f-ed1d3ba1f089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622848827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.622848827
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1277136519
Short name T504
Test name
Test status
Simulation time 9304796383 ps
CPU time 10.82 seconds
Started Jul 25 07:11:50 PM PDT 24
Finished Jul 25 07:12:01 PM PDT 24
Peak memory 200244 kb
Host smart-e3096dce-682e-4512-97cd-1b5b68b55c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277136519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1277136519
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2346634735
Short name T666
Test name
Test status
Simulation time 88863274751 ps
CPU time 26.11 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:12:12 PM PDT 24
Peak memory 199884 kb
Host smart-e6567136-b4a7-4213-858c-1893d5f0d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346634735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2346634735
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.590083880
Short name T385
Test name
Test status
Simulation time 19739848363 ps
CPU time 1083.69 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:29:58 PM PDT 24
Peak memory 200196 kb
Host smart-3d0fdd04-a06d-4e7e-856a-6cb2fa1f3fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590083880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.590083880
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2591307542
Short name T1141
Test name
Test status
Simulation time 4318087368 ps
CPU time 9.12 seconds
Started Jul 25 07:11:48 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 198436 kb
Host smart-538d5e3a-103d-4bc1-9f7d-34c80e34b31e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591307542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2591307542
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2700098244
Short name T169
Test name
Test status
Simulation time 47891975499 ps
CPU time 34.11 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:12:20 PM PDT 24
Peak memory 200272 kb
Host smart-e9bb0463-55b7-4bad-91d2-eae3bcb5cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700098244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2700098244
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2857358244
Short name T767
Test name
Test status
Simulation time 30946543104 ps
CPU time 42.24 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:12:27 PM PDT 24
Peak memory 196736 kb
Host smart-74e0d001-4b71-4b6c-8316-47170467a972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857358244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2857358244
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.105931669
Short name T1064
Test name
Test status
Simulation time 5896443343 ps
CPU time 19.61 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:12:06 PM PDT 24
Peak memory 200116 kb
Host smart-fd99de0c-53f7-4e99-a5e5-0db38227edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105931669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.105931669
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2541905445
Short name T168
Test name
Test status
Simulation time 284949972950 ps
CPU time 1315.71 seconds
Started Jul 25 07:11:48 PM PDT 24
Finished Jul 25 07:33:44 PM PDT 24
Peak memory 200212 kb
Host smart-81bdb042-2019-446d-a1a4-85274bf26d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541905445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2541905445
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1008364409
Short name T101
Test name
Test status
Simulation time 6503377352 ps
CPU time 26.37 seconds
Started Jul 25 07:11:50 PM PDT 24
Finished Jul 25 07:12:17 PM PDT 24
Peak memory 199444 kb
Host smart-266b1f49-d409-4652-90ee-a1c8df1f59ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008364409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1008364409
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4002796513
Short name T612
Test name
Test status
Simulation time 133344827949 ps
CPU time 120.46 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 200244 kb
Host smart-968079cc-7374-4cdc-bc76-4114ac8664d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002796513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4002796513
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1394170848
Short name T866
Test name
Test status
Simulation time 20960606 ps
CPU time 0.55 seconds
Started Jul 25 07:11:44 PM PDT 24
Finished Jul 25 07:11:45 PM PDT 24
Peak memory 195912 kb
Host smart-82164928-960c-470d-9997-068ec19a8e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394170848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1394170848
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.519582551
Short name T265
Test name
Test status
Simulation time 103106666175 ps
CPU time 144.4 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:14:09 PM PDT 24
Peak memory 200188 kb
Host smart-a946091c-f643-4366-af26-14d427a22678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519582551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.519582551
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3914692749
Short name T107
Test name
Test status
Simulation time 156601115324 ps
CPU time 66.37 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:12:53 PM PDT 24
Peak memory 200164 kb
Host smart-bf6db8ff-6739-47d8-a436-84a57e45ecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914692749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3914692749
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2834020903
Short name T325
Test name
Test status
Simulation time 133788311660 ps
CPU time 165.4 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:14:31 PM PDT 24
Peak memory 200216 kb
Host smart-c4bc4c49-4ce6-4198-9271-be3283fbe19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834020903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2834020903
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4136902557
Short name T513
Test name
Test status
Simulation time 62089339670 ps
CPU time 32.74 seconds
Started Jul 25 07:12:41 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 200192 kb
Host smart-0be3634d-0817-4d86-aee8-19b05037c786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136902557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4136902557
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.840931897
Short name T955
Test name
Test status
Simulation time 46648375968 ps
CPU time 116.06 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:13:42 PM PDT 24
Peak memory 200232 kb
Host smart-5f9c8a21-dbe0-401d-b4fc-40ba34712adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840931897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.840931897
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1488367562
Short name T370
Test name
Test status
Simulation time 2257589381 ps
CPU time 4.48 seconds
Started Jul 25 07:11:50 PM PDT 24
Finished Jul 25 07:11:55 PM PDT 24
Peak memory 200052 kb
Host smart-6ea02172-e9a0-4be5-bc64-5659db59484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488367562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1488367562
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2404869665
Short name T262
Test name
Test status
Simulation time 74481147639 ps
CPU time 108.47 seconds
Started Jul 25 07:11:49 PM PDT 24
Finished Jul 25 07:13:37 PM PDT 24
Peak memory 200396 kb
Host smart-eec23a3b-5301-43a9-b0d4-60928cb1a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404869665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2404869665
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.145467280
Short name T1050
Test name
Test status
Simulation time 13102982446 ps
CPU time 792.02 seconds
Started Jul 25 07:11:46 PM PDT 24
Finished Jul 25 07:24:58 PM PDT 24
Peak memory 200192 kb
Host smart-a39a2cae-41bd-4d75-b8ae-27a00ce4f043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145467280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.145467280
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3781245863
Short name T361
Test name
Test status
Simulation time 6643555972 ps
CPU time 9.28 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:11:55 PM PDT 24
Peak memory 198332 kb
Host smart-bb841bac-f2f4-4a7c-b1c6-4a4f51147bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781245863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3781245863
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.4094146576
Short name T435
Test name
Test status
Simulation time 203205762350 ps
CPU time 168.32 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 200148 kb
Host smart-c324f15b-0b69-4a2e-8a74-6c91c4ec1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094146576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4094146576
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1995506468
Short name T869
Test name
Test status
Simulation time 39759375823 ps
CPU time 16.01 seconds
Started Jul 25 07:11:49 PM PDT 24
Finished Jul 25 07:12:05 PM PDT 24
Peak memory 196080 kb
Host smart-5b162ea6-cd3d-43a6-9162-d07909c53834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995506468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1995506468
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.215782204
Short name T630
Test name
Test status
Simulation time 497037654 ps
CPU time 2.05 seconds
Started Jul 25 07:11:44 PM PDT 24
Finished Jul 25 07:11:46 PM PDT 24
Peak memory 199776 kb
Host smart-9323d6f5-59bd-4d73-8694-b3dee77229af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215782204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.215782204
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.502332220
Short name T588
Test name
Test status
Simulation time 20384292465 ps
CPU time 175.29 seconds
Started Jul 25 07:11:47 PM PDT 24
Finished Jul 25 07:14:42 PM PDT 24
Peak memory 216724 kb
Host smart-a7b7e51a-2884-41d3-b66a-81fe00846de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502332220 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.502332220
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1036848744
Short name T802
Test name
Test status
Simulation time 2124569620 ps
CPU time 2.23 seconds
Started Jul 25 07:11:45 PM PDT 24
Finished Jul 25 07:11:47 PM PDT 24
Peak memory 199836 kb
Host smart-5c8e3557-1c38-49b9-b7da-f636e7126f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036848744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1036848744
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2631674071
Short name T394
Test name
Test status
Simulation time 188213793 ps
CPU time 0.81 seconds
Started Jul 25 07:11:50 PM PDT 24
Finished Jul 25 07:11:51 PM PDT 24
Peak memory 196696 kb
Host smart-31b4de4a-9161-438f-9ca0-b258dcfb3112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631674071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2631674071
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.501088212
Short name T1158
Test name
Test status
Simulation time 25118861 ps
CPU time 0.58 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:09:32 PM PDT 24
Peak memory 195908 kb
Host smart-2467b741-9402-4ca5-8371-dc083240998e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501088212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.501088212
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.204003041
Short name T961
Test name
Test status
Simulation time 30029826554 ps
CPU time 13.18 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:03 PM PDT 24
Peak memory 200180 kb
Host smart-89b11b8f-7f99-4a5e-b3fb-7f3997a56246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204003041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.204003041
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3691430565
Short name T553
Test name
Test status
Simulation time 101292143231 ps
CPU time 160.04 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:12:17 PM PDT 24
Peak memory 200112 kb
Host smart-85416b09-90c1-4434-9376-da85db37dd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691430565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3691430565
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.647503882
Short name T1041
Test name
Test status
Simulation time 23496981233 ps
CPU time 39.62 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:10:20 PM PDT 24
Peak memory 200164 kb
Host smart-d57c2b27-42a0-4f0c-a7d3-372844e2b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647503882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.647503882
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3661911884
Short name T549
Test name
Test status
Simulation time 31555202105 ps
CPU time 7.37 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 200184 kb
Host smart-9eafcaab-6c8f-42bb-a4d8-acc3e3fbd31b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661911884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3661911884
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1991334531
Short name T1053
Test name
Test status
Simulation time 123541428121 ps
CPU time 742.97 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:21:58 PM PDT 24
Peak memory 200248 kb
Host smart-4861c41b-e7f7-4333-aab8-17cedf844546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991334531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1991334531
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3782308461
Short name T990
Test name
Test status
Simulation time 1041379989 ps
CPU time 2.44 seconds
Started Jul 25 07:09:35 PM PDT 24
Finished Jul 25 07:09:38 PM PDT 24
Peak memory 198784 kb
Host smart-af6ac8d6-c8ca-47ab-a1f1-2b00be86f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782308461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3782308461
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2017922673
Short name T777
Test name
Test status
Simulation time 168886836500 ps
CPU time 157.01 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:12:14 PM PDT 24
Peak memory 208568 kb
Host smart-12167d0a-f598-4fd8-a6d1-0b98ef1d2a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017922673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2017922673
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2434092162
Short name T559
Test name
Test status
Simulation time 12893709258 ps
CPU time 342.04 seconds
Started Jul 25 07:09:36 PM PDT 24
Finished Jul 25 07:15:18 PM PDT 24
Peak memory 200240 kb
Host smart-7dd660ae-52b0-4700-a29f-1daac991c2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434092162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2434092162
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.547189722
Short name T451
Test name
Test status
Simulation time 6526592522 ps
CPU time 14.6 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 199636 kb
Host smart-f8c14fa7-dee6-4fa5-90ad-b96531afd57e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547189722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.547189722
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3258668570
Short name T654
Test name
Test status
Simulation time 39434527251 ps
CPU time 66.18 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:49 PM PDT 24
Peak memory 200228 kb
Host smart-ca6a9c1e-7c9f-48cd-b405-1e1fcfb94bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258668570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3258668570
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3940578140
Short name T406
Test name
Test status
Simulation time 47056528600 ps
CPU time 73.94 seconds
Started Jul 25 07:09:34 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 196556 kb
Host smart-c45c471a-bd64-4c05-87a0-60eb5bda27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940578140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3940578140
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.537384805
Short name T261
Test name
Test status
Simulation time 755066881 ps
CPU time 1.26 seconds
Started Jul 25 07:09:39 PM PDT 24
Finished Jul 25 07:09:41 PM PDT 24
Peak memory 198692 kb
Host smart-6cd214fa-7527-42b9-b7e8-5f6174fd8b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537384805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.537384805
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.4123863721
Short name T805
Test name
Test status
Simulation time 125733055367 ps
CPU time 987.76 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:26:05 PM PDT 24
Peak memory 200168 kb
Host smart-ef32a8c1-bb8c-4348-a3ab-1ec61a231627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123863721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4123863721
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.374464544
Short name T828
Test name
Test status
Simulation time 43704222896 ps
CPU time 273.86 seconds
Started Jul 25 07:09:32 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 216300 kb
Host smart-b20ac892-ae41-4ade-89fe-f1bf38ab3ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374464544 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.374464544
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.406474291
Short name T305
Test name
Test status
Simulation time 9570149043 ps
CPU time 6.52 seconds
Started Jul 25 07:09:33 PM PDT 24
Finished Jul 25 07:09:40 PM PDT 24
Peak memory 200268 kb
Host smart-5a876ddd-e6e3-49d5-88e4-7eda92ef6b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406474291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.406474291
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1940583075
Short name T975
Test name
Test status
Simulation time 121545729679 ps
CPU time 83.37 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:11:04 PM PDT 24
Peak memory 200264 kb
Host smart-d9a298fa-6372-4a4d-ba8b-33628c9b24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940583075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1940583075
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1401553914
Short name T561
Test name
Test status
Simulation time 18548384428 ps
CPU time 27.41 seconds
Started Jul 25 07:11:47 PM PDT 24
Finished Jul 25 07:12:15 PM PDT 24
Peak memory 200164 kb
Host smart-d75dd701-1cb7-4e90-8faf-c583e06553d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401553914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1401553914
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1760661438
Short name T571
Test name
Test status
Simulation time 100354408641 ps
CPU time 629.95 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:22:23 PM PDT 24
Peak memory 225160 kb
Host smart-eb1c5a4c-26ac-40ca-9f0a-8b737c64b234
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760661438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1760661438
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2531262817
Short name T973
Test name
Test status
Simulation time 39846048801 ps
CPU time 30.03 seconds
Started Jul 25 07:11:56 PM PDT 24
Finished Jul 25 07:12:26 PM PDT 24
Peak memory 200268 kb
Host smart-99065836-9944-46b1-9e1d-97838fac9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531262817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2531262817
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3286979249
Short name T490
Test name
Test status
Simulation time 62377973960 ps
CPU time 91.06 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:13:24 PM PDT 24
Peak memory 200248 kb
Host smart-13921a46-d74e-43ab-aa5e-7df6eefdef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286979249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3286979249
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1386829792
Short name T1020
Test name
Test status
Simulation time 171283331452 ps
CPU time 877.88 seconds
Started Jul 25 07:11:55 PM PDT 24
Finished Jul 25 07:26:33 PM PDT 24
Peak memory 216688 kb
Host smart-4a3e6c33-d99b-40a3-9d66-5fc883aeea61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386829792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1386829792
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1503557851
Short name T444
Test name
Test status
Simulation time 48102881549 ps
CPU time 131.94 seconds
Started Jul 25 07:11:56 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 200180 kb
Host smart-7d4faf89-9da4-42d5-95f2-f5f421b6f2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503557851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1503557851
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.480091797
Short name T313
Test name
Test status
Simulation time 20079557912 ps
CPU time 171.77 seconds
Started Jul 25 07:11:52 PM PDT 24
Finished Jul 25 07:14:44 PM PDT 24
Peak memory 210664 kb
Host smart-566f5125-58b7-4336-ab39-bc6ff93ed294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480091797 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.480091797
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3127864239
Short name T212
Test name
Test status
Simulation time 37011820075 ps
CPU time 38.15 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:12:32 PM PDT 24
Peak memory 199952 kb
Host smart-8df85861-2be2-4848-aa08-cef32113fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127864239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3127864239
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1986642443
Short name T1100
Test name
Test status
Simulation time 236394976732 ps
CPU time 445.01 seconds
Started Jul 25 07:11:55 PM PDT 24
Finished Jul 25 07:19:20 PM PDT 24
Peak memory 210824 kb
Host smart-9aeb3d8d-7ed1-48bf-a0db-56da111a9199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986642443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1986642443
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2845375633
Short name T222
Test name
Test status
Simulation time 133254290444 ps
CPU time 27.9 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:12:21 PM PDT 24
Peak memory 200240 kb
Host smart-a2b2df43-8616-4a9a-b036-bb80395428f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845375633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2845375633
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3484112115
Short name T333
Test name
Test status
Simulation time 84553971110 ps
CPU time 330.26 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:17:24 PM PDT 24
Peak memory 216836 kb
Host smart-3d2ec749-8255-4c2a-89f8-712afe8c96c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484112115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3484112115
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.166294602
Short name T963
Test name
Test status
Simulation time 32367167382 ps
CPU time 44 seconds
Started Jul 25 07:11:55 PM PDT 24
Finished Jul 25 07:12:40 PM PDT 24
Peak memory 200248 kb
Host smart-76f5cf6e-fdeb-4034-808b-47d0bfc2e8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166294602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.166294602
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2350973364
Short name T845
Test name
Test status
Simulation time 20719397541 ps
CPU time 565.68 seconds
Started Jul 25 07:11:55 PM PDT 24
Finished Jul 25 07:21:21 PM PDT 24
Peak memory 211052 kb
Host smart-9106531d-ab6a-4613-9bdf-a305ffb55a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350973364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2350973364
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3965303576
Short name T138
Test name
Test status
Simulation time 68710160760 ps
CPU time 177.99 seconds
Started Jul 25 07:11:52 PM PDT 24
Finished Jul 25 07:14:50 PM PDT 24
Peak memory 200244 kb
Host smart-09a70aae-32e5-4070-a880-944bb9ba018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965303576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3965303576
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2212601134
Short name T485
Test name
Test status
Simulation time 267545423619 ps
CPU time 685.55 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:23:19 PM PDT 24
Peak memory 229520 kb
Host smart-3584bd5a-5d43-4d0e-8ada-c7c7d7519922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212601134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2212601134
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4042737270
Short name T843
Test name
Test status
Simulation time 80011652221 ps
CPU time 28.76 seconds
Started Jul 25 07:11:57 PM PDT 24
Finished Jul 25 07:12:26 PM PDT 24
Peak memory 200168 kb
Host smart-5631bfb5-506c-4751-902c-20b354621fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042737270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4042737270
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3814158718
Short name T540
Test name
Test status
Simulation time 97273862895 ps
CPU time 732.02 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:24:06 PM PDT 24
Peak memory 225068 kb
Host smart-0074ddd3-ef06-480d-b4c4-54649b4d758e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814158718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3814158718
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3781340374
Short name T419
Test name
Test status
Simulation time 26315561982 ps
CPU time 21.45 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:12:14 PM PDT 24
Peak memory 200264 kb
Host smart-7044c9c8-de81-41bf-848e-04de22f017b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781340374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3781340374
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4205962164
Short name T59
Test name
Test status
Simulation time 232482630895 ps
CPU time 371.26 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:18:06 PM PDT 24
Peak memory 216048 kb
Host smart-ff543b49-84e8-477c-9552-79cb4366eafd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205962164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4205962164
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3648699965
Short name T365
Test name
Test status
Simulation time 37563482 ps
CPU time 0.53 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:09:51 PM PDT 24
Peak memory 194600 kb
Host smart-d82edc24-668c-4be5-a5cd-33a6f50008c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648699965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3648699965
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3884169500
Short name T1026
Test name
Test status
Simulation time 46096474830 ps
CPU time 31.78 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:10:09 PM PDT 24
Peak memory 200272 kb
Host smart-570e2410-9995-489f-a349-bb14bcdc6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884169500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3884169500
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1002221371
Short name T301
Test name
Test status
Simulation time 122148686657 ps
CPU time 51.42 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:10:29 PM PDT 24
Peak memory 200212 kb
Host smart-96e954f3-7c67-4a5b-95b3-9884bd27dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002221371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1002221371
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3785136051
Short name T19
Test name
Test status
Simulation time 92626540355 ps
CPU time 123.25 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:11:42 PM PDT 24
Peak memory 199956 kb
Host smart-3579914b-df87-494f-b4a2-37481342abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785136051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3785136051
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1216397125
Short name T904
Test name
Test status
Simulation time 27438950675 ps
CPU time 18.55 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:02 PM PDT 24
Peak memory 198068 kb
Host smart-93f5ff5e-1ec3-4c18-ba93-cd231bc2889f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216397125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1216397125
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1415563567
Short name T1085
Test name
Test status
Simulation time 118384843327 ps
CPU time 990.71 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:26:17 PM PDT 24
Peak memory 200228 kb
Host smart-3a53bbb8-5e59-4a22-88bf-5f0215b398fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415563567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1415563567
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4274609187
Short name T546
Test name
Test status
Simulation time 5035274337 ps
CPU time 7.67 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:09:49 PM PDT 24
Peak memory 199112 kb
Host smart-8ded4146-2fa8-440c-a790-0fd5db5f3f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274609187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4274609187
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.163187904
Short name T729
Test name
Test status
Simulation time 60816265378 ps
CPU time 7.71 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:09:51 PM PDT 24
Peak memory 200216 kb
Host smart-db4f92b6-8c0c-4e31-9615-d4bd666f91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163187904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.163187904
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1781592032
Short name T327
Test name
Test status
Simulation time 7654791464 ps
CPU time 41.35 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:10:36 PM PDT 24
Peak memory 200232 kb
Host smart-e511b7fe-3080-4180-baaa-09b7affd7d2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781592032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1781592032
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3349172809
Short name T569
Test name
Test status
Simulation time 4213278861 ps
CPU time 16.35 seconds
Started Jul 25 07:09:38 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 198344 kb
Host smart-30df854c-b512-427a-acb0-00d352887adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349172809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3349172809
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.730398869
Short name T128
Test name
Test status
Simulation time 45602223981 ps
CPU time 36.43 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:10:19 PM PDT 24
Peak memory 200288 kb
Host smart-08ae31eb-c681-4dfc-907e-7b14ed4f8de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730398869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.730398869
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3018837779
Short name T290
Test name
Test status
Simulation time 34878022081 ps
CPU time 12.44 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:09:52 PM PDT 24
Peak memory 196248 kb
Host smart-9a4f41f0-55de-4e71-b920-6626bcb5e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018837779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3018837779
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.932634327
Short name T772
Test name
Test status
Simulation time 6336231375 ps
CPU time 22.98 seconds
Started Jul 25 07:09:37 PM PDT 24
Finished Jul 25 07:10:00 PM PDT 24
Peak memory 199800 kb
Host smart-58035120-d54d-4429-9ee5-0052106e02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932634327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.932634327
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2921432304
Short name T1030
Test name
Test status
Simulation time 635122977983 ps
CPU time 182.82 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:12:43 PM PDT 24
Peak memory 208564 kb
Host smart-62429f40-330d-481e-93dd-4871f476d785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921432304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2921432304
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3435822905
Short name T512
Test name
Test status
Simulation time 13110577841 ps
CPU time 160.81 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:12:29 PM PDT 24
Peak memory 216740 kb
Host smart-ce9f9d3e-227c-4d79-8b38-987d56e8ed1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435822905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3435822905
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1569925816
Short name T1093
Test name
Test status
Simulation time 1993374349 ps
CPU time 2.06 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 198996 kb
Host smart-618a5263-9160-4c03-857a-a96d9d34fdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569925816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1569925816
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.765275251
Short name T741
Test name
Test status
Simulation time 96089392795 ps
CPU time 91.71 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:11:15 PM PDT 24
Peak memory 200256 kb
Host smart-ac8bf4b5-dff9-4e27-a46e-9fe76b462192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765275251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.765275251
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1343108789
Short name T1032
Test name
Test status
Simulation time 83835488546 ps
CPU time 43.12 seconds
Started Jul 25 07:11:53 PM PDT 24
Finished Jul 25 07:12:37 PM PDT 24
Peak memory 200244 kb
Host smart-2d978106-708f-4a56-b45b-1cd41e10e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343108789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1343108789
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.985532812
Short name T489
Test name
Test status
Simulation time 31869494708 ps
CPU time 97.23 seconds
Started Jul 25 07:11:52 PM PDT 24
Finished Jul 25 07:13:29 PM PDT 24
Peak memory 208488 kb
Host smart-76747119-88cc-4ea2-a50f-88d8d5ae00c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985532812 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.985532812
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.166751483
Short name T1023
Test name
Test status
Simulation time 75514913895 ps
CPU time 217.89 seconds
Started Jul 25 07:11:59 PM PDT 24
Finished Jul 25 07:15:37 PM PDT 24
Peak memory 216856 kb
Host smart-7de7fdab-7df6-4100-88a2-76aa56898644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166751483 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.166751483
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1767330937
Short name T216
Test name
Test status
Simulation time 89044195940 ps
CPU time 66.79 seconds
Started Jul 25 07:11:55 PM PDT 24
Finished Jul 25 07:13:02 PM PDT 24
Peak memory 200196 kb
Host smart-f7645168-b080-4839-b214-36d5b9523a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767330937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1767330937
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.571871458
Short name T1149
Test name
Test status
Simulation time 107513680808 ps
CPU time 964.34 seconds
Started Jul 25 07:11:52 PM PDT 24
Finished Jul 25 07:27:57 PM PDT 24
Peak memory 225100 kb
Host smart-f8486380-1ecd-4f18-8b23-aa35d9540a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571871458 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.571871458
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2136427144
Short name T187
Test name
Test status
Simulation time 15128529214 ps
CPU time 27.42 seconds
Started Jul 25 07:11:54 PM PDT 24
Finished Jul 25 07:12:22 PM PDT 24
Peak memory 200260 kb
Host smart-465d8494-d69b-4748-8e55-32d9ea074b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136427144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2136427144
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.722410016
Short name T749
Test name
Test status
Simulation time 75258195429 ps
CPU time 1272.48 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:33:14 PM PDT 24
Peak memory 225100 kb
Host smart-768262eb-aaf7-4b46-a4f9-5bd6dfea1578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722410016 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.722410016
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2773249877
Short name T568
Test name
Test status
Simulation time 499900091425 ps
CPU time 704.99 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:23:47 PM PDT 24
Peak memory 216760 kb
Host smart-c5858880-fd2c-410c-b732-92f5fdaeeaa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773249877 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2773249877
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.782452513
Short name T184
Test name
Test status
Simulation time 23893247903 ps
CPU time 11.73 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:12:14 PM PDT 24
Peak memory 200272 kb
Host smart-9d48cc0b-89a3-4486-8c3a-4fd79f8231d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782452513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.782452513
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3340583194
Short name T595
Test name
Test status
Simulation time 33965613813 ps
CPU time 209.56 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:15:30 PM PDT 24
Peak memory 214524 kb
Host smart-867f1ce4-9fcb-4402-89c0-a05b719cea73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340583194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3340583194
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3156429488
Short name T848
Test name
Test status
Simulation time 55280709053 ps
CPU time 81.69 seconds
Started Jul 25 07:12:06 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200208 kb
Host smart-9d43f999-b2d8-4225-bdaf-992f58d44294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156429488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3156429488
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3871224246
Short name T63
Test name
Test status
Simulation time 523233854663 ps
CPU time 1475.98 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:36:39 PM PDT 24
Peak memory 228168 kb
Host smart-d5d5e08f-3929-4479-a8d6-6f30f990bb4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871224246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3871224246
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3683264535
Short name T1060
Test name
Test status
Simulation time 5890603884 ps
CPU time 9.85 seconds
Started Jul 25 07:12:35 PM PDT 24
Finished Jul 25 07:12:45 PM PDT 24
Peak memory 199772 kb
Host smart-f72e1742-d8cf-45a1-a1e9-6ef73d56465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683264535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3683264535
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1035459632
Short name T678
Test name
Test status
Simulation time 28073647041 ps
CPU time 183.69 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 216516 kb
Host smart-84267172-4336-4f5b-9fa6-788ff5003ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035459632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1035459632
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2069533190
Short name T537
Test name
Test status
Simulation time 48798716174 ps
CPU time 100.27 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:13:41 PM PDT 24
Peak memory 200156 kb
Host smart-e67e3639-2e8c-40e4-ba79-10925fc0405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069533190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2069533190
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3912549235
Short name T944
Test name
Test status
Simulation time 136938710489 ps
CPU time 649.78 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:22:53 PM PDT 24
Peak memory 229164 kb
Host smart-7a038303-e0d2-4c56-8276-1e2e87a34500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912549235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3912549235
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4009041635
Short name T953
Test name
Test status
Simulation time 87346448429 ps
CPU time 129.15 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:14:11 PM PDT 24
Peak memory 200264 kb
Host smart-27dc0f0b-b4e2-40bf-91db-606d4176ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009041635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4009041635
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3244992786
Short name T1128
Test name
Test status
Simulation time 17440916 ps
CPU time 0.54 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:43 PM PDT 24
Peak memory 195628 kb
Host smart-57eda8ac-125b-4fbb-8043-d001266b526f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244992786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3244992786
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3637517953
Short name T481
Test name
Test status
Simulation time 147844400991 ps
CPU time 39.92 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:10:27 PM PDT 24
Peak memory 200272 kb
Host smart-6b611830-6025-45b1-bd64-6ef10c692426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637517953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3637517953
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1657739869
Short name T748
Test name
Test status
Simulation time 120391551806 ps
CPU time 384.47 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:16:04 PM PDT 24
Peak memory 200216 kb
Host smart-0d316fbe-4f59-4608-8959-05233556342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657739869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1657739869
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3222218150
Short name T402
Test name
Test status
Simulation time 63607891578 ps
CPU time 41.91 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:10:29 PM PDT 24
Peak memory 200244 kb
Host smart-6badb8c8-a1cb-4a36-b522-54adf822cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222218150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3222218150
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1024314809
Short name T960
Test name
Test status
Simulation time 6260758533 ps
CPU time 1.98 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:09:50 PM PDT 24
Peak memory 197008 kb
Host smart-8d2919d5-65fb-4b71-94f1-b22560aa1a8c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024314809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1024314809
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1695683662
Short name T1119
Test name
Test status
Simulation time 41667140277 ps
CPU time 272.18 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:14:15 PM PDT 24
Peak memory 200248 kb
Host smart-95ebcd29-3db9-47f7-983f-7d7f9f6f1c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695683662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1695683662
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.555343476
Short name T340
Test name
Test status
Simulation time 812163312 ps
CPU time 0.72 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:46 PM PDT 24
Peak memory 196372 kb
Host smart-2281b9bb-e81f-4127-91dd-2e874fb26d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555343476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.555343476
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1977507993
Short name T876
Test name
Test status
Simulation time 98627824124 ps
CPU time 48.19 seconds
Started Jul 25 07:09:59 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 208632 kb
Host smart-dbf2b5ec-f6f0-4530-9d47-4383d3f9a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977507993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1977507993
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.622444339
Short name T1125
Test name
Test status
Simulation time 15371255252 ps
CPU time 232.9 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:13:38 PM PDT 24
Peak memory 200224 kb
Host smart-c9522099-9ff4-4478-bdc4-1f591c7b0bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622444339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.622444339
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.4172968732
Short name T350
Test name
Test status
Simulation time 6421710573 ps
CPU time 18.77 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:10:06 PM PDT 24
Peak memory 198392 kb
Host smart-24cf9483-800c-4e01-a6ca-c1671c7d2108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172968732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4172968732
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1262206612
Short name T372
Test name
Test status
Simulation time 91278800225 ps
CPU time 134.24 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:11:57 PM PDT 24
Peak memory 200200 kb
Host smart-9a9be590-4455-4be2-8b2f-ce25a9a92180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262206612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1262206612
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.936640711
Short name T1057
Test name
Test status
Simulation time 1854840563 ps
CPU time 3.14 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:48 PM PDT 24
Peak memory 195772 kb
Host smart-86be9391-80e6-45f1-aecb-56877eb8a9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936640711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.936640711
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3076301302
Short name T1039
Test name
Test status
Simulation time 548592593 ps
CPU time 2.08 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:47 PM PDT 24
Peak memory 199848 kb
Host smart-3f7a2212-f18d-440b-aafe-1952e90c1e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076301302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3076301302
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2668976491
Short name T423
Test name
Test status
Simulation time 2425478528 ps
CPU time 2.71 seconds
Started Jul 25 07:10:03 PM PDT 24
Finished Jul 25 07:10:06 PM PDT 24
Peak memory 200100 kb
Host smart-625a7e98-2af6-47ba-86d8-be8ed83cbe0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668976491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2668976491
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.774034205
Short name T862
Test name
Test status
Simulation time 117336979619 ps
CPU time 2016.02 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:43:19 PM PDT 24
Peak memory 216668 kb
Host smart-7a29563d-e8b0-4b8a-ac5c-d4006b028ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774034205 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.774034205
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3798349092
Short name T1070
Test name
Test status
Simulation time 3267098406 ps
CPU time 1.88 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 199448 kb
Host smart-8e59c406-46de-4de6-a814-485c2cdcbc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798349092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3798349092
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1371064639
Short name T1147
Test name
Test status
Simulation time 167862045068 ps
CPU time 59.44 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:10:42 PM PDT 24
Peak memory 200252 kb
Host smart-3572ea74-fdbf-4424-b05d-07b77378a65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371064639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1371064639
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2585058911
Short name T1142
Test name
Test status
Simulation time 31844924729 ps
CPU time 43.52 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 200260 kb
Host smart-e063d7f1-430d-4c0c-8650-86b96d3a2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585058911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2585058911
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1936868934
Short name T835
Test name
Test status
Simulation time 49951947306 ps
CPU time 136.91 seconds
Started Jul 25 07:12:05 PM PDT 24
Finished Jul 25 07:14:22 PM PDT 24
Peak memory 216864 kb
Host smart-f144401a-f7d1-4e13-80e0-f26c0b301751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936868934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1936868934
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2713250246
Short name T794
Test name
Test status
Simulation time 14218958495 ps
CPU time 11.67 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:12:13 PM PDT 24
Peak memory 200200 kb
Host smart-aca940aa-a139-43f8-94fc-edd72dc0357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713250246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2713250246
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2874041313
Short name T788
Test name
Test status
Simulation time 52933622316 ps
CPU time 313.32 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:17:16 PM PDT 24
Peak memory 216700 kb
Host smart-814d163f-9870-4ce7-8489-f5b01b6c0b27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874041313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2874041313
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.4039149320
Short name T60
Test name
Test status
Simulation time 329640132003 ps
CPU time 995.46 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:28:37 PM PDT 24
Peak memory 226116 kb
Host smart-3e62b021-8250-47e9-8e9e-53af366237f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039149320 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.4039149320
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1780659545
Short name T1076
Test name
Test status
Simulation time 276657966502 ps
CPU time 87.33 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:13:28 PM PDT 24
Peak memory 200244 kb
Host smart-e311fd98-edbd-4534-917c-4bee3e2139c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780659545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1780659545
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1311520978
Short name T113
Test name
Test status
Simulation time 75144617277 ps
CPU time 309.54 seconds
Started Jul 25 07:12:01 PM PDT 24
Finished Jul 25 07:17:10 PM PDT 24
Peak memory 216636 kb
Host smart-da271443-e4e2-42f9-8885-ba04e4b1b787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311520978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1311520978
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2931270765
Short name T400
Test name
Test status
Simulation time 30761080907 ps
CPU time 20.47 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:12:23 PM PDT 24
Peak memory 200236 kb
Host smart-fb3b9232-d28d-4056-85ad-edad2d5b1687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931270765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2931270765
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.76799579
Short name T796
Test name
Test status
Simulation time 48457720024 ps
CPU time 585.69 seconds
Started Jul 25 07:12:00 PM PDT 24
Finished Jul 25 07:21:46 PM PDT 24
Peak memory 225100 kb
Host smart-80797de4-305b-4d02-bfbe-382e054dd92e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76799579 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.76799579
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3054189205
Short name T1080
Test name
Test status
Simulation time 6407425934 ps
CPU time 5.86 seconds
Started Jul 25 07:12:00 PM PDT 24
Finished Jul 25 07:12:06 PM PDT 24
Peak memory 198992 kb
Host smart-2f7e5f25-1be9-44e1-be3b-fabf04ea0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054189205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3054189205
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3216326339
Short name T449
Test name
Test status
Simulation time 195977005545 ps
CPU time 787.66 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:25:11 PM PDT 24
Peak memory 213888 kb
Host smart-32ffe323-5ed6-4a18-b6ad-5bdf7bd2cbb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216326339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3216326339
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1292384254
Short name T219
Test name
Test status
Simulation time 119005576076 ps
CPU time 47.17 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:12:51 PM PDT 24
Peak memory 200260 kb
Host smart-5ea07cf4-ef3d-42dc-bea0-11663204a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292384254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1292384254
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1888040734
Short name T1065
Test name
Test status
Simulation time 73525343000 ps
CPU time 103.13 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 216896 kb
Host smart-f95b27a1-0ac7-40c1-8313-cdc0852f9228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888040734 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1888040734
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2895800508
Short name T696
Test name
Test status
Simulation time 137040431905 ps
CPU time 603.33 seconds
Started Jul 25 07:12:05 PM PDT 24
Finished Jul 25 07:22:08 PM PDT 24
Peak memory 226236 kb
Host smart-7e38f5b8-196c-4c09-9e1c-0d5cb0a2c426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895800508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2895800508
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1829269748
Short name T202
Test name
Test status
Simulation time 71302227172 ps
CPU time 36.55 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:12:40 PM PDT 24
Peak memory 200252 kb
Host smart-bf46dd69-a90b-4bc8-b923-9ec0ceb7821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829269748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1829269748
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.905399770
Short name T826
Test name
Test status
Simulation time 15966781208 ps
CPU time 82.93 seconds
Started Jul 25 07:12:03 PM PDT 24
Finished Jul 25 07:13:26 PM PDT 24
Peak memory 208712 kb
Host smart-95a1dc67-5887-4c64-a823-d5171fff1d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905399770 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.905399770
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.118010230
Short name T896
Test name
Test status
Simulation time 75787032965 ps
CPU time 29.31 seconds
Started Jul 25 07:12:07 PM PDT 24
Finished Jul 25 07:12:36 PM PDT 24
Peak memory 200240 kb
Host smart-8507ae0a-5089-41ef-a62c-987740525f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118010230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.118010230
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2126772359
Short name T1013
Test name
Test status
Simulation time 108761282781 ps
CPU time 375.87 seconds
Started Jul 25 07:12:02 PM PDT 24
Finished Jul 25 07:18:18 PM PDT 24
Peak memory 216752 kb
Host smart-550931a7-e2a9-489d-985a-b7bbd2b66dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126772359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2126772359
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4022886497
Short name T726
Test name
Test status
Simulation time 13987426 ps
CPU time 0.6 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:44 PM PDT 24
Peak memory 195676 kb
Host smart-9c137840-28c4-483d-a42f-15638b1f7555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022886497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4022886497
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3812598346
Short name T628
Test name
Test status
Simulation time 363446138372 ps
CPU time 263.78 seconds
Started Jul 25 07:09:54 PM PDT 24
Finished Jul 25 07:14:18 PM PDT 24
Peak memory 200168 kb
Host smart-2f1d639d-422d-4f2f-b4a5-9d6e1c5f40b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812598346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3812598346
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.146113610
Short name T593
Test name
Test status
Simulation time 105037343623 ps
CPU time 51.14 seconds
Started Jul 25 07:09:56 PM PDT 24
Finished Jul 25 07:10:48 PM PDT 24
Peak memory 200264 kb
Host smart-af7c91ee-d52c-4181-876c-5a4f49f5014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146113610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.146113610
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2304072687
Short name T364
Test name
Test status
Simulation time 18544316518 ps
CPU time 21.05 seconds
Started Jul 25 07:09:50 PM PDT 24
Finished Jul 25 07:10:11 PM PDT 24
Peak memory 200172 kb
Host smart-a81d3581-60ee-40c3-9ae8-af40543d8d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304072687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2304072687
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.970357258
Short name T643
Test name
Test status
Simulation time 192793137227 ps
CPU time 147.49 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:12:13 PM PDT 24
Peak memory 200252 kb
Host smart-ee9ae3de-049b-46cc-baa9-f1dae0de7dd6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970357258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.970357258
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2400949305
Short name T891
Test name
Test status
Simulation time 76623310095 ps
CPU time 538.9 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:18:42 PM PDT 24
Peak memory 200200 kb
Host smart-7badf043-9a93-4ab8-9ab4-caee484dcc76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400949305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2400949305
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1694411154
Short name T411
Test name
Test status
Simulation time 8933629232 ps
CPU time 8.56 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:52 PM PDT 24
Peak memory 199560 kb
Host smart-ac4f7965-5c5b-4ce4-9c1c-1a102ef148a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694411154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1694411154
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.624047615
Short name T379
Test name
Test status
Simulation time 5431610755 ps
CPU time 7.52 seconds
Started Jul 25 07:09:46 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 194788 kb
Host smart-5d99d019-f6ea-4013-b600-9a975d9d947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624047615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.624047615
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2944153912
Short name T412
Test name
Test status
Simulation time 5127023482 ps
CPU time 313 seconds
Started Jul 25 07:09:45 PM PDT 24
Finished Jul 25 07:14:59 PM PDT 24
Peak memory 200248 kb
Host smart-2766ef3e-f073-4af6-93fd-4c82e3245003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944153912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2944153912
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3018308517
Short name T890
Test name
Test status
Simulation time 3608692722 ps
CPU time 3.5 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:48 PM PDT 24
Peak memory 198116 kb
Host smart-3d75f688-8737-47fc-b267-cda2e3bfc90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018308517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3018308517
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1019290478
Short name T443
Test name
Test status
Simulation time 109497044717 ps
CPU time 172.66 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:12:41 PM PDT 24
Peak memory 200240 kb
Host smart-dd6822dc-b46a-4f9b-874c-56ad477af8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019290478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1019290478
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.852601381
Short name T757
Test name
Test status
Simulation time 2777171895 ps
CPU time 2.79 seconds
Started Jul 25 07:09:40 PM PDT 24
Finished Jul 25 07:09:43 PM PDT 24
Peak memory 196752 kb
Host smart-42649e83-b39f-4820-b2b5-e939c4ea94c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852601381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.852601381
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3287336232
Short name T599
Test name
Test status
Simulation time 11042796765 ps
CPU time 19.19 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:10:07 PM PDT 24
Peak memory 200216 kb
Host smart-bbd75999-20b1-4857-b12d-1ef4b30ad8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287336232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3287336232
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.588269195
Short name T684
Test name
Test status
Simulation time 148779088690 ps
CPU time 331.38 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:15:20 PM PDT 24
Peak memory 200192 kb
Host smart-4f196dd1-b5a3-4a29-9ba4-b69caa3b02e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588269195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.588269195
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.910056414
Short name T983
Test name
Test status
Simulation time 1086847399 ps
CPU time 1.47 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 198264 kb
Host smart-09053563-6ed1-4773-a427-b36783dadb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910056414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.910056414
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3900378988
Short name T1137
Test name
Test status
Simulation time 40903500852 ps
CPU time 10.48 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:09:53 PM PDT 24
Peak memory 200292 kb
Host smart-81dbda3f-dd74-48f8-936a-8687a6650f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900378988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3900378988
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3423067327
Short name T693
Test name
Test status
Simulation time 26984516641 ps
CPU time 11.54 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:12:22 PM PDT 24
Peak memory 200264 kb
Host smart-558209b1-1fe6-4be8-ad47-3d2bfcf7860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423067327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3423067327
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4263755589
Short name T176
Test name
Test status
Simulation time 162830423053 ps
CPU time 892.08 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:27:03 PM PDT 24
Peak memory 224868 kb
Host smart-c69c9367-9caf-4e7d-9288-06ee9da5d599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263755589 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4263755589
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1683556463
Short name T462
Test name
Test status
Simulation time 18542675992 ps
CPU time 31.18 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:12:41 PM PDT 24
Peak memory 200264 kb
Host smart-f2665de3-6685-43d9-a310-5cb446a0e316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683556463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1683556463
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1449955886
Short name T180
Test name
Test status
Simulation time 92754468892 ps
CPU time 493.75 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:20:23 PM PDT 24
Peak memory 216900 kb
Host smart-f6069b87-0d87-418a-8fac-3940018ac15d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449955886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1449955886
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1673917497
Short name T468
Test name
Test status
Simulation time 39758457969 ps
CPU time 20.61 seconds
Started Jul 25 07:12:08 PM PDT 24
Finished Jul 25 07:12:29 PM PDT 24
Peak memory 200132 kb
Host smart-a0e67076-63fb-4374-9413-d2c7ab4dadb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673917497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1673917497
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.567963428
Short name T687
Test name
Test status
Simulation time 67119398389 ps
CPU time 745.59 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:24:35 PM PDT 24
Peak memory 225032 kb
Host smart-e90e7ccd-3095-4c92-adfd-46caf8206537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567963428 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.567963428
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3250167359
Short name T321
Test name
Test status
Simulation time 54282163490 ps
CPU time 203.28 seconds
Started Jul 25 07:12:08 PM PDT 24
Finished Jul 25 07:15:32 PM PDT 24
Peak memory 200168 kb
Host smart-9e3e188d-9b3d-48c5-ac99-505a58fe3fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250167359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3250167359
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4063989612
Short name T465
Test name
Test status
Simulation time 18238493023 ps
CPU time 211.67 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:15:42 PM PDT 24
Peak memory 211052 kb
Host smart-f04d0f2a-d1eb-43d9-b5c2-92389c02709a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063989612 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4063989612
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2584368465
Short name T225
Test name
Test status
Simulation time 42573138982 ps
CPU time 65.34 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 200236 kb
Host smart-c87f4705-d2a8-4d25-994e-c30f2aa99978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584368465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2584368465
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1045598564
Short name T840
Test name
Test status
Simulation time 96088415190 ps
CPU time 24.02 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:12:35 PM PDT 24
Peak memory 200272 kb
Host smart-6e0d5eee-6fee-4879-8aed-28991ab4bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045598564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1045598564
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2578876561
Short name T1127
Test name
Test status
Simulation time 189700282709 ps
CPU time 521.93 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:20:51 PM PDT 24
Peak memory 216924 kb
Host smart-d37121a0-0c1f-4703-8164-2fc8f4c43acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578876561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2578876561
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3191598295
Short name T1145
Test name
Test status
Simulation time 9182817924 ps
CPU time 14.68 seconds
Started Jul 25 07:12:13 PM PDT 24
Finished Jul 25 07:12:28 PM PDT 24
Peak memory 200212 kb
Host smart-fcc970f8-453c-448a-a2ac-62a7a9d8d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191598295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3191598295
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.628179155
Short name T1157
Test name
Test status
Simulation time 23819500003 ps
CPU time 113.83 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:14:03 PM PDT 24
Peak memory 216756 kb
Host smart-55b7378e-35dc-46e2-8d38-76f0789b3bfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628179155 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.628179155
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.140446087
Short name T989
Test name
Test status
Simulation time 52486733302 ps
CPU time 18.2 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:12:29 PM PDT 24
Peak memory 200272 kb
Host smart-ccfe444e-779e-46bd-b99d-8d67832a7bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140446087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.140446087
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3736678580
Short name T112
Test name
Test status
Simulation time 26534722090 ps
CPU time 62.18 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:13:13 PM PDT 24
Peak memory 216560 kb
Host smart-a39b9bae-e7f3-4503-b440-b37ebe3d66d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736678580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3736678580
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3047175668
Short name T689
Test name
Test status
Simulation time 30399251112 ps
CPU time 535.72 seconds
Started Jul 25 07:12:46 PM PDT 24
Finished Jul 25 07:21:42 PM PDT 24
Peak memory 216760 kb
Host smart-b07c8449-6281-40d5-a39c-d1ac23c458f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047175668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3047175668
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.934254592
Short name T150
Test name
Test status
Simulation time 76922340715 ps
CPU time 37.58 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:12:47 PM PDT 24
Peak memory 200232 kb
Host smart-1af68cac-a72c-416a-9522-cf65d1258ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934254592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.934254592
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.142849288
Short name T617
Test name
Test status
Simulation time 71332545523 ps
CPU time 939.42 seconds
Started Jul 25 07:12:08 PM PDT 24
Finished Jul 25 07:27:48 PM PDT 24
Peak memory 216740 kb
Host smart-ff61b8c5-cfc5-4335-9f5f-6cd0fce3bfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142849288 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.142849288
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3470423457
Short name T708
Test name
Test status
Simulation time 37669925 ps
CPU time 0.55 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:09:45 PM PDT 24
Peak memory 195080 kb
Host smart-3efb148c-f83c-4e62-be72-bbfa4feacdb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470423457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3470423457
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.345579421
Short name T564
Test name
Test status
Simulation time 41228705264 ps
CPU time 18.39 seconds
Started Jul 25 07:10:08 PM PDT 24
Finished Jul 25 07:10:27 PM PDT 24
Peak memory 200220 kb
Host smart-b9c2a77f-a4b2-459c-a27d-809205be31c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345579421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.345579421
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1202863233
Short name T1086
Test name
Test status
Simulation time 246684392826 ps
CPU time 50.38 seconds
Started Jul 25 07:09:41 PM PDT 24
Finished Jul 25 07:10:31 PM PDT 24
Peak memory 200280 kb
Host smart-21b9094c-989f-4432-861e-b9d6673261cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202863233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1202863233
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1072101374
Short name T790
Test name
Test status
Simulation time 21021377459 ps
CPU time 35.04 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:10:22 PM PDT 24
Peak memory 200184 kb
Host smart-ce9ab86b-ad8d-4128-86c4-141c229f5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072101374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1072101374
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3687071162
Short name T20
Test name
Test status
Simulation time 55883166137 ps
CPU time 87.07 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:11:09 PM PDT 24
Peak memory 200200 kb
Host smart-74b24aca-d4c3-4c25-8d64-5632511c63d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687071162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3687071162
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3782925149
Short name T1133
Test name
Test status
Simulation time 117123558148 ps
CPU time 309.04 seconds
Started Jul 25 07:09:42 PM PDT 24
Finished Jul 25 07:14:52 PM PDT 24
Peak memory 200204 kb
Host smart-5f1f7dac-306a-4938-92cd-10a9cba52bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782925149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3782925149
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4108349881
Short name T21
Test name
Test status
Simulation time 12836048244 ps
CPU time 14.78 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:09:58 PM PDT 24
Peak memory 200188 kb
Host smart-a97dab80-47ea-4e75-88dd-5552a17d253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108349881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4108349881
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2214272270
Short name T264
Test name
Test status
Simulation time 12676449792 ps
CPU time 20.58 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:10:04 PM PDT 24
Peak memory 199408 kb
Host smart-23fd9cbc-6653-44cd-a568-173ab03c44ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214272270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2214272270
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2629056281
Short name T417
Test name
Test status
Simulation time 755923667 ps
CPU time 6.64 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:59 PM PDT 24
Peak memory 200180 kb
Host smart-65b1882b-ea9a-4f37-be50-dde9c62613ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629056281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2629056281
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.739403514
Short name T389
Test name
Test status
Simulation time 6806363489 ps
CPU time 26.31 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:10:14 PM PDT 24
Peak memory 199420 kb
Host smart-884f25fb-244c-48a1-b7f4-e7ce384caee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739403514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.739403514
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.338832229
Short name T51
Test name
Test status
Simulation time 289223758520 ps
CPU time 152.5 seconds
Started Jul 25 07:09:47 PM PDT 24
Finished Jul 25 07:12:20 PM PDT 24
Peak memory 200220 kb
Host smart-68f59cff-1fa1-41c4-88e2-51f9423e9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338832229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.338832229
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4080986475
Short name T618
Test name
Test status
Simulation time 4622071611 ps
CPU time 1.22 seconds
Started Jul 25 07:10:02 PM PDT 24
Finished Jul 25 07:10:04 PM PDT 24
Peak memory 196756 kb
Host smart-e08731ce-e0e3-40fe-8ad9-55395fba7de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080986475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4080986475
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.189050886
Short name T812
Test name
Test status
Simulation time 87826943 ps
CPU time 0.88 seconds
Started Jul 25 07:09:43 PM PDT 24
Finished Jul 25 07:09:44 PM PDT 24
Peak memory 198004 kb
Host smart-3006edb8-0e8c-4512-babe-f388235e76df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189050886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.189050886
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3563482571
Short name T918
Test name
Test status
Simulation time 422124011174 ps
CPU time 490.81 seconds
Started Jul 25 07:09:48 PM PDT 24
Finished Jul 25 07:17:59 PM PDT 24
Peak memory 200240 kb
Host smart-9390180b-4ca6-4528-9343-24f11ed4562b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563482571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3563482571
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1761505417
Short name T607
Test name
Test status
Simulation time 62693575239 ps
CPU time 232.27 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 216624 kb
Host smart-26536411-26b9-4a72-8a3c-a00aad01c472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761505417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1761505417
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2638943498
Short name T625
Test name
Test status
Simulation time 996937177 ps
CPU time 1.82 seconds
Started Jul 25 07:09:52 PM PDT 24
Finished Jul 25 07:09:54 PM PDT 24
Peak memory 198616 kb
Host smart-4c672287-46d3-4942-98ef-8b2890ea6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638943498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2638943498
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.457682142
Short name T780
Test name
Test status
Simulation time 52049760639 ps
CPU time 21.63 seconds
Started Jul 25 07:09:44 PM PDT 24
Finished Jul 25 07:10:06 PM PDT 24
Peak memory 199996 kb
Host smart-47ae8340-64f0-4140-ac7c-5ff5750caa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457682142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.457682142
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4238503557
Short name T228
Test name
Test status
Simulation time 30911208558 ps
CPU time 30.75 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:12:42 PM PDT 24
Peak memory 200276 kb
Host smart-8a7dfd2b-6cd3-47b2-9d7d-e19657b761c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238503557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4238503557
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2161585727
Short name T110
Test name
Test status
Simulation time 33576945101 ps
CPU time 323.59 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:17:35 PM PDT 24
Peak memory 216784 kb
Host smart-c45969b2-870e-4d31-bfb0-9ddaa2d8ab4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161585727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2161585727
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.178105631
Short name T197
Test name
Test status
Simulation time 45755208388 ps
CPU time 71.31 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:13:22 PM PDT 24
Peak memory 200232 kb
Host smart-0b9ba603-786e-452c-8d9d-1f7c30fb763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178105631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.178105631
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.473650362
Short name T62
Test name
Test status
Simulation time 183021447117 ps
CPU time 582.69 seconds
Started Jul 25 07:12:12 PM PDT 24
Finished Jul 25 07:21:55 PM PDT 24
Peak memory 216740 kb
Host smart-6ac343c1-aa1e-4ab7-b5be-ea05e9ffb968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473650362 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.473650362
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.600615693
Short name T665
Test name
Test status
Simulation time 129458056326 ps
CPU time 116.32 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 200272 kb
Host smart-3c1f71ed-2bed-4cd3-8fef-ebd099049594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600615693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.600615693
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.871063872
Short name T328
Test name
Test status
Simulation time 146211794750 ps
CPU time 904.61 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:27:16 PM PDT 24
Peak memory 225104 kb
Host smart-65e80302-b639-44dc-9823-6e59ad7e0109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871063872 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.871063872
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.915220226
Short name T1049
Test name
Test status
Simulation time 11627483179 ps
CPU time 18.5 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:12:30 PM PDT 24
Peak memory 200180 kb
Host smart-c64146da-c673-435f-bc79-51a611c1fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915220226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.915220226
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2034346504
Short name T560
Test name
Test status
Simulation time 28330078939 ps
CPU time 172.29 seconds
Started Jul 25 07:12:13 PM PDT 24
Finished Jul 25 07:15:05 PM PDT 24
Peak memory 211632 kb
Host smart-408cddd9-024a-48b3-bf65-c63853caf5ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034346504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2034346504
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2385655302
Short name T999
Test name
Test status
Simulation time 112404908222 ps
CPU time 172.76 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:15:04 PM PDT 24
Peak memory 200160 kb
Host smart-c4aa7fc5-081f-4f86-aaa7-d0fcd1d2bcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385655302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2385655302
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1341671152
Short name T174
Test name
Test status
Simulation time 58672661954 ps
CPU time 321.84 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:17:33 PM PDT 24
Peak memory 216844 kb
Host smart-d684a01f-a1c3-4d44-8079-86543a7d72b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341671152 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1341671152
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1367405219
Short name T213
Test name
Test status
Simulation time 20191584722 ps
CPU time 16.81 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:12:28 PM PDT 24
Peak memory 200236 kb
Host smart-fd48d101-3cdb-4ada-bea9-b6fc0ea03354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367405219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1367405219
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1644396576
Short name T562
Test name
Test status
Simulation time 24777829495 ps
CPU time 324.33 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:17:34 PM PDT 24
Peak memory 216844 kb
Host smart-d79945d5-3a1d-408a-afad-19800e671452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644396576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1644396576
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1550963343
Short name T742
Test name
Test status
Simulation time 129767423489 ps
CPU time 174.73 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:15:06 PM PDT 24
Peak memory 200196 kb
Host smart-6e4b9af2-ab3f-4dad-a0e5-c6ae518efb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550963343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1550963343
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2924613758
Short name T111
Test name
Test status
Simulation time 57458097015 ps
CPU time 338.16 seconds
Started Jul 25 07:12:10 PM PDT 24
Finished Jul 25 07:17:48 PM PDT 24
Peak memory 216860 kb
Host smart-e6f7fa19-05dd-408e-b2cb-d38af6d5ebc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924613758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2924613758
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3186918827
Short name T43
Test name
Test status
Simulation time 80292550968 ps
CPU time 114.35 seconds
Started Jul 25 07:12:11 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 200256 kb
Host smart-bdb4022f-f71d-4a90-b248-b8f1f255b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186918827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3186918827
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2241254885
Short name T937
Test name
Test status
Simulation time 97872466950 ps
CPU time 846.37 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:26:16 PM PDT 24
Peak memory 216888 kb
Host smart-33d47e03-cfc9-4144-a710-450ab4a41b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241254885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2241254885
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3040580636
Short name T620
Test name
Test status
Simulation time 263042016495 ps
CPU time 293.92 seconds
Started Jul 25 07:12:09 PM PDT 24
Finished Jul 25 07:17:03 PM PDT 24
Peak memory 200268 kb
Host smart-9f15b203-b011-48b9-ad15-c3ed1d4fb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040580636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3040580636
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1497117927
Short name T838
Test name
Test status
Simulation time 23245210149 ps
CPU time 219.37 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 216288 kb
Host smart-2222efce-89c6-4339-be28-2f23f547e52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497117927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1497117927
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2538418656
Short name T323
Test name
Test status
Simulation time 46189960277 ps
CPU time 72.92 seconds
Started Jul 25 07:12:19 PM PDT 24
Finished Jul 25 07:13:32 PM PDT 24
Peak memory 200272 kb
Host smart-5042925d-27b7-4a3b-a900-56b13cb4ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538418656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2538418656
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3729993900
Short name T1160
Test name
Test status
Simulation time 294026324445 ps
CPU time 1416.22 seconds
Started Jul 25 07:12:18 PM PDT 24
Finished Jul 25 07:35:55 PM PDT 24
Peak memory 225028 kb
Host smart-d84a5d3b-2ed2-4c14-aa47-ebc130fc8f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729993900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3729993900
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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