Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	105362	1			T1	124		T2	4		T3	2
all_values[1]	105362	1			T1	124		T2	4		T3	2
all_values[2]	105362	1			T1	124		T2	4		T3	2
all_values[3]	105362	1			T1	124		T2	4		T3	2
all_values[4]	105362	1			T1	124		T2	4		T3	2
all_values[5]	105362	1			T1	124		T2	4		T3	2
all_values[6]	105362	1			T1	124		T2	4		T3	2
all_values[7]	105362	1			T1	124		T2	4		T3	2
all_values[8]	105362	1			T1	124		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

473862

1

T1

615

T2

16

T3

18

auto[1]

474396

1

T1

501

T2

20

T5

279

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

856919

1

T1

1005

T2

27

T3

13

auto[1]

91339

1

T1

111

T2

9

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29210	1			T1	14		T5	3		T6	2
all_values[0]	auto[0]	auto[1]	21940	1			T2	2		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	31538	1			T1	2		T5	22		T7	1
all_values[0]	auto[1]	auto[1]	22674	1			T1	108		T2	2		T5	20
all_values[1]	auto[0]	auto[0]	49732	1			T1	123		T3	2		T4	2
all_values[1]	auto[0]	auto[1]	1636	1			T5	2		T7	8		T8	6
all_values[1]	auto[1]	auto[0]	52269	1			T1	1		T2	4		T5	37
all_values[1]	auto[1]	auto[1]	1725	1			T5	2		T26	1		T13	11
all_values[2]	auto[0]	auto[0]	49102	1			T1	120		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2510	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	51341	1			T1	3		T2	2		T5	30
all_values[2]	auto[1]	auto[1]	2409	1			T5	8		T6	5		T7	9
all_values[3]	auto[0]	auto[0]	49301	1			T1	3		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	294	1			T12	2		T14	3		T11	1
all_values[3]	auto[1]	auto[0]	55460	1			T1	121		T2	4		T5	34
all_values[3]	auto[1]	auto[1]	307	1			T9	2		T10	3		T14	3
all_values[4]	auto[0]	auto[0]	53761	1			T1	109		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	435	1			T10	4		T13	5		T14	6
all_values[4]	auto[1]	auto[0]	50748	1			T1	15		T2	2		T5	47
all_values[4]	auto[1]	auto[1]	418	1			T13	17		T12	2		T14	1
all_values[5]	auto[0]	auto[0]	54371	1			T1	120		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	194	1			T14	4		T25	1		T99	4
all_values[5]	auto[1]	auto[0]	50636	1			T1	4		T6	3		T7	38
all_values[5]	auto[1]	auto[1]	161	1			T12	1		T112	6		T22	4
all_values[6]	auto[0]	auto[0]	51948	1			T1	110		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	199	1			T12	1		T14	3		T25	1
all_values[6]	auto[1]	auto[0]	53059	1			T1	14		T2	2		T5	29
all_values[6]	auto[1]	auto[1]	156	1			T14	9		T25	3		T99	1
all_values[7]	auto[0]	auto[0]	55209	1			T1	15		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	360	1			T10	5		T25	2		T99	3
all_values[7]	auto[1]	auto[0]	49483	1			T1	109		T5	15		T6	15
all_values[7]	auto[1]	auto[1]	310	1			T12	1		T14	2		T25	2
all_values[8]	auto[0]	auto[0]	34991	1			T7	35		T8	7		T9	1
all_values[8]	auto[0]	auto[1]	18669	1			T3	2		T4	2		T5	12
all_values[8]	auto[1]	auto[0]	34760	1			T1	122		T5	26		T6	4
all_values[8]	auto[1]	auto[1]	16942	1			T1	2		T2	4		T5	9