Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2539

1

T1

1

T2

1

T3

1

auto[UartRx]

2539

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4517	1			T1	2		T2	2		T3	2
values[1]	41	1			T25	1		T23	1		T22	1
values[2]	60	1			T36	1		T207	1		T118	1
values[3]	58	1			T25	1		T35	1		T36	2
values[4]	60	1			T12	1		T23	1		T38	1
values[5]	48	1			T25	1		T22	1		T130	1
values[6]	53	1			T12	3		T24	1		T36	1
values[7]	49	1			T24	3		T23	2		T36	2
values[8]	43	1			T37	1		T38	1		T331	1
values[9]	57	1			T12	1		T36	1		T22	1
values[10]	65	1			T12	1		T35	1		T39	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2353	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	7	1			T23	1		T332	1		T120	1
auto[UartTx]	values[2]	18	1			T36	1		T207	1		T120	1
auto[UartTx]	values[3]	18	1			T36	1		T22	1		T118	2
auto[UartTx]	values[4]	15	1			T12	1		T117	1		T207	1
auto[UartTx]	values[5]	17	1			T22	1		T321	1		T167	1
auto[UartTx]	values[6]	20	1			T12	1		T24	1		T36	1
auto[UartTx]	values[7]	19	1			T36	1		T263	2		T160	2
auto[UartTx]	values[8]	12	1			T263	1		T333	1		T334	1
auto[UartTx]	values[9]	19	1			T36	1		T38	1		T331	1
auto[UartTx]	values[10]	28	1			T12	1		T35	1		T39	1
auto[UartRx]	values[0]	2164	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	34	1			T25	1		T22	1		T39	1
auto[UartRx]	values[2]	42	1			T118	1		T321	1		T263	1
auto[UartRx]	values[3]	40	1			T25	1		T35	1		T36	1
auto[UartRx]	values[4]	45	1			T23	1		T38	1		T207	1
auto[UartRx]	values[5]	31	1			T25	1		T130	1		T170	1
auto[UartRx]	values[6]	33	1			T12	2		T38	2		T130	1
auto[UartRx]	values[7]	30	1			T24	3		T23	2		T36	1
auto[UartRx]	values[8]	31	1			T37	1		T38	1		T331	1
auto[UartRx]	values[9]	38	1			T12	1		T22	1		T39	1
auto[UartRx]	values[10]	37	1			T130	1		T332	2		T158	1