Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2473	1			T1	1		T4	1		T5	1
auto[BaudRate115200]	1991	1			T1	1		T5	2		T6	3
auto[BaudRate230400]	2006	1			T1	1		T2	2		T5	4
auto[BaudRate128Kbps]	2086	1			T1	1		T3	1		T5	3
auto[BaudRate256Kbps]	2144	1			T1	2		T2	3		T3	1
auto[BaudRate1Mbps]	1816	1			T1	1		T4	1		T5	3
auto[BaudRate1p5Mbps]	1374	1			T5	2		T7	1		T15	5

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1317	1			T7	26		T26	9		T43	8
freqs[25]	1037	1			T9	5		T10	2		T134	6
freqs[48]	817	1			T35	14		T314	7		T126	10
freqs[50]	557	1			T98	7		T52	8		T301	5
freqs[100]	1311	1			T1	7		T296	2		T17	1

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	218	1			T7	5		T26	3		T43	1
auto[BaudRate9600]	freqs[25]	202	1			T9	1		T134	2		T19	20
auto[BaudRate9600]	freqs[48]	137	1			T35	2		T314	1		T126	1
auto[BaudRate9600]	freqs[50]	105	1			T52	1		T301	3		T335	1
auto[BaudRate9600]	freqs[100]	219	1			T1	1		T37	2		T274	1
auto[BaudRate115200]	freqs[24]	182	1			T7	4		T26	3		T43	1
auto[BaudRate115200]	freqs[25]	148	1			T10	1		T260	2		T114	2
auto[BaudRate115200]	freqs[48]	120	1			T35	2		T314	1		T153	2
auto[BaudRate115200]	freqs[50]	67	1			T98	1		T336	1		T65	2
auto[BaudRate115200]	freqs[100]	192	1			T1	1		T296	1		T310	1
auto[BaudRate230400]	freqs[24]	180	1			T7	3		T26	2		T43	1
auto[BaudRate230400]	freqs[25]	160	1			T290	1		T38	3		T308	1
auto[BaudRate230400]	freqs[48]	106	1			T35	1		T314	1		T126	3
auto[BaudRate230400]	freqs[50]	71	1			T98	1		T52	1		T307	1
auto[BaudRate230400]	freqs[100]	185	1			T1	1		T17	1		T37	3
auto[BaudRate128Kbps]	freqs[24]	184	1			T7	5		T43	3		T21	10
auto[BaudRate128Kbps]	freqs[25]	141	1			T10	1		T134	1		T260	4
auto[BaudRate128Kbps]	freqs[48]	120	1			T35	2		T314	1		T126	3
auto[BaudRate128Kbps]	freqs[50]	68	1			T52	2		T335	2		T336	3
auto[BaudRate128Kbps]	freqs[100]	180	1			T1	1		T310	2		T274	1
auto[BaudRate256Kbps]	freqs[24]	218	1			T7	7		T26	1		T43	1
auto[BaudRate256Kbps]	freqs[25]	151	1			T9	2		T134	1		T260	2
auto[BaudRate256Kbps]	freqs[48]	110	1			T35	3		T314	1		T126	1
auto[BaudRate256Kbps]	freqs[50]	68	1			T98	1		T301	2		T335	1
auto[BaudRate256Kbps]	freqs[100]	168	1			T1	2		T37	1		T310	2
auto[BaudRate1Mbps]	freqs[24]	220	1			T7	1		T43	1		T44	1
auto[BaudRate1Mbps]	freqs[25]	153	1			T9	2		T134	1		T260	1
auto[BaudRate1Mbps]	freqs[48]	104	1			T35	4		T314	1		T337	1
auto[BaudRate1Mbps]	freqs[50]	97	1			T98	3		T52	2		T338	2
auto[BaudRate1Mbps]	freqs[100]	180	1			T1	1		T37	1		T274	1
auto[BaudRate1p5Mbps]	freqs[25]	82	1			T134	1		T260	1		T38	3
auto[BaudRate1p5Mbps]	freqs[48]	120	1			T314	1		T126	2		T172	3
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T98	1		T52	2		T307	1
auto[BaudRate1p5Mbps]	freqs[100]	187	1			T296	1		T37	1		T310	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded