Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28350980	1			T1	234		T2	16		T5	277
all_levels[1]	162005	1			T1	78		T2	1		T5	28
all_levels[2]	2626	1			T1	9		T5	10		T7	22
all_levels[3]	1155	1			T5	4		T6	4		T7	8
all_levels[4]	726	1			T5	3		T7	10		T15	1
all_levels[5]	523	1			T1	1		T5	1		T7	3
all_levels[6]	415	1			T1	1		T7	5		T98	2
all_levels[7]	328	1			T1	1		T6	1		T7	3
all_levels[8]	245	1			T7	4		T26	1		T43	1
all_levels[9]	277	1			T7	4		T124	1		T45	1
all_levels[10]	198	1			T1	1		T98	1		T133	1
all_levels[11]	182	1			T7	2		T133	1		T134	1
all_levels[12]	167	1			T15	1		T98	1		T133	2
all_levels[13]	168	1			T98	1		T133	1		T40	1
all_levels[14]	114	1			T7	1		T12	1		T41	1
all_levels[15]	132	1			T14	1		T41	1		T135	2
all_levels[16]	111	1			T11	1		T135	1		T21	2
all_levels[17]	94	1			T98	2		T12	1		T40	1
all_levels[18]	121	1			T1	1		T6	1		T45	1
all_levels[19]	75	1			T6	1		T43	1		T11	1
all_levels[20]	75	1			T11	1		T99	1		T136	2
all_levels[21]	69	1			T8	2		T14	1		T99	1
all_levels[22]	51	1			T11	1		T21	1		T99	2
all_levels[23]	74	1			T134	2		T21	1		T47	1
all_levels[24]	66	1			T98	1		T12	1		T11	1
all_levels[25]	68	1			T25	1		T99	1		T37	2
all_levels[26]	52	1			T133	1		T14	1		T137	2
all_levels[27]	47	1			T124	1		T43	1		T116	3
all_levels[28]	56	1			T23	1		T99	1		T47	1
all_levels[29]	52	1			T12	1		T46	1		T22	1
all_levels[30]	49	1			T8	1		T11	1		T138	3
all_levels[31]	29	1			T40	1		T54	1		T139	1
all_levels[32]	37	1			T37	1		T54	1		T140	1
all_levels[33]	31	1			T124	2		T11	1		T141	1
all_levels[34]	19	1			T124	1		T142	1		T126	1
all_levels[35]	39	1			T124	1		T143	1		T144	1
all_levels[36]	15	1			T145	1		T146	1		T147	1
all_levels[37]	17	1			T43	1		T148	2		T149	1
all_levels[38]	21	1			T150	1		T151	1		T152	1
all_levels[39]	27	1			T139	1		T153	1		T154	1
all_levels[40]	24	1			T14	1		T125	2		T151	1
all_levels[41]	16	1			T9	1		T112	1		T116	1
all_levels[42]	21	1			T143	1		T155	1		T156	1
all_levels[43]	28	1			T43	1		T157	1		T158	2
all_levels[44]	13	1			T159	1		T160	1		T161	1
all_levels[45]	16	1			T162	1		T163	1		T164	1
all_levels[46]	19	1			T7	1		T99	1		T165	2
all_levels[47]	18	1			T38	1		T141	1		T145	2
all_levels[48]	10	1			T11	1		T112	1		T166	1
all_levels[49]	7	1			T142	1		T167	1		T168	1
all_levels[50]	18	1			T11	2		T169	1		T68	1
all_levels[51]	12	1			T150	2		T170	1		T171	1
all_levels[52]	8	1			T99	1		T112	1		T155	1
all_levels[53]	10	1			T125	1		T112	1		T172	1
all_levels[54]	11	1			T125	1		T173	1		T174	1
all_levels[55]	14	1			T125	3		T139	1		T175	1
all_levels[56]	16	1			T8	1		T172	5		T176	1
all_levels[57]	6	1			T177	2		T178	1		T179	2
all_levels[58]	10	1			T166	1		T171	1		T180	2
all_levels[59]	9	1			T126	1		T181	1		T182	3
all_levels[60]	7	1			T183	1		T184	1		T176	1
all_levels[61]	9	1			T137	1		T116	1		T156	2
all_levels[62]	7	1			T185	2		T186	1		T87	1
all_levels[63]	7	1			T43	1		T38	1		T187	1
all_levels[64]	85	1			T9	1		T11	1		T21	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28517129

1

T1

320

T2

17

T5

323

auto[1]

4808

1

T1

6

T6

9

T8

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28346648	1			T1	228		T2	16		T5	277
all_levels[0]	auto[1]	4332	1			T1	6		T6	8		T8	7
all_levels[1]	auto[0]	161916	1			T1	78		T2	1		T5	28
all_levels[1]	auto[1]	89	1			T134	2		T14	1		T11	1
all_levels[2]	auto[0]	2603	1			T1	9		T5	10		T7	22
all_levels[2]	auto[1]	23	1			T47	2		T123	2		T188	1
all_levels[3]	auto[0]	1127	1			T5	4		T6	3		T7	8
all_levels[3]	auto[1]	28	1			T6	1		T133	2		T123	1
all_levels[4]	auto[0]	705	1			T5	3		T7	10		T15	1
all_levels[4]	auto[1]	21	1			T41	1		T11	1		T189	1
all_levels[5]	auto[0]	512	1			T1	1		T5	1		T7	3
all_levels[5]	auto[1]	11	1			T68	1		T190	2		T149	1
all_levels[6]	auto[0]	408	1			T1	1		T7	5		T98	2
all_levels[6]	auto[1]	7	1			T125	2		T191	1		T192	2
all_levels[7]	auto[0]	318	1			T1	1		T6	1		T7	3
all_levels[7]	auto[1]	10	1			T193	1		T194	1		T195	1
all_levels[8]	auto[0]	241	1			T7	4		T26	1		T43	1
all_levels[8]	auto[1]	4	1			T188	1		T153	1		T196	1
all_levels[9]	auto[0]	264	1			T7	4		T124	1		T45	1
all_levels[9]	auto[1]	13	1			T41	1		T197	4		T198	1
all_levels[10]	auto[0]	188	1			T1	1		T98	1		T133	1
all_levels[10]	auto[1]	10	1			T199	3		T200	1		T201	1
all_levels[11]	auto[0]	164	1			T7	2		T133	1		T134	1
all_levels[11]	auto[1]	18	1			T188	2		T152	2		T202	1
all_levels[12]	auto[0]	150	1			T15	1		T98	1		T133	1
all_levels[12]	auto[1]	17	1			T133	1		T150	2		T203	1
all_levels[13]	auto[0]	153	1			T98	1		T133	1		T40	1
all_levels[13]	auto[1]	15	1			T204	1		T205	1		T206	1
all_levels[14]	auto[0]	108	1			T7	1		T12	1		T41	1
all_levels[14]	auto[1]	6	1			T207	1		T208	1		T209	1
all_levels[15]	auto[0]	116	1			T14	1		T41	1		T135	2
all_levels[15]	auto[1]	16	1			T137	1		T123	2		T151	1
all_levels[16]	auto[0]	104	1			T11	1		T135	1		T21	2
all_levels[16]	auto[1]	7	1			T210	1		T211	1		T196	2
all_levels[17]	auto[0]	88	1			T98	2		T12	1		T40	1
all_levels[17]	auto[1]	6	1			T212	1		T213	2		T205	1
all_levels[18]	auto[0]	110	1			T1	1		T6	1		T45	1
all_levels[18]	auto[1]	11	1			T166	2		T147	4		T214	1
all_levels[19]	auto[0]	70	1			T6	1		T43	1		T11	1
all_levels[19]	auto[1]	5	1			T215	1		T216	2		T217	2
all_levels[20]	auto[0]	67	1			T11	1		T99	1		T136	2
all_levels[20]	auto[1]	8	1			T163	2		T187	1		T167	4
all_levels[21]	auto[0]	64	1			T8	1		T14	1		T99	1
all_levels[21]	auto[1]	5	1			T8	1		T205	1		T218	3
all_levels[22]	auto[0]	45	1			T11	1		T21	1		T99	2
all_levels[22]	auto[1]	6	1			T112	1		T155	1		T130	1
all_levels[23]	auto[0]	67	1			T134	1		T21	1		T47	1
all_levels[23]	auto[1]	7	1			T134	1		T200	2		T219	1
all_levels[24]	auto[0]	55	1			T98	1		T12	1		T11	1
all_levels[24]	auto[1]	11	1			T204	1		T220	1		T215	1
all_levels[25]	auto[0]	61	1			T25	1		T99	1		T37	2
all_levels[25]	auto[1]	7	1			T221	1		T222	1		T223	1
all_levels[26]	auto[0]	49	1			T133	1		T14	1		T137	1
all_levels[26]	auto[1]	3	1			T137	1		T224	1		T225	1
all_levels[27]	auto[0]	40	1			T124	1		T43	1		T116	1
all_levels[27]	auto[1]	7	1			T116	2		T151	1		T226	1
all_levels[28]	auto[0]	53	1			T23	1		T99	1		T47	1
all_levels[28]	auto[1]	3	1			T227	2		T228	1		-	-
all_levels[29]	auto[0]	44	1			T12	1		T46	1		T22	1
all_levels[29]	auto[1]	8	1			T219	1		T229	1		T230	1
all_levels[30]	auto[0]	43	1			T8	1		T11	1		T138	1
all_levels[30]	auto[1]	6	1			T138	2		T116	2		T231	2
all_levels[31]	auto[0]	27	1			T40	1		T54	1		T139	1
all_levels[31]	auto[1]	2	1			T170	2		-	-		-	-
all_levels[32]	auto[0]	33	1			T37	1		T54	1		T140	1
all_levels[32]	auto[1]	4	1			T232	2		T71	1		T177	1
all_levels[33]	auto[0]	29	1			T124	2		T11	1		T141	1
all_levels[33]	auto[1]	2	1			T159	1		T233	1		-	-
all_levels[34]	auto[0]	16	1			T124	1		T142	1		T126	1
all_levels[34]	auto[1]	3	1			T152	1		T234	1		T235	1
all_levels[35]	auto[0]	30	1			T124	1		T143	1		T144	1
all_levels[35]	auto[1]	9	1			T173	3		T236	2		T227	1
all_levels[36]	auto[0]	15	1			T145	1		T146	1		T147	1
all_levels[37]	auto[0]	15	1			T43	1		T148	2		T149	1
all_levels[37]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[38]	auto[0]	19	1			T150	1		T151	1		T152	1
all_levels[38]	auto[1]	2	1			T182	1		T238	1		-	-
all_levels[39]	auto[0]	23	1			T139	1		T153	1		T154	1
all_levels[39]	auto[1]	4	1			T190	1		T239	1		T240	1
all_levels[40]	auto[0]	17	1			T14	1		T125	1		T151	1
all_levels[40]	auto[1]	7	1			T125	1		T241	2		T242	2
all_levels[41]	auto[0]	15	1			T9	1		T112	1		T116	1
all_levels[41]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[42]	auto[0]	15	1			T143	1		T155	1		T156	1
all_levels[42]	auto[1]	6	1			T244	1		T245	2		T246	3
all_levels[43]	auto[0]	23	1			T43	1		T157	1		T158	2
all_levels[43]	auto[1]	5	1			T247	1		T79	2		T248	1
all_levels[44]	auto[0]	13	1			T159	1		T160	1		T161	1
all_levels[45]	auto[0]	14	1			T162	1		T163	1		T164	1
all_levels[45]	auto[1]	2	1			T249	2		-	-		-	-
all_levels[46]	auto[0]	15	1			T7	1		T99	1		T165	1
all_levels[46]	auto[1]	4	1			T165	1		T250	3		-	-
all_levels[47]	auto[0]	17	1			T38	1		T141	1		T145	2
all_levels[47]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[48]	auto[0]	10	1			T11	1		T112	1		T166	1
all_levels[49]	auto[0]	7	1			T142	1		T167	1		T168	1
all_levels[50]	auto[0]	14	1			T11	1		T169	1		T68	1
all_levels[50]	auto[1]	4	1			T11	1		T252	1		T253	1
all_levels[51]	auto[0]	8	1			T150	1		T170	1		T171	1
all_levels[51]	auto[1]	4	1			T150	1		T254	2		T255	1
all_levels[52]	auto[0]	8	1			T99	1		T112	1		T155	1
all_levels[53]	auto[0]	9	1			T125	1		T112	1		T172	1
all_levels[53]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[54]	auto[0]	11	1			T125	1		T173	1		T174	1
all_levels[55]	auto[0]	13	1			T125	2		T139	1		T175	1
all_levels[55]	auto[1]	1	1			T125	1		-	-		-	-
all_levels[56]	auto[0]	12	1			T8	1		T172	1		T176	1
all_levels[56]	auto[1]	4	1			T172	4		-	-		-	-
all_levels[57]	auto[0]	5	1			T177	1		T178	1		T179	2
all_levels[57]	auto[1]	1	1			T177	1		-	-		-	-
all_levels[58]	auto[0]	8	1			T166	1		T171	1		T180	1
all_levels[58]	auto[1]	2	1			T180	1		T257	1		-	-
all_levels[59]	auto[0]	6	1			T126	1		T181	1		T182	1
all_levels[59]	auto[1]	3	1			T182	2		T83	1		-	-
all_levels[60]	auto[0]	6	1			T183	1		T184	1		T176	1
all_levels[60]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[61]	auto[0]	8	1			T137	1		T116	1		T156	2
all_levels[61]	auto[1]	1	1			T64	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T185	2		T186	1		T87	1
all_levels[62]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[63]	auto[0]	7	1			T43	1		T38	1		T187	1
all_levels[64]	auto[0]	74	1			T9	1		T11	1		T21	1
all_levels[64]	auto[1]	11	1			T137	1		T260	3		T172	2