Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	105362	1			T1	124		T2	4		T3	2
all_pins[1]	105362	1			T1	124		T2	4		T3	2
all_pins[2]	105362	1			T1	124		T2	4		T3	2
all_pins[3]	105362	1			T1	124		T2	4		T3	2
all_pins[4]	105362	1			T1	124		T2	4		T3	2
all_pins[5]	105362	1			T1	124		T2	4		T3	2
all_pins[6]	105362	1			T1	124		T2	4		T3	2
all_pins[7]	105362	1			T1	124		T2	4		T3	2
all_pins[8]	105362	1			T1	124		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	902207	1			T1	1002		T2	30		T3	18
values[0x1]	46051	1			T1	114		T2	6		T5	41
transitions[0x0=>0x1]	36901	1			T1	112		T2	4		T5	31
transitions[0x1=>0x0]	36687	1			T1	112		T2	4		T5	31

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	82624	1			T1	16		T2	2		T3	2
all_pins[0]	values[0x1]	22738	1			T1	108		T2	2		T5	21
all_pins[0]	transitions[0x0=>0x1]	22108	1			T1	108		T2	2		T5	19
all_pins[0]	transitions[0x1=>0x0]	1091	1			T26	1		T14	15		T25	2
all_pins[1]	values[0x0]	103641	1			T1	124		T2	4		T3	2
all_pins[1]	values[0x1]	1721	1			T5	2		T26	1		T13	11
all_pins[1]	transitions[0x0=>0x1]	1602	1			T5	2		T26	1		T13	11
all_pins[1]	transitions[0x1=>0x0]	2340	1			T5	8		T6	5		T7	9
all_pins[2]	values[0x0]	102903	1			T1	124		T2	4		T3	2
all_pins[2]	values[0x1]	2459	1			T5	8		T6	5		T7	9
all_pins[2]	transitions[0x0=>0x1]	2385	1			T5	8		T6	5		T7	9
all_pins[2]	transitions[0x1=>0x0]	233	1			T9	2		T10	3		T14	2
all_pins[3]	values[0x0]	105055	1			T1	124		T2	4		T3	2
all_pins[3]	values[0x1]	307	1			T9	2		T10	3		T14	3
all_pins[3]	transitions[0x0=>0x1]	273	1			T9	2		T10	3		T14	3
all_pins[3]	transitions[0x1=>0x0]	384	1			T13	17		T12	2		T14	1
all_pins[4]	values[0x0]	104944	1			T1	124		T2	4		T3	2
all_pins[4]	values[0x1]	418	1			T13	17		T12	2		T14	1
all_pins[4]	transitions[0x0=>0x1]	356	1			T13	14		T12	2		T14	1
all_pins[4]	transitions[0x1=>0x0]	166	1			T10	1		T12	1		T17	2
all_pins[5]	values[0x0]	105134	1			T1	124		T2	4		T3	2
all_pins[5]	values[0x1]	228	1			T10	1		T13	3		T12	1
all_pins[5]	transitions[0x0=>0x1]	202	1			T10	1		T13	3		T12	1
all_pins[5]	transitions[0x1=>0x0]	833	1			T1	4		T7	9		T9	2
all_pins[6]	values[0x0]	104503	1			T1	120		T2	4		T3	2
all_pins[6]	values[0x1]	859	1			T1	4		T7	9		T9	2
all_pins[6]	transitions[0x0=>0x1]	819	1			T1	4		T7	9		T9	2
all_pins[6]	transitions[0x1=>0x0]	270	1			T12	1		T14	2		T25	2
all_pins[7]	values[0x0]	105052	1			T1	124		T2	4		T3	2
all_pins[7]	values[0x1]	310	1			T12	1		T14	2		T25	2
all_pins[7]	transitions[0x0=>0x1]	170	1			T12	1		T14	1		T25	1
all_pins[7]	transitions[0x1=>0x0]	16871	1			T1	2		T2	4		T5	10
all_pins[8]	values[0x0]	88351	1			T1	122		T3	2		T4	2
all_pins[8]	values[0x1]	17011	1			T1	2		T2	4		T5	10
all_pins[8]	transitions[0x0=>0x1]	8986	1			T2	2		T5	2		T6	4
all_pins[8]	transitions[0x1=>0x0]	14499	1			T1	106		T5	13		T6	1