Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7972968	1			T1	1		T2	4		T5	112
all_levels[1]	1106093	1			T1	298		T5	65		T7	30
all_levels[2]	424057	1			T2	2		T5	31		T7	17
all_levels[3]	344246	1			T1	9		T2	2		T5	9
all_levels[4]	424826	1			T5	9		T7	17		T15	12315
all_levels[5]	192877	1			T5	3		T7	4		T8	3
all_levels[6]	239615	1			T2	1		T5	3		T7	3
all_levels[7]	186017	1			T5	27		T6	1		T7	4
all_levels[8]	220275	1			T5	1		T8	2		T15	124
all_levels[9]	226071	1			T7	2		T15	140		T26	5
all_levels[10]	275119	1			T2	4		T5	2		T7	2
all_levels[11]	172674	1			T1	12		T7	1		T15	149
all_levels[12]	223140	1			T9	1		T15	127		T26	4
all_levels[13]	438857	1			T5	20		T8	1		T15	122
all_levels[14]	410884	1			T5	1		T7	2		T15	126
all_levels[15]	336848	1			T5	5		T7	74		T8	3
all_levels[16]	325210	1			T6	2		T7	6		T10	980
all_levels[17]	239267	1			T7	2		T15	101		T134	2
all_levels[18]	233048	1			T5	1		T15	124		T45	1
all_levels[19]	196290	1			T5	2		T15	122		T26	4
all_levels[20]	345956	1			T7	3		T15	102		T45	2
all_levels[21]	288791	1			T7	1		T15	125		T45	3
all_levels[22]	222987	1			T5	2		T8	30		T15	128
all_levels[23]	495318	1			T15	127		T26	5		T134	2
all_levels[24]	196140	1			T7	2		T15	128		T26	8
all_levels[25]	223811	1			T7	2		T15	127		T26	5
all_levels[26]	509843	1			T5	3		T7	2		T15	109
all_levels[27]	151170	1			T5	23		T15	119		T45	2
all_levels[28]	271594	1			T5	2		T15	131		T45	1
all_levels[29]	175124	1			T9	7		T15	131		T14	2594
all_levels[30]	164955	1			T5	1		T7	2		T15	129
all_levels[31]	434562	1			T15	2747		T26	4		T45	1
all_levels[32]	10852894	1			T1	7		T2	5		T5	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28517129

1

T1

320

T2

17

T5

323

auto[1]

4398

1

T1

7

T2

1

T6

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7970462	1			T2	4		T5	112		T6	11
all_levels[0]	auto[1]	2506	1			T1	1		T6	3		T8	1
all_levels[1]	auto[0]	1105758	1			T1	297		T5	65		T7	30
all_levels[1]	auto[1]	335	1			T1	1		T26	1		T98	1
all_levels[2]	auto[0]	424012	1			T2	2		T5	31		T7	17
all_levels[2]	auto[1]	45	1			T14	1		T282	3		T112	2
all_levels[3]	auto[0]	344111	1			T1	8		T2	2		T5	9
all_levels[3]	auto[1]	135	1			T1	1		T15	9		T282	4
all_levels[4]	auto[0]	424794	1			T5	9		T7	17		T15	12315
all_levels[4]	auto[1]	32	1			T134	1		T144	1		T287	2
all_levels[5]	auto[0]	192837	1			T5	3		T7	4		T8	2
all_levels[5]	auto[1]	40	1			T8	1		T123	1		T340	1
all_levels[6]	auto[0]	239584	1			T2	1		T5	3		T7	3
all_levels[6]	auto[1]	31	1			T139	1		T341	3		T202	1
all_levels[7]	auto[0]	185939	1			T5	27		T6	1		T7	4
all_levels[7]	auto[1]	78	1			T15	1		T22	1		T127	7
all_levels[8]	auto[0]	220252	1			T5	1		T8	2		T15	124
all_levels[8]	auto[1]	23	1			T125	1		T278	1		T189	2
all_levels[9]	auto[0]	226035	1			T7	2		T15	140		T26	5
all_levels[9]	auto[1]	36	1			T125	2		T232	3		T285	1
all_levels[10]	auto[0]	275100	1			T2	4		T5	2		T7	2
all_levels[10]	auto[1]	19	1			T112	1		T189	1		T340	1
all_levels[11]	auto[0]	172654	1			T1	11		T7	1		T15	149
all_levels[11]	auto[1]	20	1			T1	1		T14	1		T38	1
all_levels[12]	auto[0]	223111	1			T9	1		T15	127		T26	4
all_levels[12]	auto[1]	29	1			T183	4		T116	1		T52	1
all_levels[13]	auto[0]	438817	1			T5	20		T8	1		T15	122
all_levels[13]	auto[1]	40	1			T41	1		T281	1		T292	1
all_levels[14]	auto[0]	410870	1			T5	1		T7	2		T15	126
all_levels[14]	auto[1]	14	1			T38	1		T130	1		T153	2
all_levels[15]	auto[0]	336693	1			T5	5		T7	74		T8	2
all_levels[15]	auto[1]	155	1			T8	1		T10	12		T193	1
all_levels[16]	auto[0]	325190	1			T6	2		T7	6		T10	980
all_levels[16]	auto[1]	20	1			T200	1		T342	1		T343	2
all_levels[17]	auto[0]	239234	1			T7	2		T15	101		T134	1
all_levels[17]	auto[1]	33	1			T134	1		T41	2		T138	2
all_levels[18]	auto[0]	233020	1			T5	1		T15	124		T45	1
all_levels[18]	auto[1]	28	1			T11	1		T321	1		T68	1
all_levels[19]	auto[0]	196271	1			T5	2		T15	122		T26	4
all_levels[19]	auto[1]	19	1			T40	1		T43	1		T344	2
all_levels[20]	auto[0]	345942	1			T7	3		T15	102		T45	2
all_levels[20]	auto[1]	14	1			T150	2		T345	1		T346	1
all_levels[21]	auto[0]	288760	1			T7	1		T15	125		T45	2
all_levels[21]	auto[1]	31	1			T45	1		T40	1		T289	1
all_levels[22]	auto[0]	222973	1			T5	2		T8	29		T15	128
all_levels[22]	auto[1]	14	1			T8	1		T202	2		T166	1
all_levels[23]	auto[0]	495304	1			T15	127		T26	5		T134	2
all_levels[23]	auto[1]	14	1			T41	1		T347	1		T229	3
all_levels[24]	auto[0]	196117	1			T7	2		T15	128		T26	8
all_levels[24]	auto[1]	23	1			T124	1		T137	1		T136	1
all_levels[25]	auto[0]	223794	1			T7	2		T15	127		T26	5
all_levels[25]	auto[1]	17	1			T116	2		T123	2		T265	2
all_levels[26]	auto[0]	509829	1			T5	3		T7	2		T15	109
all_levels[26]	auto[1]	14	1			T48	1		T142	1		T348	1
all_levels[27]	auto[0]	151141	1			T5	23		T15	119		T45	2
all_levels[27]	auto[1]	29	1			T112	1		T47	1		T213	2
all_levels[28]	auto[0]	271567	1			T5	2		T15	131		T45	1
all_levels[28]	auto[1]	27	1			T285	2		T207	1		T146	1
all_levels[29]	auto[0]	175112	1			T9	7		T15	131		T14	2594
all_levels[29]	auto[1]	12	1			T212	1		T303	1		T330	1
all_levels[30]	auto[0]	164936	1			T5	1		T7	2		T15	129
all_levels[30]	auto[1]	19	1			T133	2		T203	1		T153	1
all_levels[31]	auto[0]	434532	1			T15	2747		T26	4		T45	1
all_levels[31]	auto[1]	30	1			T125	1		T260	3		T271	1
all_levels[32]	auto[0]	10852378	1			T1	4		T2	4		T5	1
all_levels[32]	auto[1]	516	1			T1	3		T2	1		T6	4