Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	758	1			T12	4		T14	14		T25	7
all_values[1]	758	1			T12	4		T14	14		T25	7
all_values[2]	758	1			T12	4		T14	14		T25	7
all_values[3]	758	1			T12	4		T14	14		T25	7
all_values[4]	758	1			T12	4		T14	14		T25	7
all_values[5]	758	1			T12	4		T14	14		T25	7
all_values[6]	758	1			T12	4		T14	14		T25	7
all_values[7]	758	1			T12	4		T14	14		T25	7
all_values[8]	758	1			T12	4		T14	14		T25	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3750

1

T12

14

T14

67

T25

30

auto[1]

3072

1

T12

22

T14

59

T25

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2247

1

T12

14

T14

37

T25

16

auto[1]

4575

1

T12

22

T14

89

T25

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3996

1

T12

24

T14

75

T25

29

auto[1]

2826

1

T12

12

T14

51

T25

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	219	1			T14	3		T25	2		T36	4
all_values[0]	auto[0]	auto[1]	auto[1]	219	1			T12	3		T14	6		T25	2
all_values[0]	auto[1]	auto[0]	auto[1]	180	1			T14	3		T25	1		T99	4
all_values[0]	auto[1]	auto[1]	auto[1]	140	1			T12	1		T14	2		T25	2
all_values[1]	auto[0]	auto[0]	auto[0]	245	1			T12	1		T14	5		T25	2
all_values[1]	auto[0]	auto[1]	auto[0]	204	1			T14	3		T25	1		T99	2
all_values[1]	auto[1]	auto[0]	auto[1]	178	1			T12	3		T14	3		T25	1
all_values[1]	auto[1]	auto[1]	auto[1]	131	1			T14	3		T25	3		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T12	2		T14	4		T25	3
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T14	2		T99	2		T112	1
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T12	2		T112	1		T22	1
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T14	1		T22	3		T130	1
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T14	3		T25	2		T99	1
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T14	4		T25	2		T99	2
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T14	5		T99	6		T36	3
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T12	1		T14	2		T25	1
all_values[3]	auto[0]	auto[1]	auto[0]	123	1			T12	1		T25	1		T99	1
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T14	2		T36	1		T112	1
all_values[3]	auto[1]	auto[0]	auto[1]	165	1			T12	2		T14	3		T25	3
all_values[3]	auto[1]	auto[1]	auto[1]	144	1			T14	2		T25	2		T36	2
all_values[4]	auto[0]	auto[0]	auto[0]	171	1			T14	2		T112	1		T22	4
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T14	3		T99	1		T112	2
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T12	2		T14	1		T25	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T12	1		T14	1		T22	1
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T14	6		T25	2		T99	2
all_values[4]	auto[1]	auto[1]	auto[1]	136	1			T12	1		T14	1		T25	4
all_values[5]	auto[0]	auto[0]	auto[0]	154	1			T14	4		T25	2		T36	6
all_values[5]	auto[0]	auto[0]	auto[1]	93	1			T14	3		T25	1		T99	1
all_values[5]	auto[0]	auto[1]	auto[0]	140	1			T12	2		T14	4		T25	2
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T12	1		T112	3		T22	2
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T14	3		T25	1		T99	3
all_values[5]	auto[1]	auto[1]	auto[1]	126	1			T12	1		T25	1		T112	2
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T12	1		T25	1		T99	2
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T14	2		T99	1		T22	2
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T12	1		T25	2		T36	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T12	1		T14	4		T25	1
all_values[6]	auto[1]	auto[0]	auto[1]	175	1			T12	1		T14	3		T25	1
all_values[6]	auto[1]	auto[1]	auto[1]	141	1			T14	5		T25	2		T99	1
all_values[7]	auto[0]	auto[0]	auto[0]	150	1			T12	1		T14	2		T36	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T25	1		T99	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T12	1		T14	7		T25	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T14	1		T25	1		T99	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T25	2		T99	2		T36	1
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T12	2		T14	4		T25	2
all_values[8]	auto[0]	auto[0]	auto[1]	257	1			T12	2		T14	3		T25	3
all_values[8]	auto[0]	auto[1]	auto[1]	191	1			T12	1		T14	5		T25	1
all_values[8]	auto[1]	auto[0]	auto[1]	162	1			T14	3		T25	1		T99	1
all_values[8]	auto[1]	auto[1]	auto[1]	148	1			T12	1		T14	3		T25	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal