Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.62


Total test records in report: 1318
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T1256 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.6113928 Jul 26 06:36:07 PM PDT 24 Jul 26 06:36:08 PM PDT 24 260236156 ps
T1257 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2780310688 Jul 26 06:36:10 PM PDT 24 Jul 26 06:36:11 PM PDT 24 48624576 ps
T1258 /workspace/coverage/cover_reg_top/39.uart_intr_test.1049519672 Jul 26 06:36:40 PM PDT 24 Jul 26 06:36:41 PM PDT 24 48046363 ps
T1259 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4239187762 Jul 26 06:36:09 PM PDT 24 Jul 26 06:36:10 PM PDT 24 41498879 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3141930115 Jul 26 06:36:08 PM PDT 24 Jul 26 06:36:10 PM PDT 24 347947038 ps
T1261 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.694646355 Jul 26 06:36:04 PM PDT 24 Jul 26 06:36:05 PM PDT 24 15880485 ps
T1262 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.419358988 Jul 26 06:36:20 PM PDT 24 Jul 26 06:36:21 PM PDT 24 24221077 ps
T1263 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1834576332 Jul 26 06:36:21 PM PDT 24 Jul 26 06:36:22 PM PDT 24 35823575 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_tl_errors.139764413 Jul 26 06:36:26 PM PDT 24 Jul 26 06:36:27 PM PDT 24 194770570 ps
T1265 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1642787834 Jul 26 06:36:09 PM PDT 24 Jul 26 06:36:10 PM PDT 24 31393627 ps
T1266 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1639239727 Jul 26 06:36:04 PM PDT 24 Jul 26 06:36:05 PM PDT 24 98740267 ps
T1267 /workspace/coverage/cover_reg_top/35.uart_intr_test.1169506687 Jul 26 06:36:40 PM PDT 24 Jul 26 06:36:41 PM PDT 24 15362992 ps
T1268 /workspace/coverage/cover_reg_top/10.uart_intr_test.1921676403 Jul 26 06:36:15 PM PDT 24 Jul 26 06:36:16 PM PDT 24 45993725 ps
T1269 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.810004989 Jul 26 06:36:25 PM PDT 24 Jul 26 06:36:26 PM PDT 24 22146894 ps
T1270 /workspace/coverage/cover_reg_top/19.uart_intr_test.989314604 Jul 26 06:36:37 PM PDT 24 Jul 26 06:36:37 PM PDT 24 12472253 ps
T1271 /workspace/coverage/cover_reg_top/30.uart_intr_test.472395120 Jul 26 06:36:42 PM PDT 24 Jul 26 06:36:43 PM PDT 24 22577795 ps
T103 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3988275167 Jul 26 06:36:27 PM PDT 24 Jul 26 06:36:29 PM PDT 24 189968974 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3116803508 Jul 26 06:36:10 PM PDT 24 Jul 26 06:36:11 PM PDT 24 292377679 ps
T1273 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1821268077 Jul 26 06:36:25 PM PDT 24 Jul 26 06:36:26 PM PDT 24 66502627 ps
T1274 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3804756391 Jul 26 06:36:26 PM PDT 24 Jul 26 06:36:28 PM PDT 24 32932583 ps
T1275 /workspace/coverage/cover_reg_top/23.uart_intr_test.663282938 Jul 26 06:36:33 PM PDT 24 Jul 26 06:36:34 PM PDT 24 40738073 ps
T1276 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3846659327 Jul 26 06:36:16 PM PDT 24 Jul 26 06:36:17 PM PDT 24 130495295 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1388345876 Jul 26 06:36:06 PM PDT 24 Jul 26 06:36:07 PM PDT 24 115418771 ps
T1278 /workspace/coverage/cover_reg_top/14.uart_intr_test.180819009 Jul 26 06:36:27 PM PDT 24 Jul 26 06:36:28 PM PDT 24 26156679 ps
T1279 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3259007540 Jul 26 06:36:14 PM PDT 24 Jul 26 06:36:16 PM PDT 24 773389478 ps
T1280 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3006369302 Jul 26 06:36:23 PM PDT 24 Jul 26 06:36:24 PM PDT 24 44518406 ps
T1281 /workspace/coverage/cover_reg_top/20.uart_intr_test.1067281936 Jul 26 06:36:34 PM PDT 24 Jul 26 06:36:34 PM PDT 24 23395713 ps
T1282 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1958808996 Jul 26 06:36:24 PM PDT 24 Jul 26 06:36:25 PM PDT 24 31054329 ps
T1283 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.39860700 Jul 26 06:36:28 PM PDT 24 Jul 26 06:36:29 PM PDT 24 89087565 ps
T1284 /workspace/coverage/cover_reg_top/41.uart_intr_test.3335146980 Jul 26 06:36:43 PM PDT 24 Jul 26 06:36:44 PM PDT 24 13332391 ps
T1285 /workspace/coverage/cover_reg_top/32.uart_intr_test.3595175542 Jul 26 06:36:44 PM PDT 24 Jul 26 06:36:44 PM PDT 24 38553611 ps
T1286 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.689526944 Jul 26 06:36:22 PM PDT 24 Jul 26 06:36:24 PM PDT 24 123732212 ps
T1287 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.589036634 Jul 26 06:36:26 PM PDT 24 Jul 26 06:36:26 PM PDT 24 22299588 ps
T1288 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1898976685 Jul 26 06:36:27 PM PDT 24 Jul 26 06:36:28 PM PDT 24 35311988 ps
T1289 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3955718592 Jul 26 06:36:03 PM PDT 24 Jul 26 06:36:05 PM PDT 24 87304641 ps
T77 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3850006613 Jul 26 06:36:00 PM PDT 24 Jul 26 06:36:03 PM PDT 24 56845727 ps
T1290 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2334110886 Jul 26 06:36:28 PM PDT 24 Jul 26 06:36:29 PM PDT 24 64637648 ps
T1291 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2987392383 Jul 26 06:36:03 PM PDT 24 Jul 26 06:36:05 PM PDT 24 401350609 ps
T1292 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3286576262 Jul 26 06:36:18 PM PDT 24 Jul 26 06:36:19 PM PDT 24 32742904 ps
T1293 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1174222036 Jul 26 06:36:34 PM PDT 24 Jul 26 06:36:35 PM PDT 24 15525954 ps
T1294 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2911843441 Jul 26 06:36:03 PM PDT 24 Jul 26 06:36:04 PM PDT 24 65521498 ps
T1295 /workspace/coverage/cover_reg_top/44.uart_intr_test.3296623706 Jul 26 06:36:39 PM PDT 24 Jul 26 06:36:39 PM PDT 24 122179069 ps
T1296 /workspace/coverage/cover_reg_top/3.uart_intr_test.2260120925 Jul 26 06:36:03 PM PDT 24 Jul 26 06:36:04 PM PDT 24 21463579 ps
T1297 /workspace/coverage/cover_reg_top/19.uart_tl_errors.551684798 Jul 26 06:36:34 PM PDT 24 Jul 26 06:36:36 PM PDT 24 279487349 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.876363351 Jul 26 06:36:20 PM PDT 24 Jul 26 06:36:21 PM PDT 24 138478172 ps
T1299 /workspace/coverage/cover_reg_top/22.uart_intr_test.3805461271 Jul 26 06:36:33 PM PDT 24 Jul 26 06:36:33 PM PDT 24 14133338 ps
T1300 /workspace/coverage/cover_reg_top/42.uart_intr_test.2304630945 Jul 26 06:36:42 PM PDT 24 Jul 26 06:36:43 PM PDT 24 56187106 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1973438608 Jul 26 06:36:31 PM PDT 24 Jul 26 06:36:32 PM PDT 24 62192563 ps
T1302 /workspace/coverage/cover_reg_top/7.uart_intr_test.1366512134 Jul 26 06:36:11 PM PDT 24 Jul 26 06:36:12 PM PDT 24 53794314 ps
T108 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1195888256 Jul 26 06:36:10 PM PDT 24 Jul 26 06:36:11 PM PDT 24 79188278 ps
T1303 /workspace/coverage/cover_reg_top/4.uart_tl_errors.771070460 Jul 26 06:36:13 PM PDT 24 Jul 26 06:36:14 PM PDT 24 37634183 ps
T1304 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2142632244 Jul 26 06:36:06 PM PDT 24 Jul 26 06:36:06 PM PDT 24 16246479 ps
T1305 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3969730303 Jul 26 06:36:21 PM PDT 24 Jul 26 06:36:22 PM PDT 24 397434477 ps
T78 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3063913793 Jul 26 06:36:18 PM PDT 24 Jul 26 06:36:19 PM PDT 24 140236442 ps
T106 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1800419646 Jul 26 06:36:24 PM PDT 24 Jul 26 06:36:25 PM PDT 24 224544272 ps
T1306 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2608628110 Jul 26 06:36:13 PM PDT 24 Jul 26 06:36:14 PM PDT 24 14051571 ps
T1307 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2770987156 Jul 26 06:36:05 PM PDT 24 Jul 26 06:36:06 PM PDT 24 60894441 ps
T1308 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.748174579 Jul 26 06:36:01 PM PDT 24 Jul 26 06:36:04 PM PDT 24 1034346054 ps
T1309 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3503610162 Jul 26 06:36:26 PM PDT 24 Jul 26 06:36:27 PM PDT 24 16029531 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1800340958 Jul 26 06:36:34 PM PDT 24 Jul 26 06:36:35 PM PDT 24 116456946 ps
T1311 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1269729305 Jul 26 06:36:20 PM PDT 24 Jul 26 06:36:21 PM PDT 24 24105409 ps
T1312 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3883420578 Jul 26 06:36:12 PM PDT 24 Jul 26 06:36:13 PM PDT 24 37943759 ps
T1313 /workspace/coverage/cover_reg_top/15.uart_intr_test.127884205 Jul 26 06:36:26 PM PDT 24 Jul 26 06:36:27 PM PDT 24 22138650 ps
T1314 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1130482021 Jul 26 06:36:25 PM PDT 24 Jul 26 06:36:27 PM PDT 24 205719344 ps
T1315 /workspace/coverage/cover_reg_top/40.uart_intr_test.1928444647 Jul 26 06:36:46 PM PDT 24 Jul 26 06:36:47 PM PDT 24 45165908 ps
T1316 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2269795468 Jul 26 06:36:35 PM PDT 24 Jul 26 06:36:36 PM PDT 24 46915640 ps
T1317 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4072030028 Jul 26 06:36:10 PM PDT 24 Jul 26 06:36:11 PM PDT 24 18662939 ps
T1318 /workspace/coverage/cover_reg_top/49.uart_intr_test.2627171318 Jul 26 06:36:40 PM PDT 24 Jul 26 06:36:41 PM PDT 24 19060785 ps

Test location /workspace/coverage/default/2.uart_fifo_reset.2359323466
Short name T6
Test name
Test status
Simulation time 66262254600 ps
CPU time 35.99 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:39:52 PM PDT 24
Peak memory 200088 kb
Host smart-b1f765e6-5a69-47c4-b9db-591eb6d95e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359323466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2359323466
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2854102728
Short name T36
Test name
Test status
Simulation time 862821327984 ps
CPU time 624.3 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:54:48 PM PDT 24
Peak memory 216700 kb
Host smart-3eac50c5-ecd2-49cc-be72-cede644c5440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854102728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2854102728
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.593173782
Short name T11
Test name
Test status
Simulation time 437184289329 ps
CPU time 994.79 seconds
Started Jul 26 06:44:15 PM PDT 24
Finished Jul 26 07:00:50 PM PDT 24
Peak memory 208472 kb
Host smart-d33bffd3-656c-4992-9e73-ff30f006bf59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593173782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.593173782
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all.3402980064
Short name T21
Test name
Test status
Simulation time 325187687857 ps
CPU time 216.94 seconds
Started Jul 26 06:42:15 PM PDT 24
Finished Jul 26 06:45:52 PM PDT 24
Peak memory 200184 kb
Host smart-9d55d21b-cb32-42a7-97df-7dc54852b47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402980064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3402980064
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all.2885259502
Short name T7
Test name
Test status
Simulation time 420532221473 ps
CPU time 213.27 seconds
Started Jul 26 06:44:07 PM PDT 24
Finished Jul 26 06:47:41 PM PDT 24
Peak memory 200112 kb
Host smart-39721812-2b23-42b1-a784-05096c8f6fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885259502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2885259502
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.3926089622
Short name T99
Test name
Test status
Simulation time 225270547048 ps
CPU time 544.88 seconds
Started Jul 26 06:44:03 PM PDT 24
Finished Jul 26 06:53:08 PM PDT 24
Peak memory 200144 kb
Host smart-c3eecf53-e661-4acc-9bd2-e29c9259d640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926089622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3926089622
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3024106026
Short name T130
Test name
Test status
Simulation time 210552673499 ps
CPU time 560.09 seconds
Started Jul 26 06:46:37 PM PDT 24
Finished Jul 26 06:55:57 PM PDT 24
Peak memory 228000 kb
Host smart-540736b4-b016-44ed-98ce-b002b1a51649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024106026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3024106026
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.739047401
Short name T33
Test name
Test status
Simulation time 35741525 ps
CPU time 0.79 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:39:10 PM PDT 24
Peak memory 218328 kb
Host smart-73caeee6-be81-408b-b44a-b452863fe231
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739047401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.739047401
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2755397758
Short name T23
Test name
Test status
Simulation time 37439476731 ps
CPU time 426.97 seconds
Started Jul 26 06:43:05 PM PDT 24
Finished Jul 26 06:50:12 PM PDT 24
Peak memory 216740 kb
Host smart-63e8ed85-4812-467e-a33c-aa9d189c2fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755397758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2755397758
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3074653520
Short name T207
Test name
Test status
Simulation time 518275997759 ps
CPU time 879.73 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 224872 kb
Host smart-1c895f7e-13ed-4db3-9027-8f8967dc5a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074653520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3074653520
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1800585025
Short name T163
Test name
Test status
Simulation time 142803365258 ps
CPU time 420.17 seconds
Started Jul 26 06:46:19 PM PDT 24
Finished Jul 26 06:53:19 PM PDT 24
Peak memory 216804 kb
Host smart-c9d6e39f-f0fa-4d52-80ec-b2d6f8a27f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800585025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1800585025
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3817273360
Short name T26
Test name
Test status
Simulation time 268742424781 ps
CPU time 205.28 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:47:27 PM PDT 24
Peak memory 200168 kb
Host smart-d43210bb-ceda-48d9-86c9-9bc8ecd050d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817273360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3817273360
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1840451648
Short name T59
Test name
Test status
Simulation time 109884299209 ps
CPU time 991.38 seconds
Started Jul 26 06:44:00 PM PDT 24
Finished Jul 26 07:00:32 PM PDT 24
Peak memory 210888 kb
Host smart-f31f312d-ba04-49f0-a8fa-190246d1e335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840451648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1840451648
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2348612074
Short name T12
Test name
Test status
Simulation time 50222657044 ps
CPU time 583.06 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:55:02 PM PDT 24
Peak memory 216824 kb
Host smart-0a6cd265-ea42-4489-88fb-da076639c501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348612074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2348612074
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.2950557143
Short name T112
Test name
Test status
Simulation time 503198142178 ps
CPU time 310.44 seconds
Started Jul 26 06:40:06 PM PDT 24
Finished Jul 26 06:45:17 PM PDT 24
Peak memory 216220 kb
Host smart-fd6af192-cf51-45e9-8f6f-fd7cf36092b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950557143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2950557143
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.913764581
Short name T105
Test name
Test status
Simulation time 133555556 ps
CPU time 1.35 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 200264 kb
Host smart-ded7be06-b3e2-4fe9-9434-505d93bd022a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913764581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.913764581
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.801691060
Short name T170
Test name
Test status
Simulation time 166505661587 ps
CPU time 1620.22 seconds
Started Jul 26 06:46:10 PM PDT 24
Finished Jul 26 07:13:10 PM PDT 24
Peak memory 226312 kb
Host smart-5bc5d093-b8e6-4350-9734-5d80972b1cc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801691060 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.801691060
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_intr.923636769
Short name T127
Test name
Test status
Simulation time 46674821896 ps
CPU time 68.99 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:43:22 PM PDT 24
Peak memory 200036 kb
Host smart-f4639177-3eeb-4584-88f5-1ec18d0d0a34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923636769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.923636769
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3561726742
Short name T275
Test name
Test status
Simulation time 91982561669 ps
CPU time 35.76 seconds
Started Jul 26 06:43:54 PM PDT 24
Finished Jul 26 06:44:30 PM PDT 24
Peak memory 200092 kb
Host smart-18f6ec47-7144-4d8e-8b9f-05e489546531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561726742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3561726742
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_alert_test.2853871905
Short name T424
Test name
Test status
Simulation time 52758505 ps
CPU time 0.57 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:40:21 PM PDT 24
Peak memory 195560 kb
Host smart-e3a425ce-1167-4a3b-8c84-a0289bfd73ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853871905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2853871905
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2884140519
Short name T285
Test name
Test status
Simulation time 95173647719 ps
CPU time 172.06 seconds
Started Jul 26 06:46:03 PM PDT 24
Finished Jul 26 06:48:55 PM PDT 24
Peak memory 200136 kb
Host smart-d2796589-7d0c-4ef1-849b-4bfae5ec7403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884140519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2884140519
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3412554403
Short name T38
Test name
Test status
Simulation time 167112336884 ps
CPU time 372.6 seconds
Started Jul 26 06:46:28 PM PDT 24
Finished Jul 26 06:52:41 PM PDT 24
Peak memory 216576 kb
Host smart-cfe8cc79-ec4f-48bb-be44-49e0192a4cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412554403 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3412554403
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.4023743610
Short name T8
Test name
Test status
Simulation time 585580457636 ps
CPU time 175.03 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:51:14 PM PDT 24
Peak memory 200132 kb
Host smart-c607159b-1d1e-4fbc-aca7-8d25fa1809af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023743610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4023743610
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_noise_filter.343461103
Short name T65
Test name
Test status
Simulation time 122579805934 ps
CPU time 104.65 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:40:54 PM PDT 24
Peak memory 199456 kb
Host smart-41c365cb-9292-404d-b3c0-5a7822d74e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343461103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.343461103
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2725548066
Short name T37
Test name
Test status
Simulation time 31978507394 ps
CPU time 285.51 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:44:16 PM PDT 24
Peak memory 216704 kb
Host smart-cbbefe30-c984-4d27-9730-c8c7437ed111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725548066 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2725548066
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3064178967
Short name T74
Test name
Test status
Simulation time 423291973 ps
CPU time 2.13 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:14 PM PDT 24
Peak memory 198544 kb
Host smart-2fdb5687-02c4-44f1-bb8d-2379087fec2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064178967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3064178967
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3001959977
Short name T93
Test name
Test status
Simulation time 46226247 ps
CPU time 0.58 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 196360 kb
Host smart-e6d7b098-ea61-4909-9c9f-22387f60f68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001959977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3001959977
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.545833942
Short name T125
Test name
Test status
Simulation time 35538047883 ps
CPU time 26.83 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:25 PM PDT 24
Peak memory 200116 kb
Host smart-66b5f0b3-330e-4e58-a59e-c959d667f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545833942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.545833942
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_full.779845889
Short name T126
Test name
Test status
Simulation time 131374856707 ps
CPU time 124.26 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:45:00 PM PDT 24
Peak memory 200112 kb
Host smart-7c12395d-444e-49bb-9fc2-8fba1679eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779845889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.779845889
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_stress_all.1042849384
Short name T514
Test name
Test status
Simulation time 285451212226 ps
CPU time 653.75 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:52:17 PM PDT 24
Peak memory 208496 kb
Host smart-570abd3a-5502-47fb-ac12-01828d591c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042849384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1042849384
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all.301971203
Short name T15
Test name
Test status
Simulation time 272026702282 ps
CPU time 1091.25 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 200204 kb
Host smart-97eed255-358a-480a-b095-23ad680e9d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301971203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.301971203
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.729999790
Short name T150
Test name
Test status
Simulation time 227986841442 ps
CPU time 41.82 seconds
Started Jul 26 06:46:48 PM PDT 24
Finished Jul 26 06:47:30 PM PDT 24
Peak memory 200204 kb
Host smart-d7f8e4f3-0eb6-4ac0-9630-8503b5d1b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729999790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.729999790
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3664466603
Short name T321
Test name
Test status
Simulation time 209397794163 ps
CPU time 560.54 seconds
Started Jul 26 06:46:13 PM PDT 24
Finished Jul 26 06:55:34 PM PDT 24
Peak memory 225008 kb
Host smart-72eaf031-101b-46ff-a22b-47cd52834ac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664466603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3664466603
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4096099336
Short name T156
Test name
Test status
Simulation time 275912616588 ps
CPU time 208.88 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:42:39 PM PDT 24
Peak memory 200088 kb
Host smart-a501f2bf-6466-43c0-8fe9-29c0afea10ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096099336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4096099336
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.447897256
Short name T190
Test name
Test status
Simulation time 57169307019 ps
CPU time 23.42 seconds
Started Jul 26 06:40:15 PM PDT 24
Finished Jul 26 06:40:38 PM PDT 24
Peak memory 200192 kb
Host smart-0b6b726e-d702-4104-b2d6-a0a450672415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447897256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.447897256
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2593606541
Short name T182
Test name
Test status
Simulation time 178887960291 ps
CPU time 69.61 seconds
Started Jul 26 06:47:57 PM PDT 24
Finished Jul 26 06:49:06 PM PDT 24
Peak memory 200124 kb
Host smart-daeb4581-2e37-41b9-8d32-4413a56be149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593606541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2593606541
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3218104703
Short name T101
Test name
Test status
Simulation time 626520506 ps
CPU time 1.25 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 200216 kb
Host smart-91b05ce3-8b69-47e8-83af-d0bf76e8cac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218104703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3218104703
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.286806823
Short name T200
Test name
Test status
Simulation time 87620309142 ps
CPU time 46.45 seconds
Started Jul 26 06:48:11 PM PDT 24
Finished Jul 26 06:48:57 PM PDT 24
Peak memory 200060 kb
Host smart-44dc36d0-7df4-43b3-b555-5201c9c1bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286806823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.286806823
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1208021123
Short name T279
Test name
Test status
Simulation time 183720878053 ps
CPU time 1363.34 seconds
Started Jul 26 06:43:33 PM PDT 24
Finished Jul 26 07:06:17 PM PDT 24
Peak memory 200116 kb
Host smart-f289c1f8-4a11-4ba5-ba11-2992236b99bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208021123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1208021123
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1800419646
Short name T106
Test name
Test status
Simulation time 224544272 ps
CPU time 0.92 seconds
Started Jul 26 06:36:24 PM PDT 24
Finished Jul 26 06:36:25 PM PDT 24
Peak memory 199812 kb
Host smart-4108e1e1-66c8-4120-a2b8-862c86ea1792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800419646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1800419646
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4153844614
Short name T177
Test name
Test status
Simulation time 28805246036 ps
CPU time 47.87 seconds
Started Jul 26 06:47:28 PM PDT 24
Finished Jul 26 06:48:16 PM PDT 24
Peak memory 199908 kb
Host smart-6a4f466e-57cf-4134-b8af-67e250c5c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153844614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4153844614
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2905673412
Short name T204
Test name
Test status
Simulation time 24491967196 ps
CPU time 39.28 seconds
Started Jul 26 06:47:39 PM PDT 24
Finished Jul 26 06:48:19 PM PDT 24
Peak memory 200184 kb
Host smart-e29646ff-6da3-4893-985c-9f96121f5a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905673412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2905673412
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3792506588
Short name T166
Test name
Test status
Simulation time 180095573009 ps
CPU time 320.33 seconds
Started Jul 26 06:47:24 PM PDT 24
Finished Jul 26 06:52:45 PM PDT 24
Peak memory 200144 kb
Host smart-8bc8a3dd-b37d-4971-a131-690348c547ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792506588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3792506588
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3255827983
Short name T259
Test name
Test status
Simulation time 96251556811 ps
CPU time 144.65 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:50:34 PM PDT 24
Peak memory 200116 kb
Host smart-526afc08-de01-4ea1-b45f-00d977b9db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255827983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3255827983
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.2822135763
Short name T175
Test name
Test status
Simulation time 83124091161 ps
CPU time 69.1 seconds
Started Jul 26 06:45:07 PM PDT 24
Finished Jul 26 06:46:17 PM PDT 24
Peak memory 200184 kb
Host smart-04f2dd3f-d24a-4f98-9ca4-8dcab3943ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822135763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2822135763
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3993019299
Short name T142
Test name
Test status
Simulation time 81739650943 ps
CPU time 142.19 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:48:01 PM PDT 24
Peak memory 200116 kb
Host smart-08381224-419d-4a7e-8501-9557b9748054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993019299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3993019299
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1558317496
Short name T202
Test name
Test status
Simulation time 62189173349 ps
CPU time 111.39 seconds
Started Jul 26 06:46:40 PM PDT 24
Finished Jul 26 06:48:32 PM PDT 24
Peak memory 200188 kb
Host smart-27f3d741-7cc0-4bab-9356-c69a2b4f3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558317496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1558317496
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.237543573
Short name T41
Test name
Test status
Simulation time 31495977761 ps
CPU time 54.11 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:42:06 PM PDT 24
Peak memory 200120 kb
Host smart-c0256c41-73ac-41da-8f07-e80d8dd0c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237543573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.237543573
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1100423577
Short name T227
Test name
Test status
Simulation time 21486388626 ps
CPU time 28.48 seconds
Started Jul 26 06:47:21 PM PDT 24
Finished Jul 26 06:47:50 PM PDT 24
Peak memory 200136 kb
Host smart-e0da5b73-d5a8-4526-8719-62200a33fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100423577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1100423577
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1849499725
Short name T158
Test name
Test status
Simulation time 374305088610 ps
CPU time 735.01 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:53:39 PM PDT 24
Peak memory 216640 kb
Host smart-0916fdf4-6f65-413f-a2b5-9eeea785cdc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849499725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1849499725
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3265003756
Short name T1151
Test name
Test status
Simulation time 18399112985 ps
CPU time 21.89 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:42:17 PM PDT 24
Peak memory 200132 kb
Host smart-5b28297c-1e26-43da-8faa-56855e624a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265003756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3265003756
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.498067948
Short name T1
Test name
Test status
Simulation time 107209685848 ps
CPU time 153.21 seconds
Started Jul 26 06:47:46 PM PDT 24
Finished Jul 26 06:50:19 PM PDT 24
Peak memory 200164 kb
Host smart-5b6b768b-9f7d-41ab-a298-4a5b36259ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498067948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.498067948
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2308393360
Short name T116
Test name
Test status
Simulation time 167854228714 ps
CPU time 286.83 seconds
Started Jul 26 06:48:18 PM PDT 24
Finished Jul 26 06:53:05 PM PDT 24
Peak memory 200204 kb
Host smart-f25143fa-1ad8-484f-91fd-0d89bd1de7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308393360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2308393360
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.2579100119
Short name T235
Test name
Test status
Simulation time 207124679708 ps
CPU time 74.71 seconds
Started Jul 26 06:45:48 PM PDT 24
Finished Jul 26 06:47:03 PM PDT 24
Peak memory 200128 kb
Host smart-cdd0082b-b0de-40fc-b66b-76d8a4a0f9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579100119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2579100119
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2564504924
Short name T525
Test name
Test status
Simulation time 33628480829 ps
CPU time 27.9 seconds
Started Jul 26 06:39:06 PM PDT 24
Finished Jul 26 06:39:34 PM PDT 24
Peak memory 200144 kb
Host smart-82c078e1-f5ad-4b25-ac6e-00e1f221df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564504924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2564504924
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1415589870
Short name T640
Test name
Test status
Simulation time 532052497927 ps
CPU time 836.39 seconds
Started Jul 26 06:39:14 PM PDT 24
Finished Jul 26 06:53:11 PM PDT 24
Peak memory 216788 kb
Host smart-e22b4344-fce0-4a06-8a9f-f526cda3bb52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415589870 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1415589870
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.741681296
Short name T244
Test name
Test status
Simulation time 61427212291 ps
CPU time 109.9 seconds
Started Jul 26 06:46:40 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 200184 kb
Host smart-a9e4b832-641c-4bf1-b73e-ac6c452e5aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741681296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.741681296
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3977576788
Short name T196
Test name
Test status
Simulation time 158133047248 ps
CPU time 106.99 seconds
Started Jul 26 06:46:40 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 200124 kb
Host smart-876f337c-6e13-451a-8a4e-d6fc3f2a977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977576788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3977576788
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.3227921408
Short name T445
Test name
Test status
Simulation time 273289939834 ps
CPU time 803.54 seconds
Started Jul 26 06:40:46 PM PDT 24
Finished Jul 26 06:54:10 PM PDT 24
Peak memory 200144 kb
Host smart-74c8f54b-c9ad-4676-81ba-9b23f7bcb553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227921408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3227921408
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4281483312
Short name T258
Test name
Test status
Simulation time 133715237119 ps
CPU time 181.41 seconds
Started Jul 26 06:47:00 PM PDT 24
Finished Jul 26 06:50:02 PM PDT 24
Peak memory 200136 kb
Host smart-a6e1b3e2-3bab-4ffd-8be8-b1de623e6ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281483312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4281483312
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.175492451
Short name T257
Test name
Test status
Simulation time 11448214749 ps
CPU time 19.05 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:47:23 PM PDT 24
Peak memory 200184 kb
Host smart-353954c8-3393-4c0b-9146-8baaa9c7b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175492451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.175492451
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.518041189
Short name T137
Test name
Test status
Simulation time 73820203941 ps
CPU time 50.51 seconds
Started Jul 26 06:47:16 PM PDT 24
Finished Jul 26 06:48:07 PM PDT 24
Peak memory 200156 kb
Host smart-20f7cce0-dd94-4ce7-accb-cad08ef055eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518041189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.518041189
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1357624401
Short name T249
Test name
Test status
Simulation time 9489431250 ps
CPU time 23.07 seconds
Started Jul 26 06:47:26 PM PDT 24
Finished Jul 26 06:47:50 PM PDT 24
Peak memory 200112 kb
Host smart-7a4fb927-6036-474c-a53d-03444fb404cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357624401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1357624401
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3002218600
Short name T572
Test name
Test status
Simulation time 34950633714 ps
CPU time 44.9 seconds
Started Jul 26 06:47:28 PM PDT 24
Finished Jul 26 06:48:13 PM PDT 24
Peak memory 199888 kb
Host smart-24192959-b6bd-4467-ae31-4dd0ab0662ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002218600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3002218600
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2028323145
Short name T237
Test name
Test status
Simulation time 137421451204 ps
CPU time 47.03 seconds
Started Jul 26 06:47:31 PM PDT 24
Finished Jul 26 06:48:19 PM PDT 24
Peak memory 200072 kb
Host smart-887a175b-d1d1-4bb0-aa3f-3567a6311f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028323145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2028323145
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1335410526
Short name T217
Test name
Test status
Simulation time 39195981479 ps
CPU time 16.92 seconds
Started Jul 26 06:47:42 PM PDT 24
Finished Jul 26 06:47:59 PM PDT 24
Peak memory 200168 kb
Host smart-2773c674-76cc-459c-a1b2-961318942994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335410526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1335410526
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2273961970
Short name T64
Test name
Test status
Simulation time 15830557451 ps
CPU time 28.03 seconds
Started Jul 26 06:47:48 PM PDT 24
Finished Jul 26 06:48:16 PM PDT 24
Peak memory 200192 kb
Host smart-ca4af866-c89e-443f-9ddd-e2d8ba848675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273961970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2273961970
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3826193843
Short name T251
Test name
Test status
Simulation time 16489434099 ps
CPU time 13.59 seconds
Started Jul 26 06:47:48 PM PDT 24
Finished Jul 26 06:48:02 PM PDT 24
Peak memory 200120 kb
Host smart-0e296f22-8259-488d-81e6-355d9a7ecf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826193843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3826193843
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.234440146
Short name T250
Test name
Test status
Simulation time 32528115947 ps
CPU time 14.77 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:13 PM PDT 24
Peak memory 200164 kb
Host smart-fcdfa5d3-e971-4c5a-8777-fb64feb3552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234440146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.234440146
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1746177649
Short name T256
Test name
Test status
Simulation time 47968403885 ps
CPU time 499.74 seconds
Started Jul 26 06:45:53 PM PDT 24
Finished Jul 26 06:54:13 PM PDT 24
Peak memory 225104 kb
Host smart-f24bac20-0822-4913-b696-53a18b36576c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746177649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1746177649
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1247978277
Short name T159
Test name
Test status
Simulation time 39571212245 ps
CPU time 67.05 seconds
Started Jul 26 06:45:54 PM PDT 24
Finished Jul 26 06:47:01 PM PDT 24
Peak memory 200200 kb
Host smart-d07feea7-7f1e-4d94-864e-46be183a11ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247978277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1247978277
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2079999271
Short name T243
Test name
Test status
Simulation time 71367924555 ps
CPU time 185.54 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 06:49:07 PM PDT 24
Peak memory 213940 kb
Host smart-b7298c3c-a350-4d26-94e9-00ded00f43d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079999271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2079999271
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2279617870
Short name T172
Test name
Test status
Simulation time 20669299221 ps
CPU time 16.52 seconds
Started Jul 26 06:46:31 PM PDT 24
Finished Jul 26 06:46:47 PM PDT 24
Peak memory 200216 kb
Host smart-ffed367c-d2b8-4c2b-bbec-e1bb564e40bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279617870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2279617870
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.694646355
Short name T1261
Test name
Test status
Simulation time 15880485 ps
CPU time 0.65 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 196420 kb
Host smart-d6ee0b6f-7b8d-4399-83dc-95d9dbb09d6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694646355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.694646355
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2142632244
Short name T1304
Test name
Test status
Simulation time 16246479 ps
CPU time 0.64 seconds
Started Jul 26 06:36:06 PM PDT 24
Finished Jul 26 06:36:06 PM PDT 24
Peak memory 196264 kb
Host smart-f083b78f-fb5c-4c4d-944c-1d51dd14376c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142632244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2142632244
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4049002541
Short name T1228
Test name
Test status
Simulation time 140240493 ps
CPU time 0.63 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 197956 kb
Host smart-03812ae6-ef8f-4f76-97c0-fa66ee416dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049002541 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.4049002541
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3162768422
Short name T1197
Test name
Test status
Simulation time 53932436 ps
CPU time 0.59 seconds
Started Jul 26 06:36:05 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 195236 kb
Host smart-ef2eef15-981b-4656-85c9-d0dd920207fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162768422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3162768422
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2911843441
Short name T1294
Test name
Test status
Simulation time 65521498 ps
CPU time 0.65 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 196700 kb
Host smart-1884157f-b3ba-4795-9538-a951aae3afc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911843441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2911843441
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2677948716
Short name T1213
Test name
Test status
Simulation time 302186702 ps
CPU time 1.89 seconds
Started Jul 26 06:35:57 PM PDT 24
Finished Jul 26 06:35:59 PM PDT 24
Peak memory 200924 kb
Host smart-c05195c1-f93a-45d5-89e8-aeb25c30c233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677948716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2677948716
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1430336609
Short name T131
Test name
Test status
Simulation time 92119554 ps
CPU time 1.37 seconds
Started Jul 26 06:35:58 PM PDT 24
Finished Jul 26 06:35:59 PM PDT 24
Peak memory 200128 kb
Host smart-609d2f99-0fa9-4a22-8294-262b312e8d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430336609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1430336609
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1639239727
Short name T1266
Test name
Test status
Simulation time 98740267 ps
CPU time 0.76 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 196956 kb
Host smart-146bf93a-93dd-4e71-9786-8a482384fbf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639239727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1639239727
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2987392383
Short name T1291
Test name
Test status
Simulation time 401350609 ps
CPU time 1.51 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 198556 kb
Host smart-1eed9f99-e191-4d50-b437-d081e36bb8d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987392383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2987392383
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3534605165
Short name T73
Test name
Test status
Simulation time 55679220 ps
CPU time 0.59 seconds
Started Jul 26 06:36:05 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 196284 kb
Host smart-1a65859f-d489-4a1b-b895-eb7be20bb121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534605165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3534605165
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2666371012
Short name T1217
Test name
Test status
Simulation time 114606848 ps
CPU time 0.87 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 200688 kb
Host smart-ee2e8619-c462-45c0-bbb4-6190e06d636e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666371012 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2666371012
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2549246983
Short name T89
Test name
Test status
Simulation time 13871058 ps
CPU time 0.6 seconds
Started Jul 26 06:36:06 PM PDT 24
Finished Jul 26 06:36:06 PM PDT 24
Peak memory 196276 kb
Host smart-c958b7e3-fff4-481f-8ec2-346fc4f6712f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549246983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2549246983
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1368164436
Short name T1214
Test name
Test status
Simulation time 35606490 ps
CPU time 0.55 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 195272 kb
Host smart-f6cc8b7a-f290-4081-93a1-1134a21bca41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368164436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1368164436
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3085089794
Short name T91
Test name
Test status
Simulation time 28097707 ps
CPU time 0.8 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 197500 kb
Host smart-4e49503b-ad65-481a-a996-7067671c1b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085089794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3085089794
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1388345876
Short name T1277
Test name
Test status
Simulation time 115418771 ps
CPU time 1.19 seconds
Started Jul 26 06:36:06 PM PDT 24
Finished Jul 26 06:36:07 PM PDT 24
Peak memory 200940 kb
Host smart-e7d6ea2f-339e-46aa-94d2-43b5095082d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388345876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1388345876
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3955718592
Short name T1289
Test name
Test status
Simulation time 87304641 ps
CPU time 1.31 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 200252 kb
Host smart-41a920fd-62aa-4691-824f-872aa037098c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955718592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3955718592
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.876363351
Short name T1298
Test name
Test status
Simulation time 138478172 ps
CPU time 0.74 seconds
Started Jul 26 06:36:20 PM PDT 24
Finished Jul 26 06:36:21 PM PDT 24
Peak memory 199504 kb
Host smart-6a31184a-a2e8-4152-b454-eaa2d0aa5ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876363351 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.876363351
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3286576262
Short name T1292
Test name
Test status
Simulation time 32742904 ps
CPU time 0.58 seconds
Started Jul 26 06:36:18 PM PDT 24
Finished Jul 26 06:36:19 PM PDT 24
Peak memory 196276 kb
Host smart-05712bad-6c0a-48e1-8f56-c1b372b56bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286576262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3286576262
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1921676403
Short name T1268
Test name
Test status
Simulation time 45993725 ps
CPU time 0.58 seconds
Started Jul 26 06:36:15 PM PDT 24
Finished Jul 26 06:36:16 PM PDT 24
Peak memory 195216 kb
Host smart-31b034c7-02b2-4ba0-91e5-60a895e9c7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921676403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1921676403
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.419358988
Short name T1262
Test name
Test status
Simulation time 24221077 ps
CPU time 0.73 seconds
Started Jul 26 06:36:20 PM PDT 24
Finished Jul 26 06:36:21 PM PDT 24
Peak memory 197876 kb
Host smart-514a1648-ea01-46ac-9316-5aa5ab546d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419358988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.419358988
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2274467742
Short name T1253
Test name
Test status
Simulation time 380601612 ps
CPU time 2.18 seconds
Started Jul 26 06:36:17 PM PDT 24
Finished Jul 26 06:36:19 PM PDT 24
Peak memory 200920 kb
Host smart-e9669459-a851-4cc9-b602-c1e8c78045e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274467742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2274467742
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1103411813
Short name T1233
Test name
Test status
Simulation time 61593017 ps
CPU time 0.99 seconds
Started Jul 26 06:36:20 PM PDT 24
Finished Jul 26 06:36:21 PM PDT 24
Peak memory 199792 kb
Host smart-6b643291-4286-41f9-ba21-1da3b77ac316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103411813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1103411813
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1821268077
Short name T1273
Test name
Test status
Simulation time 66502627 ps
CPU time 0.72 seconds
Started Jul 26 06:36:25 PM PDT 24
Finished Jul 26 06:36:26 PM PDT 24
Peak memory 199804 kb
Host smart-fa35bb5b-105d-4737-bcb1-9e7fbd64d90e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821268077 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1821268077
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.848906779
Short name T1220
Test name
Test status
Simulation time 16274496 ps
CPU time 0.63 seconds
Started Jul 26 06:36:23 PM PDT 24
Finished Jul 26 06:36:24 PM PDT 24
Peak memory 196632 kb
Host smart-22c9f92b-0482-4262-8db8-30da42a9860e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848906779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.848906779
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2154542069
Short name T1191
Test name
Test status
Simulation time 41814356 ps
CPU time 0.55 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 195284 kb
Host smart-eae3f556-bee7-48b3-bd3c-d611efd07360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154542069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2154542069
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1834576332
Short name T1263
Test name
Test status
Simulation time 35823575 ps
CPU time 0.65 seconds
Started Jul 26 06:36:21 PM PDT 24
Finished Jul 26 06:36:22 PM PDT 24
Peak memory 196348 kb
Host smart-1ba48dd0-5b94-47e3-a525-c7f5eb16b441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834576332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1834576332
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4193669207
Short name T1248
Test name
Test status
Simulation time 65143041 ps
CPU time 1.41 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 200872 kb
Host smart-45eab9a0-728a-4bba-8697-a4cbc5517e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193669207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4193669207
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1186030174
Short name T1219
Test name
Test status
Simulation time 34747403 ps
CPU time 1.08 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 200728 kb
Host smart-d6cb1b6f-466c-454c-9f4a-38ef4b2b9df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186030174 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1186030174
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2134164052
Short name T1254
Test name
Test status
Simulation time 46211450 ps
CPU time 0.6 seconds
Started Jul 26 06:36:25 PM PDT 24
Finished Jul 26 06:36:26 PM PDT 24
Peak memory 196304 kb
Host smart-567f919f-13f9-43c9-a1a1-ff6952e42c69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134164052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2134164052
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.544347113
Short name T1204
Test name
Test status
Simulation time 12768323 ps
CPU time 0.58 seconds
Started Jul 26 06:36:21 PM PDT 24
Finished Jul 26 06:36:21 PM PDT 24
Peak memory 195292 kb
Host smart-23ccc9c7-8eb0-49f3-8e67-55c91a79c469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544347113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.544347113
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.810004989
Short name T1269
Test name
Test status
Simulation time 22146894 ps
CPU time 0.66 seconds
Started Jul 26 06:36:25 PM PDT 24
Finished Jul 26 06:36:26 PM PDT 24
Peak memory 196480 kb
Host smart-351e1dea-0d65-4314-9a21-0a1c0328204e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810004989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.810004989
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1958808996
Short name T1282
Test name
Test status
Simulation time 31054329 ps
CPU time 0.92 seconds
Started Jul 26 06:36:24 PM PDT 24
Finished Jul 26 06:36:25 PM PDT 24
Peak memory 200472 kb
Host smart-8e760591-f2dc-450d-a002-38765ac732b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958808996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1958808996
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.689526944
Short name T1286
Test name
Test status
Simulation time 123732212 ps
CPU time 1.27 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:24 PM PDT 24
Peak memory 200176 kb
Host smart-2191cd03-e424-45e6-9022-0b47caf80993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689526944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.689526944
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3969730303
Short name T1305
Test name
Test status
Simulation time 397434477 ps
CPU time 0.91 seconds
Started Jul 26 06:36:21 PM PDT 24
Finished Jul 26 06:36:22 PM PDT 24
Peak memory 200688 kb
Host smart-5a7d0b68-b8c0-44a0-8e0e-c760a3744a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969730303 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3969730303
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3762252895
Short name T1247
Test name
Test status
Simulation time 15575786 ps
CPU time 0.59 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 196320 kb
Host smart-06b06c9e-914b-4767-8553-1361dd1f9ce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762252895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3762252895
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2555240498
Short name T1212
Test name
Test status
Simulation time 28610246 ps
CPU time 0.56 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 195156 kb
Host smart-ab8a4c38-c3ca-4db7-bd36-f35463c9c19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555240498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2555240498
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.561909701
Short name T1207
Test name
Test status
Simulation time 21340710 ps
CPU time 0.62 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:22 PM PDT 24
Peak memory 196644 kb
Host smart-ff455ad3-a3a4-47db-9a15-92af1f1d7443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561909701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.561909701
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1130482021
Short name T1314
Test name
Test status
Simulation time 205719344 ps
CPU time 1.97 seconds
Started Jul 26 06:36:25 PM PDT 24
Finished Jul 26 06:36:27 PM PDT 24
Peak memory 200908 kb
Host smart-14cd98d8-a316-4af2-a6df-385829a47890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130482021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1130482021
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3375354922
Short name T1229
Test name
Test status
Simulation time 181154644 ps
CPU time 0.98 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 199676 kb
Host smart-b7e07405-f511-49e3-95b4-65ef98054dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375354922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3375354922
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3503610162
Short name T1309
Test name
Test status
Simulation time 16029531 ps
CPU time 0.68 seconds
Started Jul 26 06:36:26 PM PDT 24
Finished Jul 26 06:36:27 PM PDT 24
Peak memory 198480 kb
Host smart-9ba06c65-f238-4d1f-8db5-8b3c7eaff712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503610162 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3503610162
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1898976685
Short name T1288
Test name
Test status
Simulation time 35311988 ps
CPU time 0.58 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 196268 kb
Host smart-3c162883-a152-411c-8e95-e99a94dc273e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898976685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1898976685
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.180819009
Short name T1278
Test name
Test status
Simulation time 26156679 ps
CPU time 0.58 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 195240 kb
Host smart-d804644f-65dc-413a-b89f-e22a462f9e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180819009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.180819009
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.586219120
Short name T90
Test name
Test status
Simulation time 53208356 ps
CPU time 0.71 seconds
Started Jul 26 06:36:30 PM PDT 24
Finished Jul 26 06:36:31 PM PDT 24
Peak memory 197848 kb
Host smart-c8225b19-37ed-4432-a392-807c87521f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586219120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.586219120
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3006369302
Short name T1280
Test name
Test status
Simulation time 44518406 ps
CPU time 1.14 seconds
Started Jul 26 06:36:23 PM PDT 24
Finished Jul 26 06:36:24 PM PDT 24
Peak memory 200644 kb
Host smart-ff0981ba-afab-4a03-b5ae-49be472f7785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006369302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3006369302
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.39860700
Short name T1283
Test name
Test status
Simulation time 89087565 ps
CPU time 1.31 seconds
Started Jul 26 06:36:28 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 200052 kb
Host smart-dd8a06db-a998-4290-9482-127439969c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.39860700
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3097938090
Short name T1196
Test name
Test status
Simulation time 99134152 ps
CPU time 0.66 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 198556 kb
Host smart-38940a3d-da7d-4545-bac1-69eb6aaa9755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097938090 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3097938090
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1151646259
Short name T1201
Test name
Test status
Simulation time 16514515 ps
CPU time 0.64 seconds
Started Jul 26 06:36:31 PM PDT 24
Finished Jul 26 06:36:32 PM PDT 24
Peak memory 196268 kb
Host smart-8455cdc9-2345-488d-a5d0-cf16148050d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151646259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1151646259
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.127884205
Short name T1313
Test name
Test status
Simulation time 22138650 ps
CPU time 0.58 seconds
Started Jul 26 06:36:26 PM PDT 24
Finished Jul 26 06:36:27 PM PDT 24
Peak memory 195284 kb
Host smart-76869618-2045-49be-a4fb-2f9e96b4df13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127884205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.127884205
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4027662733
Short name T92
Test name
Test status
Simulation time 114478846 ps
CPU time 0.74 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 198432 kb
Host smart-9a0c8d32-2533-40c6-882c-19b0738ddee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027662733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4027662733
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.139764413
Short name T1264
Test name
Test status
Simulation time 194770570 ps
CPU time 1.03 seconds
Started Jul 26 06:36:26 PM PDT 24
Finished Jul 26 06:36:27 PM PDT 24
Peak memory 200680 kb
Host smart-22d5cf97-6f7b-4bd1-ba5e-37d73e76eda5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139764413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.139764413
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4075682406
Short name T1242
Test name
Test status
Simulation time 28284824 ps
CPU time 1.34 seconds
Started Jul 26 06:36:29 PM PDT 24
Finished Jul 26 06:36:30 PM PDT 24
Peak memory 200960 kb
Host smart-1cdb806a-305d-416b-955e-7444946824d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075682406 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4075682406
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1165811088
Short name T1246
Test name
Test status
Simulation time 17668351 ps
CPU time 0.62 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 196304 kb
Host smart-b7240b65-c8b9-4018-96e5-ec2b52ec495b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165811088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1165811088
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.419876716
Short name T1186
Test name
Test status
Simulation time 19414061 ps
CPU time 0.65 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 195248 kb
Host smart-8a7cec65-c838-4e09-be97-86eb7789f70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419876716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.419876716
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2811709683
Short name T1206
Test name
Test status
Simulation time 48832064 ps
CPU time 0.63 seconds
Started Jul 26 06:36:28 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 196464 kb
Host smart-d0293c1a-9c64-4642-83e5-24a60f1bb0ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811709683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2811709683
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3804756391
Short name T1274
Test name
Test status
Simulation time 32932583 ps
CPU time 1.63 seconds
Started Jul 26 06:36:26 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 200888 kb
Host smart-692bb673-5cbf-48c3-be27-6d138dd26b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804756391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3804756391
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3631213577
Short name T1244
Test name
Test status
Simulation time 40819996 ps
CPU time 1.01 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:28 PM PDT 24
Peak memory 199472 kb
Host smart-d40051b1-45d2-4ddb-a926-0519d063701c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631213577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3631213577
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.589036634
Short name T1287
Test name
Test status
Simulation time 22299588 ps
CPU time 0.73 seconds
Started Jul 26 06:36:26 PM PDT 24
Finished Jul 26 06:36:26 PM PDT 24
Peak memory 200096 kb
Host smart-c5b03c33-bedb-40fc-bca1-8db5425e4a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589036634 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.589036634
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2334110886
Short name T1290
Test name
Test status
Simulation time 64637648 ps
CPU time 0.6 seconds
Started Jul 26 06:36:28 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 196276 kb
Host smart-360122f0-91c0-4fbf-a8bf-f1f67b6636a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334110886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2334110886
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3596699131
Short name T1203
Test name
Test status
Simulation time 37904250 ps
CPU time 0.64 seconds
Started Jul 26 06:36:31 PM PDT 24
Finished Jul 26 06:36:32 PM PDT 24
Peak memory 195284 kb
Host smart-52f66a7a-4e58-47a6-a236-d95b040edff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596699131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3596699131
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2598492134
Short name T97
Test name
Test status
Simulation time 14933427 ps
CPU time 0.66 seconds
Started Jul 26 06:36:29 PM PDT 24
Finished Jul 26 06:36:30 PM PDT 24
Peak memory 196824 kb
Host smart-91c615cc-4c00-45a3-b050-897549fbdd28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598492134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2598492134
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3453750858
Short name T1224
Test name
Test status
Simulation time 49612105 ps
CPU time 1.2 seconds
Started Jul 26 06:36:28 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 200968 kb
Host smart-d1bd50a8-cf8a-4b73-a6f9-a499430788f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453750858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3453750858
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3988275167
Short name T103
Test name
Test status
Simulation time 189968974 ps
CPU time 1.39 seconds
Started Jul 26 06:36:27 PM PDT 24
Finished Jul 26 06:36:29 PM PDT 24
Peak memory 200236 kb
Host smart-12627da4-8e77-429b-950d-ff904d0a7fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988275167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3988275167
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1800340958
Short name T1310
Test name
Test status
Simulation time 116456946 ps
CPU time 0.9 seconds
Started Jul 26 06:36:34 PM PDT 24
Finished Jul 26 06:36:35 PM PDT 24
Peak memory 200696 kb
Host smart-7a2c5175-21c5-4d7b-ad73-c2dc5f928a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800340958 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1800340958
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2196272887
Short name T94
Test name
Test status
Simulation time 42995812 ps
CPU time 0.56 seconds
Started Jul 26 06:36:36 PM PDT 24
Finished Jul 26 06:36:37 PM PDT 24
Peak memory 196272 kb
Host smart-42e3d05a-b9e0-4aa4-9197-f3bea9d6e713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196272887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2196272887
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2545759693
Short name T1235
Test name
Test status
Simulation time 12733052 ps
CPU time 0.61 seconds
Started Jul 26 06:36:35 PM PDT 24
Finished Jul 26 06:36:36 PM PDT 24
Peak memory 195228 kb
Host smart-8a8ed23b-c2a3-48cf-9e22-875cf1894b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545759693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2545759693
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1973438608
Short name T1301
Test name
Test status
Simulation time 62192563 ps
CPU time 0.79 seconds
Started Jul 26 06:36:31 PM PDT 24
Finished Jul 26 06:36:32 PM PDT 24
Peak memory 198072 kb
Host smart-6a760da0-c145-41ae-ac63-e3138183c504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973438608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1973438608
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2524897741
Short name T1222
Test name
Test status
Simulation time 158345543 ps
CPU time 2.07 seconds
Started Jul 26 06:36:28 PM PDT 24
Finished Jul 26 06:36:30 PM PDT 24
Peak memory 200956 kb
Host smart-bddc64f6-23f2-4ad2-8f93-b75f00937c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524897741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2524897741
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1174222036
Short name T1293
Test name
Test status
Simulation time 15525954 ps
CPU time 0.71 seconds
Started Jul 26 06:36:34 PM PDT 24
Finished Jul 26 06:36:35 PM PDT 24
Peak memory 198892 kb
Host smart-d5aa967c-96ca-4b44-a1a6-2d6cd496caee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174222036 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1174222036
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2269795468
Short name T1316
Test name
Test status
Simulation time 46915640 ps
CPU time 0.63 seconds
Started Jul 26 06:36:35 PM PDT 24
Finished Jul 26 06:36:36 PM PDT 24
Peak memory 196340 kb
Host smart-72ccf0f7-1e78-4e3e-988a-14dbe966e582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269795468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2269795468
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.989314604
Short name T1270
Test name
Test status
Simulation time 12472253 ps
CPU time 0.58 seconds
Started Jul 26 06:36:37 PM PDT 24
Finished Jul 26 06:36:37 PM PDT 24
Peak memory 195252 kb
Host smart-0dd0fba6-4209-4734-a552-da016efaf97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989314604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.989314604
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4191131219
Short name T88
Test name
Test status
Simulation time 18677622 ps
CPU time 0.74 seconds
Started Jul 26 06:36:33 PM PDT 24
Finished Jul 26 06:36:33 PM PDT 24
Peak memory 197828 kb
Host smart-1a7304ad-2a89-4cf2-98d5-5d74a5c3a567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191131219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4191131219
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.551684798
Short name T1297
Test name
Test status
Simulation time 279487349 ps
CPU time 1.24 seconds
Started Jul 26 06:36:34 PM PDT 24
Finished Jul 26 06:36:36 PM PDT 24
Peak memory 200920 kb
Host smart-f1c2745c-1476-483d-b921-13ca3ac90cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551684798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.551684798
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2701711433
Short name T104
Test name
Test status
Simulation time 185461290 ps
CPU time 1.35 seconds
Started Jul 26 06:36:36 PM PDT 24
Finished Jul 26 06:36:37 PM PDT 24
Peak memory 200280 kb
Host smart-e60bf5bb-a03f-4444-b540-810f29e45bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701711433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2701711433
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3224498113
Short name T1195
Test name
Test status
Simulation time 22258871 ps
CPU time 0.71 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 196276 kb
Host smart-f73e2c1e-08de-4361-b5a1-c30493f22c7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224498113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3224498113
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.748174579
Short name T1308
Test name
Test status
Simulation time 1034346054 ps
CPU time 2.63 seconds
Started Jul 26 06:36:01 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 198708 kb
Host smart-7a550131-0ec5-4f66-bf64-c1a2443715a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748174579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.748174579
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2971820076
Short name T1239
Test name
Test status
Simulation time 158542191 ps
CPU time 0.6 seconds
Started Jul 26 06:36:05 PM PDT 24
Finished Jul 26 06:36:06 PM PDT 24
Peak memory 196288 kb
Host smart-79b9745d-2073-4c1c-b09c-e4c6e04c97dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971820076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2971820076
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2770987156
Short name T1307
Test name
Test status
Simulation time 60894441 ps
CPU time 0.69 seconds
Started Jul 26 06:36:05 PM PDT 24
Finished Jul 26 06:36:06 PM PDT 24
Peak memory 198688 kb
Host smart-73d0d479-d7b6-4f3f-9727-c25c36353511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770987156 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2770987156
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2608628110
Short name T1306
Test name
Test status
Simulation time 14051571 ps
CPU time 0.58 seconds
Started Jul 26 06:36:13 PM PDT 24
Finished Jul 26 06:36:14 PM PDT 24
Peak memory 196324 kb
Host smart-40dc9a70-4948-4e75-aae2-78b8d2590359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608628110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2608628110
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2267389161
Short name T1188
Test name
Test status
Simulation time 17521642 ps
CPU time 0.61 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 195280 kb
Host smart-a8545809-8962-45bd-b3cc-cce6e966e29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267389161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2267389161
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3165262639
Short name T1223
Test name
Test status
Simulation time 19574171 ps
CPU time 0.75 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 197388 kb
Host smart-a0027569-a8f4-4d9e-b722-77b7b35e627a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165262639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3165262639
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2632533831
Short name T1243
Test name
Test status
Simulation time 100828008 ps
CPU time 1.26 seconds
Started Jul 26 06:36:13 PM PDT 24
Finished Jul 26 06:36:14 PM PDT 24
Peak memory 200948 kb
Host smart-cf296e6f-e4f9-4a9e-82c7-1ec85ae4988c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632533831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2632533831
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2519821109
Short name T107
Test name
Test status
Simulation time 311907177 ps
CPU time 1.36 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:05 PM PDT 24
Peak memory 200228 kb
Host smart-68289611-f0f1-463a-8a62-a8c1eb455d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519821109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2519821109
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1067281936
Short name T1281
Test name
Test status
Simulation time 23395713 ps
CPU time 0.57 seconds
Started Jul 26 06:36:34 PM PDT 24
Finished Jul 26 06:36:34 PM PDT 24
Peak memory 195312 kb
Host smart-e61dab6c-9b9f-4702-9b82-692f4e3cac5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067281936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1067281936
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.232268379
Short name T1193
Test name
Test status
Simulation time 21851770 ps
CPU time 0.56 seconds
Started Jul 26 06:36:31 PM PDT 24
Finished Jul 26 06:36:31 PM PDT 24
Peak memory 195460 kb
Host smart-4efaff8c-eac2-4324-9841-2a283fd40d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232268379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.232268379
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3805461271
Short name T1299
Test name
Test status
Simulation time 14133338 ps
CPU time 0.58 seconds
Started Jul 26 06:36:33 PM PDT 24
Finished Jul 26 06:36:33 PM PDT 24
Peak memory 195132 kb
Host smart-683d8cd4-2bde-48d5-8ed4-d16a60549f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805461271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3805461271
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.663282938
Short name T1275
Test name
Test status
Simulation time 40738073 ps
CPU time 0.59 seconds
Started Jul 26 06:36:33 PM PDT 24
Finished Jul 26 06:36:34 PM PDT 24
Peak memory 195260 kb
Host smart-8568b6c1-522d-493d-ac06-a2c515ea879c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663282938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.663282938
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4286080991
Short name T1215
Test name
Test status
Simulation time 11296279 ps
CPU time 0.57 seconds
Started Jul 26 06:36:41 PM PDT 24
Finished Jul 26 06:36:42 PM PDT 24
Peak memory 195292 kb
Host smart-b5a305e1-5bdb-418c-8644-d60ca486f494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286080991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4286080991
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2315689123
Short name T1226
Test name
Test status
Simulation time 24968982 ps
CPU time 0.6 seconds
Started Jul 26 06:36:44 PM PDT 24
Finished Jul 26 06:36:45 PM PDT 24
Peak memory 195280 kb
Host smart-149e651c-26fa-4d11-8eb5-fe09e2af59ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315689123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2315689123
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.666434710
Short name T1211
Test name
Test status
Simulation time 15448018 ps
CPU time 0.61 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:43 PM PDT 24
Peak memory 195068 kb
Host smart-9b08d373-2eb6-4f55-94e6-d3947ef474d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666434710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.666434710
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1903925637
Short name T1231
Test name
Test status
Simulation time 35660803 ps
CPU time 0.59 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195276 kb
Host smart-802673f0-bc97-4f2b-8429-3dcdee2451e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903925637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1903925637
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.186222136
Short name T1190
Test name
Test status
Simulation time 201873512 ps
CPU time 0.6 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:42 PM PDT 24
Peak memory 195260 kb
Host smart-001447e6-ac02-4822-9f65-a73d6f35dc05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186222136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.186222136
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1845011403
Short name T1209
Test name
Test status
Simulation time 50643888 ps
CPU time 0.55 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:40 PM PDT 24
Peak memory 195208 kb
Host smart-bef9644f-8bd8-4d42-9f84-86794f27ef78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845011403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1845011403
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1506157368
Short name T1245
Test name
Test status
Simulation time 112387771 ps
CPU time 0.84 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 197220 kb
Host smart-d85ca0a9-f894-4f3e-aeb0-d6236682c0ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506157368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1506157368
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3850006613
Short name T77
Test name
Test status
Simulation time 56845727 ps
CPU time 2.41 seconds
Started Jul 26 06:36:00 PM PDT 24
Finished Jul 26 06:36:03 PM PDT 24
Peak memory 199008 kb
Host smart-77a78afc-6da9-42b3-8bfb-8a571b8464bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850006613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3850006613
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2044120935
Short name T1240
Test name
Test status
Simulation time 15879184 ps
CPU time 0.59 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 196140 kb
Host smart-fa50d501-fb18-4320-9012-7d5e69eede02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044120935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2044120935
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.822456323
Short name T1237
Test name
Test status
Simulation time 105238573 ps
CPU time 0.86 seconds
Started Jul 26 06:36:13 PM PDT 24
Finished Jul 26 06:36:14 PM PDT 24
Peak memory 200560 kb
Host smart-47e84149-5db9-4016-a490-c6b06824e16f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822456323 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.822456323
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.709838514
Short name T1218
Test name
Test status
Simulation time 23955714 ps
CPU time 0.54 seconds
Started Jul 26 06:36:04 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 196284 kb
Host smart-06eda5b3-6750-406a-8d6e-012d242e7c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709838514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.709838514
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2260120925
Short name T1296
Test name
Test status
Simulation time 21463579 ps
CPU time 0.59 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 195256 kb
Host smart-b677cc44-183b-4ac8-94f5-a7a12d9bd5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260120925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2260120925
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1709985956
Short name T1199
Test name
Test status
Simulation time 22099645 ps
CPU time 0.66 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 196380 kb
Host smart-d8be7cd8-a77e-4666-ba8c-fe72eed0b1d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709985956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1709985956
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3330176546
Short name T1181
Test name
Test status
Simulation time 56607834 ps
CPU time 0.97 seconds
Started Jul 26 06:36:03 PM PDT 24
Finished Jul 26 06:36:04 PM PDT 24
Peak memory 200712 kb
Host smart-eba6074a-31ed-45df-8873-9dcab7f7e759
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330176546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3330176546
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1874557918
Short name T132
Test name
Test status
Simulation time 962278500 ps
CPU time 1.3 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 200248 kb
Host smart-c3bc49f1-7098-4569-a84c-bc4d60d550c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874557918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1874557918
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.472395120
Short name T1271
Test name
Test status
Simulation time 22577795 ps
CPU time 0.57 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:43 PM PDT 24
Peak memory 195288 kb
Host smart-f4826fd9-7313-4cf0-acab-719d96d8287f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472395120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.472395120
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1781053522
Short name T1198
Test name
Test status
Simulation time 13807365 ps
CPU time 0.59 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:43 PM PDT 24
Peak memory 195148 kb
Host smart-a2873056-c42c-49a0-b9c7-a2cd39386d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781053522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1781053522
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3595175542
Short name T1285
Test name
Test status
Simulation time 38553611 ps
CPU time 0.56 seconds
Started Jul 26 06:36:44 PM PDT 24
Finished Jul 26 06:36:44 PM PDT 24
Peak memory 195164 kb
Host smart-51da6a1c-0024-4db3-9fb2-6bed335ed8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595175542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3595175542
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3103592395
Short name T1182
Test name
Test status
Simulation time 18207743 ps
CPU time 0.61 seconds
Started Jul 26 06:36:45 PM PDT 24
Finished Jul 26 06:36:45 PM PDT 24
Peak memory 195280 kb
Host smart-992b421e-94fd-4f33-a82d-a582490ec6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103592395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3103592395
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2515996029
Short name T1216
Test name
Test status
Simulation time 118804624 ps
CPU time 0.58 seconds
Started Jul 26 06:36:38 PM PDT 24
Finished Jul 26 06:36:39 PM PDT 24
Peak memory 195288 kb
Host smart-b352b930-2e3b-4c45-9d06-1481e5a56a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515996029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2515996029
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1169506687
Short name T1267
Test name
Test status
Simulation time 15362992 ps
CPU time 0.58 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195288 kb
Host smart-0d2be741-9506-452d-976b-97ea3e313c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169506687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1169506687
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3110198923
Short name T1187
Test name
Test status
Simulation time 28350534 ps
CPU time 0.61 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:42 PM PDT 24
Peak memory 195268 kb
Host smart-9723629d-40ad-4634-af23-7c74a576f3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110198923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3110198923
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2307902316
Short name T1241
Test name
Test status
Simulation time 29244849 ps
CPU time 0.56 seconds
Started Jul 26 06:36:44 PM PDT 24
Finished Jul 26 06:36:44 PM PDT 24
Peak memory 195212 kb
Host smart-ec1dd932-08c9-49c9-8d31-b9ebb9c61e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307902316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2307902316
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4103299128
Short name T1230
Test name
Test status
Simulation time 13139776 ps
CPU time 0.57 seconds
Started Jul 26 06:36:41 PM PDT 24
Finished Jul 26 06:36:42 PM PDT 24
Peak memory 195180 kb
Host smart-b9770fca-b7fa-418c-9aa7-dd34da4653cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103299128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4103299128
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1049519672
Short name T1258
Test name
Test status
Simulation time 48046363 ps
CPU time 0.57 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195216 kb
Host smart-43a721a5-f1e9-45f1-b574-9cf26023fb5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049519672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1049519672
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1232462384
Short name T76
Test name
Test status
Simulation time 59466476 ps
CPU time 0.78 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 197136 kb
Host smart-dbb2c3b4-1ff6-4d79-b657-7629d794e86a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232462384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1232462384
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3259007540
Short name T1279
Test name
Test status
Simulation time 773389478 ps
CPU time 2.43 seconds
Started Jul 26 06:36:14 PM PDT 24
Finished Jul 26 06:36:16 PM PDT 24
Peak memory 198764 kb
Host smart-15e6e7ce-c630-46f6-bbcb-1868d229537d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259007540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3259007540
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3883420578
Short name T1312
Test name
Test status
Simulation time 37943759 ps
CPU time 0.63 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 196176 kb
Host smart-07e7c57b-0267-4150-92f1-98d3c32bc10c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883420578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3883420578
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2480527313
Short name T1234
Test name
Test status
Simulation time 21622187 ps
CPU time 0.81 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 200656 kb
Host smart-bc50896a-0512-4005-b35c-a96cc41fc124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480527313 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2480527313
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2239331414
Short name T96
Test name
Test status
Simulation time 12671571 ps
CPU time 0.63 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 196480 kb
Host smart-4e49e0ea-b713-44e5-9f3c-e09bc96a884d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239331414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2239331414
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4163344042
Short name T1184
Test name
Test status
Simulation time 22704214 ps
CPU time 0.6 seconds
Started Jul 26 06:36:09 PM PDT 24
Finished Jul 26 06:36:10 PM PDT 24
Peak memory 195480 kb
Host smart-8ebc9ecf-db37-4d8f-b573-de4f41f1a32c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163344042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4163344042
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3846659327
Short name T1276
Test name
Test status
Simulation time 130495295 ps
CPU time 0.64 seconds
Started Jul 26 06:36:16 PM PDT 24
Finished Jul 26 06:36:17 PM PDT 24
Peak memory 195420 kb
Host smart-d46f8728-ecf7-47ea-bf67-051c7f76eab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846659327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3846659327
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.771070460
Short name T1303
Test name
Test status
Simulation time 37634183 ps
CPU time 1.38 seconds
Started Jul 26 06:36:13 PM PDT 24
Finished Jul 26 06:36:14 PM PDT 24
Peak memory 200884 kb
Host smart-f8e36108-1b72-4dea-83e4-a7cede6b7e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771070460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.771070460
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4239187762
Short name T1259
Test name
Test status
Simulation time 41498879 ps
CPU time 0.95 seconds
Started Jul 26 06:36:09 PM PDT 24
Finished Jul 26 06:36:10 PM PDT 24
Peak memory 200068 kb
Host smart-682a4194-88c7-4245-b258-822f6d474210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239187762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4239187762
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1928444647
Short name T1315
Test name
Test status
Simulation time 45165908 ps
CPU time 0.58 seconds
Started Jul 26 06:36:46 PM PDT 24
Finished Jul 26 06:36:47 PM PDT 24
Peak memory 195280 kb
Host smart-901dfeeb-bc15-4428-9afe-752da3171ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928444647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1928444647
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3335146980
Short name T1284
Test name
Test status
Simulation time 13332391 ps
CPU time 0.6 seconds
Started Jul 26 06:36:43 PM PDT 24
Finished Jul 26 06:36:44 PM PDT 24
Peak memory 195268 kb
Host smart-7d03d2d4-140b-4fe6-8551-e68f74da1bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335146980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3335146980
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2304630945
Short name T1300
Test name
Test status
Simulation time 56187106 ps
CPU time 0.56 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:43 PM PDT 24
Peak memory 195244 kb
Host smart-7981764a-c50a-4e7e-83b2-6d459ca7eb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304630945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2304630945
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2922298290
Short name T1249
Test name
Test status
Simulation time 48457075 ps
CPU time 0.58 seconds
Started Jul 26 06:36:43 PM PDT 24
Finished Jul 26 06:36:43 PM PDT 24
Peak memory 195276 kb
Host smart-26bdf470-7d07-4c66-9bac-d059476f8f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922298290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2922298290
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3296623706
Short name T1295
Test name
Test status
Simulation time 122179069 ps
CPU time 0.55 seconds
Started Jul 26 06:36:39 PM PDT 24
Finished Jul 26 06:36:39 PM PDT 24
Peak memory 195300 kb
Host smart-f7c90a8b-f57e-498c-87f1-bc30e2725823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296623706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3296623706
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3961050086
Short name T1236
Test name
Test status
Simulation time 35421135 ps
CPU time 0.63 seconds
Started Jul 26 06:36:41 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195316 kb
Host smart-20bfd359-24f4-45cd-999c-7137e7760839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961050086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3961050086
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.221654654
Short name T1183
Test name
Test status
Simulation time 44435350 ps
CPU time 0.61 seconds
Started Jul 26 06:36:46 PM PDT 24
Finished Jul 26 06:36:47 PM PDT 24
Peak memory 195160 kb
Host smart-3e76fca4-ffec-4bf8-8245-d0edd2d89b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221654654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.221654654
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2174243627
Short name T1189
Test name
Test status
Simulation time 17040946 ps
CPU time 0.59 seconds
Started Jul 26 06:36:41 PM PDT 24
Finished Jul 26 06:36:42 PM PDT 24
Peak memory 195280 kb
Host smart-6962f8bb-9366-4638-aba8-13aaac96abc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174243627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2174243627
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2389549191
Short name T1238
Test name
Test status
Simulation time 12741236 ps
CPU time 0.56 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195168 kb
Host smart-734d79e8-a605-4e9e-afb1-0f015f177e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389549191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2389549191
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2627171318
Short name T1318
Test name
Test status
Simulation time 19060785 ps
CPU time 0.6 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 195244 kb
Host smart-2f2ecfa4-e0aa-41de-a2b2-a6c1d15b2e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627171318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2627171318
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3116803508
Short name T1272
Test name
Test status
Simulation time 292377679 ps
CPU time 0.81 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 200712 kb
Host smart-2ca4331b-e052-4d24-a5c2-ab218f0d195f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116803508 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3116803508
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1413043655
Short name T1202
Test name
Test status
Simulation time 21543301 ps
CPU time 0.58 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 196276 kb
Host smart-c5d80d9e-1203-4792-a1f0-c085ae788fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413043655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1413043655
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.640173704
Short name T1208
Test name
Test status
Simulation time 18162789 ps
CPU time 0.58 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:12 PM PDT 24
Peak memory 195268 kb
Host smart-9ed985e4-bd91-4e1d-b129-231734d35a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640173704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.640173704
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.553720173
Short name T1232
Test name
Test status
Simulation time 64079505 ps
CPU time 0.64 seconds
Started Jul 26 06:36:15 PM PDT 24
Finished Jul 26 06:36:15 PM PDT 24
Peak memory 195684 kb
Host smart-813274cf-8dd1-42cb-a0ed-467cff57ac16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553720173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.553720173
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4162919277
Short name T1194
Test name
Test status
Simulation time 45091962 ps
CPU time 1.55 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 200992 kb
Host smart-a784b1b2-e201-4da3-a454-8d8a36aaa231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162919277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4162919277
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1612709587
Short name T100
Test name
Test status
Simulation time 152965131 ps
CPU time 0.97 seconds
Started Jul 26 06:36:08 PM PDT 24
Finished Jul 26 06:36:09 PM PDT 24
Peak memory 199944 kb
Host smart-9a16c04a-3298-4125-b751-3a0eb9916fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612709587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1612709587
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2069718437
Short name T1252
Test name
Test status
Simulation time 36726806 ps
CPU time 1.23 seconds
Started Jul 26 06:36:15 PM PDT 24
Finished Jul 26 06:36:16 PM PDT 24
Peak memory 200864 kb
Host smart-c364929c-779e-40bf-8a4e-76901273aeb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069718437 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2069718437
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1413808985
Short name T1255
Test name
Test status
Simulation time 23763208 ps
CPU time 0.59 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:10 PM PDT 24
Peak memory 196292 kb
Host smart-090db8fb-6d14-4f0f-bed0-0df677cd0ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413808985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1413808985
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.757237391
Short name T1251
Test name
Test status
Simulation time 20944589 ps
CPU time 0.58 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:12 PM PDT 24
Peak memory 195188 kb
Host smart-2f3f38ee-112b-4643-b8e3-cf64a7711a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757237391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.757237391
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2780310688
Short name T1257
Test name
Test status
Simulation time 48624576 ps
CPU time 0.68 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 197644 kb
Host smart-a24d3c64-672f-4532-9a0b-5081d046c45a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780310688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2780310688
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3141930115
Short name T1260
Test name
Test status
Simulation time 347947038 ps
CPU time 2.01 seconds
Started Jul 26 06:36:08 PM PDT 24
Finished Jul 26 06:36:10 PM PDT 24
Peak memory 200936 kb
Host smart-424da448-2ac3-41ec-8110-986daff58b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141930115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3141930115
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.6113928
Short name T1256
Test name
Test status
Simulation time 260236156 ps
CPU time 1.03 seconds
Started Jul 26 06:36:07 PM PDT 24
Finished Jul 26 06:36:08 PM PDT 24
Peak memory 199560 kb
Host smart-7a86c5af-2f36-4fca-9d6a-6e2c51492add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6113928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.6113928
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4072030028
Short name T1317
Test name
Test status
Simulation time 18662939 ps
CPU time 0.68 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 198824 kb
Host smart-e57e1e52-675b-4f16-b40e-e04e8058fa76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072030028 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4072030028
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.675406480
Short name T75
Test name
Test status
Simulation time 74301152 ps
CPU time 0.63 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 196420 kb
Host smart-e4fbf478-4a1b-459d-864f-f5261007700f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675406480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.675406480
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1366512134
Short name T1302
Test name
Test status
Simulation time 53794314 ps
CPU time 0.6 seconds
Started Jul 26 06:36:11 PM PDT 24
Finished Jul 26 06:36:12 PM PDT 24
Peak memory 195316 kb
Host smart-39081cce-c72b-4722-a21d-4a9b7f2e981c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366512134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1366512134
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1642787834
Short name T1265
Test name
Test status
Simulation time 31393627 ps
CPU time 0.62 seconds
Started Jul 26 06:36:09 PM PDT 24
Finished Jul 26 06:36:10 PM PDT 24
Peak memory 196324 kb
Host smart-5cfed7cd-ba85-42dd-aede-f8f1a93419f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642787834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1642787834
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1034532341
Short name T1250
Test name
Test status
Simulation time 59835401 ps
CPU time 1.2 seconds
Started Jul 26 06:36:08 PM PDT 24
Finished Jul 26 06:36:09 PM PDT 24
Peak memory 200960 kb
Host smart-51595072-c839-4cf8-ac44-bafe579145f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034532341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1034532341
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1195888256
Short name T108
Test name
Test status
Simulation time 79188278 ps
CPU time 0.92 seconds
Started Jul 26 06:36:10 PM PDT 24
Finished Jul 26 06:36:11 PM PDT 24
Peak memory 199584 kb
Host smart-45076d39-abaf-4d28-b8c6-66d8f3820980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195888256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1195888256
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.470741004
Short name T1185
Test name
Test status
Simulation time 72212550 ps
CPU time 1.12 seconds
Started Jul 26 06:36:21 PM PDT 24
Finished Jul 26 06:36:22 PM PDT 24
Peak memory 200904 kb
Host smart-1447e516-0e3e-4ae0-aa5c-77f292b8e89f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470741004 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.470741004
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3599657985
Short name T1210
Test name
Test status
Simulation time 14237355 ps
CPU time 0.63 seconds
Started Jul 26 06:36:15 PM PDT 24
Finished Jul 26 06:36:16 PM PDT 24
Peak memory 196476 kb
Host smart-5aa0b900-699a-4ef5-924d-785a12be7a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599657985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3599657985
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3319442434
Short name T1225
Test name
Test status
Simulation time 15525878 ps
CPU time 0.59 seconds
Started Jul 26 06:36:17 PM PDT 24
Finished Jul 26 06:36:18 PM PDT 24
Peak memory 195228 kb
Host smart-e80ed560-841b-4a75-9ad5-50837d6ed256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319442434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3319442434
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1269729305
Short name T1311
Test name
Test status
Simulation time 24105409 ps
CPU time 0.72 seconds
Started Jul 26 06:36:20 PM PDT 24
Finished Jul 26 06:36:21 PM PDT 24
Peak memory 198712 kb
Host smart-9e8b2481-c158-47d1-a75b-348315304f08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269729305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1269729305
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3529740867
Short name T1200
Test name
Test status
Simulation time 276624223 ps
CPU time 1.54 seconds
Started Jul 26 06:36:12 PM PDT 24
Finished Jul 26 06:36:13 PM PDT 24
Peak memory 200836 kb
Host smart-30bdc5bc-edfd-449f-9c2f-54c18f68b660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529740867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3529740867
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4050552276
Short name T102
Test name
Test status
Simulation time 192436763 ps
CPU time 0.96 seconds
Started Jul 26 06:36:18 PM PDT 24
Finished Jul 26 06:36:19 PM PDT 24
Peak memory 199844 kb
Host smart-88d46c24-6d41-4db5-abbf-66c61ad0c461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050552276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4050552276
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3248749845
Short name T1205
Test name
Test status
Simulation time 17254647 ps
CPU time 0.67 seconds
Started Jul 26 06:36:16 PM PDT 24
Finished Jul 26 06:36:17 PM PDT 24
Peak memory 198372 kb
Host smart-29e26781-5fb5-4909-b502-ae649d243129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248749845 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3248749845
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3063913793
Short name T78
Test name
Test status
Simulation time 140236442 ps
CPU time 0.61 seconds
Started Jul 26 06:36:18 PM PDT 24
Finished Jul 26 06:36:19 PM PDT 24
Peak memory 196384 kb
Host smart-a1988b39-5e30-4596-8658-37173035123c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063913793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3063913793
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.844541861
Short name T1192
Test name
Test status
Simulation time 63531876 ps
CPU time 0.57 seconds
Started Jul 26 06:36:18 PM PDT 24
Finished Jul 26 06:36:18 PM PDT 24
Peak memory 195220 kb
Host smart-1582c384-dd43-4200-9493-82b83f158877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844541861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.844541861
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4221537353
Short name T95
Test name
Test status
Simulation time 34053790 ps
CPU time 0.77 seconds
Started Jul 26 06:36:17 PM PDT 24
Finished Jul 26 06:36:17 PM PDT 24
Peak memory 197868 kb
Host smart-b33d13b2-87a3-4a9f-92c4-3dc82740a39e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221537353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4221537353
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1556787416
Short name T1227
Test name
Test status
Simulation time 139185502 ps
CPU time 1.73 seconds
Started Jul 26 06:36:22 PM PDT 24
Finished Jul 26 06:36:23 PM PDT 24
Peak memory 200900 kb
Host smart-698fe607-494a-4d32-bb7c-61fd340b3b55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556787416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1556787416
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1232409172
Short name T1221
Test name
Test status
Simulation time 104973301 ps
CPU time 0.93 seconds
Started Jul 26 06:36:15 PM PDT 24
Finished Jul 26 06:36:16 PM PDT 24
Peak memory 199532 kb
Host smart-1ccd9d5e-fe23-4946-83d5-5f5ceee9e7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232409172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1232409172
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2041999907
Short name T533
Test name
Test status
Simulation time 40468571 ps
CPU time 0.57 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:39:10 PM PDT 24
Peak memory 195600 kb
Host smart-79082ccb-ffa6-4ad4-b819-eaacf4091a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041999907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2041999907
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3784342512
Short name T905
Test name
Test status
Simulation time 18596976594 ps
CPU time 28.01 seconds
Started Jul 26 06:39:05 PM PDT 24
Finished Jul 26 06:39:33 PM PDT 24
Peak memory 200088 kb
Host smart-1d64a5fd-0d9b-4ca2-90e7-e5a1f610ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784342512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3784342512
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1469642678
Short name T841
Test name
Test status
Simulation time 11940864422 ps
CPU time 18.54 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:21 PM PDT 24
Peak memory 200160 kb
Host smart-31187b2a-d57e-4683-9bf1-c4f014a09a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469642678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1469642678
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.743999826
Short name T948
Test name
Test status
Simulation time 24852648968 ps
CPU time 36.93 seconds
Started Jul 26 06:39:05 PM PDT 24
Finished Jul 26 06:39:42 PM PDT 24
Peak memory 200144 kb
Host smart-b4d76625-6844-4f84-baec-aae7338578a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743999826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.743999826
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.907054538
Short name T1077
Test name
Test status
Simulation time 22249543488 ps
CPU time 27 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:30 PM PDT 24
Peak memory 200068 kb
Host smart-64b9c1d2-aa35-43d3-b3de-5ccc71eaef4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907054538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.907054538
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2716643596
Short name T394
Test name
Test status
Simulation time 173320875868 ps
CPU time 437.73 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:46:21 PM PDT 24
Peak memory 200172 kb
Host smart-26a35904-2d10-4c8e-b72a-da20f232fbea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716643596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2716643596
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1041967009
Short name T390
Test name
Test status
Simulation time 7644893342 ps
CPU time 7.89 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:11 PM PDT 24
Peak memory 199364 kb
Host smart-54616c97-a192-4aee-a8ba-f8964fc95d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041967009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1041967009
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3217327548
Short name T663
Test name
Test status
Simulation time 227864615442 ps
CPU time 48.55 seconds
Started Jul 26 06:39:02 PM PDT 24
Finished Jul 26 06:39:51 PM PDT 24
Peak memory 200356 kb
Host smart-186fd00c-252f-40f6-bfeb-c7aef8f07f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217327548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3217327548
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1955315448
Short name T765
Test name
Test status
Simulation time 10839542624 ps
CPU time 144.03 seconds
Started Jul 26 06:39:02 PM PDT 24
Finished Jul 26 06:41:27 PM PDT 24
Peak memory 199976 kb
Host smart-7177ed63-e02a-4439-98ee-d2c3818d4701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955315448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1955315448
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1108314161
Short name T434
Test name
Test status
Simulation time 5002644083 ps
CPU time 35.71 seconds
Started Jul 26 06:39:06 PM PDT 24
Finished Jul 26 06:39:42 PM PDT 24
Peak memory 200072 kb
Host smart-3abd644a-89ab-44e6-aecd-83f07f4acf88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108314161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1108314161
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4280535757
Short name T463
Test name
Test status
Simulation time 3073385150 ps
CPU time 3.04 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:06 PM PDT 24
Peak memory 196192 kb
Host smart-fbf6635a-ecda-42ef-a221-b56909860f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280535757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4280535757
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1612476399
Short name T109
Test name
Test status
Simulation time 122622913 ps
CPU time 0.86 seconds
Started Jul 26 06:39:12 PM PDT 24
Finished Jul 26 06:39:13 PM PDT 24
Peak memory 218380 kb
Host smart-04c7549d-e936-4080-bea9-72889f98c3c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612476399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1612476399
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3685339422
Short name T969
Test name
Test status
Simulation time 774093477 ps
CPU time 1.66 seconds
Started Jul 26 06:39:04 PM PDT 24
Finished Jul 26 06:39:06 PM PDT 24
Peak memory 198728 kb
Host smart-15b7ea35-ed8d-4ea7-97a2-2e679e0afac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685339422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3685339422
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.361733368
Short name T714
Test name
Test status
Simulation time 426129392879 ps
CPU time 853.22 seconds
Started Jul 26 06:39:15 PM PDT 24
Finished Jul 26 06:53:28 PM PDT 24
Peak memory 208484 kb
Host smart-976b25af-c7b8-4772-8b63-e7012eabcf6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361733368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.361733368
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1480940912
Short name T987
Test name
Test status
Simulation time 99834765892 ps
CPU time 1130.84 seconds
Started Jul 26 06:39:02 PM PDT 24
Finished Jul 26 06:57:53 PM PDT 24
Peak memory 217056 kb
Host smart-708b2ccf-679d-4293-9d4c-7dc175c29c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480940912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1480940912
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1353075226
Short name T291
Test name
Test status
Simulation time 1977732606 ps
CPU time 2.08 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:05 PM PDT 24
Peak memory 199176 kb
Host smart-ff0a4f94-cd1d-46ea-b539-393721b846f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353075226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1353075226
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2565419534
Short name T789
Test name
Test status
Simulation time 58876222028 ps
CPU time 88.48 seconds
Started Jul 26 06:39:04 PM PDT 24
Finished Jul 26 06:40:32 PM PDT 24
Peak memory 200112 kb
Host smart-f6a93221-920f-4d01-8e8e-05f308ef559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565419534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2565419534
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.145316676
Short name T498
Test name
Test status
Simulation time 30197421 ps
CPU time 0.56 seconds
Started Jul 26 06:39:15 PM PDT 24
Finished Jul 26 06:39:16 PM PDT 24
Peak memory 195528 kb
Host smart-5114c7b3-f40f-4990-a730-9f1d27621c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145316676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.145316676
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4085638718
Short name T839
Test name
Test status
Simulation time 25814406395 ps
CPU time 20.76 seconds
Started Jul 26 06:39:12 PM PDT 24
Finished Jul 26 06:39:33 PM PDT 24
Peak memory 200176 kb
Host smart-ba3ce725-93a2-44e7-8870-04d244cff957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085638718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4085638718
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2583365389
Short name T569
Test name
Test status
Simulation time 113192395768 ps
CPU time 84.9 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:40:34 PM PDT 24
Peak memory 200112 kb
Host smart-a2de9c7d-4efa-48d2-8dfa-2d57012986be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583365389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2583365389
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3021992381
Short name T727
Test name
Test status
Simulation time 266551097970 ps
CPU time 490.07 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:47:20 PM PDT 24
Peak memory 200068 kb
Host smart-039239d2-2d45-44de-a8af-67f800e3e948
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021992381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3021992381
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2939044801
Short name T1069
Test name
Test status
Simulation time 85967490464 ps
CPU time 139.93 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:41:36 PM PDT 24
Peak memory 200060 kb
Host smart-029a3c53-8b8e-4424-bbc6-95ec626b64b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939044801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2939044801
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3069997345
Short name T802
Test name
Test status
Simulation time 2689711226 ps
CPU time 5.54 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:39:15 PM PDT 24
Peak memory 198844 kb
Host smart-854b63b2-8da3-41c2-9f6e-237ceceedd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069997345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3069997345
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.12739497
Short name T680
Test name
Test status
Simulation time 8279580228 ps
CPU time 259.2 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:43:29 PM PDT 24
Peak memory 200176 kb
Host smart-448d185e-16dd-44bf-854a-0033dc1923a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12739497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.12739497
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.42885036
Short name T478
Test name
Test status
Simulation time 4186970743 ps
CPU time 6.43 seconds
Started Jul 26 06:39:12 PM PDT 24
Finished Jul 26 06:39:19 PM PDT 24
Peak memory 198332 kb
Host smart-b9a7bc08-2eb8-4f0f-9f3d-b359f90391c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42885036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.42885036
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2083151298
Short name T767
Test name
Test status
Simulation time 34672740244 ps
CPU time 14.78 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:39:25 PM PDT 24
Peak memory 200108 kb
Host smart-9e1af8f1-d0c2-4101-b07a-ce1b9873dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083151298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2083151298
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.615759550
Short name T417
Test name
Test status
Simulation time 3377280512 ps
CPU time 5.85 seconds
Started Jul 26 06:39:15 PM PDT 24
Finished Jul 26 06:39:21 PM PDT 24
Peak memory 196256 kb
Host smart-da965315-9599-4bff-ae0c-b65efc838664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615759550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.615759550
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.3955920327
Short name T819
Test name
Test status
Simulation time 5490053595 ps
CPU time 20.3 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:39:29 PM PDT 24
Peak memory 200112 kb
Host smart-9ea9270f-eae8-4c83-9fd0-26869011271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955920327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3955920327
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.4083171480
Short name T312
Test name
Test status
Simulation time 46736089790 ps
CPU time 28.2 seconds
Started Jul 26 06:39:13 PM PDT 24
Finished Jul 26 06:39:41 PM PDT 24
Peak memory 200204 kb
Host smart-6df6c5d3-1f04-4890-9a59-af855f32cacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083171480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4083171480
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.511567922
Short name T756
Test name
Test status
Simulation time 7315596557 ps
CPU time 12.15 seconds
Started Jul 26 06:39:12 PM PDT 24
Finished Jul 26 06:39:24 PM PDT 24
Peak memory 200068 kb
Host smart-6b5a5313-8924-44a9-a9e4-870ed104ffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511567922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.511567922
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.273840216
Short name T267
Test name
Test status
Simulation time 109425354896 ps
CPU time 68.1 seconds
Started Jul 26 06:39:09 PM PDT 24
Finished Jul 26 06:40:17 PM PDT 24
Peak memory 200176 kb
Host smart-b667eb67-8c7b-49f5-8491-0e1ced7622cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273840216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.273840216
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3814696199
Short name T803
Test name
Test status
Simulation time 21101616 ps
CPU time 0.55 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:40:13 PM PDT 24
Peak memory 195540 kb
Host smart-fab55006-cfc7-4fac-a144-ff28fd4dbbf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814696199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3814696199
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.4001641040
Short name T786
Test name
Test status
Simulation time 88029996123 ps
CPU time 25 seconds
Started Jul 26 06:40:08 PM PDT 24
Finished Jul 26 06:40:33 PM PDT 24
Peak memory 200120 kb
Host smart-964c377b-ef45-4a38-8bb1-7393f286785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001641040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4001641040
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2920888695
Short name T820
Test name
Test status
Simulation time 141331247661 ps
CPU time 844.62 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:54:12 PM PDT 24
Peak memory 200116 kb
Host smart-256dd180-e7cb-475b-80b2-aa1fa3162d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920888695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2920888695
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2661569590
Short name T193
Test name
Test status
Simulation time 57583200853 ps
CPU time 49.09 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:40:57 PM PDT 24
Peak memory 200200 kb
Host smart-4e3b9a94-40ea-490b-829d-706de63f0996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661569590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2661569590
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3737990914
Short name T1010
Test name
Test status
Simulation time 32888662830 ps
CPU time 53.61 seconds
Started Jul 26 06:40:06 PM PDT 24
Finished Jul 26 06:41:00 PM PDT 24
Peak memory 200048 kb
Host smart-14df3eff-52ab-45ff-9ecf-2a2b7b2c68f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737990914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3737990914
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2429143957
Short name T594
Test name
Test status
Simulation time 116347870311 ps
CPU time 264.72 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:44:38 PM PDT 24
Peak memory 200152 kb
Host smart-7b61cb9d-7eea-40d4-aeb9-b2d0469d9342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429143957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2429143957
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3732971957
Short name T355
Test name
Test status
Simulation time 8190240354 ps
CPU time 5.42 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:40:19 PM PDT 24
Peak memory 200128 kb
Host smart-bafe2cbe-94cb-40c5-ad45-4af2035756dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732971957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3732971957
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.29199551
Short name T522
Test name
Test status
Simulation time 66293608451 ps
CPU time 72.42 seconds
Started Jul 26 06:40:08 PM PDT 24
Finished Jul 26 06:41:20 PM PDT 24
Peak memory 200312 kb
Host smart-0760e623-bca0-4e0b-a233-bc506051b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29199551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.29199551
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2178502882
Short name T414
Test name
Test status
Simulation time 14008308948 ps
CPU time 197.92 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:43:31 PM PDT 24
Peak memory 200084 kb
Host smart-b6aba36a-e20f-4cf4-b0ab-6287ff2557f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178502882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2178502882
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.422249333
Short name T722
Test name
Test status
Simulation time 5827497757 ps
CPU time 25.34 seconds
Started Jul 26 06:40:06 PM PDT 24
Finished Jul 26 06:40:31 PM PDT 24
Peak memory 199448 kb
Host smart-7eb18c5d-4e36-4f05-bb7a-b6306572703e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422249333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.422249333
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2628453683
Short name T289
Test name
Test status
Simulation time 45680578513 ps
CPU time 67.52 seconds
Started Jul 26 06:40:14 PM PDT 24
Finished Jul 26 06:41:21 PM PDT 24
Peak memory 200140 kb
Host smart-2e4405c2-a8f7-4efd-b23d-9d18d73eb94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628453683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2628453683
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.4043294263
Short name T499
Test name
Test status
Simulation time 45306457682 ps
CPU time 67.32 seconds
Started Jul 26 06:40:06 PM PDT 24
Finished Jul 26 06:41:14 PM PDT 24
Peak memory 195988 kb
Host smart-294fa777-a7d5-4386-b517-4f65e607597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043294263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4043294263
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.979555803
Short name T357
Test name
Test status
Simulation time 6337518208 ps
CPU time 3.32 seconds
Started Jul 26 06:40:05 PM PDT 24
Finished Jul 26 06:40:08 PM PDT 24
Peak memory 199668 kb
Host smart-2c35cd88-4e59-4285-bf6d-c1cfe4bd575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979555803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.979555803
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2511762146
Short name T1078
Test name
Test status
Simulation time 198671644759 ps
CPU time 737.79 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:52:31 PM PDT 24
Peak memory 208516 kb
Host smart-9054c704-e51e-4cd4-9798-1cccf7ed6d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511762146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2511762146
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1219072619
Short name T757
Test name
Test status
Simulation time 238524898769 ps
CPU time 819.09 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:53:52 PM PDT 24
Peak memory 224924 kb
Host smart-3c76a5ab-5bad-47dc-b9bc-4a9c2ae68dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219072619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1219072619
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1220144692
Short name T688
Test name
Test status
Simulation time 8608976791 ps
CPU time 8.47 seconds
Started Jul 26 06:40:15 PM PDT 24
Finished Jul 26 06:40:23 PM PDT 24
Peak memory 200196 kb
Host smart-6abd728d-c617-47c2-8b54-777dfba39a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220144692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1220144692
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4064298681
Short name T822
Test name
Test status
Simulation time 73245660053 ps
CPU time 62.02 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:41:09 PM PDT 24
Peak memory 200132 kb
Host smart-a062f773-fd4b-4974-bf41-09788f51db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064298681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4064298681
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3151298950
Short name T219
Test name
Test status
Simulation time 202063391740 ps
CPU time 55.37 seconds
Started Jul 26 06:46:44 PM PDT 24
Finished Jul 26 06:47:39 PM PDT 24
Peak memory 200268 kb
Host smart-7fc50d58-f8a7-4a0e-94d9-ec0df8e75d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151298950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3151298950
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1958776795
Short name T185
Test name
Test status
Simulation time 71707488455 ps
CPU time 51.77 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:47:30 PM PDT 24
Peak memory 200168 kb
Host smart-44a3d319-6a82-4693-8a28-dad28ba9961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958776795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1958776795
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2721384927
Short name T760
Test name
Test status
Simulation time 59101892741 ps
CPU time 25.63 seconds
Started Jul 26 06:46:37 PM PDT 24
Finished Jul 26 06:47:02 PM PDT 24
Peak memory 200056 kb
Host smart-5e8073b9-cd99-4f0c-9e8c-0bf16750509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721384927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2721384927
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3085510262
Short name T566
Test name
Test status
Simulation time 225215803360 ps
CPU time 55.84 seconds
Started Jul 26 06:46:44 PM PDT 24
Finished Jul 26 06:47:40 PM PDT 24
Peak memory 200256 kb
Host smart-dbb65da5-34e2-4a5f-8698-1c476fdcc69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085510262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3085510262
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.620814957
Short name T644
Test name
Test status
Simulation time 15789084887 ps
CPU time 24.35 seconds
Started Jul 26 06:46:36 PM PDT 24
Finished Jul 26 06:47:01 PM PDT 24
Peak memory 200124 kb
Host smart-cdc219bd-e394-4aa2-ab24-2d6e2a22c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620814957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.620814957
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2766954925
Short name T1099
Test name
Test status
Simulation time 37854918549 ps
CPU time 13.81 seconds
Started Jul 26 06:46:42 PM PDT 24
Finished Jul 26 06:46:56 PM PDT 24
Peak memory 200256 kb
Host smart-364f8db6-34d2-4079-9c91-bc70b5ab7a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766954925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2766954925
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1504790643
Short name T226
Test name
Test status
Simulation time 30694201360 ps
CPU time 13.04 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:46:52 PM PDT 24
Peak memory 200180 kb
Host smart-7fc74caa-34d4-487e-a32b-458fefa4e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504790643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1504790643
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2367880768
Short name T229
Test name
Test status
Simulation time 34629134709 ps
CPU time 12.69 seconds
Started Jul 26 06:46:36 PM PDT 24
Finished Jul 26 06:46:49 PM PDT 24
Peak memory 200352 kb
Host smart-048c7f75-8fcd-4137-82f1-bb8703813bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367880768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2367880768
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.875665754
Short name T850
Test name
Test status
Simulation time 186237797447 ps
CPU time 346.99 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:45:59 PM PDT 24
Peak memory 200148 kb
Host smart-0431c7d3-2285-4181-8e72-6d10062f0cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875665754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.875665754
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3432131550
Short name T174
Test name
Test status
Simulation time 41729999966 ps
CPU time 36.15 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:40:50 PM PDT 24
Peak memory 200120 kb
Host smart-883b66c1-a43c-4b6d-be47-630af5822af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432131550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3432131550
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2432016321
Short name T565
Test name
Test status
Simulation time 45352079393 ps
CPU time 43.92 seconds
Started Jul 26 06:40:14 PM PDT 24
Finished Jul 26 06:40:58 PM PDT 24
Peak memory 200128 kb
Host smart-b1bb5abd-9c41-4c3a-835b-f05dd51fde61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432016321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2432016321
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.954521971
Short name T1143
Test name
Test status
Simulation time 201402912968 ps
CPU time 77.51 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:41:38 PM PDT 24
Peak memory 200196 kb
Host smart-9883f4f5-3ca8-4f4a-b0e2-78d04bd882ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954521971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.954521971
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3050545075
Short name T1082
Test name
Test status
Simulation time 7115330244 ps
CPU time 11.38 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:40:32 PM PDT 24
Peak memory 198536 kb
Host smart-388182f2-866c-44d9-a435-0a7081a52dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050545075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3050545075
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1190935601
Short name T735
Test name
Test status
Simulation time 26473904627 ps
CPU time 39.37 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:40:52 PM PDT 24
Peak memory 199580 kb
Host smart-331012ed-65d2-42d6-a7ee-fbfe0050782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190935601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1190935601
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1795832809
Short name T992
Test name
Test status
Simulation time 8648482216 ps
CPU time 108.13 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:42:08 PM PDT 24
Peak memory 200036 kb
Host smart-f28f35fc-25b1-4145-86dc-391b9a3e5086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795832809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1795832809
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.670916423
Short name T429
Test name
Test status
Simulation time 7475500809 ps
CPU time 32.03 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:40:45 PM PDT 24
Peak memory 200096 kb
Host smart-7aa37a9d-6c65-41c8-82f1-cb2e374585c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670916423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.670916423
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.544554721
Short name T472
Test name
Test status
Simulation time 52359911724 ps
CPU time 108.48 seconds
Started Jul 26 06:40:14 PM PDT 24
Finished Jul 26 06:42:03 PM PDT 24
Peak memory 199892 kb
Host smart-60436c98-59eb-49f7-b6cf-086553b16090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544554721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.544554721
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1218671783
Short name T27
Test name
Test status
Simulation time 41727959470 ps
CPU time 28.78 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:40:41 PM PDT 24
Peak memory 196372 kb
Host smart-600341fa-bd74-4f0c-acc4-648a81b9f362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218671783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1218671783
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3635481697
Short name T725
Test name
Test status
Simulation time 705426940 ps
CPU time 2.21 seconds
Started Jul 26 06:40:12 PM PDT 24
Finished Jul 26 06:40:14 PM PDT 24
Peak memory 199720 kb
Host smart-8e39c5b7-1e4c-4b2f-8907-8dee97a0c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635481697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3635481697
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3902366897
Short name T829
Test name
Test status
Simulation time 136121795084 ps
CPU time 1405.84 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 07:03:46 PM PDT 24
Peak memory 208464 kb
Host smart-5ae62e17-42d3-4f64-91b8-84750b4ecef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902366897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3902366897
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.135592701
Short name T606
Test name
Test status
Simulation time 18190672737 ps
CPU time 236.64 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:44:18 PM PDT 24
Peak memory 208476 kb
Host smart-1f6181c0-a40a-4b37-b50e-2b3acf1d07ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135592701 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.135592701
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2325382231
Short name T51
Test name
Test status
Simulation time 5536399294 ps
CPU time 1.48 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:40:22 PM PDT 24
Peak memory 199164 kb
Host smart-7b09d476-c241-4d1e-81c4-d95fe075c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325382231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2325382231
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2094201787
Short name T869
Test name
Test status
Simulation time 30581547989 ps
CPU time 17.13 seconds
Started Jul 26 06:40:13 PM PDT 24
Finished Jul 26 06:40:30 PM PDT 24
Peak memory 200120 kb
Host smart-fcd2c2e6-e46a-4afb-8835-d387a3721b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094201787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2094201787
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.270909011
Short name T838
Test name
Test status
Simulation time 72303133604 ps
CPU time 29.13 seconds
Started Jul 26 06:46:36 PM PDT 24
Finished Jul 26 06:47:06 PM PDT 24
Peak memory 200180 kb
Host smart-ee0a65d4-587e-4f76-9fa6-1f9fa8c67ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270909011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.270909011
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2356068082
Short name T326
Test name
Test status
Simulation time 73429480238 ps
CPU time 32.77 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:47:12 PM PDT 24
Peak memory 200124 kb
Host smart-692f0b11-c67a-4fb1-9a39-ec927fc83bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356068082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2356068082
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4241248736
Short name T136
Test name
Test status
Simulation time 60480676167 ps
CPU time 84.76 seconds
Started Jul 26 06:46:38 PM PDT 24
Finished Jul 26 06:48:03 PM PDT 24
Peak memory 200180 kb
Host smart-3157dbfd-2b87-4f3a-a86f-263d7c43ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241248736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4241248736
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.32754497
Short name T943
Test name
Test status
Simulation time 23001308122 ps
CPU time 42.75 seconds
Started Jul 26 06:46:45 PM PDT 24
Finished Jul 26 06:47:27 PM PDT 24
Peak memory 200184 kb
Host smart-a6dd52d9-1540-49e5-bcbf-4daea44a40de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32754497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.32754497
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2388746141
Short name T124
Test name
Test status
Simulation time 22920307496 ps
CPU time 16.74 seconds
Started Jul 26 06:46:48 PM PDT 24
Finished Jul 26 06:47:05 PM PDT 24
Peak memory 200120 kb
Host smart-f94f2a58-7d70-4712-8f7b-2ce547bb4abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388746141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2388746141
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2479656935
Short name T341
Test name
Test status
Simulation time 13102530641 ps
CPU time 24.94 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:47:11 PM PDT 24
Peak memory 200204 kb
Host smart-3f1f5dd3-2670-4da6-850e-601b6287b7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479656935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2479656935
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2042158717
Short name T531
Test name
Test status
Simulation time 246342139873 ps
CPU time 48.9 seconds
Started Jul 26 06:46:44 PM PDT 24
Finished Jul 26 06:47:33 PM PDT 24
Peak memory 200200 kb
Host smart-8b38e4d1-aa24-484e-9542-b6ccd2105032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042158717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2042158717
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1040578869
Short name T1060
Test name
Test status
Simulation time 18463930082 ps
CPU time 9.17 seconds
Started Jul 26 06:46:45 PM PDT 24
Finished Jul 26 06:46:55 PM PDT 24
Peak memory 200188 kb
Host smart-d2a67c08-6938-4073-8ea6-e42807d10ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040578869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1040578869
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.127921654
Short name T187
Test name
Test status
Simulation time 146715766337 ps
CPU time 42.03 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:47:28 PM PDT 24
Peak memory 200192 kb
Host smart-dfde171b-0114-4e61-9bbe-0aa766ea090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127921654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.127921654
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1686390442
Short name T356
Test name
Test status
Simulation time 15490466 ps
CPU time 0.59 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:40:32 PM PDT 24
Peak memory 195448 kb
Host smart-88a9b10d-25f9-4ad1-b224-ea89f4fee6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686390442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1686390442
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1774902270
Short name T391
Test name
Test status
Simulation time 130741284364 ps
CPU time 198.77 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:43:39 PM PDT 24
Peak memory 200148 kb
Host smart-5bda5898-b78b-42df-806e-440f3867ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774902270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1774902270
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3713141925
Short name T743
Test name
Test status
Simulation time 45117303079 ps
CPU time 60.88 seconds
Started Jul 26 06:40:22 PM PDT 24
Finished Jul 26 06:41:23 PM PDT 24
Peak memory 200088 kb
Host smart-a02bb841-c546-414f-b2f9-6d5d8031e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713141925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3713141925
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3139489842
Short name T245
Test name
Test status
Simulation time 59833979098 ps
CPU time 24.21 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:40:44 PM PDT 24
Peak memory 200152 kb
Host smart-9023a4df-dae7-4c40-8ea2-50bfba16a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139489842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3139489842
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4084415168
Short name T378
Test name
Test status
Simulation time 13542411629 ps
CPU time 11.26 seconds
Started Jul 26 06:40:20 PM PDT 24
Finished Jul 26 06:40:31 PM PDT 24
Peak memory 198032 kb
Host smart-497cd346-e8f5-4e95-98d6-b05d538b2e0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084415168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4084415168
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.75223102
Short name T632
Test name
Test status
Simulation time 151601609773 ps
CPU time 389.01 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:46:59 PM PDT 24
Peak memory 200180 kb
Host smart-d6dd07c6-a843-4430-94b5-360e984b125b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75223102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.75223102
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2600164631
Short name T637
Test name
Test status
Simulation time 7956064739 ps
CPU time 6.36 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:40:36 PM PDT 24
Peak memory 199972 kb
Host smart-e93133e6-4bfd-4508-8ab5-61d3a6435025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600164631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2600164631
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.277965456
Short name T399
Test name
Test status
Simulation time 35924776473 ps
CPU time 65.09 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:41:26 PM PDT 24
Peak memory 200316 kb
Host smart-f6731ba5-fec7-4730-abf6-6382962e90b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277965456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.277965456
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4279248886
Short name T618
Test name
Test status
Simulation time 2235547669 ps
CPU time 114.41 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:42:25 PM PDT 24
Peak memory 200176 kb
Host smart-7c0a3406-180a-4605-a98d-98eb659c2d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279248886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4279248886
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.467568410
Short name T660
Test name
Test status
Simulation time 6861216500 ps
CPU time 30.55 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:40:52 PM PDT 24
Peak memory 198864 kb
Host smart-ff86f68f-5f7c-4a0b-a83f-8501e1cdd577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467568410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.467568410
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2407038660
Short name T683
Test name
Test status
Simulation time 122854804847 ps
CPU time 218.49 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:44:08 PM PDT 24
Peak memory 200204 kb
Host smart-d227650d-8432-4834-b0f4-92d122e52d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407038660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2407038660
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.891780568
Short name T526
Test name
Test status
Simulation time 1980050736 ps
CPU time 1.39 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:40:31 PM PDT 24
Peak memory 195896 kb
Host smart-4ffdc284-ba0b-4a77-af1c-c85afe789b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891780568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.891780568
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3014671339
Short name T570
Test name
Test status
Simulation time 544596569 ps
CPU time 2.34 seconds
Started Jul 26 06:40:19 PM PDT 24
Finished Jul 26 06:40:21 PM PDT 24
Peak memory 200096 kb
Host smart-301568b2-595d-4da5-a94c-ad34ef9d4f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014671339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3014671339
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3745098380
Short name T922
Test name
Test status
Simulation time 192690650471 ps
CPU time 1667.28 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 07:08:18 PM PDT 24
Peak memory 200192 kb
Host smart-9907d238-a7dc-4a1c-98cb-01485aef8ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745098380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3745098380
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1311135720
Short name T772
Test name
Test status
Simulation time 270221115492 ps
CPU time 848.41 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 230416 kb
Host smart-3990046b-8b03-4346-82eb-6b669e10fa6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311135720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1311135720
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2361688153
Short name T954
Test name
Test status
Simulation time 7424806585 ps
CPU time 13.26 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:40:43 PM PDT 24
Peak memory 200128 kb
Host smart-287ab268-df76-47ff-8377-7f7dbba5e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361688153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2361688153
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4190334879
Short name T925
Test name
Test status
Simulation time 29122867490 ps
CPU time 11.93 seconds
Started Jul 26 06:40:21 PM PDT 24
Finished Jul 26 06:40:33 PM PDT 24
Peak memory 200188 kb
Host smart-b21acb32-e3b0-40e9-be17-4b1efee59972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190334879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4190334879
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3083445109
Short name T649
Test name
Test status
Simulation time 106867467468 ps
CPU time 185.18 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:49:51 PM PDT 24
Peak memory 200116 kb
Host smart-a9c4e0fe-c2db-4056-af58-398aaa1b34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083445109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3083445109
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.849255920
Short name T864
Test name
Test status
Simulation time 39944657737 ps
CPU time 50.49 seconds
Started Jul 26 06:46:45 PM PDT 24
Finished Jul 26 06:47:36 PM PDT 24
Peak memory 200196 kb
Host smart-2ac8bc33-c849-4928-8191-b6e61bc4011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849255920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.849255920
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4248852787
Short name T287
Test name
Test status
Simulation time 73186218958 ps
CPU time 208.7 seconds
Started Jul 26 06:46:45 PM PDT 24
Finished Jul 26 06:50:14 PM PDT 24
Peak memory 200188 kb
Host smart-64f79102-1d83-4c01-a8ad-60801026452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248852787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4248852787
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3714198350
Short name T1017
Test name
Test status
Simulation time 76423400904 ps
CPU time 372.86 seconds
Started Jul 26 06:46:48 PM PDT 24
Finished Jul 26 06:53:01 PM PDT 24
Peak memory 200232 kb
Host smart-720c4f34-6f50-48bc-b48b-198e9a78581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714198350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3714198350
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.593597564
Short name T834
Test name
Test status
Simulation time 29425966066 ps
CPU time 10.28 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:46:57 PM PDT 24
Peak memory 198656 kb
Host smart-b2e94238-a226-4489-bab3-c4b80f26daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593597564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.593597564
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.81790616
Short name T690
Test name
Test status
Simulation time 104232627545 ps
CPU time 86.27 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:48:12 PM PDT 24
Peak memory 200176 kb
Host smart-07883456-82f3-4846-b4f6-e513220de3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81790616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.81790616
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3466273612
Short name T209
Test name
Test status
Simulation time 81368948633 ps
CPU time 76.68 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:48:02 PM PDT 24
Peak memory 200120 kb
Host smart-9142e3da-0ead-4169-9d20-375f006e14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466273612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3466273612
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1283609632
Short name T903
Test name
Test status
Simulation time 120021218617 ps
CPU time 102.59 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 200168 kb
Host smart-1c62d24a-8b07-47f1-996a-a5d2146c2085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283609632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1283609632
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1702626662
Short name T418
Test name
Test status
Simulation time 42702624057 ps
CPU time 9.74 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:46:56 PM PDT 24
Peak memory 200188 kb
Host smart-da4db980-0762-4016-93e0-b535830daa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702626662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1702626662
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3989327908
Short name T571
Test name
Test status
Simulation time 21713151 ps
CPU time 0.55 seconds
Started Jul 26 06:40:47 PM PDT 24
Finished Jul 26 06:40:48 PM PDT 24
Peak memory 195216 kb
Host smart-299ce56b-35fe-40f4-8599-99e3f33af41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989327908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3989327908
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3975532711
Short name T301
Test name
Test status
Simulation time 109220184286 ps
CPU time 75.34 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:41:46 PM PDT 24
Peak memory 200132 kb
Host smart-85c82ad7-c293-4e82-ae01-675c33eacb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975532711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3975532711
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3472522982
Short name T1149
Test name
Test status
Simulation time 69309987178 ps
CPU time 94.1 seconds
Started Jul 26 06:40:29 PM PDT 24
Finished Jul 26 06:42:04 PM PDT 24
Peak memory 200132 kb
Host smart-b6ef894a-db69-44b9-8cf1-c01a7fbd5581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472522982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3472522982
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1048160646
Short name T293
Test name
Test status
Simulation time 65379165725 ps
CPU time 99.67 seconds
Started Jul 26 06:40:32 PM PDT 24
Finished Jul 26 06:42:12 PM PDT 24
Peak memory 200124 kb
Host smart-36315a6d-dd44-45ed-8113-2f690c0c53f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048160646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1048160646
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3448845532
Short name T10
Test name
Test status
Simulation time 42880790488 ps
CPU time 21.78 seconds
Started Jul 26 06:40:32 PM PDT 24
Finished Jul 26 06:40:54 PM PDT 24
Peak memory 200052 kb
Host smart-652230be-bd60-4c63-bedc-dc71125f2790
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448845532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3448845532
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2554820648
Short name T377
Test name
Test status
Simulation time 73434137245 ps
CPU time 359.83 seconds
Started Jul 26 06:40:46 PM PDT 24
Finished Jul 26 06:46:46 PM PDT 24
Peak memory 200144 kb
Host smart-53f67100-8e91-48a2-83fb-eeed16055a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554820648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2554820648
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2872493234
Short name T458
Test name
Test status
Simulation time 1970320363 ps
CPU time 1.72 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:40:46 PM PDT 24
Peak memory 197404 kb
Host smart-0d6b67d3-a07c-41b6-8960-130e8b260750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872493234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2872493234
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.574158355
Short name T345
Test name
Test status
Simulation time 170698164907 ps
CPU time 86.15 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:41:57 PM PDT 24
Peak memory 199744 kb
Host smart-b50f8e44-6648-40bc-8855-dddd038c86d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574158355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.574158355
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.601201274
Short name T298
Test name
Test status
Simulation time 17451321155 ps
CPU time 898.51 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:55:43 PM PDT 24
Peak memory 200172 kb
Host smart-71172a32-55f6-4618-be3d-79c2471d48df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601201274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.601201274
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2879690299
Short name T361
Test name
Test status
Simulation time 4402225884 ps
CPU time 22.28 seconds
Started Jul 26 06:40:32 PM PDT 24
Finished Jul 26 06:40:54 PM PDT 24
Peak memory 200136 kb
Host smart-d3ff23f6-4620-4cb4-9515-5fcdb110a643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879690299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2879690299
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2705793763
Short name T278
Test name
Test status
Simulation time 105224430253 ps
CPU time 40.32 seconds
Started Jul 26 06:40:31 PM PDT 24
Finished Jul 26 06:41:12 PM PDT 24
Peak memory 199128 kb
Host smart-ddf40ca2-7160-46fd-bc82-3986b8a064b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705793763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2705793763
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3247340972
Short name T1164
Test name
Test status
Simulation time 3293876891 ps
CPU time 5.14 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:40:35 PM PDT 24
Peak memory 196460 kb
Host smart-2aeaca02-e3c5-4a38-b89d-879683a706d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247340972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3247340972
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2776525126
Short name T1014
Test name
Test status
Simulation time 6071703072 ps
CPU time 34.28 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:41:04 PM PDT 24
Peak memory 200100 kb
Host smart-bfec205a-d377-4e2f-925e-dedf09616892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776525126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2776525126
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3684017410
Short name T332
Test name
Test status
Simulation time 104940273184 ps
CPU time 1157.6 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 07:00:03 PM PDT 24
Peak memory 224852 kb
Host smart-a1a16cbb-a1cd-45a5-ac45-698159cb5ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684017410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3684017410
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.666207502
Short name T863
Test name
Test status
Simulation time 883160922 ps
CPU time 3.44 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:40:48 PM PDT 24
Peak memory 198980 kb
Host smart-6cf46a79-ff56-409e-bb22-4cbdec8c4ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666207502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.666207502
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2612755498
Short name T459
Test name
Test status
Simulation time 32521363867 ps
CPU time 13.12 seconds
Started Jul 26 06:40:30 PM PDT 24
Finished Jul 26 06:40:43 PM PDT 24
Peak memory 200188 kb
Host smart-fbd6d00c-7670-493c-8326-fe4238db103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612755498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2612755498
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3707189824
Short name T881
Test name
Test status
Simulation time 329787152175 ps
CPU time 154.76 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:49:21 PM PDT 24
Peak memory 200136 kb
Host smart-15b8ed3f-c6b6-4df5-b43d-058b58fa12d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707189824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3707189824
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3149038519
Short name T1104
Test name
Test status
Simulation time 106250587872 ps
CPU time 173.49 seconds
Started Jul 26 06:46:46 PM PDT 24
Finished Jul 26 06:49:40 PM PDT 24
Peak memory 200088 kb
Host smart-61029667-4d2c-4832-931a-6303a16a43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149038519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3149038519
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3550804995
Short name T990
Test name
Test status
Simulation time 22050197045 ps
CPU time 19.13 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:17 PM PDT 24
Peak memory 200176 kb
Host smart-52b99078-7726-4148-92dd-5dffd8bfc1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550804995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3550804995
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.693992958
Short name T624
Test name
Test status
Simulation time 3723901452 ps
CPU time 6.15 seconds
Started Jul 26 06:46:57 PM PDT 24
Finished Jul 26 06:47:03 PM PDT 24
Peak memory 199428 kb
Host smart-7e20447d-72c8-4d8a-b923-9b747f19f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693992958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.693992958
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.10480873
Short name T344
Test name
Test status
Simulation time 99690715855 ps
CPU time 101.14 seconds
Started Jul 26 06:46:57 PM PDT 24
Finished Jul 26 06:48:38 PM PDT 24
Peak memory 200168 kb
Host smart-8e1aa057-b5a3-48cf-bfd0-a7b62f182e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10480873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.10480873
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4085999788
Short name T739
Test name
Test status
Simulation time 185673229600 ps
CPU time 70.01 seconds
Started Jul 26 06:46:59 PM PDT 24
Finished Jul 26 06:48:09 PM PDT 24
Peak memory 200176 kb
Host smart-412a2edf-b393-4992-8e09-29071c80a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085999788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4085999788
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1804183708
Short name T551
Test name
Test status
Simulation time 19829608791 ps
CPU time 15.32 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:13 PM PDT 24
Peak memory 200180 kb
Host smart-804fdef4-f546-4a58-810b-40a5bc8e737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804183708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1804183708
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2021887322
Short name T517
Test name
Test status
Simulation time 14268801715 ps
CPU time 7.75 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:05 PM PDT 24
Peak memory 200072 kb
Host smart-57e8aee2-fe5b-4449-85de-85bf689db374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021887322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2021887322
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2679592868
Short name T347
Test name
Test status
Simulation time 25830597383 ps
CPU time 37.95 seconds
Started Jul 26 06:46:56 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 200296 kb
Host smart-cff4997b-d071-473a-afaa-9e1b4a9db5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679592868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2679592868
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.558224411
Short name T423
Test name
Test status
Simulation time 93957527396 ps
CPU time 31.01 seconds
Started Jul 26 06:47:00 PM PDT 24
Finished Jul 26 06:47:31 PM PDT 24
Peak memory 200160 kb
Host smart-5a59d98e-dd2e-4f5f-8d9d-5c4f55c38036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558224411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.558224411
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3084705531
Short name T1050
Test name
Test status
Simulation time 11441388 ps
CPU time 0.55 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:40:56 PM PDT 24
Peak memory 195844 kb
Host smart-e7b1aa15-10db-439b-8414-b83148da2856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084705531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3084705531
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.876716579
Short name T98
Test name
Test status
Simulation time 28864074009 ps
CPU time 25.12 seconds
Started Jul 26 06:40:46 PM PDT 24
Finished Jul 26 06:41:12 PM PDT 24
Peak memory 200192 kb
Host smart-0e5af3e3-19e3-433c-b17e-a5b84f612c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876716579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.876716579
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1335206216
Short name T1043
Test name
Test status
Simulation time 13951673247 ps
CPU time 11.3 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:40:57 PM PDT 24
Peak memory 199700 kb
Host smart-7f8bab79-b03f-4c6b-9f30-36da68b641fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335206216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1335206216
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.476720619
Short name T343
Test name
Test status
Simulation time 27721796640 ps
CPU time 41.55 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:41:26 PM PDT 24
Peak memory 200084 kb
Host smart-f0ab01a5-3fbe-4d39-a905-cd10dc224819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476720619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.476720619
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1084431262
Short name T304
Test name
Test status
Simulation time 34953406142 ps
CPU time 55.46 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:41:39 PM PDT 24
Peak memory 200092 kb
Host smart-5424adcf-d241-469e-9eda-c636476d496f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084431262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1084431262
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2996105953
Short name T831
Test name
Test status
Simulation time 67847766554 ps
CPU time 393.31 seconds
Started Jul 26 06:40:47 PM PDT 24
Finished Jul 26 06:47:21 PM PDT 24
Peak memory 200200 kb
Host smart-1c19e5fe-1ff0-4361-a2be-2e5f3543d6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996105953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2996105953
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3149800613
Short name T516
Test name
Test status
Simulation time 1208005432 ps
CPU time 4.07 seconds
Started Jul 26 06:40:42 PM PDT 24
Finished Jul 26 06:40:46 PM PDT 24
Peak memory 198848 kb
Host smart-7f04d952-6ace-4414-9de8-c130f5bb0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149800613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3149800613
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3664695840
Short name T1112
Test name
Test status
Simulation time 68119110782 ps
CPU time 51.46 seconds
Started Jul 26 06:40:48 PM PDT 24
Finished Jul 26 06:41:40 PM PDT 24
Peak memory 208048 kb
Host smart-0514ac2e-0253-47de-a787-56b7b9cf47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664695840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3664695840
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1681412399
Short name T679
Test name
Test status
Simulation time 15118732238 ps
CPU time 879.81 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:55:25 PM PDT 24
Peak memory 200088 kb
Host smart-58b7b855-5ead-4d35-9f10-2b4fb18a67fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681412399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1681412399
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.601720663
Short name T373
Test name
Test status
Simulation time 2742331653 ps
CPU time 21.77 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:41:07 PM PDT 24
Peak memory 198688 kb
Host smart-4ae315b2-f5a6-4612-ad01-0a908adc9b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601720663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.601720663
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1676242953
Short name T1095
Test name
Test status
Simulation time 135718151126 ps
CPU time 59.76 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:41:44 PM PDT 24
Peak memory 199972 kb
Host smart-97db50fc-9031-4b05-92a6-c5a32198ac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676242953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1676242953
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3479093075
Short name T325
Test name
Test status
Simulation time 36751009495 ps
CPU time 57.11 seconds
Started Jul 26 06:40:44 PM PDT 24
Finished Jul 26 06:41:41 PM PDT 24
Peak memory 196464 kb
Host smart-891d3b8f-0b50-433c-ba93-1ef8f711c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479093075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3479093075
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1878700620
Short name T890
Test name
Test status
Simulation time 462022239 ps
CPU time 2.2 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:40:48 PM PDT 24
Peak memory 199048 kb
Host smart-e593ff94-2e83-4e99-ab9a-6f0eeb4267ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878700620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1878700620
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1771237519
Short name T697
Test name
Test status
Simulation time 161769171351 ps
CPU time 236.8 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:44:42 PM PDT 24
Peak memory 200200 kb
Host smart-35f632b9-07e1-4112-848e-26714c5512f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771237519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1771237519
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3560201508
Short name T118
Test name
Test status
Simulation time 83731984699 ps
CPU time 394.39 seconds
Started Jul 26 06:40:46 PM PDT 24
Finished Jul 26 06:47:20 PM PDT 24
Peak memory 216652 kb
Host smart-84d783fb-d9bc-43fe-830b-075ca2583f43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560201508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3560201508
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1447569130
Short name T1074
Test name
Test status
Simulation time 1264481096 ps
CPU time 2.32 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:40:48 PM PDT 24
Peak memory 199060 kb
Host smart-d03dfcc0-5341-4a16-a849-0f9a7399f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447569130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1447569130
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1795341434
Short name T5
Test name
Test status
Simulation time 40855282366 ps
CPU time 80.61 seconds
Started Jul 26 06:40:45 PM PDT 24
Finished Jul 26 06:42:06 PM PDT 24
Peak memory 200180 kb
Host smart-31a2363e-dce3-48a9-ad12-04ed1df04e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795341434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1795341434
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1136451997
Short name T198
Test name
Test status
Simulation time 33592129026 ps
CPU time 14 seconds
Started Jul 26 06:46:56 PM PDT 24
Finished Jul 26 06:47:10 PM PDT 24
Peak memory 200004 kb
Host smart-5c330fae-780a-47db-ad3a-3b9994e40524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136451997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1136451997
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.982631642
Short name T1034
Test name
Test status
Simulation time 112096217174 ps
CPU time 90.73 seconds
Started Jul 26 06:46:56 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 200084 kb
Host smart-50bda167-e7f8-4ed3-8017-54626aefa57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982631642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.982631642
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.859462336
Short name T1003
Test name
Test status
Simulation time 153363868288 ps
CPU time 113 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:48:51 PM PDT 24
Peak memory 200168 kb
Host smart-64eee2d4-852c-4072-af69-5e1e97602c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859462336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.859462336
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.570750925
Short name T504
Test name
Test status
Simulation time 77153975796 ps
CPU time 38.17 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:36 PM PDT 24
Peak memory 200116 kb
Host smart-f9397b84-26a1-4f60-a9f8-9aa3a354bc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570750925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.570750925
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.732654854
Short name T189
Test name
Test status
Simulation time 25429377005 ps
CPU time 44.57 seconds
Started Jul 26 06:46:55 PM PDT 24
Finished Jul 26 06:47:39 PM PDT 24
Peak memory 200248 kb
Host smart-95e46bf4-e7d5-4e63-b829-2eeb46443ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732654854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.732654854
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.761182994
Short name T623
Test name
Test status
Simulation time 117317579618 ps
CPU time 214.04 seconds
Started Jul 26 06:46:57 PM PDT 24
Finished Jul 26 06:50:31 PM PDT 24
Peak memory 200256 kb
Host smart-c60345aa-6b5d-4791-8b75-03033bc39643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761182994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.761182994
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2389675305
Short name T555
Test name
Test status
Simulation time 23246202895 ps
CPU time 32.46 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:31 PM PDT 24
Peak memory 200016 kb
Host smart-587d9d53-3e1f-41f0-aa1e-37919e57cb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389675305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2389675305
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3440727691
Short name T1044
Test name
Test status
Simulation time 76666065702 ps
CPU time 15.66 seconds
Started Jul 26 06:46:58 PM PDT 24
Finished Jul 26 06:47:14 PM PDT 24
Peak memory 200116 kb
Host smart-8440f583-6ed6-4f18-8b27-53b127752022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440727691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3440727691
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.387709984
Short name T955
Test name
Test status
Simulation time 9794815325 ps
CPU time 16.43 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:47:20 PM PDT 24
Peak memory 200156 kb
Host smart-992474a7-77c6-4051-a1e4-52df881e685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387709984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.387709984
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.739144038
Short name T1145
Test name
Test status
Simulation time 135675113218 ps
CPU time 14.2 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:47:17 PM PDT 24
Peak memory 200148 kb
Host smart-a5ae1197-13ff-443d-9474-772d67d89fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739144038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.739144038
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1075459610
Short name T358
Test name
Test status
Simulation time 136868494 ps
CPU time 0.58 seconds
Started Jul 26 06:40:59 PM PDT 24
Finished Jul 26 06:41:00 PM PDT 24
Peak memory 195548 kb
Host smart-91a20a8e-affc-47ce-8b22-a32c5aa8bcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075459610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1075459610
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3518230404
Short name T1175
Test name
Test status
Simulation time 71004034226 ps
CPU time 32.95 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:41:30 PM PDT 24
Peak memory 200088 kb
Host smart-d84fc535-05af-4749-8c30-55ed6340fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518230404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3518230404
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3751586494
Short name T490
Test name
Test status
Simulation time 28573556346 ps
CPU time 11.34 seconds
Started Jul 26 06:40:55 PM PDT 24
Finished Jul 26 06:41:07 PM PDT 24
Peak memory 199988 kb
Host smart-a67ce232-23f8-4cd3-b2eb-c540194d6769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751586494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3751586494
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2973082000
Short name T208
Test name
Test status
Simulation time 118406222174 ps
CPU time 108.08 seconds
Started Jul 26 06:40:55 PM PDT 24
Finished Jul 26 06:42:43 PM PDT 24
Peak memory 200120 kb
Host smart-4bff6c2c-7ed6-4bfc-8d33-0ec9d4640504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973082000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2973082000
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3493616755
Short name T851
Test name
Test status
Simulation time 46274112987 ps
CPU time 39.58 seconds
Started Jul 26 06:40:57 PM PDT 24
Finished Jul 26 06:41:36 PM PDT 24
Peak memory 199976 kb
Host smart-14f08f8f-74de-401a-ba12-c227fa0cd3d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493616755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3493616755
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2759835615
Short name T538
Test name
Test status
Simulation time 75246356682 ps
CPU time 84.7 seconds
Started Jul 26 06:40:58 PM PDT 24
Finished Jul 26 06:42:23 PM PDT 24
Peak memory 200164 kb
Host smart-83c3e08c-788b-4c4c-b064-c14e7d240d0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759835615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2759835615
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2192646436
Short name T1120
Test name
Test status
Simulation time 7444716113 ps
CPU time 13.45 seconds
Started Jul 26 06:40:54 PM PDT 24
Finished Jul 26 06:41:07 PM PDT 24
Peak memory 198868 kb
Host smart-fbe33ba3-fcc5-4580-8dff-0787815a925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192646436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2192646436
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.190486776
Short name T470
Test name
Test status
Simulation time 41138504253 ps
CPU time 11.69 seconds
Started Jul 26 06:40:54 PM PDT 24
Finished Jul 26 06:41:06 PM PDT 24
Peak memory 200028 kb
Host smart-e9d8b75e-8589-4d3b-b4fc-afed8a46f7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190486776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.190486776
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3706562219
Short name T1046
Test name
Test status
Simulation time 6548248938 ps
CPU time 87.17 seconds
Started Jul 26 06:40:57 PM PDT 24
Finished Jul 26 06:42:25 PM PDT 24
Peak memory 200112 kb
Host smart-78b0adab-db9c-46c7-921d-b62e3fa27bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706562219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3706562219
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3321750125
Short name T19
Test name
Test status
Simulation time 7155532148 ps
CPU time 16.97 seconds
Started Jul 26 06:40:57 PM PDT 24
Finished Jul 26 06:41:14 PM PDT 24
Peak memory 199084 kb
Host smart-587f46b2-18ab-4c64-90b4-525c2f9f5a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321750125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3321750125
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3451019667
Short name T143
Test name
Test status
Simulation time 35767506828 ps
CPU time 12.08 seconds
Started Jul 26 06:40:55 PM PDT 24
Finished Jul 26 06:41:08 PM PDT 24
Peak memory 200100 kb
Host smart-23d6179a-8d14-4480-862c-3b8151623509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451019667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3451019667
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.767218352
Short name T806
Test name
Test status
Simulation time 4061042651 ps
CPU time 5.91 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:41:02 PM PDT 24
Peak memory 197000 kb
Host smart-62ab9fcf-3d33-48b3-b27c-2eb9634f6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767218352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.767218352
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1555831681
Short name T923
Test name
Test status
Simulation time 454088031 ps
CPU time 1.92 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:40:58 PM PDT 24
Peak memory 199484 kb
Host smart-e6ad5e35-d5ef-46b5-b5aa-92bf3c6e332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555831681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1555831681
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3054561888
Short name T989
Test name
Test status
Simulation time 92119768121 ps
CPU time 145.91 seconds
Started Jul 26 06:40:57 PM PDT 24
Finished Jul 26 06:43:23 PM PDT 24
Peak memory 200188 kb
Host smart-1091d2c5-381d-4c10-93f9-0de40490bfca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054561888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3054561888
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.408425136
Short name T983
Test name
Test status
Simulation time 16853668171 ps
CPU time 174.35 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:43:50 PM PDT 24
Peak memory 216776 kb
Host smart-2ecebcb2-7f73-4969-90c4-eba9c4731923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408425136 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.408425136
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4257245198
Short name T284
Test name
Test status
Simulation time 1367686519 ps
CPU time 3.28 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:41:00 PM PDT 24
Peak memory 199968 kb
Host smart-23e649f0-3b40-4244-8fde-9f59da297755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257245198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4257245198
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3079534898
Short name T676
Test name
Test status
Simulation time 42132600643 ps
CPU time 36.68 seconds
Started Jul 26 06:40:55 PM PDT 24
Finished Jul 26 06:41:31 PM PDT 24
Peak memory 200212 kb
Host smart-661ef5fa-dec0-4b58-b45b-4ee10d4b2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079534898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3079534898
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3711152662
Short name T1162
Test name
Test status
Simulation time 73954751116 ps
CPU time 51.82 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:47:55 PM PDT 24
Peak memory 200136 kb
Host smart-00154759-d68a-4c00-ab5d-ffb2c368fc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711152662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3711152662
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.197724805
Short name T387
Test name
Test status
Simulation time 17562795685 ps
CPU time 30.94 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:47:35 PM PDT 24
Peak memory 200176 kb
Host smart-5f4f3d22-0002-42f4-90f3-5e3a89619c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197724805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.197724805
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1984800060
Short name T1004
Test name
Test status
Simulation time 52455554453 ps
CPU time 81.88 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:48:26 PM PDT 24
Peak memory 200128 kb
Host smart-097d03dd-36be-4194-bfc7-62ced842a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984800060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1984800060
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2974418437
Short name T730
Test name
Test status
Simulation time 52345552407 ps
CPU time 14.66 seconds
Started Jul 26 06:47:01 PM PDT 24
Finished Jul 26 06:47:16 PM PDT 24
Peak memory 200172 kb
Host smart-c6e3355a-bda3-434f-a4b0-fa181e526543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974418437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2974418437
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.152024140
Short name T71
Test name
Test status
Simulation time 153611320403 ps
CPU time 112.95 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:48:55 PM PDT 24
Peak memory 200160 kb
Host smart-903ad0de-0f2b-4582-9663-34ddbaf98065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152024140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.152024140
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2461164671
Short name T220
Test name
Test status
Simulation time 37625675090 ps
CPU time 14.15 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:47:16 PM PDT 24
Peak memory 200200 kb
Host smart-200d8fa3-770c-4f7a-b240-4e8d4174cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461164671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2461164671
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3238874846
Short name T218
Test name
Test status
Simulation time 103875260602 ps
CPU time 50.21 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:47:52 PM PDT 24
Peak memory 200184 kb
Host smart-a7e439b1-b852-4703-a32d-2ea7e9b9e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238874846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3238874846
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3740564973
Short name T884
Test name
Test status
Simulation time 40290526468 ps
CPU time 13.77 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:47:17 PM PDT 24
Peak memory 200124 kb
Host smart-324b1456-ed33-4251-88ff-38eecf65dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740564973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3740564973
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2277162698
Short name T800
Test name
Test status
Simulation time 108038305841 ps
CPU time 83.2 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:48:25 PM PDT 24
Peak memory 200172 kb
Host smart-f4fb8b57-ee41-42b2-8a9a-97d2a61fbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277162698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2277162698
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1039301555
Short name T892
Test name
Test status
Simulation time 14495243 ps
CPU time 0.59 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:41:11 PM PDT 24
Peak memory 195560 kb
Host smart-4fe300d7-1a13-4436-a947-cd7b07527f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039301555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1039301555
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2510336347
Short name T984
Test name
Test status
Simulation time 40931405640 ps
CPU time 39.37 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:51 PM PDT 24
Peak memory 200104 kb
Host smart-6c3c4e38-143e-41e1-931b-d8f1c2362a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510336347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2510336347
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2560724346
Short name T616
Test name
Test status
Simulation time 91570299674 ps
CPU time 32.71 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:44 PM PDT 24
Peak memory 200084 kb
Host smart-91784d91-9921-4b29-ab9c-64f05af0bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560724346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2560724346
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.992432730
Short name T295
Test name
Test status
Simulation time 11469594645 ps
CPU time 21.35 seconds
Started Jul 26 06:41:13 PM PDT 24
Finished Jul 26 06:41:34 PM PDT 24
Peak memory 200104 kb
Host smart-77f99126-6ada-47d9-a151-089a7307b22d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992432730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.992432730
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3786681017
Short name T733
Test name
Test status
Simulation time 100402232446 ps
CPU time 323.68 seconds
Started Jul 26 06:41:12 PM PDT 24
Finished Jul 26 06:46:35 PM PDT 24
Peak memory 200144 kb
Host smart-8abc4cfc-b08b-4057-a367-b9f7f518850f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786681017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3786681017
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.391684806
Short name T460
Test name
Test status
Simulation time 10433767432 ps
CPU time 6.8 seconds
Started Jul 26 06:41:14 PM PDT 24
Finished Jul 26 06:41:20 PM PDT 24
Peak memory 200200 kb
Host smart-748cbdc2-b75b-4995-b8c9-a5c33f90eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391684806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.391684806
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4125815554
Short name T788
Test name
Test status
Simulation time 58446685343 ps
CPU time 52.4 seconds
Started Jul 26 06:41:09 PM PDT 24
Finished Jul 26 06:42:02 PM PDT 24
Peak memory 199440 kb
Host smart-c4ab47ab-fc3f-4b1e-af4b-fae1315e7dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125815554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4125815554
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2771259322
Short name T581
Test name
Test status
Simulation time 13077290273 ps
CPU time 179.21 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:44:10 PM PDT 24
Peak memory 200184 kb
Host smart-1e3f9416-91ad-4d2a-ad5e-5c8798e91b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771259322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2771259322
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1261307918
Short name T349
Test name
Test status
Simulation time 3823226994 ps
CPU time 9.18 seconds
Started Jul 26 06:41:12 PM PDT 24
Finished Jul 26 06:41:21 PM PDT 24
Peak memory 199084 kb
Host smart-9a454e47-9abe-4dff-b9d5-09a1d90cad48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261307918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1261307918
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1012176058
Short name T264
Test name
Test status
Simulation time 145548718573 ps
CPU time 231.53 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:45:02 PM PDT 24
Peak memory 200180 kb
Host smart-d45598a6-c7bf-4133-9a76-37839a1e4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012176058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1012176058
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1743420990
Short name T627
Test name
Test status
Simulation time 2564597782 ps
CPU time 1.65 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:13 PM PDT 24
Peak memory 196736 kb
Host smart-5ccdf6f4-d412-490e-a6f9-285a11dc128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743420990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1743420990
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3051861610
Short name T449
Test name
Test status
Simulation time 910514163 ps
CPU time 2.49 seconds
Started Jul 26 06:40:55 PM PDT 24
Finished Jul 26 06:40:57 PM PDT 24
Peak memory 199084 kb
Host smart-742adbec-dc48-44fb-8fe6-95c5f9cf9eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051861610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3051861610
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.19070768
Short name T492
Test name
Test status
Simulation time 302782712747 ps
CPU time 755.91 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:53:47 PM PDT 24
Peak memory 200140 kb
Host smart-74336798-0c86-4e4d-bf07-b7eaa8a54c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19070768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.19070768
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.34185942
Short name T853
Test name
Test status
Simulation time 20045093476 ps
CPU time 232.11 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:45:04 PM PDT 24
Peak memory 216836 kb
Host smart-b6157daa-77d3-4cb5-8407-984821c64b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185942 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.34185942
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1887812574
Short name T593
Test name
Test status
Simulation time 1047165562 ps
CPU time 3.54 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:15 PM PDT 24
Peak memory 199404 kb
Host smart-3966f43c-ce25-42ff-8438-6c17e01b9eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887812574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1887812574
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2471695119
Short name T548
Test name
Test status
Simulation time 36672416110 ps
CPU time 27.56 seconds
Started Jul 26 06:40:56 PM PDT 24
Finished Jul 26 06:41:23 PM PDT 24
Peak memory 200148 kb
Host smart-fa26ef98-2414-428a-a9d7-a567adc08deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471695119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2471695119
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3009476164
Short name T1005
Test name
Test status
Simulation time 18122444781 ps
CPU time 32.13 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:47:36 PM PDT 24
Peak memory 200236 kb
Host smart-4d190086-a792-4484-9c8c-0f51490e3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009476164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3009476164
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2383520828
Short name T856
Test name
Test status
Simulation time 80755213401 ps
CPU time 44.62 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200188 kb
Host smart-48aa93bd-a1f2-4b1a-b0b2-c03aab00c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383520828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2383520828
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2515195163
Short name T590
Test name
Test status
Simulation time 22632447105 ps
CPU time 10.44 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:47:13 PM PDT 24
Peak memory 200136 kb
Host smart-2511f249-0b98-40e3-910e-ea6b07df9c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515195163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2515195163
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1301217143
Short name T694
Test name
Test status
Simulation time 35331225601 ps
CPU time 28.7 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:47:31 PM PDT 24
Peak memory 200096 kb
Host smart-1b324c5b-6a5b-4e24-886c-77a73b717aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301217143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1301217143
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.26301173
Short name T495
Test name
Test status
Simulation time 67871566885 ps
CPU time 127.73 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 200184 kb
Host smart-88ebfb1d-105c-4656-a8a9-229a5a18ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26301173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.26301173
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4226386504
Short name T1178
Test name
Test status
Simulation time 35134274331 ps
CPU time 58.56 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:48:00 PM PDT 24
Peak memory 200200 kb
Host smart-7c09b4bf-8e5b-4989-9734-d78829b43112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226386504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4226386504
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2311563870
Short name T186
Test name
Test status
Simulation time 52054531114 ps
CPU time 62.3 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:48:05 PM PDT 24
Peak memory 200092 kb
Host smart-d4391131-2f41-4fdd-a4bb-22a2afb17283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311563870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2311563870
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1534408727
Short name T909
Test name
Test status
Simulation time 40769026662 ps
CPU time 15.64 seconds
Started Jul 26 06:47:03 PM PDT 24
Finished Jul 26 06:47:19 PM PDT 24
Peak memory 199684 kb
Host smart-d5160bb4-ff99-4d8d-bb2c-517b1247a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534408727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1534408727
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2001837315
Short name T248
Test name
Test status
Simulation time 76510323544 ps
CPU time 216.56 seconds
Started Jul 26 06:47:04 PM PDT 24
Finished Jul 26 06:50:40 PM PDT 24
Peak memory 200188 kb
Host smart-a9a8f3a0-bf39-4044-b774-83dd0afe5254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001837315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2001837315
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2796369530
Short name T1156
Test name
Test status
Simulation time 40949148 ps
CPU time 0.56 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:41:25 PM PDT 24
Peak memory 195492 kb
Host smart-d3553fcc-becf-40eb-8f72-d8d6f0239982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796369530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2796369530
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.745799197
Short name T723
Test name
Test status
Simulation time 185103271611 ps
CPU time 65.29 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:42:15 PM PDT 24
Peak memory 200212 kb
Host smart-3944e49f-a16a-4185-b203-69ba4a37ab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745799197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.745799197
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.4169357245
Short name T1160
Test name
Test status
Simulation time 14228278309 ps
CPU time 27.08 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:41:37 PM PDT 24
Peak memory 200108 kb
Host smart-0ba35950-5488-4c9c-b955-831e03d8d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169357245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4169357245
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1215396414
Short name T180
Test name
Test status
Simulation time 153545177523 ps
CPU time 30.41 seconds
Started Jul 26 06:41:09 PM PDT 24
Finished Jul 26 06:41:39 PM PDT 24
Peak memory 200004 kb
Host smart-f20ebf95-aeb7-4b35-9040-d0e304a7e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215396414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1215396414
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1097501030
Short name T467
Test name
Test status
Simulation time 19961755498 ps
CPU time 16.58 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:41:40 PM PDT 24
Peak memory 197152 kb
Host smart-48a4b0c6-5450-439f-8900-9dfdff74f39d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097501030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1097501030
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2908294590
Short name T1137
Test name
Test status
Simulation time 64915478027 ps
CPU time 97.28 seconds
Started Jul 26 06:41:26 PM PDT 24
Finished Jul 26 06:43:03 PM PDT 24
Peak memory 200436 kb
Host smart-6119b986-2930-4abb-93f1-3a0505b652ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908294590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2908294590
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.580736206
Short name T444
Test name
Test status
Simulation time 5039064547 ps
CPU time 12.15 seconds
Started Jul 26 06:41:25 PM PDT 24
Finished Jul 26 06:41:38 PM PDT 24
Peak memory 200356 kb
Host smart-7697181d-a272-4053-a5de-455dc39cf161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580736206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.580736206
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2452866799
Short name T407
Test name
Test status
Simulation time 115083693884 ps
CPU time 34.45 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:41:58 PM PDT 24
Peak memory 208476 kb
Host smart-bfb478c6-53bf-46da-8822-efd39cd428c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452866799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2452866799
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2886525644
Short name T848
Test name
Test status
Simulation time 14924028945 ps
CPU time 223.77 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:45:08 PM PDT 24
Peak memory 200140 kb
Host smart-ab843242-1930-403a-b257-1aadcc713d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886525644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2886525644
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4279631170
Short name T379
Test name
Test status
Simulation time 4574713377 ps
CPU time 20.15 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:31 PM PDT 24
Peak memory 199440 kb
Host smart-5d062f09-4ac9-4b69-9779-1af3fac95c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279631170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4279631170
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3469735118
Short name T318
Test name
Test status
Simulation time 355954189006 ps
CPU time 35.04 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:41:59 PM PDT 24
Peak memory 200172 kb
Host smart-ae76ff49-5ae6-440a-829a-0e1742b6c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469735118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3469735118
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2160117398
Short name T365
Test name
Test status
Simulation time 2514746319 ps
CPU time 4.57 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:41:27 PM PDT 24
Peak memory 195976 kb
Host smart-7305c81d-b4c1-4013-8214-d3ccab31c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160117398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2160117398
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3088735686
Short name T486
Test name
Test status
Simulation time 647568175 ps
CPU time 2.86 seconds
Started Jul 26 06:41:10 PM PDT 24
Finished Jul 26 06:41:13 PM PDT 24
Peak memory 199024 kb
Host smart-6fa33e89-b1fe-4992-9924-4aef2fcb049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088735686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3088735686
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2826164064
Short name T746
Test name
Test status
Simulation time 97620043911 ps
CPU time 168.2 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:44:11 PM PDT 24
Peak memory 200188 kb
Host smart-3e1ed954-57b6-46b9-aebf-ea9e24decace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826164064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2826164064
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.34418884
Short name T846
Test name
Test status
Simulation time 1678598128 ps
CPU time 2.96 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:41:25 PM PDT 24
Peak memory 198964 kb
Host smart-7002673d-d186-4439-89b8-f4a8c6fc6994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34418884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.34418884
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3154343949
Short name T327
Test name
Test status
Simulation time 54934191294 ps
CPU time 33.76 seconds
Started Jul 26 06:41:11 PM PDT 24
Finished Jul 26 06:41:45 PM PDT 24
Peak memory 200208 kb
Host smart-bd1d13bf-1218-4f45-9f52-54bfbc9ed9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154343949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3154343949
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3190343704
Short name T144
Test name
Test status
Simulation time 35237421889 ps
CPU time 19.37 seconds
Started Jul 26 06:47:02 PM PDT 24
Finished Jul 26 06:47:22 PM PDT 24
Peak memory 200192 kb
Host smart-209c0688-61ec-4844-9c54-2d04677d1817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190343704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3190343704
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.117031484
Short name T795
Test name
Test status
Simulation time 27866526953 ps
CPU time 43.39 seconds
Started Jul 26 06:47:12 PM PDT 24
Finished Jul 26 06:47:56 PM PDT 24
Peak memory 200140 kb
Host smart-e6ae1562-8e96-46b2-a3bd-69e9dbafce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117031484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.117031484
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1279377545
Short name T882
Test name
Test status
Simulation time 57371079316 ps
CPU time 106.44 seconds
Started Jul 26 06:47:11 PM PDT 24
Finished Jul 26 06:48:57 PM PDT 24
Peak memory 200148 kb
Host smart-2496fb2f-c53d-474d-8fff-42f2b16e179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279377545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1279377545
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1864012506
Short name T139
Test name
Test status
Simulation time 97973134085 ps
CPU time 38.12 seconds
Started Jul 26 06:47:10 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200112 kb
Host smart-a2ad72f4-cc8c-43b2-92e6-645228d54253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864012506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1864012506
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3988715586
Short name T888
Test name
Test status
Simulation time 18631948129 ps
CPU time 36.17 seconds
Started Jul 26 06:47:11 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200128 kb
Host smart-ef7bce15-3ce9-453a-944d-cc4f691a8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988715586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3988715586
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.214964013
Short name T835
Test name
Test status
Simulation time 203326641618 ps
CPU time 198.5 seconds
Started Jul 26 06:47:11 PM PDT 24
Finished Jul 26 06:50:30 PM PDT 24
Peak memory 200176 kb
Host smart-29079f46-0f5f-4fd9-afa7-ddff54dfc78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214964013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.214964013
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.452251939
Short name T173
Test name
Test status
Simulation time 54028881369 ps
CPU time 13.21 seconds
Started Jul 26 06:47:12 PM PDT 24
Finished Jul 26 06:47:25 PM PDT 24
Peak memory 200064 kb
Host smart-3bed82c5-af1c-4983-9725-d698d68f1bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452251939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.452251939
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2345817844
Short name T83
Test name
Test status
Simulation time 192206305976 ps
CPU time 80.43 seconds
Started Jul 26 06:47:11 PM PDT 24
Finished Jul 26 06:48:31 PM PDT 24
Peak memory 200136 kb
Host smart-09da16f5-f0fc-47d1-aafc-c11bde918567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345817844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2345817844
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3388729215
Short name T370
Test name
Test status
Simulation time 27478043677 ps
CPU time 12.71 seconds
Started Jul 26 06:47:10 PM PDT 24
Finished Jul 26 06:47:23 PM PDT 24
Peak memory 200148 kb
Host smart-71d2b404-03a6-42a3-b9a1-3f8b8ffd3ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388729215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3388729215
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.239845597
Short name T500
Test name
Test status
Simulation time 99547769455 ps
CPU time 17.45 seconds
Started Jul 26 06:47:10 PM PDT 24
Finished Jul 26 06:47:27 PM PDT 24
Peak memory 200176 kb
Host smart-2729aec5-d668-4422-a85d-88025cb72751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239845597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.239845597
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2778735632
Short name T1147
Test name
Test status
Simulation time 29699089 ps
CPU time 0.58 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:41:23 PM PDT 24
Peak memory 195836 kb
Host smart-e6837d7b-f5e1-4dce-9395-a00157243434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778735632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2778735632
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.965430589
Short name T604
Test name
Test status
Simulation time 132689992222 ps
CPU time 50.21 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:42:13 PM PDT 24
Peak memory 200168 kb
Host smart-9919ad13-f098-4533-9703-98dadf8378d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965430589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.965430589
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.7131526
Short name T523
Test name
Test status
Simulation time 95803001732 ps
CPU time 146.23 seconds
Started Jul 26 06:41:21 PM PDT 24
Finished Jul 26 06:43:47 PM PDT 24
Peak memory 200208 kb
Host smart-256c573f-0114-4b79-b6a7-850a6aed6e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7131526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.7131526
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2179069776
Short name T261
Test name
Test status
Simulation time 163922512247 ps
CPU time 54.37 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:42:18 PM PDT 24
Peak memory 200140 kb
Host smart-940784c2-1e2b-4975-b04a-db1ebed93665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179069776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2179069776
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3743417166
Short name T128
Test name
Test status
Simulation time 37642088005 ps
CPU time 56.09 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:42:19 PM PDT 24
Peak memory 200020 kb
Host smart-8bdf13c9-b300-40e0-855f-9760ceb025ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743417166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3743417166
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.979975282
Short name T66
Test name
Test status
Simulation time 122305722749 ps
CPU time 332.02 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:46:54 PM PDT 24
Peak memory 200164 kb
Host smart-236f24be-607b-411d-8f52-6b4b981eb7c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979975282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.979975282
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.438325739
Short name T870
Test name
Test status
Simulation time 4803190262 ps
CPU time 8.86 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:41:33 PM PDT 24
Peak memory 199560 kb
Host smart-da44a3f9-539f-4227-8b5f-5eccd2f56680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438325739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.438325739
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2874776154
Short name T404
Test name
Test status
Simulation time 43026054041 ps
CPU time 92.29 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:42:56 PM PDT 24
Peak memory 200284 kb
Host smart-041ce17f-6e8c-41cc-aaf0-46083077e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874776154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2874776154
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2049836443
Short name T1111
Test name
Test status
Simulation time 1537959585 ps
CPU time 45.28 seconds
Started Jul 26 06:41:26 PM PDT 24
Finished Jul 26 06:42:11 PM PDT 24
Peak memory 200296 kb
Host smart-a9440ca6-9288-490d-91ae-b4634c2cc4de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049836443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2049836443
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2285541458
Short name T652
Test name
Test status
Simulation time 5226327079 ps
CPU time 21.14 seconds
Started Jul 26 06:41:22 PM PDT 24
Finished Jul 26 06:41:44 PM PDT 24
Peak memory 198156 kb
Host smart-f89d9a54-a6c3-4ae0-84c5-afeeddb8bdb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285541458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2285541458
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1364154525
Short name T1027
Test name
Test status
Simulation time 54835881434 ps
CPU time 56.1 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:42:19 PM PDT 24
Peak memory 200160 kb
Host smart-6b55a076-e6b5-4985-8e3e-49a02da0a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364154525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1364154525
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.813279599
Short name T818
Test name
Test status
Simulation time 5650862129 ps
CPU time 2.62 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:41:25 PM PDT 24
Peak memory 196260 kb
Host smart-3dd2d1fc-a6b9-4640-b9c1-6487fe62b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813279599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.813279599
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2692732153
Short name T549
Test name
Test status
Simulation time 5498319507 ps
CPU time 6.13 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:41:30 PM PDT 24
Peak memory 199952 kb
Host smart-be69a5ee-f594-41aa-af7c-00982af4846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692732153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2692732153
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.462739565
Short name T837
Test name
Test status
Simulation time 22852539575 ps
CPU time 292.77 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:46:17 PM PDT 24
Peak memory 213244 kb
Host smart-a56ff814-f6e0-4156-94af-905325520889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462739565 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.462739565
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4062045674
Short name T396
Test name
Test status
Simulation time 1389829033 ps
CPU time 1.99 seconds
Started Jul 26 06:41:24 PM PDT 24
Finished Jul 26 06:41:27 PM PDT 24
Peak memory 200080 kb
Host smart-d3fa8444-9aaa-4840-9de3-45e8f8e4f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062045674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4062045674
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4069418962
Short name T670
Test name
Test status
Simulation time 47934514852 ps
CPU time 91.87 seconds
Started Jul 26 06:41:23 PM PDT 24
Finished Jul 26 06:42:55 PM PDT 24
Peak memory 200148 kb
Host smart-7d1e51b4-4b3b-4e03-9664-972dd4edb9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069418962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4069418962
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.143942873
Short name T568
Test name
Test status
Simulation time 120429549426 ps
CPU time 140.22 seconds
Started Jul 26 06:47:20 PM PDT 24
Finished Jul 26 06:49:40 PM PDT 24
Peak memory 200144 kb
Host smart-4a9d75d5-6ea1-4e35-8218-658a8bbf7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143942873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.143942873
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2987771691
Short name T715
Test name
Test status
Simulation time 18575160491 ps
CPU time 15.22 seconds
Started Jul 26 06:47:19 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 198908 kb
Host smart-658d73fc-5586-45a3-84dd-46fd45bb0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987771691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2987771691
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2713026625
Short name T511
Test name
Test status
Simulation time 34690943859 ps
CPU time 32.69 seconds
Started Jul 26 06:47:19 PM PDT 24
Finished Jul 26 06:47:52 PM PDT 24
Peak memory 200188 kb
Host smart-758f70d4-9310-4ca4-92a1-64dc111320e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713026625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2713026625
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2346858183
Short name T155
Test name
Test status
Simulation time 115351277827 ps
CPU time 311.87 seconds
Started Jul 26 06:47:20 PM PDT 24
Finished Jul 26 06:52:32 PM PDT 24
Peak memory 199980 kb
Host smart-b43e657e-e609-4f7c-a74e-c6fb67288e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346858183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2346858183
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.853597072
Short name T861
Test name
Test status
Simulation time 226120002225 ps
CPU time 92.59 seconds
Started Jul 26 06:47:20 PM PDT 24
Finished Jul 26 06:48:52 PM PDT 24
Peak memory 200008 kb
Host smart-ad575724-30d1-4695-9fa7-1a13aebf5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853597072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.853597072
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4099269764
Short name T47
Test name
Test status
Simulation time 146845128041 ps
CPU time 183.37 seconds
Started Jul 26 06:47:20 PM PDT 24
Finished Jul 26 06:50:23 PM PDT 24
Peak memory 200192 kb
Host smart-e24320d3-d756-47f9-a83c-a1e820fc9ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099269764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4099269764
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.58588815
Short name T133
Test name
Test status
Simulation time 112135326613 ps
CPU time 84.8 seconds
Started Jul 26 06:47:19 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 200180 kb
Host smart-5b0cedf7-64de-4c12-8f56-d1c7bf5a3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58588815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.58588815
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.948539884
Short name T674
Test name
Test status
Simulation time 23320896987 ps
CPU time 16.47 seconds
Started Jul 26 06:47:17 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 199924 kb
Host smart-99e86531-5513-4c6b-9a67-b1ba1249d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948539884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.948539884
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.778517884
Short name T836
Test name
Test status
Simulation time 51217413416 ps
CPU time 34.57 seconds
Started Jul 26 06:47:20 PM PDT 24
Finished Jul 26 06:47:54 PM PDT 24
Peak memory 200068 kb
Host smart-f5381f0d-de2b-44a7-bf93-35cb3613648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778517884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.778517884
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2719320646
Short name T466
Test name
Test status
Simulation time 17064226 ps
CPU time 0.58 seconds
Started Jul 26 06:41:34 PM PDT 24
Finished Jul 26 06:41:35 PM PDT 24
Peak memory 195564 kb
Host smart-6541be79-1092-4e4c-8c82-0d36ca7e9bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719320646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2719320646
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.922692839
Short name T964
Test name
Test status
Simulation time 27484614733 ps
CPU time 10.94 seconds
Started Jul 26 06:41:31 PM PDT 24
Finished Jul 26 06:41:42 PM PDT 24
Peak memory 200136 kb
Host smart-22c16d87-e21a-4713-8cc6-3997b97dcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922692839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.922692839
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1940696934
Short name T731
Test name
Test status
Simulation time 20135125138 ps
CPU time 28.88 seconds
Started Jul 26 06:41:33 PM PDT 24
Finished Jul 26 06:42:02 PM PDT 24
Peak memory 200136 kb
Host smart-f8105133-fad9-4a5e-8daa-44574e0a61c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940696934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1940696934
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3866777423
Short name T221
Test name
Test status
Simulation time 11433920054 ps
CPU time 17.39 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:41:49 PM PDT 24
Peak memory 200184 kb
Host smart-2b39a05e-7b1f-4bdf-a049-37314290ab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866777423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3866777423
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4006209090
Short name T420
Test name
Test status
Simulation time 308759140735 ps
CPU time 304.61 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:46:37 PM PDT 24
Peak memory 199132 kb
Host smart-6c470d6b-43f8-455e-9e75-43d9b78c6312
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006209090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4006209090
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.887485082
Short name T596
Test name
Test status
Simulation time 76162644380 ps
CPU time 182.86 seconds
Started Jul 26 06:41:33 PM PDT 24
Finished Jul 26 06:44:36 PM PDT 24
Peak memory 200124 kb
Host smart-75d93088-4fd3-4c83-8a39-6b558334758e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887485082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.887485082
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2094644729
Short name T452
Test name
Test status
Simulation time 4149015366 ps
CPU time 3.85 seconds
Started Jul 26 06:41:33 PM PDT 24
Finished Jul 26 06:41:37 PM PDT 24
Peak memory 198656 kb
Host smart-4455d323-9603-4bf1-bb37-a1023d917f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094644729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2094644729
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.4064963809
Short name T546
Test name
Test status
Simulation time 34994632372 ps
CPU time 12.05 seconds
Started Jul 26 06:41:31 PM PDT 24
Finished Jul 26 06:41:43 PM PDT 24
Peak memory 198524 kb
Host smart-e3d3ef0c-8094-4644-84d3-86bac029928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064963809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4064963809
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.156914570
Short name T1136
Test name
Test status
Simulation time 14890185486 ps
CPU time 67.85 seconds
Started Jul 26 06:41:33 PM PDT 24
Finished Jul 26 06:42:41 PM PDT 24
Peak memory 200132 kb
Host smart-fd10226b-90ee-4f4a-8b23-e30488b4efc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156914570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.156914570
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3271385937
Short name T354
Test name
Test status
Simulation time 7249049986 ps
CPU time 26.93 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:41:59 PM PDT 24
Peak memory 198160 kb
Host smart-d40b56a1-518e-4d9c-95f3-fe95522097bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271385937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3271385937
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.482907011
Short name T613
Test name
Test status
Simulation time 30939485980 ps
CPU time 27.71 seconds
Started Jul 26 06:41:37 PM PDT 24
Finished Jul 26 06:42:05 PM PDT 24
Peak memory 200444 kb
Host smart-eb4c9968-831e-4202-aab4-ee438edc331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482907011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.482907011
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.979648792
Short name T28
Test name
Test status
Simulation time 3053469975 ps
CPU time 4.08 seconds
Started Jul 26 06:41:31 PM PDT 24
Finished Jul 26 06:41:35 PM PDT 24
Peak memory 196696 kb
Host smart-34c15145-1a50-4d8c-92df-b971a835c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979648792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.979648792
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2961167660
Short name T941
Test name
Test status
Simulation time 700527620 ps
CPU time 2.17 seconds
Started Jul 26 06:41:36 PM PDT 24
Finished Jul 26 06:41:38 PM PDT 24
Peak memory 200328 kb
Host smart-9a527c56-4b3a-4ddb-8c9e-42f092edbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961167660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2961167660
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2519291140
Short name T876
Test name
Test status
Simulation time 27549826250 ps
CPU time 222.2 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:45:14 PM PDT 24
Peak memory 214060 kb
Host smart-0ad39f1a-3688-45b1-9e06-4ca5391b2410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519291140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2519291140
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3305705965
Short name T405
Test name
Test status
Simulation time 6951436657 ps
CPU time 9.63 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:41:42 PM PDT 24
Peak memory 200100 kb
Host smart-a82a3022-6557-467f-bab8-ac501ff98cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305705965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3305705965
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3378033931
Short name T1132
Test name
Test status
Simulation time 56428076194 ps
CPU time 74.83 seconds
Started Jul 26 06:41:34 PM PDT 24
Finished Jul 26 06:42:49 PM PDT 24
Peak memory 200128 kb
Host smart-3ea6db56-6b05-4323-bec4-599f220f3610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378033931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3378033931
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1902174808
Short name T975
Test name
Test status
Simulation time 35074187606 ps
CPU time 22.76 seconds
Started Jul 26 06:47:18 PM PDT 24
Finished Jul 26 06:47:41 PM PDT 24
Peak memory 200092 kb
Host smart-a610d0a1-768b-43c2-aa2c-38fc1e2c2710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902174808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1902174808
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.302584865
Short name T350
Test name
Test status
Simulation time 29510283098 ps
CPU time 11.57 seconds
Started Jul 26 06:47:17 PM PDT 24
Finished Jul 26 06:47:28 PM PDT 24
Peak memory 198184 kb
Host smart-d640c05d-03bb-44e2-bf53-877935e69829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302584865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.302584865
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2276381046
Short name T631
Test name
Test status
Simulation time 39888345488 ps
CPU time 15.17 seconds
Started Jul 26 06:47:19 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 199132 kb
Host smart-188bc2d0-ce34-40dc-af07-8c596e6275d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276381046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2276381046
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.840837078
Short name T792
Test name
Test status
Simulation time 74416802245 ps
CPU time 11.86 seconds
Started Jul 26 06:47:24 PM PDT 24
Finished Jul 26 06:47:36 PM PDT 24
Peak memory 200096 kb
Host smart-4a58eba3-a297-4523-843b-50c7d5d696f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840837078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.840837078
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2454401623
Short name T712
Test name
Test status
Simulation time 109047238790 ps
CPU time 203.28 seconds
Started Jul 26 06:47:25 PM PDT 24
Finished Jul 26 06:50:49 PM PDT 24
Peak memory 200148 kb
Host smart-0bbc4f5f-1a79-4960-a2db-3e39f774f1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454401623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2454401623
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1625159284
Short name T265
Test name
Test status
Simulation time 96055895677 ps
CPU time 222.4 seconds
Started Jul 26 06:47:25 PM PDT 24
Finished Jul 26 06:51:08 PM PDT 24
Peak memory 200412 kb
Host smart-47a1eb6d-c404-458b-85e2-4819fbbbd757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625159284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1625159284
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.370196702
Short name T1041
Test name
Test status
Simulation time 40875585436 ps
CPU time 50.72 seconds
Started Jul 26 06:47:24 PM PDT 24
Finished Jul 26 06:48:15 PM PDT 24
Peak memory 200136 kb
Host smart-ef725c19-1677-47d2-818f-452ce5fc8ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370196702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.370196702
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1628141378
Short name T860
Test name
Test status
Simulation time 34630888 ps
CPU time 0.55 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:39:23 PM PDT 24
Peak memory 195572 kb
Host smart-220fd501-9a9f-4da5-b408-aa2fbc270459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628141378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1628141378
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2928273044
Short name T50
Test name
Test status
Simulation time 143779306726 ps
CPU time 398.16 seconds
Started Jul 26 06:39:15 PM PDT 24
Finished Jul 26 06:45:54 PM PDT 24
Peak memory 200080 kb
Host smart-2e34b3bc-2395-40f5-93e9-8b8cf020cd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928273044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2928273044
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3444173213
Short name T164
Test name
Test status
Simulation time 23540461067 ps
CPU time 34.77 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:39:51 PM PDT 24
Peak memory 199884 kb
Host smart-a13f64ca-e0ec-4b03-afa1-df73e895568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444173213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3444173213
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.478117034
Short name T1124
Test name
Test status
Simulation time 6639669853 ps
CPU time 3.14 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:39:19 PM PDT 24
Peak memory 196708 kb
Host smart-ff3b1337-22dd-4857-b282-1b00eb6b456e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478117034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.478117034
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2564051901
Short name T664
Test name
Test status
Simulation time 22086041299 ps
CPU time 143.56 seconds
Started Jul 26 06:39:24 PM PDT 24
Finished Jul 26 06:41:47 PM PDT 24
Peak memory 200116 kb
Host smart-28d2b614-b32a-4aac-acf7-dc09de2f7eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564051901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2564051901
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2075078072
Short name T698
Test name
Test status
Simulation time 14555683179 ps
CPU time 8.44 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:39:31 PM PDT 24
Peak memory 199856 kb
Host smart-29cd560f-7191-4a97-becf-a6108a3c8ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075078072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2075078072
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.558403072
Short name T586
Test name
Test status
Simulation time 32529905182 ps
CPU time 12.68 seconds
Started Jul 26 06:39:17 PM PDT 24
Finished Jul 26 06:39:30 PM PDT 24
Peak memory 200068 kb
Host smart-dd393974-9ce4-4f14-b6ea-a58f7e5c0ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558403072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.558403072
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2583207195
Short name T1152
Test name
Test status
Simulation time 11724278893 ps
CPU time 89.02 seconds
Started Jul 26 06:39:21 PM PDT 24
Finished Jul 26 06:40:50 PM PDT 24
Peak memory 200080 kb
Host smart-9e3416cf-4f31-45c9-971b-aec6501c9088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583207195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2583207195
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.759925377
Short name T18
Test name
Test status
Simulation time 7602547205 ps
CPU time 64.44 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:40:21 PM PDT 24
Peak memory 198364 kb
Host smart-649f394b-c0c2-4de5-9b63-b1be0e2dff2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759925377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.759925377
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1488409609
Short name T784
Test name
Test status
Simulation time 47792969306 ps
CPU time 64.19 seconds
Started Jul 26 06:39:17 PM PDT 24
Finished Jul 26 06:40:21 PM PDT 24
Peak memory 200168 kb
Host smart-183db765-5655-4ff2-95f3-e989cd9826f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488409609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1488409609
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.494400134
Short name T945
Test name
Test status
Simulation time 525927681 ps
CPU time 1.52 seconds
Started Jul 26 06:39:17 PM PDT 24
Finished Jul 26 06:39:18 PM PDT 24
Peak memory 195948 kb
Host smart-d848f0d3-bc42-4c7b-8fa8-e3b75c0e72bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494400134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.494400134
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1122430735
Short name T32
Test name
Test status
Simulation time 149295507 ps
CPU time 0.81 seconds
Started Jul 26 06:39:25 PM PDT 24
Finished Jul 26 06:39:26 PM PDT 24
Peak memory 218356 kb
Host smart-21cc84b6-3527-4ed9-ab25-18bd68f635d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122430735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1122430735
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3194148763
Short name T532
Test name
Test status
Simulation time 714373960 ps
CPU time 1.32 seconds
Started Jul 26 06:39:10 PM PDT 24
Finished Jul 26 06:39:12 PM PDT 24
Peak memory 199788 kb
Host smart-cd268611-798f-449d-a1ba-77c5813c3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194148763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3194148763
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3821521128
Short name T1139
Test name
Test status
Simulation time 198183570700 ps
CPU time 490.03 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:47:32 PM PDT 24
Peak memory 200480 kb
Host smart-eb99527b-1bcc-4973-9586-c96d48844aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821521128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3821521128
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1931714579
Short name T749
Test name
Test status
Simulation time 44555063487 ps
CPU time 539.21 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:48:22 PM PDT 24
Peak memory 208476 kb
Host smart-bf9dc4e6-ca47-4ad0-81f6-b10f4b08cd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931714579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1931714579
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1670128733
Short name T728
Test name
Test status
Simulation time 715253575 ps
CPU time 3.32 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:39:19 PM PDT 24
Peak memory 200020 kb
Host smart-670bf444-4d2a-4b0a-9da2-3a4a7f41c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670128733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1670128733
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3388767319
Short name T988
Test name
Test status
Simulation time 57497497310 ps
CPU time 62.66 seconds
Started Jul 26 06:39:16 PM PDT 24
Finished Jul 26 06:40:19 PM PDT 24
Peak memory 200192 kb
Host smart-7280504c-88f1-4090-a96d-1281393775d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388767319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3388767319
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2641406089
Short name T966
Test name
Test status
Simulation time 57033461 ps
CPU time 0.53 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:41:46 PM PDT 24
Peak memory 195528 kb
Host smart-9d7e5043-b497-41fa-ba4b-9007251cf14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641406089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2641406089
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3163081916
Short name T266
Test name
Test status
Simulation time 54730139193 ps
CPU time 90.41 seconds
Started Jul 26 06:41:46 PM PDT 24
Finished Jul 26 06:43:17 PM PDT 24
Peak memory 200116 kb
Host smart-60ed56ba-127b-456c-aaca-875eaaca4679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163081916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3163081916
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2920371010
Short name T949
Test name
Test status
Simulation time 106287047546 ps
CPU time 208.1 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:45:11 PM PDT 24
Peak memory 200084 kb
Host smart-df2b63dd-8fef-4a0d-85f6-aa2eba377c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920371010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2920371010
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2192180663
Short name T1119
Test name
Test status
Simulation time 162772411011 ps
CPU time 396.2 seconds
Started Jul 26 06:41:44 PM PDT 24
Finished Jul 26 06:48:20 PM PDT 24
Peak memory 200108 kb
Host smart-104f01bf-d1eb-4014-b844-19016d4654fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192180663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2192180663
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.79084367
Short name T521
Test name
Test status
Simulation time 59990555521 ps
CPU time 25.1 seconds
Started Jul 26 06:41:44 PM PDT 24
Finished Jul 26 06:42:09 PM PDT 24
Peak memory 200072 kb
Host smart-5633dfd8-1f84-4fa9-af83-e0339faa9db3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79084367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.79084367
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2651343365
Short name T658
Test name
Test status
Simulation time 83170755039 ps
CPU time 700.15 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:53:23 PM PDT 24
Peak memory 200216 kb
Host smart-26de969c-7981-464e-b7e3-4c0399bc623b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651343365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2651343365
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3662657763
Short name T381
Test name
Test status
Simulation time 1988629086 ps
CPU time 1.77 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:41:45 PM PDT 24
Peak memory 198748 kb
Host smart-2836f8bb-81aa-4582-a208-3da610244e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662657763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3662657763
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1327783915
Short name T1094
Test name
Test status
Simulation time 265081754583 ps
CPU time 73.28 seconds
Started Jul 26 06:41:44 PM PDT 24
Finished Jul 26 06:42:57 PM PDT 24
Peak memory 200276 kb
Host smart-a260cde3-7067-4b7d-9d35-dabd4bf082c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327783915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1327783915
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1468243825
Short name T962
Test name
Test status
Simulation time 5163631407 ps
CPU time 64.95 seconds
Started Jul 26 06:41:44 PM PDT 24
Finished Jul 26 06:42:49 PM PDT 24
Peak memory 200036 kb
Host smart-e45112ae-38fa-4106-b15e-0d84d1eb21c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468243825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1468243825
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1960946980
Short name T402
Test name
Test status
Simulation time 3910860019 ps
CPU time 15.97 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:41:59 PM PDT 24
Peak memory 198080 kb
Host smart-02b7222d-398b-4b72-acc8-b21cf61e8df4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960946980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1960946980
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.368790033
Short name T1000
Test name
Test status
Simulation time 47599762571 ps
CPU time 83.69 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:43:07 PM PDT 24
Peak memory 200144 kb
Host smart-b3e8d7da-55dc-4ce2-b882-6ce5dfd17d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368790033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.368790033
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2377700923
Short name T552
Test name
Test status
Simulation time 75246810643 ps
CPU time 112.28 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:43:38 PM PDT 24
Peak memory 195976 kb
Host smart-25ba2ed2-b06e-45d0-b5ae-743298691e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377700923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2377700923
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3274328487
Short name T1171
Test name
Test status
Simulation time 316871277 ps
CPU time 1.18 seconds
Started Jul 26 06:41:32 PM PDT 24
Finished Jul 26 06:41:34 PM PDT 24
Peak memory 198528 kb
Host smart-fc098a22-a1c6-4af9-b424-c94861a36d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274328487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3274328487
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.4216759576
Short name T1030
Test name
Test status
Simulation time 65029406720 ps
CPU time 160.05 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:44:23 PM PDT 24
Peak memory 200156 kb
Host smart-2f22c2bb-452c-46b2-a15b-67e0f1b28464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216759576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4216759576
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1351649545
Short name T22
Test name
Test status
Simulation time 48272818005 ps
CPU time 588.12 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:51:33 PM PDT 24
Peak memory 227888 kb
Host smart-cac81d83-3748-470c-96a6-55ee0de54e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351649545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1351649545
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2425004809
Short name T319
Test name
Test status
Simulation time 9241696616 ps
CPU time 2.05 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:41:47 PM PDT 24
Peak memory 199688 kb
Host smart-26fe7c2a-b515-47ee-9337-6e43ad01df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425004809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2425004809
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.700161862
Short name T753
Test name
Test status
Simulation time 95403475688 ps
CPU time 80.23 seconds
Started Jul 26 06:41:31 PM PDT 24
Finished Jul 26 06:42:52 PM PDT 24
Peak memory 200116 kb
Host smart-fcac1b83-2224-4f4e-b272-0ce116125841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700161862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.700161862
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3126320548
Short name T147
Test name
Test status
Simulation time 21668058575 ps
CPU time 19.25 seconds
Started Jul 26 06:47:25 PM PDT 24
Finished Jul 26 06:47:45 PM PDT 24
Peak memory 200188 kb
Host smart-14577c9c-26da-4cd6-8dd6-1759cc2c8589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126320548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3126320548
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1854505804
Short name T971
Test name
Test status
Simulation time 51831321800 ps
CPU time 34.03 seconds
Started Jul 26 06:47:24 PM PDT 24
Finished Jul 26 06:47:58 PM PDT 24
Peak memory 200124 kb
Host smart-e3a1e0a5-749f-4e58-aede-b343b214a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854505804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1854505804
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3906142706
Short name T1055
Test name
Test status
Simulation time 15784832522 ps
CPU time 23.11 seconds
Started Jul 26 06:47:25 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200072 kb
Host smart-8101e71e-d5f6-4a0d-b1e3-cdd00ec89606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906142706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3906142706
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1502123637
Short name T778
Test name
Test status
Simulation time 8777714465 ps
CPU time 17.28 seconds
Started Jul 26 06:47:32 PM PDT 24
Finished Jul 26 06:47:49 PM PDT 24
Peak memory 200132 kb
Host smart-b52d1fff-a6c0-470a-9ef2-a38ad5f54238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502123637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1502123637
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.370974356
Short name T639
Test name
Test status
Simulation time 31471751042 ps
CPU time 58.27 seconds
Started Jul 26 06:47:32 PM PDT 24
Finished Jul 26 06:48:31 PM PDT 24
Peak memory 200144 kb
Host smart-24428984-0bd4-49b1-a994-0ef47e9dd365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370974356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.370974356
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2505037735
Short name T699
Test name
Test status
Simulation time 167890343500 ps
CPU time 92.49 seconds
Started Jul 26 06:47:34 PM PDT 24
Finished Jul 26 06:49:06 PM PDT 24
Peak memory 200172 kb
Host smart-253fff9f-b977-4928-b7bf-4472364fb847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505037735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2505037735
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2241532416
Short name T940
Test name
Test status
Simulation time 72072711177 ps
CPU time 42.56 seconds
Started Jul 26 06:47:33 PM PDT 24
Finished Jul 26 06:48:16 PM PDT 24
Peak memory 200076 kb
Host smart-0a2eaad2-a791-4534-9346-23fe068af629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241532416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2241532416
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.500764990
Short name T388
Test name
Test status
Simulation time 91192445 ps
CPU time 0.55 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:41:55 PM PDT 24
Peak memory 194964 kb
Host smart-06fd72a5-3bb0-4874-a7c8-13559a76d720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500764990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.500764990
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.949685581
Short name T843
Test name
Test status
Simulation time 84284243490 ps
CPU time 70.64 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:42:56 PM PDT 24
Peak memory 200120 kb
Host smart-ee1c9618-2915-4222-8be5-7fedfc177c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949685581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.949685581
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3220100627
Short name T141
Test name
Test status
Simulation time 244743028037 ps
CPU time 125.85 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:43:51 PM PDT 24
Peak memory 200168 kb
Host smart-0b6daa14-3e46-4f26-aaa6-ced085f3c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220100627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3220100627
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.507318161
Short name T398
Test name
Test status
Simulation time 152604184960 ps
CPU time 226.92 seconds
Started Jul 26 06:41:46 PM PDT 24
Finished Jul 26 06:45:33 PM PDT 24
Peak memory 200132 kb
Host smart-44d30dc2-c8a4-480c-a753-704a0bfb62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507318161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.507318161
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.671934890
Short name T474
Test name
Test status
Simulation time 27239086659 ps
CPU time 21.86 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:42:07 PM PDT 24
Peak memory 199716 kb
Host smart-a1f77e9e-4576-4a34-86b4-85febecc887c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671934890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.671934890
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.167051562
Short name T979
Test name
Test status
Simulation time 76629480584 ps
CPU time 654.57 seconds
Started Jul 26 06:41:53 PM PDT 24
Finished Jul 26 06:52:48 PM PDT 24
Peak memory 200148 kb
Host smart-bb7205ce-699c-4e11-8ae6-10fe32f7e9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167051562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.167051562
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1840848774
Short name T386
Test name
Test status
Simulation time 1523804667 ps
CPU time 3.05 seconds
Started Jul 26 06:41:54 PM PDT 24
Finished Jul 26 06:41:57 PM PDT 24
Peak memory 197468 kb
Host smart-9293f7f4-0afd-466f-adc0-1a20715f67cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840848774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1840848774
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2454639042
Short name T42
Test name
Test status
Simulation time 54682274093 ps
CPU time 24.12 seconds
Started Jul 26 06:41:44 PM PDT 24
Finished Jul 26 06:42:09 PM PDT 24
Peak memory 195996 kb
Host smart-5e70ff53-edda-43ca-95ce-b6bf5f4efd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454639042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2454639042
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1426645627
Short name T642
Test name
Test status
Simulation time 21873537205 ps
CPU time 347 seconds
Started Jul 26 06:41:58 PM PDT 24
Finished Jul 26 06:47:45 PM PDT 24
Peak memory 200180 kb
Host smart-6c3b982c-4deb-4c67-9315-7609d5a4024f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426645627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1426645627
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2279266446
Short name T353
Test name
Test status
Simulation time 5779815062 ps
CPU time 50.41 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:42:35 PM PDT 24
Peak memory 199512 kb
Host smart-3b1c5ef6-d7f2-47e4-8bf4-2b1fed47aa28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279266446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2279266446
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4264887489
Short name T1102
Test name
Test status
Simulation time 46584126154 ps
CPU time 68.26 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:43:03 PM PDT 24
Peak memory 200132 kb
Host smart-9dcec8a2-d702-4354-b574-a4ef58d02534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264887489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4264887489
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1205620721
Short name T477
Test name
Test status
Simulation time 2881559926 ps
CPU time 1.39 seconds
Started Jul 26 06:42:03 PM PDT 24
Finished Jul 26 06:42:04 PM PDT 24
Peak memory 195992 kb
Host smart-77afdab6-9e85-45f9-bedd-f88ae04b98aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205620721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1205620721
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2682241372
Short name T1167
Test name
Test status
Simulation time 5327477678 ps
CPU time 19.3 seconds
Started Jul 26 06:41:43 PM PDT 24
Finished Jul 26 06:42:03 PM PDT 24
Peak memory 199924 kb
Host smart-59c34347-bf58-41fc-8ca2-74e6cdb4cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682241372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2682241372
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1010223379
Short name T622
Test name
Test status
Simulation time 173176666607 ps
CPU time 1310.36 seconds
Started Jul 26 06:41:58 PM PDT 24
Finished Jul 26 07:03:48 PM PDT 24
Peak memory 216184 kb
Host smart-2a4adaaa-60a3-4854-8f19-c83946ace0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010223379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1010223379
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3430678739
Short name T1031
Test name
Test status
Simulation time 140814199227 ps
CPU time 1934.56 seconds
Started Jul 26 06:42:00 PM PDT 24
Finished Jul 26 07:14:15 PM PDT 24
Peak memory 230680 kb
Host smart-b36572a0-69bc-4a52-94ae-ab21c3df5546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430678739 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3430678739
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1573502589
Short name T980
Test name
Test status
Simulation time 1384815009 ps
CPU time 4.71 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:42:00 PM PDT 24
Peak memory 198492 kb
Host smart-ee78e007-411a-49c6-b10f-035f9ef93691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573502589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1573502589
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2354624340
Short name T929
Test name
Test status
Simulation time 10241503337 ps
CPU time 8.39 seconds
Started Jul 26 06:41:45 PM PDT 24
Finished Jul 26 06:41:53 PM PDT 24
Peak memory 200164 kb
Host smart-3de52f25-e92f-4147-a189-cbecd3f1017c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354624340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2354624340
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1788536251
Short name T874
Test name
Test status
Simulation time 12841774031 ps
CPU time 10.47 seconds
Started Jul 26 06:47:33 PM PDT 24
Finished Jul 26 06:47:43 PM PDT 24
Peak memory 200132 kb
Host smart-fd818cd3-30e9-4519-b9cd-644e2810440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788536251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1788536251
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3419641831
Short name T427
Test name
Test status
Simulation time 42217281713 ps
CPU time 14.97 seconds
Started Jul 26 06:47:33 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200144 kb
Host smart-cd18d519-fa70-416e-a8e7-3562ca0c62a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419641831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3419641831
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1860150215
Short name T518
Test name
Test status
Simulation time 37120587030 ps
CPU time 14.13 seconds
Started Jul 26 06:47:34 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 198660 kb
Host smart-850f51d9-f288-4b07-85ea-3a512f56c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860150215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1860150215
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.743571108
Short name T827
Test name
Test status
Simulation time 72338053838 ps
CPU time 92.03 seconds
Started Jul 26 06:47:33 PM PDT 24
Finished Jul 26 06:49:05 PM PDT 24
Peak memory 200168 kb
Host smart-c85d4ab0-b247-42cf-b880-0079ce491993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743571108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.743571108
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1071372028
Short name T68
Test name
Test status
Simulation time 93849976932 ps
CPU time 39.05 seconds
Started Jul 26 06:47:32 PM PDT 24
Finished Jul 26 06:48:12 PM PDT 24
Peak memory 200124 kb
Host smart-2d2f9781-2005-451c-ad96-e07f9c134179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071372028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1071372028
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2491728614
Short name T183
Test name
Test status
Simulation time 19014854088 ps
CPU time 17.27 seconds
Started Jul 26 06:47:36 PM PDT 24
Finished Jul 26 06:47:54 PM PDT 24
Peak memory 200256 kb
Host smart-1356bd88-1c8b-4bcb-aeed-6352e801f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491728614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2491728614
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1854649188
Short name T335
Test name
Test status
Simulation time 49836664022 ps
CPU time 41.88 seconds
Started Jul 26 06:47:35 PM PDT 24
Finished Jul 26 06:48:16 PM PDT 24
Peak memory 200136 kb
Host smart-6e8c3891-50a8-42c6-ac63-a38ccefbaad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854649188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1854649188
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1821287821
Short name T305
Test name
Test status
Simulation time 158182125372 ps
CPU time 78.33 seconds
Started Jul 26 06:47:31 PM PDT 24
Finished Jul 26 06:48:49 PM PDT 24
Peak memory 200180 kb
Host smart-ea0a4a23-b954-4157-a9b2-dd239309e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821287821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1821287821
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.838132786
Short name T939
Test name
Test status
Simulation time 60894429041 ps
CPU time 126.91 seconds
Started Jul 26 06:47:41 PM PDT 24
Finished Jul 26 06:49:48 PM PDT 24
Peak memory 200184 kb
Host smart-b98d5981-97d6-4093-888f-e627beafcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838132786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.838132786
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1082026520
Short name T368
Test name
Test status
Simulation time 47545752 ps
CPU time 0.55 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:42:14 PM PDT 24
Peak memory 195552 kb
Host smart-802eb730-fb0b-4875-88f0-ac2b4adb0ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082026520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1082026520
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2918109339
Short name T619
Test name
Test status
Simulation time 245333507753 ps
CPU time 22.21 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:42:17 PM PDT 24
Peak memory 200148 kb
Host smart-1612aca1-7012-4b80-ad4d-4de43b106a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918109339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2918109339
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3377833416
Short name T45
Test name
Test status
Simulation time 40389665764 ps
CPU time 28.86 seconds
Started Jul 26 06:41:54 PM PDT 24
Finished Jul 26 06:42:23 PM PDT 24
Peak memory 199992 kb
Host smart-383acd98-d658-4695-93b8-e8a0f562a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377833416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3377833416
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.1347914569
Short name T1068
Test name
Test status
Simulation time 20015853338 ps
CPU time 29.15 seconds
Started Jul 26 06:41:59 PM PDT 24
Finished Jul 26 06:42:28 PM PDT 24
Peak memory 197928 kb
Host smart-5f329b8d-c685-4ff3-b15f-31d1ed13c0a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347914569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1347914569
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2450897403
Short name T761
Test name
Test status
Simulation time 193917855102 ps
CPU time 622.61 seconds
Started Jul 26 06:41:58 PM PDT 24
Finished Jul 26 06:52:21 PM PDT 24
Peak memory 200108 kb
Host smart-37164a84-a4c1-4b1c-9c39-c508f3087377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450897403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2450897403
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2817514512
Short name T932
Test name
Test status
Simulation time 11275743503 ps
CPU time 6.45 seconds
Started Jul 26 06:42:02 PM PDT 24
Finished Jul 26 06:42:09 PM PDT 24
Peak memory 198800 kb
Host smart-46260a73-1587-4885-a798-2567e3a16000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817514512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2817514512
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.4138866961
Short name T736
Test name
Test status
Simulation time 56889923045 ps
CPU time 88.17 seconds
Started Jul 26 06:42:03 PM PDT 24
Finished Jul 26 06:43:31 PM PDT 24
Peak memory 199904 kb
Host smart-a09377dc-c44d-4a36-aff7-cf211072632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138866961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4138866961
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.472760618
Short name T1091
Test name
Test status
Simulation time 3918854763 ps
CPU time 99.22 seconds
Started Jul 26 06:41:59 PM PDT 24
Finished Jul 26 06:43:39 PM PDT 24
Peak memory 200184 kb
Host smart-543afd9c-286d-41af-81b5-fa63b7236590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472760618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.472760618
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1903288167
Short name T411
Test name
Test status
Simulation time 4666217259 ps
CPU time 40.42 seconds
Started Jul 26 06:41:55 PM PDT 24
Finished Jul 26 06:42:36 PM PDT 24
Peak memory 198272 kb
Host smart-b1fd7ee2-8f6f-4831-94ef-fa7edc5700c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903288167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1903288167
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2257099800
Short name T140
Test name
Test status
Simulation time 96249399344 ps
CPU time 303.74 seconds
Started Jul 26 06:41:54 PM PDT 24
Finished Jul 26 06:46:58 PM PDT 24
Peak memory 200212 kb
Host smart-40fb0097-ad78-4b42-b6dd-570f0b8b8ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257099800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2257099800
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.423314912
Short name T960
Test name
Test status
Simulation time 3565373115 ps
CPU time 2.21 seconds
Started Jul 26 06:41:56 PM PDT 24
Finished Jul 26 06:41:58 PM PDT 24
Peak memory 196524 kb
Host smart-2da0aa30-87cf-4fdf-9c93-da4c5b5ed4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423314912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.423314912
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2407696567
Short name T4
Test name
Test status
Simulation time 5384194273 ps
CPU time 15.78 seconds
Started Jul 26 06:41:54 PM PDT 24
Finished Jul 26 06:42:10 PM PDT 24
Peak memory 199992 kb
Host smart-e77609cc-6f14-438b-a4bd-76633fd932fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407696567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2407696567
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.55139924
Short name T117
Test name
Test status
Simulation time 26287907640 ps
CPU time 217.4 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:45:51 PM PDT 24
Peak memory 208512 kb
Host smart-8b5613e7-bc98-484f-b736-7199ebbf47f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55139924 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.55139924
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1601777000
Short name T3
Test name
Test status
Simulation time 1263292207 ps
CPU time 2.41 seconds
Started Jul 26 06:41:59 PM PDT 24
Finished Jul 26 06:42:01 PM PDT 24
Peak memory 198952 kb
Host smart-73bc5188-657b-482c-af31-fbfb59a55d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601777000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1601777000
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2152533171
Short name T625
Test name
Test status
Simulation time 56606548419 ps
CPU time 21.92 seconds
Started Jul 26 06:41:59 PM PDT 24
Finished Jul 26 06:42:21 PM PDT 24
Peak memory 198016 kb
Host smart-46c6eb1b-346b-4a2f-a339-7a9432aa7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152533171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2152533171
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3267226805
Short name T231
Test name
Test status
Simulation time 36225719091 ps
CPU time 15.81 seconds
Started Jul 26 06:47:43 PM PDT 24
Finished Jul 26 06:47:59 PM PDT 24
Peak memory 200076 kb
Host smart-c4169b9d-9ba9-4ecd-b62e-d079eba5816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267226805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3267226805
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3753265869
Short name T883
Test name
Test status
Simulation time 121558471772 ps
CPU time 420.09 seconds
Started Jul 26 06:47:39 PM PDT 24
Finished Jul 26 06:54:39 PM PDT 24
Peak memory 200264 kb
Host smart-75dae381-6207-4e82-9bb4-d10d1fc899eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753265869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3753265869
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.258462926
Short name T254
Test name
Test status
Simulation time 47991463506 ps
CPU time 74.62 seconds
Started Jul 26 06:47:46 PM PDT 24
Finished Jul 26 06:49:01 PM PDT 24
Peak memory 200164 kb
Host smart-aaf788af-ea13-4592-988d-1b20fa345a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258462926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.258462926
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1098815448
Short name T826
Test name
Test status
Simulation time 66949416719 ps
CPU time 13.53 seconds
Started Jul 26 06:47:46 PM PDT 24
Finished Jul 26 06:48:00 PM PDT 24
Peak memory 200184 kb
Host smart-4e9c29c1-889d-4d15-9f87-564c4d3f4ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098815448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1098815448
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.876664393
Short name T1021
Test name
Test status
Simulation time 84775578915 ps
CPU time 18.23 seconds
Started Jul 26 06:47:41 PM PDT 24
Finished Jul 26 06:48:00 PM PDT 24
Peak memory 200148 kb
Host smart-f4dce745-f3c1-45ec-82e8-5e52157b209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876664393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.876664393
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.36543957
Short name T740
Test name
Test status
Simulation time 21129586653 ps
CPU time 24.08 seconds
Started Jul 26 06:47:40 PM PDT 24
Finished Jul 26 06:48:04 PM PDT 24
Peak memory 200184 kb
Host smart-ff2f0249-cc4f-4fa5-9f43-2fcb8cf029e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36543957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.36543957
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2270457326
Short name T1085
Test name
Test status
Simulation time 33858964430 ps
CPU time 27.59 seconds
Started Jul 26 06:47:42 PM PDT 24
Finished Jul 26 06:48:10 PM PDT 24
Peak memory 200304 kb
Host smart-69128697-f26d-4bd0-b861-3521f22c03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270457326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2270457326
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2944936736
Short name T738
Test name
Test status
Simulation time 31084404538 ps
CPU time 25.03 seconds
Started Jul 26 06:47:41 PM PDT 24
Finished Jul 26 06:48:06 PM PDT 24
Peak memory 200172 kb
Host smart-64d08aac-2c16-4048-9ed5-dc2d4440a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944936736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2944936736
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1768459533
Short name T780
Test name
Test status
Simulation time 13118293 ps
CPU time 0.56 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:42:14 PM PDT 24
Peak memory 195632 kb
Host smart-c662b1bd-c36f-40f5-ab63-9835a277765c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768459533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1768459533
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.544404340
Short name T316
Test name
Test status
Simulation time 35328099711 ps
CPU time 50.14 seconds
Started Jul 26 06:42:12 PM PDT 24
Finished Jul 26 06:43:03 PM PDT 24
Peak memory 200148 kb
Host smart-fa81ed07-ac20-4904-b141-3604a371bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544404340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.544404340
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1590803160
Short name T635
Test name
Test status
Simulation time 105494533795 ps
CPU time 86.57 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:43:40 PM PDT 24
Peak memory 200192 kb
Host smart-aa93dc5e-f615-47eb-8104-34cc5367c4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590803160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1590803160
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1088252242
Short name T134
Test name
Test status
Simulation time 134015056906 ps
CPU time 53.39 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:43:07 PM PDT 24
Peak memory 200348 kb
Host smart-1207c4fc-6dec-48e6-a958-065e39775ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088252242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1088252242
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3119452945
Short name T852
Test name
Test status
Simulation time 101742052228 ps
CPU time 962.45 seconds
Started Jul 26 06:42:15 PM PDT 24
Finished Jul 26 06:58:18 PM PDT 24
Peak memory 200068 kb
Host smart-7a37f572-47b9-4cf4-9641-be82d915e219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119452945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3119452945
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1766241243
Short name T1008
Test name
Test status
Simulation time 5996177865 ps
CPU time 3.27 seconds
Started Jul 26 06:42:15 PM PDT 24
Finished Jul 26 06:42:18 PM PDT 24
Peak memory 199684 kb
Host smart-a1e78e26-714e-4cdc-89bf-20468aae69de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766241243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1766241243
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3436731372
Short name T489
Test name
Test status
Simulation time 89563443262 ps
CPU time 148.88 seconds
Started Jul 26 06:42:17 PM PDT 24
Finished Jul 26 06:44:46 PM PDT 24
Peak memory 200356 kb
Host smart-372164f7-3fa5-4b17-a94b-db62cd9f0ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436731372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3436731372
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.983720590
Short name T961
Test name
Test status
Simulation time 12051434857 ps
CPU time 319.78 seconds
Started Jul 26 06:42:15 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 200152 kb
Host smart-c16a8cc9-96fe-45db-9c50-fdf3f545bc35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983720590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.983720590
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3982773870
Short name T981
Test name
Test status
Simulation time 5110909018 ps
CPU time 35.34 seconds
Started Jul 26 06:42:12 PM PDT 24
Finished Jul 26 06:42:48 PM PDT 24
Peak memory 200120 kb
Host smart-e3b58dbf-6d72-4b2a-9512-8c9a8704ddbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982773870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3982773870
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3018822222
Short name T479
Test name
Test status
Simulation time 17399581841 ps
CPU time 26.79 seconds
Started Jul 26 06:42:12 PM PDT 24
Finished Jul 26 06:42:39 PM PDT 24
Peak memory 199884 kb
Host smart-457a8788-8baa-4b18-9ffd-f4c3b09cb198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018822222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3018822222
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3709110243
Short name T410
Test name
Test status
Simulation time 468729796 ps
CPU time 1.31 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:42:15 PM PDT 24
Peak memory 195664 kb
Host smart-8fe93f1d-27ac-4ea9-8df6-64fad5b390b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709110243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3709110243
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.704776835
Short name T1083
Test name
Test status
Simulation time 935428672 ps
CPU time 3.91 seconds
Started Jul 26 06:42:16 PM PDT 24
Finished Jul 26 06:42:20 PM PDT 24
Peak memory 198524 kb
Host smart-884ce9db-2bee-4fef-b9f6-95cef9a799a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704776835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.704776835
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1421551438
Short name T557
Test name
Test status
Simulation time 380674531440 ps
CPU time 1014.86 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:59:08 PM PDT 24
Peak memory 200108 kb
Host smart-05446bd2-eec1-4e12-a304-b3648d2eb98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421551438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1421551438
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2181177616
Short name T24
Test name
Test status
Simulation time 31191573681 ps
CPU time 172.37 seconds
Started Jul 26 06:42:16 PM PDT 24
Finished Jul 26 06:45:08 PM PDT 24
Peak memory 211824 kb
Host smart-4dfa86be-7543-4994-9ac6-e915d6111965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181177616 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2181177616
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1499194727
Short name T1028
Test name
Test status
Simulation time 7550310710 ps
CPU time 14.62 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:42:29 PM PDT 24
Peak memory 199584 kb
Host smart-6759a0ad-bddf-4ca0-b8a3-e9ef7c67d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499194727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1499194727
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3938967725
Short name T558
Test name
Test status
Simulation time 3523595848 ps
CPU time 5.4 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:42:19 PM PDT 24
Peak memory 196976 kb
Host smart-f10879f9-821b-4b8a-9ac1-dd645f7cd0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938967725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3938967725
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2447877115
Short name T382
Test name
Test status
Simulation time 29116589563 ps
CPU time 40.19 seconds
Started Jul 26 06:47:43 PM PDT 24
Finished Jul 26 06:48:23 PM PDT 24
Peak memory 200372 kb
Host smart-3fd561f4-fb5f-4e7d-92ab-b2ce3d383ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447877115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2447877115
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1521040926
Short name T188
Test name
Test status
Simulation time 69937753770 ps
CPU time 105.59 seconds
Started Jul 26 06:47:38 PM PDT 24
Finished Jul 26 06:49:24 PM PDT 24
Peak memory 200160 kb
Host smart-5e4e620c-bc1a-43c0-9331-771680dddf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521040926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1521040926
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3950810549
Short name T993
Test name
Test status
Simulation time 13928833944 ps
CPU time 30.4 seconds
Started Jul 26 06:47:39 PM PDT 24
Finished Jul 26 06:48:10 PM PDT 24
Peak memory 200136 kb
Host smart-9b70a3b6-2ab6-49cf-8689-6c83a8a3910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950810549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3950810549
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3049949392
Short name T877
Test name
Test status
Simulation time 19916313791 ps
CPU time 7.78 seconds
Started Jul 26 06:47:46 PM PDT 24
Finished Jul 26 06:47:54 PM PDT 24
Peak memory 200172 kb
Host smart-f0543e0b-0906-4cb7-af01-f15cd68a4c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049949392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3049949392
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.204827407
Short name T930
Test name
Test status
Simulation time 44770262939 ps
CPU time 17.42 seconds
Started Jul 26 06:47:43 PM PDT 24
Finished Jul 26 06:48:01 PM PDT 24
Peak memory 200436 kb
Host smart-05bc9710-6be4-4b1c-8642-a74ed37162cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204827407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.204827407
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3142866930
Short name T832
Test name
Test status
Simulation time 16908038581 ps
CPU time 25.61 seconds
Started Jul 26 06:47:47 PM PDT 24
Finished Jul 26 06:48:12 PM PDT 24
Peak memory 200168 kb
Host smart-7c8d1361-fe75-4a6b-877d-5d93d969b4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142866930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3142866930
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2820388324
Short name T567
Test name
Test status
Simulation time 62940076727 ps
CPU time 25.86 seconds
Started Jul 26 06:47:47 PM PDT 24
Finished Jul 26 06:48:13 PM PDT 24
Peak memory 200152 kb
Host smart-cac601de-d889-4efc-9e95-a60214b11b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820388324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2820388324
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2922710685
Short name T153
Test name
Test status
Simulation time 42939616204 ps
CPU time 29.02 seconds
Started Jul 26 06:47:48 PM PDT 24
Finished Jul 26 06:48:17 PM PDT 24
Peak memory 200128 kb
Host smart-02092e5a-22fd-4a70-b081-5408a33b599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922710685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2922710685
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3626395746
Short name T1051
Test name
Test status
Simulation time 70065091893 ps
CPU time 17.24 seconds
Started Jul 26 06:47:47 PM PDT 24
Finished Jul 26 06:48:05 PM PDT 24
Peak memory 199696 kb
Host smart-b6486e63-320a-4015-9991-3aa92b79a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626395746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3626395746
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2365734640
Short name T1013
Test name
Test status
Simulation time 125881791902 ps
CPU time 40.13 seconds
Started Jul 26 06:47:47 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 200072 kb
Host smart-b3790733-2ad7-4074-a219-a76582e0e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365734640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2365734640
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.14611184
Short name T31
Test name
Test status
Simulation time 54144639 ps
CPU time 0.56 seconds
Started Jul 26 06:42:33 PM PDT 24
Finished Jul 26 06:42:34 PM PDT 24
Peak memory 195564 kb
Host smart-94a52a28-0a65-4ac3-8975-b3b43ffd3340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.14611184
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1308966750
Short name T591
Test name
Test status
Simulation time 41540034962 ps
CPU time 62.09 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:43:16 PM PDT 24
Peak memory 200112 kb
Host smart-2a36e7e6-660b-4581-aeff-0010ab266850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308966750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1308966750
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1192658296
Short name T397
Test name
Test status
Simulation time 31232644266 ps
CPU time 49.2 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:43:03 PM PDT 24
Peak memory 199988 kb
Host smart-0cbd67c9-a2f6-47f5-94ca-e5db0fe97c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192658296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1192658296
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2266638340
Short name T201
Test name
Test status
Simulation time 70476396265 ps
CPU time 63.92 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:43:18 PM PDT 24
Peak memory 200128 kb
Host smart-02a26803-e4cc-4213-9c74-8c0e6025a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266638340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2266638340
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2191649551
Short name T758
Test name
Test status
Simulation time 47993000837 ps
CPU time 26.91 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:42:51 PM PDT 24
Peak memory 200188 kb
Host smart-e9a9497a-afd7-49c0-a4ae-3ee7c1161476
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191649551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2191649551
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.589666019
Short name T804
Test name
Test status
Simulation time 59625822181 ps
CPU time 587.77 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:52:10 PM PDT 24
Peak memory 200184 kb
Host smart-20945d90-790b-4084-96cb-6befa66668c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589666019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.589666019
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3626863277
Short name T872
Test name
Test status
Simulation time 10785368082 ps
CPU time 9.7 seconds
Started Jul 26 06:42:25 PM PDT 24
Finished Jul 26 06:42:35 PM PDT 24
Peak memory 200268 kb
Host smart-9118effc-e489-478e-a115-ce8c10cdd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626863277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3626863277
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2357110250
Short name T348
Test name
Test status
Simulation time 81133492796 ps
CPU time 123.64 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:44:27 PM PDT 24
Peak memory 199956 kb
Host smart-e52e1d35-09b3-47c2-a2e8-5a996b837916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357110250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2357110250
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2634001285
Short name T986
Test name
Test status
Simulation time 13403847758 ps
CPU time 758.9 seconds
Started Jul 26 06:42:23 PM PDT 24
Finished Jul 26 06:55:02 PM PDT 24
Peak memory 200180 kb
Host smart-ea4a197f-4244-4c9e-8660-4f106be3200e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634001285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2634001285
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4050581546
Short name T726
Test name
Test status
Simulation time 3772209362 ps
CPU time 8.31 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:42:23 PM PDT 24
Peak memory 198392 kb
Host smart-e30567c1-48dc-4509-9622-7b895f260c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050581546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4050581546
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2858457533
Short name T496
Test name
Test status
Simulation time 32888698218 ps
CPU time 24.37 seconds
Started Jul 26 06:42:34 PM PDT 24
Finished Jul 26 06:42:58 PM PDT 24
Peak memory 199540 kb
Host smart-c19861fc-d543-460a-b643-a96622c7f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858457533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2858457533
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2919779405
Short name T875
Test name
Test status
Simulation time 3800304866 ps
CPU time 3.67 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:42:26 PM PDT 24
Peak memory 197016 kb
Host smart-68a5bc39-6390-4a1c-becb-b03505672f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919779405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2919779405
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2323108257
Short name T462
Test name
Test status
Simulation time 297511512 ps
CPU time 1.1 seconds
Started Jul 26 06:42:14 PM PDT 24
Finished Jul 26 06:42:16 PM PDT 24
Peak memory 198836 kb
Host smart-58a2941d-93e7-46bd-8f95-e3ef3fffbd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323108257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2323108257
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1836311856
Short name T657
Test name
Test status
Simulation time 617574440927 ps
CPU time 71.16 seconds
Started Jul 26 06:42:23 PM PDT 24
Finished Jul 26 06:43:34 PM PDT 24
Peak memory 208588 kb
Host smart-6329545d-4f87-4100-a18b-d16dfddd7ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836311856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1836311856
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4087714713
Short name T331
Test name
Test status
Simulation time 22156726643 ps
CPU time 326.2 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:47:50 PM PDT 24
Peak memory 215784 kb
Host smart-c31cb69c-5414-4d64-8449-65deab1395e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087714713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4087714713
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1340881162
Short name T638
Test name
Test status
Simulation time 934049063 ps
CPU time 3.41 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:42:27 PM PDT 24
Peak memory 198884 kb
Host smart-23f6d6c5-533c-487b-b834-0b3d6fddbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340881162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1340881162
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1971649266
Short name T661
Test name
Test status
Simulation time 54997788785 ps
CPU time 75.9 seconds
Started Jul 26 06:42:13 PM PDT 24
Finished Jul 26 06:43:29 PM PDT 24
Peak memory 200112 kb
Host smart-c2aff451-1d0f-47a6-8261-e1a7af73ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971649266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1971649266
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3466802077
Short name T1134
Test name
Test status
Simulation time 107707198875 ps
CPU time 47.64 seconds
Started Jul 26 06:47:48 PM PDT 24
Finished Jul 26 06:48:36 PM PDT 24
Peak memory 199960 kb
Host smart-6c97e641-b304-4c48-a725-e8db2fe4d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466802077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3466802077
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2833701585
Short name T972
Test name
Test status
Simulation time 19475271645 ps
CPU time 8.15 seconds
Started Jul 26 06:47:49 PM PDT 24
Finished Jul 26 06:47:58 PM PDT 24
Peak memory 200168 kb
Host smart-5163e136-6f09-4cf5-ad1d-d6ab707ed678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833701585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2833701585
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1382697840
Short name T1169
Test name
Test status
Simulation time 8863114501 ps
CPU time 3.7 seconds
Started Jul 26 06:47:56 PM PDT 24
Finished Jul 26 06:47:59 PM PDT 24
Peak memory 198992 kb
Host smart-73e0fe02-01a0-4ce3-8af7-07627218205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382697840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1382697840
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.573021212
Short name T253
Test name
Test status
Simulation time 134715584774 ps
CPU time 137.27 seconds
Started Jul 26 06:47:45 PM PDT 24
Finished Jul 26 06:50:02 PM PDT 24
Peak memory 200120 kb
Host smart-9ff58991-9ab6-4cbb-8576-9f7a9f3d556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573021212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.573021212
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.243527655
Short name T600
Test name
Test status
Simulation time 75177159686 ps
CPU time 56.91 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:56 PM PDT 24
Peak memory 200160 kb
Host smart-27bdb8c3-c2d5-4c05-9e8e-f9e81e9e46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243527655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.243527655
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2822876272
Short name T527
Test name
Test status
Simulation time 23812735313 ps
CPU time 10.34 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:09 PM PDT 24
Peak memory 200200 kb
Host smart-b339fd0e-3819-4ecc-9820-99b8ba8d7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822876272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2822876272
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1732029128
Short name T603
Test name
Test status
Simulation time 11393339 ps
CPU time 0.54 seconds
Started Jul 26 06:42:30 PM PDT 24
Finished Jul 26 06:42:31 PM PDT 24
Peak memory 195552 kb
Host smart-e45079d2-0be1-491d-9aba-be816a69645f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732029128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1732029128
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1582134075
Short name T292
Test name
Test status
Simulation time 51083506665 ps
CPU time 74.6 seconds
Started Jul 26 06:42:34 PM PDT 24
Finished Jul 26 06:43:49 PM PDT 24
Peak memory 200132 kb
Host smart-e1dbe77b-e616-44cc-8c18-b484ef79fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582134075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1582134075
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.4270046185
Short name T700
Test name
Test status
Simulation time 29945465960 ps
CPU time 16.48 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:42:40 PM PDT 24
Peak memory 199912 kb
Host smart-80dfb4d0-4490-40d9-b671-97a8726e1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270046185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4270046185
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.568310729
Short name T1029
Test name
Test status
Simulation time 127765683671 ps
CPU time 174.84 seconds
Started Jul 26 06:42:23 PM PDT 24
Finished Jul 26 06:45:18 PM PDT 24
Peak memory 200136 kb
Host smart-f485a69c-85f7-446e-8ca7-399b0645cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568310729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.568310729
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4163783047
Short name T339
Test name
Test status
Simulation time 36314357580 ps
CPU time 37.34 seconds
Started Jul 26 06:42:33 PM PDT 24
Finished Jul 26 06:43:11 PM PDT 24
Peak memory 199920 kb
Host smart-45b8026e-c9c6-4ca8-b112-bdfa464cb6ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163783047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4163783047
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.403634952
Short name T1056
Test name
Test status
Simulation time 128264949225 ps
CPU time 1014.62 seconds
Started Jul 26 06:42:23 PM PDT 24
Finished Jul 26 06:59:18 PM PDT 24
Peak memory 200096 kb
Host smart-45d4bd29-a2c7-493c-9a77-c34da547f520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403634952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.403634952
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.903499691
Short name T1012
Test name
Test status
Simulation time 2209698012 ps
CPU time 5.51 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:42:29 PM PDT 24
Peak memory 199196 kb
Host smart-8de580ae-c8a0-42a0-902f-a2f38ffc6f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903499691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.903499691
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2814851714
Short name T1079
Test name
Test status
Simulation time 88826424071 ps
CPU time 80.72 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:43:43 PM PDT 24
Peak memory 208464 kb
Host smart-64a93e34-1cb3-4d60-8d60-af3e6c8ce4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814851714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2814851714
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.401895626
Short name T982
Test name
Test status
Simulation time 17200732228 ps
CPU time 196.25 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:45:38 PM PDT 24
Peak memory 200116 kb
Host smart-9e9a6223-faef-4097-8207-057f2f3755c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401895626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.401895626
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3387114739
Short name T814
Test name
Test status
Simulation time 5776049028 ps
CPU time 17.26 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:42:40 PM PDT 24
Peak memory 199728 kb
Host smart-59812312-9d26-4fba-90c6-70a8a2073933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387114739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3387114739
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3903797456
Short name T858
Test name
Test status
Simulation time 41304273682 ps
CPU time 33.9 seconds
Started Jul 26 06:42:22 PM PDT 24
Finished Jul 26 06:42:56 PM PDT 24
Peak memory 200092 kb
Host smart-002c7ea4-b744-479f-8cc9-ad1cdb3ebc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903797456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3903797456
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3644104616
Short name T584
Test name
Test status
Simulation time 49128487432 ps
CPU time 7.15 seconds
Started Jul 26 06:42:25 PM PDT 24
Finished Jul 26 06:42:32 PM PDT 24
Peak memory 197224 kb
Host smart-4daef531-f1aa-4eff-a372-95ee5a0f4c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644104616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3644104616
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2238745694
Short name T272
Test name
Test status
Simulation time 97879922 ps
CPU time 0.79 seconds
Started Jul 26 06:42:24 PM PDT 24
Finished Jul 26 06:42:25 PM PDT 24
Peak memory 197944 kb
Host smart-2a0ea958-ae93-490e-894b-9e8ca6a6339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238745694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2238745694
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3460772355
Short name T149
Test name
Test status
Simulation time 355106750484 ps
CPU time 411.11 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:49:23 PM PDT 24
Peak memory 200024 kb
Host smart-42a40f5e-059e-4d90-bde4-75d8e32e2007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460772355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3460772355
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4208925586
Short name T539
Test name
Test status
Simulation time 19050468663 ps
CPU time 213.43 seconds
Started Jul 26 06:42:33 PM PDT 24
Finished Jul 26 06:46:07 PM PDT 24
Peak memory 211048 kb
Host smart-af6c97e7-d097-4023-8502-8d42889249ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208925586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4208925586
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4180864274
Short name T645
Test name
Test status
Simulation time 6390918449 ps
CPU time 14.63 seconds
Started Jul 26 06:42:34 PM PDT 24
Finished Jul 26 06:42:49 PM PDT 24
Peak memory 199676 kb
Host smart-867e9b33-5309-4b65-8c61-fcead7c5c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180864274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4180864274
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1754231034
Short name T67
Test name
Test status
Simulation time 13926840081 ps
CPU time 37.54 seconds
Started Jul 26 06:42:23 PM PDT 24
Finished Jul 26 06:43:00 PM PDT 24
Peak memory 199972 kb
Host smart-d59740f7-9fb0-433b-8d2b-9c52d66fcf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754231034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1754231034
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1062113784
Short name T505
Test name
Test status
Simulation time 81777462888 ps
CPU time 16.57 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:14 PM PDT 24
Peak memory 200092 kb
Host smart-bcefc67d-3548-469e-9bfe-3dfd64674c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062113784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1062113784
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2632816150
Short name T910
Test name
Test status
Simulation time 40446578893 ps
CPU time 16.04 seconds
Started Jul 26 06:47:57 PM PDT 24
Finished Jul 26 06:48:13 PM PDT 24
Peak memory 200136 kb
Host smart-64490f5b-d412-4512-91ec-e73140cf473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632816150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2632816150
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3954540618
Short name T560
Test name
Test status
Simulation time 22621323995 ps
CPU time 38.68 seconds
Started Jul 26 06:48:00 PM PDT 24
Finished Jul 26 06:48:39 PM PDT 24
Peak memory 200184 kb
Host smart-e690bfc7-fedc-4fbf-9994-20d48411d0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954540618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3954540618
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2043187404
Short name T628
Test name
Test status
Simulation time 7743388379 ps
CPU time 13.46 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:48:12 PM PDT 24
Peak memory 200024 kb
Host smart-4d3b6046-1b38-4ef9-aa08-0e2500b975e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043187404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2043187404
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3595096163
Short name T1159
Test name
Test status
Simulation time 213275423247 ps
CPU time 86.14 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:49:24 PM PDT 24
Peak memory 200168 kb
Host smart-7d60b4dc-9a9e-486e-aeb7-66131693ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595096163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3595096163
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1457363542
Short name T907
Test name
Test status
Simulation time 134575888518 ps
CPU time 195.52 seconds
Started Jul 26 06:47:58 PM PDT 24
Finished Jul 26 06:51:14 PM PDT 24
Peak memory 200236 kb
Host smart-caa6169a-ada3-4ad4-947b-5cd4ac74027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457363542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1457363542
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2458016059
Short name T197
Test name
Test status
Simulation time 307719831090 ps
CPU time 31.3 seconds
Started Jul 26 06:47:56 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 200112 kb
Host smart-d28dadbf-933c-41f9-a080-bf49f4e5f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458016059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2458016059
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3583024498
Short name T1057
Test name
Test status
Simulation time 12233106023 ps
CPU time 34.26 seconds
Started Jul 26 06:47:57 PM PDT 24
Finished Jul 26 06:48:32 PM PDT 24
Peak memory 200100 kb
Host smart-c1acee83-2759-4213-b816-b569446191bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583024498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3583024498
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2274168011
Short name T991
Test name
Test status
Simulation time 18532839812 ps
CPU time 55.84 seconds
Started Jul 26 06:47:56 PM PDT 24
Finished Jul 26 06:48:52 PM PDT 24
Peak memory 200144 kb
Host smart-29af884c-12e9-42f5-8725-627cea6a8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274168011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2274168011
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.391901839
Short name T369
Test name
Test status
Simulation time 29003122 ps
CPU time 0.54 seconds
Started Jul 26 06:42:46 PM PDT 24
Finished Jul 26 06:42:47 PM PDT 24
Peak memory 195036 kb
Host smart-a2298374-e8fe-44a1-a9c4-b4ddf397d58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391901839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.391901839
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1531299999
Short name T469
Test name
Test status
Simulation time 7916504361 ps
CPU time 6.35 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:42:38 PM PDT 24
Peak memory 199764 kb
Host smart-2ad51399-6121-47fa-9253-c5c6634f94d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531299999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1531299999
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4212733888
Short name T947
Test name
Test status
Simulation time 32660763511 ps
CPU time 15.79 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:42:47 PM PDT 24
Peak memory 200024 kb
Host smart-6924500b-98a4-4dbf-8b8a-af69a2efe086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212733888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4212733888
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.284579417
Short name T277
Test name
Test status
Simulation time 31055917048 ps
CPU time 12.52 seconds
Started Jul 26 06:42:32 PM PDT 24
Finished Jul 26 06:42:45 PM PDT 24
Peak memory 200124 kb
Host smart-c010d40b-ec33-4b1c-80f3-e06069ba905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284579417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.284579417
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1017017616
Short name T811
Test name
Test status
Simulation time 39957567005 ps
CPU time 32.38 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:43:04 PM PDT 24
Peak memory 199648 kb
Host smart-1559e6e5-f5cb-462b-b093-8e12ae52ace5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017017616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1017017616
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3525363504
Short name T482
Test name
Test status
Simulation time 248620314521 ps
CPU time 240.57 seconds
Started Jul 26 06:42:32 PM PDT 24
Finished Jul 26 06:46:32 PM PDT 24
Peak memory 200176 kb
Host smart-ff5698c5-1299-4913-92bb-b7899bde3607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525363504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3525363504
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3105391576
Short name T360
Test name
Test status
Simulation time 8278352327 ps
CPU time 5.19 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:42:37 PM PDT 24
Peak memory 200112 kb
Host smart-fefb0e43-1b2e-4415-843d-111b46b30ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105391576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3105391576
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3581487369
Short name T779
Test name
Test status
Simulation time 104285177137 ps
CPU time 46.63 seconds
Started Jul 26 06:42:32 PM PDT 24
Finished Jul 26 06:43:18 PM PDT 24
Peak memory 199996 kb
Host smart-f6337621-f948-41b7-b219-a2c9305ae922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581487369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3581487369
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2573193545
Short name T912
Test name
Test status
Simulation time 21949454412 ps
CPU time 152.83 seconds
Started Jul 26 06:42:30 PM PDT 24
Finished Jul 26 06:45:03 PM PDT 24
Peak memory 200168 kb
Host smart-96e274e4-bbaa-43e7-ae5e-087077471edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573193545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2573193545
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3763416002
Short name T609
Test name
Test status
Simulation time 5440568863 ps
CPU time 45.48 seconds
Started Jul 26 06:42:33 PM PDT 24
Finished Jul 26 06:43:18 PM PDT 24
Peak memory 198244 kb
Host smart-1918942d-6012-4fce-8bf8-2ddb8fed0abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763416002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3763416002
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2213392048
Short name T602
Test name
Test status
Simulation time 123898624580 ps
CPU time 112.82 seconds
Started Jul 26 06:42:32 PM PDT 24
Finished Jul 26 06:44:25 PM PDT 24
Peak memory 199512 kb
Host smart-40775cf5-80d3-41a6-9325-8f8d36b28894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213392048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2213392048
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.23745405
Short name T687
Test name
Test status
Simulation time 2358937591 ps
CPU time 2.26 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:42:34 PM PDT 24
Peak memory 196188 kb
Host smart-86667961-8b16-4fbd-98a5-8bbdfd2735d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23745405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.23745405
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2235464254
Short name T507
Test name
Test status
Simulation time 5792487190 ps
CPU time 27 seconds
Started Jul 26 06:42:33 PM PDT 24
Finished Jul 26 06:43:00 PM PDT 24
Peak memory 200116 kb
Host smart-26b9e7f2-ba47-4bd8-a987-32eea442c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235464254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2235464254
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.532369979
Short name T228
Test name
Test status
Simulation time 259385037081 ps
CPU time 1677.71 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 07:10:45 PM PDT 24
Peak memory 208596 kb
Host smart-ae413551-f7ba-4cbe-b191-be8b7bcfa0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532369979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.532369979
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3104776607
Short name T701
Test name
Test status
Simulation time 33448925545 ps
CPU time 171.48 seconds
Started Jul 26 06:42:32 PM PDT 24
Finished Jul 26 06:45:24 PM PDT 24
Peak memory 215808 kb
Host smart-8da4a201-6c82-464d-a471-144d9b8ea4ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104776607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3104776607
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2073912140
Short name T317
Test name
Test status
Simulation time 3766058256 ps
CPU time 2.09 seconds
Started Jul 26 06:42:31 PM PDT 24
Finished Jul 26 06:42:34 PM PDT 24
Peak memory 199044 kb
Host smart-9960400a-120e-4f1f-96ad-abf5b3dd15a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073912140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2073912140
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3203957164
Short name T908
Test name
Test status
Simulation time 83541562952 ps
CPU time 27 seconds
Started Jul 26 06:42:34 PM PDT 24
Finished Jul 26 06:43:01 PM PDT 24
Peak memory 200196 kb
Host smart-1629f308-922e-47e7-8c4c-ffc5afe64840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203957164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3203957164
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.431709581
Short name T553
Test name
Test status
Simulation time 11988148801 ps
CPU time 12.23 seconds
Started Jul 26 06:47:57 PM PDT 24
Finished Jul 26 06:48:09 PM PDT 24
Peak memory 200124 kb
Host smart-a7350697-a60d-4a45-a4f0-23b629bde1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431709581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.431709581
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1399629065
Short name T976
Test name
Test status
Simulation time 261687500325 ps
CPU time 58.3 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:49:08 PM PDT 24
Peak memory 200188 kb
Host smart-a4c43762-0100-48cb-a3b6-0db32402a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399629065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1399629065
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3289143258
Short name T171
Test name
Test status
Simulation time 78461907171 ps
CPU time 65.99 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:49:16 PM PDT 24
Peak memory 200136 kb
Host smart-776fb128-2811-4238-b358-32b0a4bbf126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289143258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3289143258
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1374726148
Short name T146
Test name
Test status
Simulation time 52740409537 ps
CPU time 23.34 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:48:33 PM PDT 24
Peak memory 200196 kb
Host smart-762a6a5d-a5b4-4e4d-9d48-019691ebf34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374726148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1374726148
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2771109026
Short name T371
Test name
Test status
Simulation time 33080523597 ps
CPU time 10.21 seconds
Started Jul 26 06:48:10 PM PDT 24
Finished Jul 26 06:48:20 PM PDT 24
Peak memory 200172 kb
Host smart-53580322-be34-46cf-a1bf-d549171dccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771109026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2771109026
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1299892749
Short name T873
Test name
Test status
Simulation time 28611036875 ps
CPU time 61.7 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 200120 kb
Host smart-72aac880-cc39-444d-9ca7-077af0a8b4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299892749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1299892749
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1023761010
Short name T951
Test name
Test status
Simulation time 40903396068 ps
CPU time 14.81 seconds
Started Jul 26 06:48:11 PM PDT 24
Finished Jul 26 06:48:26 PM PDT 24
Peak memory 200188 kb
Host smart-ba264d15-5a00-416e-8825-effa45127b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023761010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1023761010
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.498967650
Short name T510
Test name
Test status
Simulation time 112465636745 ps
CPU time 162.39 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:50:52 PM PDT 24
Peak memory 200112 kb
Host smart-05131327-627b-4fba-b98a-5383754be9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498967650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.498967650
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2437451805
Short name T322
Test name
Test status
Simulation time 70740760342 ps
CPU time 32.46 seconds
Started Jul 26 06:48:10 PM PDT 24
Finished Jul 26 06:48:43 PM PDT 24
Peak memory 200140 kb
Host smart-a55afb0b-da9b-4b8b-99a8-ac0cc607fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437451805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2437451805
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.957760910
Short name T447
Test name
Test status
Simulation time 14444796 ps
CPU time 0.57 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:42:48 PM PDT 24
Peak memory 195560 kb
Host smart-bc34d3c2-e753-40bc-9229-8051dd2053fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957760910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.957760910
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2028538484
Short name T978
Test name
Test status
Simulation time 159070813961 ps
CPU time 219.12 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:46:26 PM PDT 24
Peak memory 200112 kb
Host smart-4019b653-726b-4f48-87c4-03ae857ef639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028538484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2028538484
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3678268381
Short name T181
Test name
Test status
Simulation time 298263246549 ps
CPU time 56.57 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:43:44 PM PDT 24
Peak memory 200040 kb
Host smart-c2d4434b-8d32-4ad0-9ab8-44c2aef320fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678268381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3678268381
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1972597450
Short name T906
Test name
Test status
Simulation time 58136056489 ps
CPU time 40.68 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:43:28 PM PDT 24
Peak memory 200064 kb
Host smart-4fda9712-fdbd-4b0d-b2b9-767cb015b00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972597450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1972597450
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4190829262
Short name T994
Test name
Test status
Simulation time 48311684409 ps
CPU time 88.77 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:44:17 PM PDT 24
Peak memory 200152 kb
Host smart-f36d8693-7819-4bbb-8a9b-73bc95ef65a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190829262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4190829262
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3726624917
Short name T599
Test name
Test status
Simulation time 38715949755 ps
CPU time 76.95 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:44:07 PM PDT 24
Peak memory 200168 kb
Host smart-bdc659e8-1498-4c17-9b5d-1ce519941c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726624917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3726624917
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2309822265
Short name T519
Test name
Test status
Simulation time 11165130809 ps
CPU time 15.71 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:43:04 PM PDT 24
Peak memory 200056 kb
Host smart-07afa4d6-926c-49da-a3a4-098e0f25d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309822265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2309822265
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.136868719
Short name T561
Test name
Test status
Simulation time 157998151543 ps
CPU time 161.52 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:45:30 PM PDT 24
Peak memory 200320 kb
Host smart-588ae0e5-77c7-42e0-b805-ac3815d23fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136868719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.136868719
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2431980013
Short name T634
Test name
Test status
Simulation time 17665758821 ps
CPU time 985.41 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:59:14 PM PDT 24
Peak memory 200188 kb
Host smart-f273cc2d-a0b6-4450-8a98-3a5e8abcb87b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431980013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2431980013
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2316355969
Short name T428
Test name
Test status
Simulation time 6050941380 ps
CPU time 11.01 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:42:58 PM PDT 24
Peak memory 198220 kb
Host smart-d8e94ec3-4900-4efe-a6e9-935eb2e0f90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316355969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2316355969
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2481884379
Short name T178
Test name
Test status
Simulation time 16438731497 ps
CPU time 24.15 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:43:14 PM PDT 24
Peak memory 200088 kb
Host smart-06e7c709-b8f6-441b-ae28-41d2e4c2e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481884379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2481884379
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3183880935
Short name T707
Test name
Test status
Simulation time 34231468344 ps
CPU time 40.87 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:43:29 PM PDT 24
Peak memory 196564 kb
Host smart-5c969f88-6839-461f-992f-9ec469991606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183880935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3183880935
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.844030675
Short name T1116
Test name
Test status
Simulation time 289919688 ps
CPU time 1.38 seconds
Started Jul 26 06:42:49 PM PDT 24
Finished Jul 26 06:42:51 PM PDT 24
Peak memory 198748 kb
Host smart-ac61b5a8-c9e2-45a7-a8eb-cbb464342ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844030675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.844030675
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3675470949
Short name T942
Test name
Test status
Simulation time 59012624381 ps
CPU time 53.79 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:43:44 PM PDT 24
Peak memory 200096 kb
Host smart-b1b65db1-de07-4874-ba27-43053ddf2b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675470949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3675470949
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4189716273
Short name T775
Test name
Test status
Simulation time 39700817989 ps
CPU time 484.86 seconds
Started Jul 26 06:42:47 PM PDT 24
Finished Jul 26 06:50:52 PM PDT 24
Peak memory 216864 kb
Host smart-64b3f4e1-72cf-4ada-935f-1ab57add4881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189716273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4189716273
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2069622048
Short name T380
Test name
Test status
Simulation time 1065401972 ps
CPU time 1.42 seconds
Started Jul 26 06:42:46 PM PDT 24
Finished Jul 26 06:42:48 PM PDT 24
Peak memory 198840 kb
Host smart-07eb26c9-88cf-4658-82f3-cf418d247fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069622048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2069622048
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4236157757
Short name T439
Test name
Test status
Simulation time 73691976102 ps
CPU time 36.96 seconds
Started Jul 26 06:42:49 PM PDT 24
Finished Jul 26 06:43:26 PM PDT 24
Peak memory 200032 kb
Host smart-b57e8e0c-0966-43de-9d5c-1fa62ccbb25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236157757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4236157757
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.523437472
Short name T647
Test name
Test status
Simulation time 19253806673 ps
CPU time 9.98 seconds
Started Jul 26 06:48:12 PM PDT 24
Finished Jul 26 06:48:22 PM PDT 24
Peak memory 200124 kb
Host smart-fc356204-3289-496f-8fda-ef576272f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523437472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.523437472
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1217466913
Short name T751
Test name
Test status
Simulation time 26242343423 ps
CPU time 13.51 seconds
Started Jul 26 06:48:22 PM PDT 24
Finished Jul 26 06:48:36 PM PDT 24
Peak memory 200100 kb
Host smart-15dba0da-17cc-4575-86ba-36d171111f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217466913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1217466913
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1060171172
Short name T40
Test name
Test status
Simulation time 41744717232 ps
CPU time 38.38 seconds
Started Jul 26 06:48:10 PM PDT 24
Finished Jul 26 06:48:48 PM PDT 24
Peak memory 200024 kb
Host smart-50f631ac-2b02-43cc-90c9-a5ffca823728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060171172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1060171172
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3693659455
Short name T896
Test name
Test status
Simulation time 85682603037 ps
CPU time 142.16 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:50:32 PM PDT 24
Peak memory 200168 kb
Host smart-0e09ac93-d6aa-4c4e-9f78-bef78fd27105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693659455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3693659455
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2883381303
Short name T785
Test name
Test status
Simulation time 29621229409 ps
CPU time 13.34 seconds
Started Jul 26 06:48:15 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 200172 kb
Host smart-e428a3ab-11a7-4d48-98fd-3c52d97ed9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883381303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2883381303
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1461460360
Short name T902
Test name
Test status
Simulation time 68071271654 ps
CPU time 59.84 seconds
Started Jul 26 06:48:09 PM PDT 24
Finished Jul 26 06:49:09 PM PDT 24
Peak memory 200196 kb
Host smart-5634bc18-d12f-4ace-83f8-9ec8bbc08ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461460360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1461460360
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.555390171
Short name T675
Test name
Test status
Simulation time 115993016467 ps
CPU time 92.78 seconds
Started Jul 26 06:48:11 PM PDT 24
Finished Jul 26 06:49:44 PM PDT 24
Peak memory 200232 kb
Host smart-eabeef0b-b9e8-42a0-9be8-d9a83b09c026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555390171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.555390171
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1185126463
Short name T598
Test name
Test status
Simulation time 8743126934 ps
CPU time 20.47 seconds
Started Jul 26 06:48:11 PM PDT 24
Finished Jul 26 06:48:32 PM PDT 24
Peak memory 200024 kb
Host smart-69469c51-1d8e-49f2-ac87-125ff5ca42df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185126463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1185126463
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.726639281
Short name T540
Test name
Test status
Simulation time 20661719738 ps
CPU time 16.24 seconds
Started Jul 26 06:48:11 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 200108 kb
Host smart-1b2af988-1584-4c5f-ac8f-9def3a6708df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726639281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.726639281
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3078875008
Short name T194
Test name
Test status
Simulation time 25179795721 ps
CPU time 28.26 seconds
Started Jul 26 06:48:10 PM PDT 24
Finished Jul 26 06:48:39 PM PDT 24
Peak memory 200108 kb
Host smart-41a9f2a0-64a8-4a1d-b9ad-8469d3702eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078875008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3078875008
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3504802004
Short name T1072
Test name
Test status
Simulation time 24841243 ps
CPU time 0.56 seconds
Started Jul 26 06:42:54 PM PDT 24
Finished Jul 26 06:42:55 PM PDT 24
Peak memory 195528 kb
Host smart-97726b83-e5ae-477b-b00c-637a0b8112ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504802004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3504802004
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.73974761
Short name T615
Test name
Test status
Simulation time 100444442487 ps
CPU time 41.11 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:43:31 PM PDT 24
Peak memory 200120 kb
Host smart-51db82ed-75fd-4eca-afd4-c28dd36e0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73974761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.73974761
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.989965702
Short name T487
Test name
Test status
Simulation time 39798973788 ps
CPU time 65.3 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:43:55 PM PDT 24
Peak memory 200148 kb
Host smart-a353fd35-928c-4abd-948b-2ccda6a128c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989965702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.989965702
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2726801759
Short name T162
Test name
Test status
Simulation time 34482058511 ps
CPU time 17.53 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:43:06 PM PDT 24
Peak memory 199808 kb
Host smart-ffb53b7c-b630-4040-a0a1-d060583fbbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726801759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2726801759
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4202951166
Short name T1173
Test name
Test status
Simulation time 16778102323 ps
CPU time 13.63 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:43:02 PM PDT 24
Peak memory 197108 kb
Host smart-c2fd5352-93ed-4dcf-bc46-84b6dd9fac59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202951166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4202951166
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.149838822
Short name T113
Test name
Test status
Simulation time 211446093431 ps
CPU time 248.06 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:47:04 PM PDT 24
Peak memory 200184 kb
Host smart-acdaee2c-1a1b-4ebd-9d6f-8eb3c963f7c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149838822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.149838822
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.550586905
Short name T20
Test name
Test status
Simulation time 8785493807 ps
CPU time 16.44 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:43:12 PM PDT 24
Peak memory 199792 kb
Host smart-aca862dd-d504-457f-97e0-45c45096b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550586905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.550586905
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3435638077
Short name T268
Test name
Test status
Simulation time 36420177082 ps
CPU time 66.99 seconds
Started Jul 26 06:42:50 PM PDT 24
Finished Jul 26 06:43:57 PM PDT 24
Peak memory 200216 kb
Host smart-f9c5daa4-8e04-4bcc-af42-3097d32439e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435638077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3435638077
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3211206115
Short name T958
Test name
Test status
Simulation time 8949281882 ps
CPU time 234.41 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:46:50 PM PDT 24
Peak memory 200144 kb
Host smart-9a11aa2f-e470-4446-8929-0fce94bd0326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211206115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3211206115
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2233884603
Short name T441
Test name
Test status
Simulation time 4502639785 ps
CPU time 15.4 seconds
Started Jul 26 06:42:49 PM PDT 24
Finished Jul 26 06:43:04 PM PDT 24
Peak memory 200036 kb
Host smart-69b97fb8-b41a-45fc-8eca-523c618e3a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233884603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2233884603
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2273305559
Short name T87
Test name
Test status
Simulation time 136332772954 ps
CPU time 73.67 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:44:09 PM PDT 24
Peak memory 200064 kb
Host smart-64b9c661-1e06-4147-9152-2fc518af015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273305559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2273305559
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.491103455
Short name T1037
Test name
Test status
Simulation time 42846943502 ps
CPU time 64.46 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 196332 kb
Host smart-791aa4a0-94b3-4bbe-aa17-d0e13c61a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491103455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.491103455
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2375013746
Short name T934
Test name
Test status
Simulation time 723991121 ps
CPU time 1.23 seconds
Started Jul 26 06:42:49 PM PDT 24
Finished Jul 26 06:42:50 PM PDT 24
Peak memory 198832 kb
Host smart-470ec767-6ebb-45ad-afd7-38e94885d6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375013746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2375013746
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.526763218
Short name T1090
Test name
Test status
Simulation time 90310542845 ps
CPU time 168.99 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:45:45 PM PDT 24
Peak memory 208516 kb
Host smart-04d28205-0968-4b32-b729-827c15fbdade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526763218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.526763218
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2529147753
Short name T63
Test name
Test status
Simulation time 256292035875 ps
CPU time 636.86 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:53:32 PM PDT 24
Peak memory 225056 kb
Host smart-65bdc8d4-ad74-414d-b0b6-ee33e8f2db3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529147753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2529147753
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2110202247
Short name T1061
Test name
Test status
Simulation time 947845226 ps
CPU time 3.47 seconds
Started Jul 26 06:42:57 PM PDT 24
Finished Jul 26 06:43:00 PM PDT 24
Peak memory 198864 kb
Host smart-52c4c425-db52-457a-ad63-34247a097c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110202247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2110202247
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1017093769
Short name T573
Test name
Test status
Simulation time 83524629389 ps
CPU time 67.93 seconds
Started Jul 26 06:42:48 PM PDT 24
Finished Jul 26 06:43:56 PM PDT 24
Peak memory 200184 kb
Host smart-6aee3435-ac58-4b01-a7e1-908ab859d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017093769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1017093769
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.43818812
Short name T400
Test name
Test status
Simulation time 32683989364 ps
CPU time 76.71 seconds
Started Jul 26 06:48:20 PM PDT 24
Finished Jul 26 06:49:37 PM PDT 24
Peak memory 200196 kb
Host smart-2d84bd06-182c-4758-93b1-8ee634adb607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43818812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.43818812
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3244843279
Short name T223
Test name
Test status
Simulation time 61416014457 ps
CPU time 38.52 seconds
Started Jul 26 06:48:23 PM PDT 24
Finished Jul 26 06:49:02 PM PDT 24
Peak memory 200228 kb
Host smart-b449d347-13c6-4b45-895c-471a51befac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244843279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3244843279
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.801603287
Short name T239
Test name
Test status
Simulation time 53381725082 ps
CPU time 45.6 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:49:05 PM PDT 24
Peak memory 200136 kb
Host smart-6b80c7fb-b41c-4fa3-8b37-35542cd9f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801603287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.801603287
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3369999180
Short name T1022
Test name
Test status
Simulation time 109003778878 ps
CPU time 175.28 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:51:14 PM PDT 24
Peak memory 200188 kb
Host smart-929cd0c9-f1c5-42df-8b1e-75e55add6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369999180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3369999180
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1739016684
Short name T216
Test name
Test status
Simulation time 18648134458 ps
CPU time 27.82 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:47 PM PDT 24
Peak memory 200180 kb
Host smart-600f6649-2e98-4c70-8fc6-074eee6033a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739016684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1739016684
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4096168829
Short name T685
Test name
Test status
Simulation time 46672974729 ps
CPU time 17.75 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:37 PM PDT 24
Peak memory 200180 kb
Host smart-2dc042a4-1f97-4539-b1a0-fc8d7a826607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096168829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4096168829
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3113950836
Short name T708
Test name
Test status
Simulation time 108058814988 ps
CPU time 93.27 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:49:52 PM PDT 24
Peak memory 200352 kb
Host smart-16f0bf56-4e67-40dd-b98d-1b169a407241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113950836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3113950836
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.45484207
Short name T1180
Test name
Test status
Simulation time 70372513925 ps
CPU time 94.35 seconds
Started Jul 26 06:48:20 PM PDT 24
Finished Jul 26 06:49:54 PM PDT 24
Peak memory 200032 kb
Host smart-cfbb3476-f120-4fcf-83d9-a34471fd1e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45484207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.45484207
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1662168771
Short name T1026
Test name
Test status
Simulation time 18449262 ps
CPU time 0.56 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 06:43:08 PM PDT 24
Peak memory 195016 kb
Host smart-dbbde90e-8588-4b3b-924c-816562c63767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662168771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1662168771
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2616869797
Short name T1108
Test name
Test status
Simulation time 112406453618 ps
CPU time 71.94 seconds
Started Jul 26 06:42:54 PM PDT 24
Finished Jul 26 06:44:06 PM PDT 24
Peak memory 200180 kb
Host smart-38a06914-a5d1-4262-a06b-bcf861dc9606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616869797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2616869797
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3631224502
Short name T205
Test name
Test status
Simulation time 139826663741 ps
CPU time 95.94 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:44:32 PM PDT 24
Peak memory 200116 kb
Host smart-3c93998e-e996-4195-9a1e-5bbb58d23959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631224502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3631224502
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1186525325
Short name T512
Test name
Test status
Simulation time 41783934341 ps
CPU time 39.66 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:43:36 PM PDT 24
Peak memory 199804 kb
Host smart-ed28428b-1340-428c-a9dd-5446924d55f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186525325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1186525325
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1051227981
Short name T1053
Test name
Test status
Simulation time 95062430393 ps
CPU time 153.1 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 200112 kb
Host smart-a5cd4457-85da-4b7b-91b1-a6af05440448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051227981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1051227981
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.294663892
Short name T416
Test name
Test status
Simulation time 3374673855 ps
CPU time 6.16 seconds
Started Jul 26 06:42:58 PM PDT 24
Finished Jul 26 06:43:05 PM PDT 24
Peak memory 198392 kb
Host smart-a2e04581-32c0-432e-86e4-5fc956a64577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294663892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.294663892
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2104598815
Short name T476
Test name
Test status
Simulation time 26203057901 ps
CPU time 56.38 seconds
Started Jul 26 06:42:57 PM PDT 24
Finished Jul 26 06:43:53 PM PDT 24
Peak memory 199476 kb
Host smart-a84f17c4-298f-4632-9f93-081e99f89e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104598815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2104598815
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1109086045
Short name T364
Test name
Test status
Simulation time 15340751434 ps
CPU time 355.42 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:48:51 PM PDT 24
Peak memory 200120 kb
Host smart-9bf6bcde-e883-4dbf-a9c5-8a394219d940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109086045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1109086045
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3169401969
Short name T597
Test name
Test status
Simulation time 5783695791 ps
CPU time 12.72 seconds
Started Jul 26 06:42:56 PM PDT 24
Finished Jul 26 06:43:09 PM PDT 24
Peak memory 198332 kb
Host smart-e851f176-0037-49d0-b16d-a73efcf210f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169401969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3169401969
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1159954871
Short name T895
Test name
Test status
Simulation time 37009124130 ps
CPU time 18.94 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:43:14 PM PDT 24
Peak memory 200192 kb
Host smart-08930ba9-d185-41eb-b374-602cec5e1fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159954871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1159954871
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3885847618
Short name T421
Test name
Test status
Simulation time 1495548522 ps
CPU time 2.86 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:42:58 PM PDT 24
Peak memory 195652 kb
Host smart-ace68cce-64d9-404e-bdf3-0713092511f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885847618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3885847618
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3789466971
Short name T692
Test name
Test status
Simulation time 529654002 ps
CPU time 1.74 seconds
Started Jul 26 06:42:54 PM PDT 24
Finished Jul 26 06:42:55 PM PDT 24
Peak memory 200084 kb
Host smart-027742cb-2ee0-4cd0-bf9f-1064ac3fcb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789466971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3789466971
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.74119087
Short name T667
Test name
Test status
Simulation time 100526964425 ps
CPU time 431.95 seconds
Started Jul 26 06:43:09 PM PDT 24
Finished Jul 26 06:50:21 PM PDT 24
Peak memory 208516 kb
Host smart-5b59a96a-19b8-4cff-a27b-5a0165412f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74119087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.74119087
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2192287235
Short name T1075
Test name
Test status
Simulation time 1257012988 ps
CPU time 2.64 seconds
Started Jul 26 06:42:55 PM PDT 24
Finished Jul 26 06:42:58 PM PDT 24
Peak memory 199972 kb
Host smart-ae51ac9c-31a8-4dcf-b189-f017aade98ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192287235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2192287235
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3283660860
Short name T435
Test name
Test status
Simulation time 56557975586 ps
CPU time 40.46 seconds
Started Jul 26 06:42:54 PM PDT 24
Finished Jul 26 06:43:35 PM PDT 24
Peak memory 200124 kb
Host smart-713d57ad-ef23-47fd-a887-435014b50ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283660860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3283660860
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.764417875
Short name T232
Test name
Test status
Simulation time 34963696359 ps
CPU time 16.1 seconds
Started Jul 26 06:48:18 PM PDT 24
Finished Jul 26 06:48:34 PM PDT 24
Peak memory 200116 kb
Host smart-c9d57d47-4d27-41bf-a641-1404e88398ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764417875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.764417875
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2395132427
Short name T626
Test name
Test status
Simulation time 7885665103 ps
CPU time 11.06 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 199684 kb
Host smart-cc1c328d-b09a-4922-b497-4fb547c802a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395132427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2395132427
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2872296661
Short name T693
Test name
Test status
Simulation time 17784583075 ps
CPU time 8.35 seconds
Started Jul 26 06:48:21 PM PDT 24
Finished Jul 26 06:48:29 PM PDT 24
Peak memory 199764 kb
Host smart-64a8cef1-0faa-4b85-a0ea-4c3da845e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872296661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2872296661
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3705193188
Short name T192
Test name
Test status
Simulation time 55963050904 ps
CPU time 102.07 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:50:02 PM PDT 24
Peak memory 200352 kb
Host smart-745c2614-314e-4aa8-9544-c2ef5ceb6875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705193188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3705193188
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3209871732
Short name T255
Test name
Test status
Simulation time 41294460528 ps
CPU time 23.46 seconds
Started Jul 26 06:48:21 PM PDT 24
Finished Jul 26 06:48:44 PM PDT 24
Peak memory 199928 kb
Host smart-b6e72a16-1a7a-44b6-89da-c78108ab1929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209871732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3209871732
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2291758898
Short name T997
Test name
Test status
Simulation time 149355276512 ps
CPU time 63.09 seconds
Started Jul 26 06:48:22 PM PDT 24
Finished Jul 26 06:49:25 PM PDT 24
Peak memory 200256 kb
Host smart-200add5c-7259-4c51-a508-b8f9ee08bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291758898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2291758898
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.263534816
Short name T195
Test name
Test status
Simulation time 33847495509 ps
CPU time 15.52 seconds
Started Jul 26 06:48:22 PM PDT 24
Finished Jul 26 06:48:38 PM PDT 24
Peak memory 200112 kb
Host smart-bc72b171-4d9c-463b-81b4-3a87c5ca73f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263534816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.263534816
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2128829229
Short name T184
Test name
Test status
Simulation time 62574522743 ps
CPU time 25.88 seconds
Started Jul 26 06:48:20 PM PDT 24
Finished Jul 26 06:48:46 PM PDT 24
Peak memory 200092 kb
Host smart-8f5183d8-68fc-4c53-b014-9d8621410d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128829229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2128829229
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.237224918
Short name T1011
Test name
Test status
Simulation time 20310706875 ps
CPU time 46.01 seconds
Started Jul 26 06:48:19 PM PDT 24
Finished Jul 26 06:49:06 PM PDT 24
Peak memory 200172 kb
Host smart-39ca46dc-38d0-4e42-8c63-33a2b25cd9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237224918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.237224918
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1615600181
Short name T542
Test name
Test status
Simulation time 11720014 ps
CPU time 0.57 seconds
Started Jul 26 06:39:31 PM PDT 24
Finished Jul 26 06:39:32 PM PDT 24
Peak memory 195560 kb
Host smart-cbb54970-f4f0-4db3-abf0-2684099c4fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615600181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1615600181
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2544993949
Short name T1045
Test name
Test status
Simulation time 219139307008 ps
CPU time 284.85 seconds
Started Jul 26 06:39:24 PM PDT 24
Finished Jul 26 06:44:09 PM PDT 24
Peak memory 200160 kb
Host smart-32a08f8f-af71-47ec-a8ed-1d95e59c242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544993949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2544993949
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3890419217
Short name T43
Test name
Test status
Simulation time 121583593486 ps
CPU time 47.49 seconds
Started Jul 26 06:39:23 PM PDT 24
Finished Jul 26 06:40:11 PM PDT 24
Peak memory 200152 kb
Host smart-7905c8a7-0d3e-4a61-9073-39b5e4d609a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890419217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3890419217
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3589523551
Short name T681
Test name
Test status
Simulation time 178096609070 ps
CPU time 159.54 seconds
Started Jul 26 06:39:24 PM PDT 24
Finished Jul 26 06:42:03 PM PDT 24
Peak memory 200108 kb
Host smart-140f40b2-49ef-44bb-acf6-9dd23683d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589523551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3589523551
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4033998091
Short name T1125
Test name
Test status
Simulation time 229694291886 ps
CPU time 180.59 seconds
Started Jul 26 06:39:23 PM PDT 24
Finished Jul 26 06:42:24 PM PDT 24
Peak memory 199944 kb
Host smart-2dcbb6bf-214a-4af1-b844-7d5afea5e334
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033998091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4033998091
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3329284609
Short name T719
Test name
Test status
Simulation time 185437644463 ps
CPU time 141.9 seconds
Started Jul 26 06:39:31 PM PDT 24
Finished Jul 26 06:41:53 PM PDT 24
Peak memory 200128 kb
Host smart-1c3f850a-e150-44b5-ae13-7fc239be3fe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329284609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3329284609
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2803526005
Short name T916
Test name
Test status
Simulation time 9254678640 ps
CPU time 17.58 seconds
Started Jul 26 06:39:23 PM PDT 24
Finished Jul 26 06:39:41 PM PDT 24
Peak memory 197860 kb
Host smart-77935e12-5474-430b-9c43-91ed54def5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803526005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2803526005
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3759740889
Short name T793
Test name
Test status
Simulation time 38981175969 ps
CPU time 64.15 seconds
Started Jul 26 06:39:24 PM PDT 24
Finished Jul 26 06:40:28 PM PDT 24
Peak memory 199852 kb
Host smart-706944f4-45e7-4ca1-af45-dff56256c2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759740889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3759740889
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1743601368
Short name T1129
Test name
Test status
Simulation time 20912180017 ps
CPU time 145.18 seconds
Started Jul 26 06:39:23 PM PDT 24
Finished Jul 26 06:41:49 PM PDT 24
Peak memory 200120 kb
Host smart-4990e676-d8d0-4102-8d40-79511b0800c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743601368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1743601368
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1741633847
Short name T605
Test name
Test status
Simulation time 6002601824 ps
CPU time 52.27 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:40:15 PM PDT 24
Peak memory 199968 kb
Host smart-028bc833-7891-4ada-9515-dd22ae85c913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741633847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1741633847
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1287643384
Short name T433
Test name
Test status
Simulation time 143558030203 ps
CPU time 62.01 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:40:24 PM PDT 24
Peak memory 199996 kb
Host smart-65b91217-244e-453e-b215-3b080fe4af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287643384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1287643384
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2682594043
Short name T889
Test name
Test status
Simulation time 52907900995 ps
CPU time 78.44 seconds
Started Jul 26 06:39:22 PM PDT 24
Finished Jul 26 06:40:41 PM PDT 24
Peak memory 196132 kb
Host smart-3a268c0f-4f52-4106-992e-520908bd35e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682594043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2682594043
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1860068752
Short name T110
Test name
Test status
Simulation time 56290673 ps
CPU time 0.84 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:39:29 PM PDT 24
Peak memory 218440 kb
Host smart-161ba848-234a-48ef-8867-70d2df9feb0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860068752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1860068752
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.527556241
Short name T401
Test name
Test status
Simulation time 10593467417 ps
CPU time 31.92 seconds
Started Jul 26 06:39:21 PM PDT 24
Finished Jul 26 06:39:53 PM PDT 24
Peak memory 200136 kb
Host smart-564c98dc-3e0a-4899-bafe-089bafc989a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527556241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.527556241
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2152321540
Short name T1033
Test name
Test status
Simulation time 111523924981 ps
CPU time 216.97 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:43:05 PM PDT 24
Peak memory 200084 kb
Host smart-edb478d3-6b7b-47ce-91ec-fd8efa339245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152321540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2152321540
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2822669096
Short name T563
Test name
Test status
Simulation time 136532344993 ps
CPU time 780.59 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 216608 kb
Host smart-20d60034-0f38-44ad-a9b4-0bb531e411f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822669096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2822669096
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2190227087
Short name T672
Test name
Test status
Simulation time 616386195 ps
CPU time 2.96 seconds
Started Jul 26 06:39:23 PM PDT 24
Finished Jul 26 06:39:27 PM PDT 24
Peak memory 200052 kb
Host smart-16a30213-1a14-435d-a66a-7df6b75a2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190227087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2190227087
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2935009105
Short name T796
Test name
Test status
Simulation time 8136263294 ps
CPU time 6.72 seconds
Started Jul 26 06:39:21 PM PDT 24
Finished Jul 26 06:39:28 PM PDT 24
Peak memory 199996 kb
Host smart-dd403fea-a00a-49e3-b4d0-bbb725218825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935009105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2935009105
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1994779455
Short name T556
Test name
Test status
Simulation time 13816217 ps
CPU time 0.56 seconds
Started Jul 26 06:43:05 PM PDT 24
Finished Jul 26 06:43:06 PM PDT 24
Peak memory 195556 kb
Host smart-117c8386-10b7-466c-9fcd-81f7f796ae94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994779455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1994779455
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.75788433
Short name T1042
Test name
Test status
Simulation time 303015073456 ps
CPU time 79.24 seconds
Started Jul 26 06:43:09 PM PDT 24
Finished Jul 26 06:44:29 PM PDT 24
Peak memory 200256 kb
Host smart-2995a9fa-d50b-4754-96c8-f7a5909869cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75788433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.75788433
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.694380897
Short name T1140
Test name
Test status
Simulation time 36835949674 ps
CPU time 13.93 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 06:43:21 PM PDT 24
Peak memory 198648 kb
Host smart-427565e8-7d33-4083-9b25-67aa0d9ed40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694380897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.694380897
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1964085745
Short name T840
Test name
Test status
Simulation time 96167591202 ps
CPU time 40.36 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 06:43:47 PM PDT 24
Peak memory 200200 kb
Host smart-2698d17d-2308-4e0c-b46f-09d03523bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964085745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1964085745
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2064746753
Short name T931
Test name
Test status
Simulation time 51162076937 ps
CPU time 18.72 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:43:25 PM PDT 24
Peak memory 200132 kb
Host smart-d649d61c-0016-4967-9d29-dde1ef2a0c3f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064746753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2064746753
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.489915460
Short name T85
Test name
Test status
Simulation time 104454010523 ps
CPU time 259.31 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:47:26 PM PDT 24
Peak memory 200172 kb
Host smart-3efa5c66-59cb-4137-a492-5e4e28b78499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489915460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.489915460
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1286713301
Short name T577
Test name
Test status
Simulation time 9226181335 ps
CPU time 4.89 seconds
Started Jul 26 06:43:09 PM PDT 24
Finished Jul 26 06:43:14 PM PDT 24
Peak memory 199192 kb
Host smart-90a247f3-a84a-47a0-a0e2-79d99e98f2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286713301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1286713301
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3543816913
Short name T897
Test name
Test status
Simulation time 13867733225 ps
CPU time 21.98 seconds
Started Jul 26 06:43:08 PM PDT 24
Finished Jul 26 06:43:30 PM PDT 24
Peak memory 198720 kb
Host smart-780d351c-8dd3-4d57-ba6b-c59e696e8baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543816913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3543816913
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.87421302
Short name T1114
Test name
Test status
Simulation time 5728402721 ps
CPU time 249.74 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 06:47:17 PM PDT 24
Peak memory 200172 kb
Host smart-ba2b2ff3-7b02-4b3f-a1e8-003a723d2e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87421302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.87421302
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1780226589
Short name T406
Test name
Test status
Simulation time 3069070851 ps
CPU time 5 seconds
Started Jul 26 06:43:10 PM PDT 24
Finished Jul 26 06:43:15 PM PDT 24
Peak memory 198504 kb
Host smart-e40408d8-3eb8-4180-9abf-8afa75360f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780226589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1780226589
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3596296195
Short name T734
Test name
Test status
Simulation time 81420053839 ps
CPU time 172.99 seconds
Started Jul 26 06:43:08 PM PDT 24
Finished Jul 26 06:46:01 PM PDT 24
Peak memory 200204 kb
Host smart-8fb71f6b-6803-4410-b043-c54df6692037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596296195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3596296195
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1936613139
Short name T1018
Test name
Test status
Simulation time 574790832 ps
CPU time 1.1 seconds
Started Jul 26 06:43:05 PM PDT 24
Finished Jul 26 06:43:06 PM PDT 24
Peak memory 195668 kb
Host smart-0dc93a82-d6c2-40d2-bf36-671cd773f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936613139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1936613139
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2136113072
Short name T308
Test name
Test status
Simulation time 692930084 ps
CPU time 1.76 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:43:08 PM PDT 24
Peak memory 199144 kb
Host smart-4b8c592e-6321-4298-b096-c641dc62b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136113072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2136113072
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.183757919
Short name T509
Test name
Test status
Simulation time 401340448775 ps
CPU time 68.14 seconds
Started Jul 26 06:43:09 PM PDT 24
Finished Jul 26 06:44:17 PM PDT 24
Peak memory 208544 kb
Host smart-cc3f08fb-8ef1-4c19-83a6-da690f04a0f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183757919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.183757919
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.467936655
Short name T1087
Test name
Test status
Simulation time 70769892707 ps
CPU time 1044.48 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 07:00:31 PM PDT 24
Peak memory 231984 kb
Host smart-67f8b406-4130-48f5-90ff-70a7e7eb1649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467936655 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.467936655
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2674270022
Short name T408
Test name
Test status
Simulation time 1146841371 ps
CPU time 1.65 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:43:08 PM PDT 24
Peak memory 199224 kb
Host smart-5999ba19-13c5-4f9b-8153-49f5200ea5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674270022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2674270022
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1653813369
Short name T303
Test name
Test status
Simulation time 25903801684 ps
CPU time 47.54 seconds
Started Jul 26 06:43:07 PM PDT 24
Finished Jul 26 06:43:54 PM PDT 24
Peak memory 200092 kb
Host smart-3b3c8f39-ad9f-4c2b-89ea-8b864ff50abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653813369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1653813369
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1881811649
Short name T791
Test name
Test status
Simulation time 41005172 ps
CPU time 0.55 seconds
Started Jul 26 06:43:14 PM PDT 24
Finished Jul 26 06:43:14 PM PDT 24
Peak memory 195568 kb
Host smart-cda8b4c5-3e67-4a3c-bf41-428a31857141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881811649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1881811649
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2181342887
Short name T1179
Test name
Test status
Simulation time 161824249513 ps
CPU time 258.62 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:47:25 PM PDT 24
Peak memory 200120 kb
Host smart-e666941d-d367-4850-830a-8f13bc43a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181342887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2181342887
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2796508168
Short name T550
Test name
Test status
Simulation time 180791785978 ps
CPU time 139.81 seconds
Started Jul 26 06:43:09 PM PDT 24
Finished Jul 26 06:45:29 PM PDT 24
Peak memory 200168 kb
Host smart-ce24023e-6fc5-4d62-a0ed-e0eb9ceee495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796508168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2796508168
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1151093154
Short name T1133
Test name
Test status
Simulation time 65474544930 ps
CPU time 27.78 seconds
Started Jul 26 06:43:14 PM PDT 24
Finished Jul 26 06:43:42 PM PDT 24
Peak memory 200128 kb
Host smart-3ca7c33c-587f-4f91-be56-01f46f4007ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151093154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1151093154
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4139747134
Short name T392
Test name
Test status
Simulation time 62011860108 ps
CPU time 98 seconds
Started Jul 26 06:43:14 PM PDT 24
Finished Jul 26 06:44:52 PM PDT 24
Peak memory 200176 kb
Host smart-24e0098b-e20e-4ba0-8bf9-b0dbfdfa142d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139747134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4139747134
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.183858012
Short name T1148
Test name
Test status
Simulation time 246463730836 ps
CPU time 301.79 seconds
Started Jul 26 06:43:12 PM PDT 24
Finished Jul 26 06:48:14 PM PDT 24
Peak memory 200156 kb
Host smart-0b17f940-1721-4d36-a0e7-78fc7be2003f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=183858012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.183858012
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3228971001
Short name T646
Test name
Test status
Simulation time 7092795360 ps
CPU time 12.46 seconds
Started Jul 26 06:43:12 PM PDT 24
Finished Jul 26 06:43:25 PM PDT 24
Peak memory 199736 kb
Host smart-941350e8-a2ad-49bc-9bbf-3fe8c0c610c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228971001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3228971001
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3569833854
Short name T403
Test name
Test status
Simulation time 46504031725 ps
CPU time 21.83 seconds
Started Jul 26 06:43:11 PM PDT 24
Finished Jul 26 06:43:33 PM PDT 24
Peak memory 199996 kb
Host smart-f6136262-9a80-4d02-90c7-97897fc12c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569833854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3569833854
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4231422506
Short name T696
Test name
Test status
Simulation time 14244530762 ps
CPU time 194.69 seconds
Started Jul 26 06:43:13 PM PDT 24
Finished Jul 26 06:46:27 PM PDT 24
Peak memory 200204 kb
Host smart-8d8d24d0-5401-4c2c-8e5a-8076127def61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231422506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4231422506
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3733967701
Short name T389
Test name
Test status
Simulation time 3831157391 ps
CPU time 8.06 seconds
Started Jul 26 06:43:13 PM PDT 24
Finished Jul 26 06:43:21 PM PDT 24
Peak memory 198520 kb
Host smart-631a722d-1d08-4917-aac5-61e24dc66d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733967701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3733967701
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3002133549
Short name T1007
Test name
Test status
Simulation time 120183605678 ps
CPU time 81.64 seconds
Started Jul 26 06:43:12 PM PDT 24
Finished Jul 26 06:44:34 PM PDT 24
Peak memory 200184 kb
Host smart-58f2ca02-cfc3-4795-9dbf-57840b7fed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002133549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3002133549
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2446559932
Short name T440
Test name
Test status
Simulation time 2348909977 ps
CPU time 4.28 seconds
Started Jul 26 06:43:12 PM PDT 24
Finished Jul 26 06:43:17 PM PDT 24
Peak memory 195780 kb
Host smart-09de43c7-3925-4e87-b470-415d1c49e380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446559932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2446559932
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1672048497
Short name T366
Test name
Test status
Simulation time 743787423 ps
CPU time 2.2 seconds
Started Jul 26 06:43:05 PM PDT 24
Finished Jul 26 06:43:07 PM PDT 24
Peak memory 198956 kb
Host smart-d2e7bcb4-e261-4850-bd67-e0c037be5332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672048497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1672048497
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.4235787704
Short name T821
Test name
Test status
Simulation time 167475350050 ps
CPU time 491.83 seconds
Started Jul 26 06:43:14 PM PDT 24
Finished Jul 26 06:51:26 PM PDT 24
Peak memory 200116 kb
Host smart-87c8ae0a-57f7-4a6e-a73e-1671a039f3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235787704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4235787704
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.348910944
Short name T547
Test name
Test status
Simulation time 115377129399 ps
CPU time 344.98 seconds
Started Jul 26 06:43:15 PM PDT 24
Finished Jul 26 06:49:01 PM PDT 24
Peak memory 210324 kb
Host smart-84944b63-1896-40cf-93f9-00da9df43795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348910944 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.348910944
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3382124685
Short name T1080
Test name
Test status
Simulation time 953132182 ps
CPU time 3.21 seconds
Started Jul 26 06:43:12 PM PDT 24
Finished Jul 26 06:43:15 PM PDT 24
Peak memory 199920 kb
Host smart-dcd2aaaa-ada2-4b3f-a135-4a9025fd170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382124685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3382124685
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2949490789
Short name T691
Test name
Test status
Simulation time 21686530273 ps
CPU time 53.3 seconds
Started Jul 26 06:43:06 PM PDT 24
Finished Jul 26 06:44:00 PM PDT 24
Peak memory 200084 kb
Host smart-34ed48b0-7968-4a89-856c-a4249d478dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949490789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2949490789
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4012368809
Short name T1001
Test name
Test status
Simulation time 26336833 ps
CPU time 0.55 seconds
Started Jul 26 06:43:22 PM PDT 24
Finished Jul 26 06:43:22 PM PDT 24
Peak memory 195528 kb
Host smart-854c0296-17e4-4f26-92cd-096f24696983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012368809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4012368809
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.418189589
Short name T1006
Test name
Test status
Simulation time 176818184721 ps
CPU time 180.11 seconds
Started Jul 26 06:43:19 PM PDT 24
Finished Jul 26 06:46:19 PM PDT 24
Peak memory 200092 kb
Host smart-2fe7989e-001c-491d-b9c5-0a56a1507f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418189589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.418189589
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3312036580
Short name T1063
Test name
Test status
Simulation time 93351623570 ps
CPU time 70.46 seconds
Started Jul 26 06:43:22 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 199628 kb
Host smart-93162db3-1827-4a81-88be-a1e8a4e4d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312036580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3312036580
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1621449974
Short name T211
Test name
Test status
Simulation time 11143967434 ps
CPU time 26.57 seconds
Started Jul 26 06:43:23 PM PDT 24
Finished Jul 26 06:43:50 PM PDT 24
Peak memory 200068 kb
Host smart-8c17e6b0-95dd-420d-9c33-84c22125c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621449974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1621449974
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1669804860
Short name T494
Test name
Test status
Simulation time 6554773195 ps
CPU time 3.33 seconds
Started Jul 26 06:43:28 PM PDT 24
Finished Jul 26 06:43:32 PM PDT 24
Peak memory 200192 kb
Host smart-b5395884-4f24-4688-9a30-1e0065179ed1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669804860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1669804860
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.487971056
Short name T1002
Test name
Test status
Simulation time 280467850411 ps
CPU time 362.27 seconds
Started Jul 26 06:43:21 PM PDT 24
Finished Jul 26 06:49:23 PM PDT 24
Peak memory 200180 kb
Host smart-378072c1-32c6-4f1f-999d-36b5357bf0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487971056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.487971056
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.4023194149
Short name T957
Test name
Test status
Simulation time 1588640911 ps
CPU time 3.28 seconds
Started Jul 26 06:43:27 PM PDT 24
Finished Jul 26 06:43:30 PM PDT 24
Peak memory 197520 kb
Host smart-94957dc5-f44d-4aac-92bb-f15ed6536c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023194149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4023194149
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1169157031
Short name T1096
Test name
Test status
Simulation time 106792292930 ps
CPU time 39.84 seconds
Started Jul 26 06:43:26 PM PDT 24
Finished Jul 26 06:44:06 PM PDT 24
Peak memory 198988 kb
Host smart-6c520395-6b2c-4c1d-a33c-8851254e93f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169157031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1169157031
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3801427094
Short name T1036
Test name
Test status
Simulation time 34277221525 ps
CPU time 420.8 seconds
Started Jul 26 06:43:20 PM PDT 24
Finished Jul 26 06:50:21 PM PDT 24
Peak memory 200192 kb
Host smart-2abf8880-5b6c-4932-9bb7-da1764921b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801427094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3801427094
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3878420717
Short name T456
Test name
Test status
Simulation time 4047324095 ps
CPU time 9.78 seconds
Started Jul 26 06:43:27 PM PDT 24
Finished Jul 26 06:43:37 PM PDT 24
Peak memory 199056 kb
Host smart-2168d719-f459-46bd-82bb-e540650abaf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878420717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3878420717
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3531856283
Short name T937
Test name
Test status
Simulation time 172171173586 ps
CPU time 35.5 seconds
Started Jul 26 06:43:25 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 200096 kb
Host smart-15ad0aee-5008-4d60-8394-8015927b1b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531856283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3531856283
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.317697020
Short name T44
Test name
Test status
Simulation time 1748339804 ps
CPU time 1.26 seconds
Started Jul 26 06:43:20 PM PDT 24
Finished Jul 26 06:43:22 PM PDT 24
Peak memory 195676 kb
Host smart-c839cf1a-2069-4f75-951a-dfec5a2b13d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317697020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.317697020
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.12521380
Short name T747
Test name
Test status
Simulation time 5731008342 ps
CPU time 28.2 seconds
Started Jul 26 06:43:21 PM PDT 24
Finished Jul 26 06:43:49 PM PDT 24
Peak memory 199864 kb
Host smart-897db56e-a1ab-4b07-86a6-7cbd027c2cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12521380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.12521380
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3051317780
Short name T1158
Test name
Test status
Simulation time 186569344000 ps
CPU time 619.5 seconds
Started Jul 26 06:43:19 PM PDT 24
Finished Jul 26 06:53:39 PM PDT 24
Peak memory 208784 kb
Host smart-50588653-d295-4607-83f0-77eebda80fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051317780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3051317780
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.4027738478
Short name T866
Test name
Test status
Simulation time 266064261729 ps
CPU time 1486.47 seconds
Started Jul 26 06:43:21 PM PDT 24
Finished Jul 26 07:08:08 PM PDT 24
Peak memory 230640 kb
Host smart-12326de9-148f-4cf8-9830-98109f918a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027738478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.4027738478
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2576790643
Short name T898
Test name
Test status
Simulation time 1775914374 ps
CPU time 3.29 seconds
Started Jul 26 06:43:23 PM PDT 24
Finished Jul 26 06:43:26 PM PDT 24
Peak memory 200056 kb
Host smart-5c962903-b1eb-4574-9c06-9a04c13d16c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576790643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2576790643
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1423053879
Short name T878
Test name
Test status
Simulation time 125237902276 ps
CPU time 13.83 seconds
Started Jul 26 06:43:21 PM PDT 24
Finished Jul 26 06:43:35 PM PDT 24
Peak memory 200160 kb
Host smart-c68fcecc-f88d-4d84-ba80-771ce0b7ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423053879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1423053879
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1616195687
Short name T426
Test name
Test status
Simulation time 15895999 ps
CPU time 0.57 seconds
Started Jul 26 06:43:37 PM PDT 24
Finished Jul 26 06:43:37 PM PDT 24
Peak memory 195800 kb
Host smart-dd919ea4-33c4-4605-a2b5-d2fddad364c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616195687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1616195687
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2273830274
Short name T271
Test name
Test status
Simulation time 30969359209 ps
CPU time 48.31 seconds
Started Jul 26 06:43:28 PM PDT 24
Finished Jul 26 06:44:16 PM PDT 24
Peak memory 200116 kb
Host smart-6e2c009b-eba9-4f54-8d85-bc7a9066ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273830274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2273830274
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3950498094
Short name T601
Test name
Test status
Simulation time 160774707568 ps
CPU time 320.05 seconds
Started Jul 26 06:43:29 PM PDT 24
Finished Jul 26 06:48:49 PM PDT 24
Peak memory 200132 kb
Host smart-60022cfb-badf-4d71-b51a-8c06a58937ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950498094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3950498094
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.521732025
Short name T732
Test name
Test status
Simulation time 86375535398 ps
CPU time 24.14 seconds
Started Jul 26 06:43:31 PM PDT 24
Finished Jul 26 06:43:55 PM PDT 24
Peak memory 199876 kb
Host smart-fab5d511-4704-4fb2-aff6-f587935257d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521732025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.521732025
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1616301888
Short name T1084
Test name
Test status
Simulation time 5728198029 ps
CPU time 4.59 seconds
Started Jul 26 06:43:33 PM PDT 24
Finished Jul 26 06:43:38 PM PDT 24
Peak memory 196936 kb
Host smart-e02e3310-2380-44e0-b5a0-5ffd2966044c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616301888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1616301888
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_loopback.1924668711
Short name T383
Test name
Test status
Simulation time 1595991883 ps
CPU time 1.44 seconds
Started Jul 26 06:43:29 PM PDT 24
Finished Jul 26 06:43:31 PM PDT 24
Peak memory 197372 kb
Host smart-dab23a23-eceb-4df7-aa95-57c7fe452569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924668711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1924668711
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4144649508
Short name T503
Test name
Test status
Simulation time 335074673557 ps
CPU time 71.7 seconds
Started Jul 26 06:43:28 PM PDT 24
Finished Jul 26 06:44:40 PM PDT 24
Peak memory 199584 kb
Host smart-0ef888fd-f06a-4dec-8489-15b84699dc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144649508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4144649508
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1388309212
Short name T270
Test name
Test status
Simulation time 23655989004 ps
CPU time 315.63 seconds
Started Jul 26 06:43:33 PM PDT 24
Finished Jul 26 06:48:48 PM PDT 24
Peak memory 200060 kb
Host smart-d902b695-3b2c-4ce7-9585-2c13a1e0a32e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388309212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1388309212
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3188136946
Short name T457
Test name
Test status
Simulation time 4745957592 ps
CPU time 42.04 seconds
Started Jul 26 06:43:29 PM PDT 24
Finished Jul 26 06:44:11 PM PDT 24
Peak memory 199484 kb
Host smart-584d75de-f1b0-4d05-8ede-4e66264c3764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188136946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3188136946
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4079697028
Short name T280
Test name
Test status
Simulation time 34498949038 ps
CPU time 64 seconds
Started Jul 26 06:43:25 PM PDT 24
Finished Jul 26 06:44:30 PM PDT 24
Peak memory 200216 kb
Host smart-353c14b3-b011-40ba-b8f4-5b485055c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079697028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4079697028
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2482025628
Short name T595
Test name
Test status
Simulation time 45156725014 ps
CPU time 15.73 seconds
Started Jul 26 06:43:29 PM PDT 24
Finished Jul 26 06:43:45 PM PDT 24
Peak memory 196168 kb
Host smart-68165b33-3aae-45d9-b66a-d4beac75e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482025628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2482025628
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3821356321
Short name T917
Test name
Test status
Simulation time 5874728177 ps
CPU time 11.32 seconds
Started Jul 26 06:43:18 PM PDT 24
Finished Jul 26 06:43:30 PM PDT 24
Peak memory 199356 kb
Host smart-79b38329-e810-416c-85ef-7a30285be3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821356321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3821356321
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1346886877
Short name T1052
Test name
Test status
Simulation time 202563695775 ps
CPU time 184.68 seconds
Started Jul 26 06:43:30 PM PDT 24
Finished Jul 26 06:46:35 PM PDT 24
Peak memory 200124 kb
Host smart-ce36d241-a9ae-416a-b351-83383666f397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346886877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1346886877
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3157982909
Short name T86
Test name
Test status
Simulation time 161068090934 ps
CPU time 651.42 seconds
Started Jul 26 06:43:34 PM PDT 24
Finished Jul 26 06:54:26 PM PDT 24
Peak memory 212680 kb
Host smart-cb0732db-ea72-4aea-8cda-9b46c2b020a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157982909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3157982909
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2964552910
Short name T480
Test name
Test status
Simulation time 7203858492 ps
CPU time 7.44 seconds
Started Jul 26 06:43:29 PM PDT 24
Finished Jul 26 06:43:37 PM PDT 24
Peak memory 199952 kb
Host smart-8a571ebb-3009-4813-86db-a6a11ae74ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964552910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2964552910
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.879389001
Short name T49
Test name
Test status
Simulation time 53919020356 ps
CPU time 75.13 seconds
Started Jul 26 06:43:27 PM PDT 24
Finished Jul 26 06:44:43 PM PDT 24
Peak memory 200192 kb
Host smart-35bc7a2c-5fe4-4867-9145-b51d45ec85c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879389001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.879389001
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1468747522
Short name T578
Test name
Test status
Simulation time 24761110 ps
CPU time 0.58 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:43:45 PM PDT 24
Peak memory 195016 kb
Host smart-d5043a99-13c8-4c33-8b47-159b34a1ede9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468747522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1468747522
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2421253004
Short name T741
Test name
Test status
Simulation time 181105024227 ps
CPU time 526.45 seconds
Started Jul 26 06:43:39 PM PDT 24
Finished Jul 26 06:52:26 PM PDT 24
Peak memory 200180 kb
Host smart-70f565d4-fb7f-41fd-8797-9c20eb6df101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421253004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2421253004
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2705940056
Short name T328
Test name
Test status
Simulation time 251499933228 ps
CPU time 60.12 seconds
Started Jul 26 06:43:38 PM PDT 24
Finished Jul 26 06:44:38 PM PDT 24
Peak memory 200040 kb
Host smart-c1160490-3c48-4f90-97f7-ec3a6d9c2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705940056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2705940056
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.909625563
Short name T899
Test name
Test status
Simulation time 55349454408 ps
CPU time 22.77 seconds
Started Jul 26 06:43:38 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 198580 kb
Host smart-7621a2a1-b680-4048-a07b-172d99c4e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909625563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.909625563
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4239155895
Short name T528
Test name
Test status
Simulation time 20207087182 ps
CPU time 16.41 seconds
Started Jul 26 06:43:37 PM PDT 24
Finished Jul 26 06:43:54 PM PDT 24
Peak memory 200072 kb
Host smart-aa5443bf-06b3-44da-934b-747d1aa86eb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239155895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4239155895
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.203054685
Short name T844
Test name
Test status
Simulation time 36600396488 ps
CPU time 242.05 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:47:46 PM PDT 24
Peak memory 200116 kb
Host smart-8721d4ea-4576-45d3-8f4c-686c05f34263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203054685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.203054685
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.234055157
Short name T710
Test name
Test status
Simulation time 9550647876 ps
CPU time 12.88 seconds
Started Jul 26 06:43:37 PM PDT 24
Finished Jul 26 06:43:50 PM PDT 24
Peak memory 199948 kb
Host smart-cf41f64d-6dc5-49e4-ba92-48584f04ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234055157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.234055157
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2639962682
Short name T952
Test name
Test status
Simulation time 164438499684 ps
CPU time 100.34 seconds
Started Jul 26 06:43:36 PM PDT 24
Finished Jul 26 06:45:16 PM PDT 24
Peak memory 208528 kb
Host smart-086ff015-b194-4f42-bada-d1a1c423aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639962682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2639962682
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2933992394
Short name T845
Test name
Test status
Simulation time 12132167508 ps
CPU time 144.99 seconds
Started Jul 26 06:43:43 PM PDT 24
Finished Jul 26 06:46:09 PM PDT 24
Peak memory 200192 kb
Host smart-0560ca6d-43ca-4768-826e-f26bb0df487d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933992394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2933992394
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3598245910
Short name T914
Test name
Test status
Simulation time 4631472511 ps
CPU time 39.34 seconds
Started Jul 26 06:43:42 PM PDT 24
Finished Jul 26 06:44:21 PM PDT 24
Peak memory 199424 kb
Host smart-b9912db8-8d29-4e3e-b9b7-197f42f9d3c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598245910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3598245910
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.523977232
Short name T161
Test name
Test status
Simulation time 46281944545 ps
CPU time 28.34 seconds
Started Jul 26 06:43:37 PM PDT 24
Finished Jul 26 06:44:06 PM PDT 24
Peak memory 200044 kb
Host smart-7875e359-12f2-495d-af7c-d649f3af13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523977232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.523977232
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3157658392
Short name T935
Test name
Test status
Simulation time 42473571001 ps
CPU time 4.73 seconds
Started Jul 26 06:43:36 PM PDT 24
Finished Jul 26 06:43:41 PM PDT 24
Peak memory 196980 kb
Host smart-4a7f593f-fbe7-427f-a67f-fdbc27231677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157658392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3157658392
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.866993265
Short name T1058
Test name
Test status
Simulation time 652114908 ps
CPU time 1.47 seconds
Started Jul 26 06:43:38 PM PDT 24
Finished Jul 26 06:43:40 PM PDT 24
Peak memory 200072 kb
Host smart-90a17fb9-f3ad-467a-bdc3-ba0864edb7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866993265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.866993265
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.236165262
Short name T953
Test name
Test status
Simulation time 230491268296 ps
CPU time 377.97 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:50:04 PM PDT 24
Peak memory 200248 kb
Host smart-1166e431-3286-40f2-8ebc-e77327bcdfa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236165262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.236165262
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1935083579
Short name T1023
Test name
Test status
Simulation time 112691801785 ps
CPU time 372.11 seconds
Started Jul 26 06:43:46 PM PDT 24
Finished Jul 26 06:49:58 PM PDT 24
Peak memory 208968 kb
Host smart-77810245-e61c-4a19-adc1-1ffe379f984a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935083579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1935083579
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.688968843
Short name T946
Test name
Test status
Simulation time 7062165323 ps
CPU time 18.83 seconds
Started Jul 26 06:43:38 PM PDT 24
Finished Jul 26 06:43:57 PM PDT 24
Peak memory 200168 kb
Host smart-86a72697-919a-4693-a4a1-1872d152e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688968843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.688968843
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.870823059
Short name T919
Test name
Test status
Simulation time 197679461491 ps
CPU time 158.12 seconds
Started Jul 26 06:43:37 PM PDT 24
Finished Jul 26 06:46:15 PM PDT 24
Peak memory 200200 kb
Host smart-7f47ce25-7e23-45e7-8066-caa74b0e57bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870823059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.870823059
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3576058803
Short name T362
Test name
Test status
Simulation time 55774314 ps
CPU time 0.58 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:43:45 PM PDT 24
Peak memory 195492 kb
Host smart-bb0e760d-65ba-4dac-8ca2-545584c61100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576058803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3576058803
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3770006418
Short name T46
Test name
Test status
Simulation time 11597686642 ps
CPU time 19.29 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:44:04 PM PDT 24
Peak memory 200048 kb
Host smart-5a10b179-a284-45e0-8fbe-28b58ba98dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770006418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3770006418
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3949384185
Short name T541
Test name
Test status
Simulation time 156907118184 ps
CPU time 44.66 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:44:29 PM PDT 24
Peak memory 200132 kb
Host smart-56212119-52f5-452d-81b5-b3418733d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949384185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3949384185
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1372887137
Short name T974
Test name
Test status
Simulation time 40213532678 ps
CPU time 18.99 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:44:03 PM PDT 24
Peak memory 200004 kb
Host smart-e797ffd2-d8ca-4814-b202-c328ac4f1bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372887137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1372887137
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2373892963
Short name T384
Test name
Test status
Simulation time 19314271024 ps
CPU time 29.64 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:44:14 PM PDT 24
Peak memory 197084 kb
Host smart-4bb353f4-e84c-478e-aec2-5e4f1b29964d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373892963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2373892963
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3923139405
Short name T515
Test name
Test status
Simulation time 169645185668 ps
CPU time 307.27 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:48:53 PM PDT 24
Peak memory 200212 kb
Host smart-5e1e7807-2d88-4971-9cb6-1e395000afa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923139405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3923139405
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3654681767
Short name T810
Test name
Test status
Simulation time 9363189762 ps
CPU time 4.61 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:43:50 PM PDT 24
Peak memory 200064 kb
Host smart-f460e3f9-d2bb-4bf7-ad96-27896cdc9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654681767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3654681767
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2136617629
Short name T375
Test name
Test status
Simulation time 2740950532 ps
CPU time 4.5 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:43:49 PM PDT 24
Peak memory 200092 kb
Host smart-83cd4555-2927-4536-ad99-9e2c97393f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136617629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2136617629
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2431174983
Short name T1032
Test name
Test status
Simulation time 10052518457 ps
CPU time 507.45 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:52:12 PM PDT 24
Peak memory 200072 kb
Host smart-a3e2a2c5-8268-4156-a288-3bbfa9b792f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431174983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2431174983
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1895469330
Short name T1113
Test name
Test status
Simulation time 6356674950 ps
CPU time 21.6 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:44:06 PM PDT 24
Peak memory 198520 kb
Host smart-a1da12c7-a580-44a4-9428-6775d1a4301b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895469330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1895469330
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1717575572
Short name T774
Test name
Test status
Simulation time 106420218916 ps
CPU time 159.61 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:46:25 PM PDT 24
Peak memory 200132 kb
Host smart-751e630a-4ecb-4c6e-9f40-a0062777c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717575572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1717575572
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2708705257
Short name T372
Test name
Test status
Simulation time 44887200490 ps
CPU time 15.12 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:44:00 PM PDT 24
Peak memory 196172 kb
Host smart-0d876439-cfdc-4f57-a82c-d12d84f4f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708705257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2708705257
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.927296876
Short name T329
Test name
Test status
Simulation time 5880829668 ps
CPU time 16.93 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:44:03 PM PDT 24
Peak memory 199940 kb
Host smart-c0fb561f-e79a-408b-9251-db45edf41850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927296876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.927296876
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3053006480
Short name T830
Test name
Test status
Simulation time 183636122749 ps
CPU time 109.3 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:45:33 PM PDT 24
Peak memory 208892 kb
Host smart-77e364f3-d43f-4f58-ad4f-1b80dc0ce564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053006480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3053006480
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1598708222
Short name T167
Test name
Test status
Simulation time 300797668231 ps
CPU time 445.39 seconds
Started Jul 26 06:43:46 PM PDT 24
Finished Jul 26 06:51:12 PM PDT 24
Peak memory 216720 kb
Host smart-eb4e6b9c-b3ca-4ab7-984e-8ad17cd86418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598708222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1598708222
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.789096047
Short name T502
Test name
Test status
Simulation time 1398691132 ps
CPU time 1.5 seconds
Started Jul 26 06:43:46 PM PDT 24
Finished Jul 26 06:43:47 PM PDT 24
Peak memory 198640 kb
Host smart-3f597cf6-21f8-4724-9054-f66f1a160e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789096047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.789096047
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.986466613
Short name T1093
Test name
Test status
Simulation time 32295141468 ps
CPU time 25.14 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:44:11 PM PDT 24
Peak memory 198644 kb
Host smart-5f9c72af-f485-417c-87a5-42de77146abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986466613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.986466613
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2208810338
Short name T706
Test name
Test status
Simulation time 15236912 ps
CPU time 0.57 seconds
Started Jul 26 06:44:00 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 195612 kb
Host smart-969898d0-f580-424e-b2a6-945e08143b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208810338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2208810338
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.842868820
Short name T1025
Test name
Test status
Simulation time 16185034124 ps
CPU time 12 seconds
Started Jul 26 06:43:53 PM PDT 24
Finished Jul 26 06:44:05 PM PDT 24
Peak memory 199976 kb
Host smart-675bba50-ba11-4d6f-9ec1-1a595fcd1851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842868820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.842868820
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.864319855
Short name T236
Test name
Test status
Simulation time 46803122639 ps
CPU time 67.06 seconds
Started Jul 26 06:43:55 PM PDT 24
Finished Jul 26 06:45:02 PM PDT 24
Peak memory 200088 kb
Host smart-27bdc7f1-4e36-49be-a3c6-97990ddd9bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864319855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.864319855
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1888228620
Short name T437
Test name
Test status
Simulation time 44081158080 ps
CPU time 5.98 seconds
Started Jul 26 06:43:54 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 200160 kb
Host smart-e102f250-7bbc-41ab-971e-8fdd00c44783
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888228620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1888228620
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3893641203
Short name T1106
Test name
Test status
Simulation time 77854436052 ps
CPU time 817.12 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:57:39 PM PDT 24
Peak memory 200104 kb
Host smart-313f1d58-a1ea-450a-93c6-e1e881c831be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893641203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3893641203
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2050545347
Short name T1048
Test name
Test status
Simulation time 6834482659 ps
CPU time 6.86 seconds
Started Jul 26 06:43:53 PM PDT 24
Finished Jul 26 06:43:59 PM PDT 24
Peak memory 199780 kb
Host smart-3ae67b8b-ebee-4ce4-8867-1927bae7add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050545347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2050545347
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.2396186417
Short name T425
Test name
Test status
Simulation time 13766543139 ps
CPU time 872.59 seconds
Started Jul 26 06:43:53 PM PDT 24
Finished Jul 26 06:58:26 PM PDT 24
Peak memory 200232 kb
Host smart-898c8f2a-f1cd-4333-b536-b017057b90e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396186417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2396186417
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2568359151
Short name T359
Test name
Test status
Simulation time 5126378990 ps
CPU time 38.7 seconds
Started Jul 26 06:43:52 PM PDT 24
Finished Jul 26 06:44:31 PM PDT 24
Peak memory 199460 kb
Host smart-ce309aab-e718-48d2-b13d-e81a238feb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568359151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2568359151
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.224353313
Short name T179
Test name
Test status
Simulation time 192541484364 ps
CPU time 80.99 seconds
Started Jul 26 06:43:54 PM PDT 24
Finished Jul 26 06:45:15 PM PDT 24
Peak memory 200196 kb
Host smart-b9719a3c-924a-4df7-92a5-cb7028f6717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224353313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.224353313
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1981879712
Short name T1128
Test name
Test status
Simulation time 1882828080 ps
CPU time 1.31 seconds
Started Jul 26 06:43:53 PM PDT 24
Finished Jul 26 06:43:54 PM PDT 24
Peak memory 195692 kb
Host smart-152b7a75-f2fc-4704-bb2a-1516fe167d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981879712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1981879712
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.299209522
Short name T769
Test name
Test status
Simulation time 882459808 ps
CPU time 3.72 seconds
Started Jul 26 06:43:44 PM PDT 24
Finished Jul 26 06:43:48 PM PDT 24
Peak memory 198564 kb
Host smart-956980a6-70b6-4b75-9f31-3545ac428d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299209522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.299209522
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1276764584
Short name T307
Test name
Test status
Simulation time 873161952 ps
CPU time 1.8 seconds
Started Jul 26 06:43:53 PM PDT 24
Finished Jul 26 06:43:55 PM PDT 24
Peak memory 199016 kb
Host smart-32fd76b2-8c5c-47a3-a7ef-2b150b62451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276764584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1276764584
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3696429929
Short name T465
Test name
Test status
Simulation time 50601384934 ps
CPU time 38.26 seconds
Started Jul 26 06:43:45 PM PDT 24
Finished Jul 26 06:44:24 PM PDT 24
Peak memory 200208 kb
Host smart-f565579e-998b-42f0-ad81-353bb931844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696429929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3696429929
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3614614698
Short name T443
Test name
Test status
Simulation time 72304336 ps
CPU time 0.57 seconds
Started Jul 26 06:44:08 PM PDT 24
Finished Jul 26 06:44:08 PM PDT 24
Peak memory 195512 kb
Host smart-a886ba36-1014-4392-9c22-b433e6f10e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614614698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3614614698
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.942295833
Short name T324
Test name
Test status
Simulation time 93985564095 ps
CPU time 157.15 seconds
Started Jul 26 06:44:03 PM PDT 24
Finished Jul 26 06:46:40 PM PDT 24
Peak memory 200096 kb
Host smart-1c4e8e55-ebdc-49dc-9c96-11d853821f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942295833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.942295833
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3860094830
Short name T246
Test name
Test status
Simulation time 32356840886 ps
CPU time 16.64 seconds
Started Jul 26 06:43:59 PM PDT 24
Finished Jul 26 06:44:16 PM PDT 24
Peak memory 200180 kb
Host smart-7144eae5-caa4-4645-8235-75db6cdbba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860094830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3860094830
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3870712169
Short name T828
Test name
Test status
Simulation time 74928500787 ps
CPU time 122.39 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:46:04 PM PDT 24
Peak memory 200140 kb
Host smart-4459d631-f180-4213-87b8-f407a0add4ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870712169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3870712169
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2012016499
Short name T262
Test name
Test status
Simulation time 64345221375 ps
CPU time 273.49 seconds
Started Jul 26 06:44:09 PM PDT 24
Finished Jul 26 06:48:42 PM PDT 24
Peak memory 199988 kb
Host smart-5004ff0e-d7ec-40c6-880d-11fbcc694468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012016499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2012016499
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2869871929
Short name T464
Test name
Test status
Simulation time 3266695868 ps
CPU time 3.48 seconds
Started Jul 26 06:44:12 PM PDT 24
Finished Jul 26 06:44:16 PM PDT 24
Peak memory 196220 kb
Host smart-9a68c345-d9d1-4eb8-b8ee-afdb761b06fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869871929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2869871929
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.895340627
Short name T1138
Test name
Test status
Simulation time 79022079567 ps
CPU time 83.09 seconds
Started Jul 26 06:43:59 PM PDT 24
Finished Jul 26 06:45:22 PM PDT 24
Peak memory 208528 kb
Host smart-65e99202-66e6-4b1f-9edd-6c048b929f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895340627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.895340627
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2297075405
Short name T273
Test name
Test status
Simulation time 7902507685 ps
CPU time 75.97 seconds
Started Jul 26 06:44:09 PM PDT 24
Finished Jul 26 06:45:25 PM PDT 24
Peak memory 199968 kb
Host smart-ff57a509-9209-4526-b9a1-af65e631e226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297075405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2297075405
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.536469667
Short name T833
Test name
Test status
Simulation time 3187614506 ps
CPU time 10.61 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:44:12 PM PDT 24
Peak memory 198936 kb
Host smart-bf2678e5-60d3-4772-a522-c1904bb1d9c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536469667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.536469667
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.769380404
Short name T454
Test name
Test status
Simulation time 63391386826 ps
CPU time 95.74 seconds
Started Jul 26 06:44:02 PM PDT 24
Finished Jul 26 06:45:38 PM PDT 24
Peak memory 200140 kb
Host smart-1c8d1bee-c036-4c5d-b946-c458064bb471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769380404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.769380404
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2118614146
Short name T1174
Test name
Test status
Simulation time 1844790483 ps
CPU time 1.33 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:44:03 PM PDT 24
Peak memory 195672 kb
Host smart-670fd309-cfde-46b1-86de-0094c7bea465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118614146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2118614146
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2014237301
Short name T1144
Test name
Test status
Simulation time 961633996 ps
CPU time 2.44 seconds
Started Jul 26 06:44:01 PM PDT 24
Finished Jul 26 06:44:04 PM PDT 24
Peak memory 198508 kb
Host smart-d9ad64d7-534c-44b6-a68d-581f000e467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014237301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2014237301
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1806780851
Short name T798
Test name
Test status
Simulation time 63918032634 ps
CPU time 497.5 seconds
Started Jul 26 06:44:10 PM PDT 24
Finished Jul 26 06:52:27 PM PDT 24
Peak memory 216928 kb
Host smart-0192ebfe-f365-48db-a18c-fedf8fb28fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806780851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1806780851
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.492380650
Short name T921
Test name
Test status
Simulation time 958297421 ps
CPU time 2.59 seconds
Started Jul 26 06:44:00 PM PDT 24
Finished Jul 26 06:44:03 PM PDT 24
Peak memory 198972 kb
Host smart-2cf2c28a-b694-4d19-8e5c-444ce3e29d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492380650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.492380650
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2769786939
Short name T665
Test name
Test status
Simulation time 96641941835 ps
CPU time 58.04 seconds
Started Jul 26 06:44:02 PM PDT 24
Finished Jul 26 06:45:01 PM PDT 24
Peak memory 200152 kb
Host smart-cc987705-9aae-464e-bb37-6376422c26b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769786939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2769786939
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3921162939
Short name T720
Test name
Test status
Simulation time 44780615 ps
CPU time 0.54 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:17 PM PDT 24
Peak memory 195560 kb
Host smart-16e9752e-2e17-49ab-b5ad-8a2ef2bbb434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921162939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3921162939
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3155257239
Short name T607
Test name
Test status
Simulation time 14542636977 ps
CPU time 6.26 seconds
Started Jul 26 06:44:09 PM PDT 24
Finished Jul 26 06:44:15 PM PDT 24
Peak memory 199964 kb
Host smart-26ac058d-31df-4228-bcfe-2183e1c7fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155257239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3155257239
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2331930486
Short name T766
Test name
Test status
Simulation time 100056541234 ps
CPU time 53.28 seconds
Started Jul 26 06:44:07 PM PDT 24
Finished Jul 26 06:45:01 PM PDT 24
Peak memory 200180 kb
Host smart-b5948c31-cbf6-4095-ba22-20093e08187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331930486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2331930486
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1859070504
Short name T783
Test name
Test status
Simulation time 18739766073 ps
CPU time 36.32 seconds
Started Jul 26 06:44:08 PM PDT 24
Finished Jul 26 06:44:44 PM PDT 24
Peak memory 200088 kb
Host smart-e97cd9f0-aea9-4401-9630-13ef8ce2846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859070504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1859070504
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3270350126
Short name T306
Test name
Test status
Simulation time 48127739041 ps
CPU time 71.59 seconds
Started Jul 26 06:44:12 PM PDT 24
Finished Jul 26 06:45:24 PM PDT 24
Peak memory 200232 kb
Host smart-65c2649f-7519-48d0-afa0-2ee1c39c674f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270350126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3270350126
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1383028063
Short name T1117
Test name
Test status
Simulation time 140225034596 ps
CPU time 149.63 seconds
Started Jul 26 06:44:18 PM PDT 24
Finished Jul 26 06:46:48 PM PDT 24
Peak memory 200192 kb
Host smart-32bf5e30-c4d7-4791-824a-db5261b75c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383028063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1383028063
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1896773407
Short name T920
Test name
Test status
Simulation time 5814055344 ps
CPU time 8.9 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:25 PM PDT 24
Peak memory 197788 kb
Host smart-d9592801-66f5-4736-86bc-f0a48cee4d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896773407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1896773407
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.300746497
Short name T677
Test name
Test status
Simulation time 266476701626 ps
CPU time 137.03 seconds
Started Jul 26 06:44:08 PM PDT 24
Finished Jul 26 06:46:25 PM PDT 24
Peak memory 208400 kb
Host smart-d32ebd8b-9ccd-4b90-b4dc-d03689e8efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300746497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.300746497
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.158112570
Short name T294
Test name
Test status
Simulation time 16000630306 ps
CPU time 711.45 seconds
Started Jul 26 06:44:17 PM PDT 24
Finished Jul 26 06:56:08 PM PDT 24
Peak memory 200168 kb
Host smart-0fd6904a-0b3c-4f41-97bf-987006190959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158112570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.158112570
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1373734639
Short name T887
Test name
Test status
Simulation time 5986420210 ps
CPU time 14.26 seconds
Started Jul 26 06:44:09 PM PDT 24
Finished Jul 26 06:44:23 PM PDT 24
Peak memory 198952 kb
Host smart-0bd4384a-77e3-4c7c-b7c0-a168d1bdea6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373734639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1373734639
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2895455397
Short name T918
Test name
Test status
Simulation time 47206085668 ps
CPU time 73.66 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:45:30 PM PDT 24
Peak memory 200040 kb
Host smart-284fd36d-8431-49cb-8ec6-0af984a0ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895455397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2895455397
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2565141543
Short name T297
Test name
Test status
Simulation time 3922445562 ps
CPU time 5.49 seconds
Started Jul 26 06:44:08 PM PDT 24
Finished Jul 26 06:44:14 PM PDT 24
Peak memory 196716 kb
Host smart-dcda7ea2-9f5a-42f5-aa86-f8e5c9623d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565141543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2565141543
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3819712439
Short name T1146
Test name
Test status
Simulation time 674399505 ps
CPU time 1.62 seconds
Started Jul 26 06:44:12 PM PDT 24
Finished Jul 26 06:44:13 PM PDT 24
Peak memory 199112 kb
Host smart-f9f36430-e284-4fb7-aab8-cf17a9bfb61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819712439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3819712439
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3845577529
Short name T506
Test name
Test status
Simulation time 48366316447 ps
CPU time 459.21 seconds
Started Jul 26 06:44:13 PM PDT 24
Finished Jul 26 06:51:52 PM PDT 24
Peak memory 215432 kb
Host smart-ea9750a6-85e3-461f-97b5-c9f20c2854f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845577529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3845577529
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1151507748
Short name T81
Test name
Test status
Simulation time 6549587602 ps
CPU time 10.3 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:27 PM PDT 24
Peak memory 200044 kb
Host smart-9e24ce13-0c20-4a6a-89d8-550c8958ff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151507748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1151507748
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2177786054
Short name T1118
Test name
Test status
Simulation time 58807064299 ps
CPU time 42.88 seconds
Started Jul 26 06:44:12 PM PDT 24
Finished Jul 26 06:44:55 PM PDT 24
Peak memory 199488 kb
Host smart-5802fff6-2498-4e9a-95ea-cdf95e192c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177786054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2177786054
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3993482504
Short name T744
Test name
Test status
Simulation time 28164915 ps
CPU time 0.53 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:44:25 PM PDT 24
Peak memory 195016 kb
Host smart-df69f359-9587-41ff-bd26-598e6b9b73d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993482504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3993482504
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4248037469
Short name T926
Test name
Test status
Simulation time 38838865575 ps
CPU time 32.36 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:48 PM PDT 24
Peak memory 200248 kb
Host smart-212b21b9-2290-44e3-98d2-3a42617d1ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248037469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4248037469
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1999181466
Short name T973
Test name
Test status
Simulation time 91366651776 ps
CPU time 151.71 seconds
Started Jul 26 06:44:14 PM PDT 24
Finished Jul 26 06:46:46 PM PDT 24
Peak memory 200196 kb
Host smart-4cfb5a80-6f78-4872-88f2-fbd4b28fac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999181466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1999181466
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1366901117
Short name T611
Test name
Test status
Simulation time 66865942385 ps
CPU time 27.59 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:44 PM PDT 24
Peak memory 200044 kb
Host smart-e3ff5ba8-0286-48ff-b67e-cd64989873de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366901117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1366901117
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3924445384
Short name T885
Test name
Test status
Simulation time 38553165964 ps
CPU time 17.9 seconds
Started Jul 26 06:44:15 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 200116 kb
Host smart-9101202c-1856-45a9-81bf-12b4e8b01967
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924445384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3924445384
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2422311708
Short name T886
Test name
Test status
Simulation time 70288482843 ps
CPU time 210.49 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:47:55 PM PDT 24
Peak memory 200052 kb
Host smart-10f14504-1070-4256-94d5-0122fe9b98fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422311708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2422311708
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.801292351
Short name T415
Test name
Test status
Simulation time 2414748384 ps
CPU time 2.84 seconds
Started Jul 26 06:44:14 PM PDT 24
Finished Jul 26 06:44:17 PM PDT 24
Peak memory 197648 kb
Host smart-07ff4201-dc17-4fb8-9729-de86e94c8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801292351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.801292351
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1970558218
Short name T1019
Test name
Test status
Simulation time 152494248854 ps
CPU time 63.83 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 200348 kb
Host smart-f69e006e-d672-4b8a-b10c-a6019a7d705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970558218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1970558218
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.92486933
Short name T717
Test name
Test status
Simulation time 5355870835 ps
CPU time 307.35 seconds
Started Jul 26 06:44:15 PM PDT 24
Finished Jul 26 06:49:23 PM PDT 24
Peak memory 200140 kb
Host smart-e006e77a-1526-4e31-835c-75518b6bbc25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92486933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.92486933
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.675271865
Short name T53
Test name
Test status
Simulation time 2622980708 ps
CPU time 17.35 seconds
Started Jul 26 06:44:15 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 198620 kb
Host smart-8b99920e-4722-489e-bd3c-23a950f10aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675271865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.675271865
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2215136790
Short name T529
Test name
Test status
Simulation time 20436323979 ps
CPU time 30.28 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:47 PM PDT 24
Peak memory 200088 kb
Host smart-536b5ba4-8529-4e11-83e8-1b7640184d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215136790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2215136790
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1810062533
Short name T776
Test name
Test status
Simulation time 1729591604 ps
CPU time 3.41 seconds
Started Jul 26 06:44:17 PM PDT 24
Finished Jul 26 06:44:20 PM PDT 24
Peak memory 195664 kb
Host smart-58404701-7931-4a29-986c-bdc2613c8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810062533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1810062533
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.472187389
Short name T409
Test name
Test status
Simulation time 307370083 ps
CPU time 1 seconds
Started Jul 26 06:44:13 PM PDT 24
Finished Jul 26 06:44:14 PM PDT 24
Peak memory 198516 kb
Host smart-fdd0ec7a-7a10-4ca8-9bb3-df5f5be134fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472187389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.472187389
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.199364437
Short name T14
Test name
Test status
Simulation time 225022340894 ps
CPU time 879.76 seconds
Started Jul 26 06:44:23 PM PDT 24
Finished Jul 26 06:59:03 PM PDT 24
Peak memory 200140 kb
Host smart-2bdef600-37db-4be3-9665-22bfe3c3ab04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199364437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.199364437
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1433979078
Short name T288
Test name
Test status
Simulation time 7125067575 ps
CPU time 19 seconds
Started Jul 26 06:44:15 PM PDT 24
Finished Jul 26 06:44:34 PM PDT 24
Peak memory 200004 kb
Host smart-9b448b58-3239-412e-91fe-3979d902e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433979078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1433979078
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2433082164
Short name T419
Test name
Test status
Simulation time 21063525733 ps
CPU time 32.51 seconds
Started Jul 26 06:44:16 PM PDT 24
Finished Jul 26 06:44:48 PM PDT 24
Peak memory 200188 kb
Host smart-192e145d-f36a-478e-b712-731262858a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433082164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2433082164
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.587396376
Short name T475
Test name
Test status
Simulation time 11948188 ps
CPU time 0.57 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:39:28 PM PDT 24
Peak memory 195836 kb
Host smart-ee738ce1-b7c5-4238-8a85-cf2f13856eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587396376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.587396376
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2301673295
Short name T446
Test name
Test status
Simulation time 40014100707 ps
CPU time 66.92 seconds
Started Jul 26 06:39:31 PM PDT 24
Finished Jul 26 06:40:38 PM PDT 24
Peak memory 200092 kb
Host smart-921fb8de-be12-4757-9f22-7e2134f641f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301673295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2301673295
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3962882882
Short name T928
Test name
Test status
Simulation time 159636617503 ps
CPU time 249.93 seconds
Started Jul 26 06:39:27 PM PDT 24
Finished Jul 26 06:43:37 PM PDT 24
Peak memory 199940 kb
Host smart-47a2d523-6e72-4654-b767-32eb42d52754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962882882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3962882882
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2207613581
Short name T206
Test name
Test status
Simulation time 67130440214 ps
CPU time 24.07 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:39:56 PM PDT 24
Peak memory 200088 kb
Host smart-1c2f6afe-97e2-41d1-b3dd-f014c30ab9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207613581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2207613581
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.397110512
Short name T376
Test name
Test status
Simulation time 29477385680 ps
CPU time 10.89 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:39:40 PM PDT 24
Peak memory 199116 kb
Host smart-022fc6b1-c74d-4d73-853a-9a3180e45d5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397110512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.397110512
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3782984136
Short name T453
Test name
Test status
Simulation time 166500226733 ps
CPU time 283 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:44:13 PM PDT 24
Peak memory 200148 kb
Host smart-754486a4-64a4-4605-a474-89ab6ed2b344
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782984136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3782984136
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3347939431
Short name T682
Test name
Test status
Simulation time 6380677975 ps
CPU time 4.05 seconds
Started Jul 26 06:39:33 PM PDT 24
Finished Jul 26 06:39:37 PM PDT 24
Peak memory 198344 kb
Host smart-ff910a2d-d9b7-4234-9642-d79636d39cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347939431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3347939431
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3046410918
Short name T777
Test name
Test status
Simulation time 64094355640 ps
CPU time 69.22 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:40:41 PM PDT 24
Peak memory 200320 kb
Host smart-d7eba8f7-8ed9-42c9-951f-f7d981405d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046410918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3046410918
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3263707889
Short name T115
Test name
Test status
Simulation time 14625907858 ps
CPU time 646.77 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:50:17 PM PDT 24
Peak memory 200084 kb
Host smart-1d906a35-853e-48d1-8682-7eff8554bdf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263707889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3263707889
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1030783193
Short name T363
Test name
Test status
Simulation time 6730815209 ps
CPU time 15.27 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:39:47 PM PDT 24
Peak memory 199212 kb
Host smart-4d67064e-4632-4c62-b938-0ec9fa037a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030783193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1030783193
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1113120777
Short name T1130
Test name
Test status
Simulation time 18343811230 ps
CPU time 29.15 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:39:59 PM PDT 24
Peak memory 200120 kb
Host smart-ffb4e490-4309-4a56-8600-cf4f7f396cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113120777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1113120777
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2267638647
Short name T750
Test name
Test status
Simulation time 3237614645 ps
CPU time 5.09 seconds
Started Jul 26 06:39:33 PM PDT 24
Finished Jul 26 06:39:38 PM PDT 24
Peak memory 196060 kb
Host smart-ef7887c2-1ce0-4f01-816f-4aae4b414383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267638647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2267638647
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.819131338
Short name T34
Test name
Test status
Simulation time 172777427 ps
CPU time 0.77 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:39:31 PM PDT 24
Peak memory 218372 kb
Host smart-b3338660-b5dc-42f4-8ed2-f83a6770b7d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819131338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.819131338
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2171735757
Short name T1039
Test name
Test status
Simulation time 719480386 ps
CPU time 1.43 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:39:32 PM PDT 24
Peak memory 198544 kb
Host smart-9d37646f-6417-4715-85a5-a37f961729bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171735757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2171735757
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3905341213
Short name T241
Test name
Test status
Simulation time 504914578667 ps
CPU time 246.03 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:43:36 PM PDT 24
Peak memory 200048 kb
Host smart-9cc3b7d6-7025-4c9e-b518-6ff0c2051486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905341213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3905341213
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1684765863
Short name T247
Test name
Test status
Simulation time 35836546227 ps
CPU time 237.25 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:43:25 PM PDT 24
Peak memory 215768 kb
Host smart-8526e1df-1ccc-4cf8-a902-92c377b9b822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684765863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1684765863
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3790126603
Short name T508
Test name
Test status
Simulation time 386718082 ps
CPU time 1.52 seconds
Started Jul 26 06:39:31 PM PDT 24
Finished Jul 26 06:39:32 PM PDT 24
Peak memory 200048 kb
Host smart-1d7fc65b-642a-46d2-8064-57c9c890fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790126603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3790126603
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3649841155
Short name T891
Test name
Test status
Simulation time 13469605688 ps
CPU time 39.19 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:40:07 PM PDT 24
Peak memory 200064 kb
Host smart-5c2f9bbb-ab18-4805-b526-9324992a644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649841155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3649841155
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2245861996
Short name T630
Test name
Test status
Simulation time 16564897 ps
CPU time 0.53 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 194484 kb
Host smart-5c4ccbb5-e78f-4c5d-ba88-43bb689c022e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245861996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2245861996
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1834329406
Short name T801
Test name
Test status
Simulation time 162513167300 ps
CPU time 48.93 seconds
Started Jul 26 06:44:23 PM PDT 24
Finished Jul 26 06:45:12 PM PDT 24
Peak memory 200060 kb
Host smart-3d11a127-8a9a-4ad0-a272-7ef05492a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834329406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1834329406
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2444436174
Short name T1105
Test name
Test status
Simulation time 129962832952 ps
CPU time 235.24 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:48:19 PM PDT 24
Peak memory 200124 kb
Host smart-a7f3d6ef-eb6b-4130-a50c-b9df0c120ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444436174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2444436174
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.823531560
Short name T413
Test name
Test status
Simulation time 63819317113 ps
CPU time 23.29 seconds
Started Jul 26 06:44:23 PM PDT 24
Finished Jul 26 06:44:46 PM PDT 24
Peak memory 199700 kb
Host smart-d12ce86e-09b2-470a-b7eb-ab305425db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823531560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.823531560
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1125614338
Short name T752
Test name
Test status
Simulation time 44370048976 ps
CPU time 10.18 seconds
Started Jul 26 06:44:23 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 200204 kb
Host smart-5a8dfc56-84ed-4720-b78a-0b67cb21dd37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125614338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1125614338
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4256669391
Short name T950
Test name
Test status
Simulation time 98714503052 ps
CPU time 78.83 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:45:50 PM PDT 24
Peak memory 200192 kb
Host smart-9148e6d7-3fbd-44f4-96a3-d30574ff9e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256669391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4256669391
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3032000252
Short name T662
Test name
Test status
Simulation time 11697217190 ps
CPU time 16.32 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:44:50 PM PDT 24
Peak memory 199908 kb
Host smart-2a25c115-aae0-4211-9048-8e0352fca0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032000252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3032000252
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.4041644890
Short name T52
Test name
Test status
Simulation time 56929087430 ps
CPU time 49.07 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:45:13 PM PDT 24
Peak memory 200320 kb
Host smart-53a4fb92-95be-4c98-b152-99a95a825315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041644890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4041644890
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.4066023594
Short name T996
Test name
Test status
Simulation time 6976775244 ps
CPU time 111.19 seconds
Started Jul 26 06:44:34 PM PDT 24
Finished Jul 26 06:46:25 PM PDT 24
Peak memory 200184 kb
Host smart-66b26a99-0da7-4d9c-8ee9-4cfc64627f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066023594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.4066023594
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4081215467
Short name T729
Test name
Test status
Simulation time 5123895673 ps
CPU time 41.63 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:45:06 PM PDT 24
Peak memory 199660 kb
Host smart-e3984713-cb9f-40e6-b82f-4ccc1e0033fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081215467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4081215467
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1880876998
Short name T290
Test name
Test status
Simulation time 46588626093 ps
CPU time 23.48 seconds
Started Jul 26 06:44:22 PM PDT 24
Finished Jul 26 06:44:46 PM PDT 24
Peak memory 200200 kb
Host smart-e5735ba9-3543-44a9-bb5d-ae2b760f2a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880876998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1880876998
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3378524938
Short name T963
Test name
Test status
Simulation time 35482262904 ps
CPU time 5.6 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:44:29 PM PDT 24
Peak memory 195944 kb
Host smart-f0fa9e3c-70b9-4f99-bf06-3d7c9f376151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378524938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3378524938
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.721706784
Short name T493
Test name
Test status
Simulation time 703563620 ps
CPU time 2.52 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:44:26 PM PDT 24
Peak memory 198896 kb
Host smart-7045597c-65a7-4e73-9048-324e498de5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721706784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.721706784
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3097176266
Short name T234
Test name
Test status
Simulation time 163141510673 ps
CPU time 241.48 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:48:34 PM PDT 24
Peak memory 208504 kb
Host smart-a55c379a-341c-46de-930e-df638d5082ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097176266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3097176266
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3797499611
Short name T633
Test name
Test status
Simulation time 61653990219 ps
CPU time 603.47 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:54:35 PM PDT 24
Peak memory 216416 kb
Host smart-651810d8-c6ce-4493-876f-ec5a2cf95d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797499611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3797499611
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3548824886
Short name T337
Test name
Test status
Simulation time 1379225320 ps
CPU time 2.35 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:44:26 PM PDT 24
Peak memory 199448 kb
Host smart-5a7c4bdb-6373-46ed-aa86-4227beed291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548824886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3548824886
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3083015479
Short name T48
Test name
Test status
Simulation time 45092166613 ps
CPU time 75.02 seconds
Started Jul 26 06:44:24 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 200140 kb
Host smart-33ce77d0-26a3-41dd-abe1-373a47a19812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083015479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3083015479
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1749010854
Short name T755
Test name
Test status
Simulation time 13033798 ps
CPU time 0.56 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:45:09 PM PDT 24
Peak memory 195496 kb
Host smart-9dc1cb74-e7fe-4d21-b09c-8c20e679332b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749010854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1749010854
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2142471620
Short name T135
Test name
Test status
Simulation time 32480904999 ps
CPU time 47.18 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:45:19 PM PDT 24
Peak memory 200112 kb
Host smart-5596970e-81c5-4786-b828-8e3050ec2e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142471620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2142471620
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.953155350
Short name T1154
Test name
Test status
Simulation time 76077066285 ps
CPU time 31.86 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:45:04 PM PDT 24
Peak memory 200188 kb
Host smart-bbf68fa4-aff5-4a4d-b2d9-3801095b3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953155350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.953155350
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4178158058
Short name T862
Test name
Test status
Simulation time 32889655924 ps
CPU time 53.8 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:45:26 PM PDT 24
Peak memory 200088 kb
Host smart-2b0112b9-68a9-4cb2-b86e-4ba9b2378bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178158058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4178158058
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.123694109
Short name T1135
Test name
Test status
Simulation time 19434050432 ps
CPU time 5.82 seconds
Started Jul 26 06:44:35 PM PDT 24
Finished Jul 26 06:44:41 PM PDT 24
Peak memory 197940 kb
Host smart-4efba195-15c8-4300-a844-cede961216a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123694109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.123694109
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2262908836
Short name T959
Test name
Test status
Simulation time 85111900865 ps
CPU time 165.8 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:47:19 PM PDT 24
Peak memory 200140 kb
Host smart-9046211b-e2ef-4b94-b48b-247a080d208f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262908836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2262908836
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1020013235
Short name T771
Test name
Test status
Simulation time 11533534318 ps
CPU time 19.1 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:44:51 PM PDT 24
Peak memory 200096 kb
Host smart-4c6331fc-e738-40ff-b5a7-b5b29102cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020013235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1020013235
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3928821896
Short name T703
Test name
Test status
Simulation time 26851387670 ps
CPU time 10.87 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:44:43 PM PDT 24
Peak memory 194908 kb
Host smart-522b03a9-f21b-43fa-ab49-0f49ab2b2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928821896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3928821896
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2652060524
Short name T970
Test name
Test status
Simulation time 21110097776 ps
CPU time 594.56 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:54:27 PM PDT 24
Peak memory 199976 kb
Host smart-187e952d-9a90-4628-802f-0bf2cc07b967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652060524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2652060524
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1837619274
Short name T998
Test name
Test status
Simulation time 6335462563 ps
CPU time 12.23 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:44:44 PM PDT 24
Peak memory 198300 kb
Host smart-1c4d9e61-cdd2-44c3-9b17-6ffed164beb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837619274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1837619274
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.339839874
Short name T867
Test name
Test status
Simulation time 39118505067 ps
CPU time 19.71 seconds
Started Jul 26 06:44:32 PM PDT 24
Finished Jul 26 06:44:52 PM PDT 24
Peak memory 200180 kb
Host smart-699c35e4-dd3e-47b6-abc1-95110ca901b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339839874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.339839874
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.713705547
Short name T432
Test name
Test status
Simulation time 615417614 ps
CPU time 1.44 seconds
Started Jul 26 06:44:33 PM PDT 24
Finished Jul 26 06:44:35 PM PDT 24
Peak memory 195780 kb
Host smart-4cbcbea4-8755-4d02-a7b0-9ac0ca76b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713705547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.713705547
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2009488227
Short name T69
Test name
Test status
Simulation time 129748218 ps
CPU time 1.13 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 198596 kb
Host smart-ce8e744f-2cd0-4b3b-bd14-0dfa75239eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009488227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2009488227
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1183217916
Short name T56
Test name
Test status
Simulation time 76662087210 ps
CPU time 613.26 seconds
Started Jul 26 06:45:07 PM PDT 24
Finished Jul 26 06:55:21 PM PDT 24
Peak memory 216708 kb
Host smart-3630fe9f-735e-4ebf-9c1c-1e7d17ce1f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183217916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1183217916
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3910546518
Short name T653
Test name
Test status
Simulation time 893969709 ps
CPU time 2.7 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:44:33 PM PDT 24
Peak memory 199984 kb
Host smart-f21f7ad3-785b-456b-ba7e-4853d3bee891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910546518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3910546518
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.12367507
Short name T1115
Test name
Test status
Simulation time 112070616881 ps
CPU time 47.77 seconds
Started Jul 26 06:44:31 PM PDT 24
Finished Jul 26 06:45:19 PM PDT 24
Peak memory 200176 kb
Host smart-2ac54748-3715-4251-a2ba-e94858cc3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12367507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.12367507
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3453037535
Short name T30
Test name
Test status
Simulation time 14524421 ps
CPU time 0.57 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 195516 kb
Host smart-326c46ab-9b48-4506-bf12-1d9e938f3f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453037535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3453037535
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2624564349
Short name T985
Test name
Test status
Simulation time 97013244156 ps
CPU time 39.23 seconds
Started Jul 26 06:45:09 PM PDT 24
Finished Jul 26 06:45:48 PM PDT 24
Peak memory 200028 kb
Host smart-49a7bd44-b785-412f-8562-f767aa978513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624564349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2624564349
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2322899375
Short name T9
Test name
Test status
Simulation time 30134047585 ps
CPU time 13.68 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:45:22 PM PDT 24
Peak memory 199856 kb
Host smart-4ae8f572-558e-4610-a36c-e9486f5dea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322899375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2322899375
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3336455894
Short name T230
Test name
Test status
Simulation time 70814510704 ps
CPU time 200.66 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:48:28 PM PDT 24
Peak memory 200068 kb
Host smart-51c27442-e60e-4893-a0e3-94ff25d61302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336455894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3336455894
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1450112310
Short name T1015
Test name
Test status
Simulation time 38738471757 ps
CPU time 8.57 seconds
Started Jul 26 06:45:07 PM PDT 24
Finished Jul 26 06:45:16 PM PDT 24
Peak memory 200160 kb
Host smart-d6eb3c31-2653-4835-ae68-43f0367b4240
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450112310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1450112310
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4047796470
Short name T629
Test name
Test status
Simulation time 168818605133 ps
CPU time 450.88 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:52:50 PM PDT 24
Peak memory 200156 kb
Host smart-fe245c88-4d9d-4ee7-8a68-1a6fa3888520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047796470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4047796470
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.476246704
Short name T1049
Test name
Test status
Simulation time 10523111143 ps
CPU time 5.46 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:45:25 PM PDT 24
Peak memory 199656 kb
Host smart-35cabe40-2014-43c7-b3d0-9a0a59418c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476246704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.476246704
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3717727468
Short name T684
Test name
Test status
Simulation time 41222680809 ps
CPU time 76.01 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:46:24 PM PDT 24
Peak memory 200344 kb
Host smart-8b87f220-6b32-4fce-9e5f-75b7b94c601e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717727468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3717727468
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4250523168
Short name T718
Test name
Test status
Simulation time 8633356475 ps
CPU time 514.27 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:53:53 PM PDT 24
Peak memory 200100 kb
Host smart-80fd415f-b07c-4b28-848f-02b0f6ef85ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250523168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4250523168
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.411326012
Short name T999
Test name
Test status
Simulation time 2009482504 ps
CPU time 12.28 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 197988 kb
Host smart-c095b607-eca4-4d32-983e-22c1f963d19b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411326012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.411326012
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3692473264
Short name T450
Test name
Test status
Simulation time 96962021196 ps
CPU time 295.86 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:50:04 PM PDT 24
Peak memory 200172 kb
Host smart-cf624da1-5477-4040-bfeb-10cb5f826a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692473264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3692473264
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3353092390
Short name T588
Test name
Test status
Simulation time 2903041885 ps
CPU time 4.76 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:45:13 PM PDT 24
Peak memory 196100 kb
Host smart-2ab9466e-5207-43b2-9c79-7eaec144ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353092390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3353092390
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4294747002
Short name T114
Test name
Test status
Simulation time 956994966 ps
CPU time 2.59 seconds
Started Jul 26 06:45:07 PM PDT 24
Finished Jul 26 06:45:10 PM PDT 24
Peak memory 198812 kb
Host smart-768a8fd5-8865-4753-9029-04fffc25694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294747002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4294747002
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3426001303
Short name T650
Test name
Test status
Simulation time 171887849438 ps
CPU time 233.28 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 200080 kb
Host smart-3c3a6b39-9343-4ff2-a20c-3d9b70db7e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426001303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3426001303
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3256664803
Short name T160
Test name
Test status
Simulation time 140818223747 ps
CPU time 502.35 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:53:41 PM PDT 24
Peak memory 216808 kb
Host smart-52460a3d-d058-4d92-b6b3-d17c0571662d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256664803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3256664803
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1760932447
Short name T393
Test name
Test status
Simulation time 1898719725 ps
CPU time 2.15 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:45:21 PM PDT 24
Peak memory 198748 kb
Host smart-efc7ea6b-acfa-4f81-8607-79685daacce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760932447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1760932447
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.300334613
Short name T678
Test name
Test status
Simulation time 63729644187 ps
CPU time 14.97 seconds
Started Jul 26 06:45:08 PM PDT 24
Finished Jul 26 06:45:23 PM PDT 24
Peak memory 198228 kb
Host smart-b1f902ee-5deb-46f8-86e6-6c1744c62ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300334613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.300334613
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1712531558
Short name T847
Test name
Test status
Simulation time 21323820 ps
CPU time 0.56 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 195552 kb
Host smart-c5218059-9c05-454a-8dfb-1a11a97825a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712531558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1712531558
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1975469173
Short name T54
Test name
Test status
Simulation time 25085565724 ps
CPU time 32.59 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:45:53 PM PDT 24
Peak memory 200180 kb
Host smart-196b6e17-461d-49e9-9550-10f7b444fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975469173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1975469173
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2603927270
Short name T880
Test name
Test status
Simulation time 69358318854 ps
CPU time 29.69 seconds
Started Jul 26 06:45:17 PM PDT 24
Finished Jul 26 06:45:46 PM PDT 24
Peak memory 200132 kb
Host smart-47615bd4-e64e-4f77-ae81-49e7badccea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603927270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2603927270
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1941958227
Short name T225
Test name
Test status
Simulation time 79474206111 ps
CPU time 70.76 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:46:29 PM PDT 24
Peak memory 200180 kb
Host smart-153a5363-5c47-4812-bcdc-ebb0addfbe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941958227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1941958227
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1811599901
Short name T773
Test name
Test status
Simulation time 69188860644 ps
CPU time 81.43 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:46:41 PM PDT 24
Peak memory 199848 kb
Host smart-8c0b92c6-2b66-4b05-91a8-80401435baa4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811599901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1811599901
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3311844844
Short name T855
Test name
Test status
Simulation time 99926266054 ps
CPU time 185.73 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:48:25 PM PDT 24
Peak memory 200164 kb
Host smart-02954e75-f795-47a8-8765-905ec997fecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311844844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3311844844
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3214015743
Short name T430
Test name
Test status
Simulation time 3734003382 ps
CPU time 4.29 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:45:22 PM PDT 24
Peak memory 199124 kb
Host smart-05c03957-1f59-4770-8b29-ec1b43ba6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214015743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3214015743
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.4097682932
Short name T1163
Test name
Test status
Simulation time 79256319929 ps
CPU time 116.67 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:47:17 PM PDT 24
Peak memory 200324 kb
Host smart-ea374e27-12bf-4c8e-a4ef-cf1605d2503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097682932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.4097682932
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.806592240
Short name T799
Test name
Test status
Simulation time 15005765385 ps
CPU time 45.61 seconds
Started Jul 26 06:45:17 PM PDT 24
Finished Jul 26 06:46:03 PM PDT 24
Peak memory 200124 kb
Host smart-35fd097d-aca0-4ceb-87bd-5b264176d284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806592240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.806592240
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3294652785
Short name T1150
Test name
Test status
Simulation time 7784261855 ps
CPU time 61.57 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:46:21 PM PDT 24
Peak memory 199080 kb
Host smart-d85470e9-f38d-43cc-8963-cfb96dd11b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294652785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3294652785
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1367484211
Short name T585
Test name
Test status
Simulation time 331235581860 ps
CPU time 71.35 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:46:30 PM PDT 24
Peak memory 200220 kb
Host smart-eef8496d-30e8-4574-8093-4ce4f53a1d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367484211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1367484211
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3892215131
Short name T754
Test name
Test status
Simulation time 23664353463 ps
CPU time 10.14 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:45:28 PM PDT 24
Peak memory 196380 kb
Host smart-d8c57e3f-bd47-415c-9139-6ba07d6b1d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892215131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3892215131
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1058272393
Short name T768
Test name
Test status
Simulation time 407015472 ps
CPU time 2.48 seconds
Started Jul 26 06:45:17 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 198348 kb
Host smart-55791861-681f-44ff-bf2d-88867fc8ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058272393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1058272393
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2605261633
Short name T748
Test name
Test status
Simulation time 82725791101 ps
CPU time 68.75 seconds
Started Jul 26 06:45:17 PM PDT 24
Finished Jul 26 06:46:26 PM PDT 24
Peak memory 200132 kb
Host smart-b936a4a1-f585-4d6b-832d-b2fbf98f8fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605261633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2605261633
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2498613948
Short name T55
Test name
Test status
Simulation time 15763839733 ps
CPU time 192.36 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:48:30 PM PDT 24
Peak memory 209868 kb
Host smart-503ab0c2-edaa-4149-9de0-b3bd72132780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498613948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2498613948
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3612138630
Short name T374
Test name
Test status
Simulation time 1368540173 ps
CPU time 3.72 seconds
Started Jul 26 06:45:21 PM PDT 24
Finished Jul 26 06:45:25 PM PDT 24
Peak memory 199524 kb
Host smart-7d0bcb21-9c2e-4b50-b07f-c67769ddf8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612138630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3612138630
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.614919401
Short name T871
Test name
Test status
Simulation time 163765126547 ps
CPU time 291.75 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:50:10 PM PDT 24
Peak memory 200096 kb
Host smart-e94831e6-7e52-4495-b08c-312b73b314b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614919401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.614919401
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2312287730
Short name T816
Test name
Test status
Simulation time 13803651 ps
CPU time 0.55 seconds
Started Jul 26 06:45:28 PM PDT 24
Finished Jul 26 06:45:28 PM PDT 24
Peak memory 195540 kb
Host smart-621dd3e0-f42c-4efc-a324-78299400223c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312287730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2312287730
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3872397311
Short name T338
Test name
Test status
Simulation time 53472032041 ps
CPU time 46.92 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:46:06 PM PDT 24
Peak memory 200188 kb
Host smart-dbe0cc78-0dc6-4019-8c83-def2001d9b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872397311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3872397311
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1515712973
Short name T977
Test name
Test status
Simulation time 22851812637 ps
CPU time 21.59 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:45:41 PM PDT 24
Peak memory 199944 kb
Host smart-ff05a664-74c1-4163-afd0-bf4cac3a0154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515712973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1515712973
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3169519135
Short name T199
Test name
Test status
Simulation time 137901681961 ps
CPU time 204.98 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:48:45 PM PDT 24
Peak memory 200180 kb
Host smart-5af833e7-f876-406f-8c2e-b11242eed207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169519135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3169519135
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2769406173
Short name T129
Test name
Test status
Simulation time 408162784626 ps
CPU time 134.7 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:47:33 PM PDT 24
Peak memory 200096 kb
Host smart-6acf81b2-71a7-4ebb-9484-88ec98c57d91
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769406173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2769406173
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1254756202
Short name T451
Test name
Test status
Simulation time 95771339107 ps
CPU time 148.61 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:47:47 PM PDT 24
Peak memory 200092 kb
Host smart-0f3a3980-98a2-46b4-92bc-992ee57dce87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254756202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1254756202
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.309913857
Short name T497
Test name
Test status
Simulation time 5900585715 ps
CPU time 11.06 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:45:30 PM PDT 24
Peak memory 199548 kb
Host smart-05371077-3bcd-43b1-8eca-1c26e3ba2981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309913857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.309913857
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.367075392
Short name T713
Test name
Test status
Simulation time 47620619198 ps
CPU time 59.21 seconds
Started Jul 26 06:45:16 PM PDT 24
Finished Jul 26 06:46:16 PM PDT 24
Peak memory 198296 kb
Host smart-21731e59-5c2d-4674-aec2-77b3b12ce65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367075392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.367075392
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2439717083
Short name T956
Test name
Test status
Simulation time 8191365345 ps
CPU time 417.56 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:52:15 PM PDT 24
Peak memory 200192 kb
Host smart-48e55ce4-b614-4684-9795-1dfbb0366409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439717083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2439717083
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.101112439
Short name T351
Test name
Test status
Simulation time 3778912550 ps
CPU time 4.5 seconds
Started Jul 26 06:45:17 PM PDT 24
Finished Jul 26 06:45:21 PM PDT 24
Peak memory 199244 kb
Host smart-ec99c714-6de1-457c-a692-85e809545310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101112439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.101112439
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3352896111
Short name T641
Test name
Test status
Simulation time 114433537557 ps
CPU time 165.07 seconds
Started Jul 26 06:45:19 PM PDT 24
Finished Jul 26 06:48:05 PM PDT 24
Peak memory 200208 kb
Host smart-0da146b8-5fba-4daa-b86e-8c07122a6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352896111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3352896111
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.546009253
Short name T745
Test name
Test status
Simulation time 5867004525 ps
CPU time 8.69 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:45:27 PM PDT 24
Peak memory 197024 kb
Host smart-2ed24d7e-b23b-44d4-af5c-008bc5bd5fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546009253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.546009253
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1329797442
Short name T704
Test name
Test status
Simulation time 781462868 ps
CPU time 1.45 seconds
Started Jul 26 06:45:18 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 200108 kb
Host smart-6fac42c1-696a-4c16-b67d-8e1ec734ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329797442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1329797442
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1729430450
Short name T461
Test name
Test status
Simulation time 178323984025 ps
CPU time 910.51 seconds
Started Jul 26 06:45:29 PM PDT 24
Finished Jul 26 07:00:40 PM PDT 24
Peak memory 200172 kb
Host smart-d478add2-1fcc-4eaa-9d9e-e5603a68f2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729430450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1729430450
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3020375700
Short name T513
Test name
Test status
Simulation time 1705464259 ps
CPU time 1.79 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:45:22 PM PDT 24
Peak memory 198544 kb
Host smart-23f21e98-0eb8-4fb8-bcc7-021d3803d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020375700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3020375700
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.291808466
Short name T1071
Test name
Test status
Simulation time 81057390180 ps
CPU time 44.79 seconds
Started Jul 26 06:45:20 PM PDT 24
Finished Jul 26 06:46:05 PM PDT 24
Peak memory 200100 kb
Host smart-7358518a-cca6-4f27-a470-46483eb371a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291808466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.291808466
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2482508822
Short name T29
Test name
Test status
Simulation time 11670243 ps
CPU time 0.54 seconds
Started Jul 26 06:45:33 PM PDT 24
Finished Jul 26 06:45:34 PM PDT 24
Peak memory 195492 kb
Host smart-c1db8b3c-f074-47d9-8664-a5b5e0c08561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482508822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2482508822
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2340949451
Short name T145
Test name
Test status
Simulation time 62548478194 ps
CPU time 25.75 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:45:56 PM PDT 24
Peak memory 200380 kb
Host smart-cde5ccc8-8bc9-4318-b307-44086b027da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340949451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2340949451
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1316573299
Short name T1054
Test name
Test status
Simulation time 23536741459 ps
CPU time 22.06 seconds
Started Jul 26 06:45:26 PM PDT 24
Finished Jul 26 06:45:48 PM PDT 24
Peak memory 200188 kb
Host smart-67e4f633-3c62-4443-b29b-04fab4245c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316573299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1316573299
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2877446417
Short name T213
Test name
Test status
Simulation time 17884282909 ps
CPU time 26.93 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:45:57 PM PDT 24
Peak memory 200172 kb
Host smart-a8a94f50-d989-46b2-b9d3-3e7873e93728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877446417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2877446417
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.772124947
Short name T17
Test name
Test status
Simulation time 2018896836 ps
CPU time 3.37 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:45:31 PM PDT 24
Peak memory 195944 kb
Host smart-b07986cc-171b-4b8a-b4ce-af5136eb8472
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772124947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.772124947
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2067992918
Short name T121
Test name
Test status
Simulation time 66274807736 ps
CPU time 500.61 seconds
Started Jul 26 06:45:28 PM PDT 24
Finished Jul 26 06:53:48 PM PDT 24
Peak memory 200116 kb
Host smart-1fd76f7e-512c-4aa0-868b-d6260716b451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067992918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2067992918
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2742366683
Short name T520
Test name
Test status
Simulation time 3186979830 ps
CPU time 5.06 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:45:32 PM PDT 24
Peak memory 196944 kb
Host smart-8456f9bc-e92a-47d8-bb5b-70833995eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742366683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2742366683
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.127104084
Short name T1170
Test name
Test status
Simulation time 24092715105 ps
CPU time 16.82 seconds
Started Jul 26 06:45:33 PM PDT 24
Finished Jul 26 06:45:50 PM PDT 24
Peak memory 199388 kb
Host smart-55466962-6620-466c-b70a-55729ae6fb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127104084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.127104084
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2095407962
Short name T582
Test name
Test status
Simulation time 19894514694 ps
CPU time 1168.45 seconds
Started Jul 26 06:45:28 PM PDT 24
Finished Jul 26 07:04:57 PM PDT 24
Peak memory 200232 kb
Host smart-d4eb815f-5006-4698-8850-088054d61fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095407962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2095407962
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3913394182
Short name T385
Test name
Test status
Simulation time 7856270918 ps
CPU time 35.24 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:46:03 PM PDT 24
Peak memory 199680 kb
Host smart-fdf2e495-f783-4eda-987d-175665e2c00a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913394182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3913394182
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3650701283
Short name T559
Test name
Test status
Simulation time 103699472787 ps
CPU time 156.81 seconds
Started Jul 26 06:45:32 PM PDT 24
Finished Jul 26 06:48:09 PM PDT 24
Peak memory 200116 kb
Host smart-9753cbf4-bc75-45d2-98d8-6fdf0e97ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650701283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3650701283
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3705047061
Short name T709
Test name
Test status
Simulation time 3944893891 ps
CPU time 7.17 seconds
Started Jul 26 06:45:32 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 196952 kb
Host smart-371373de-4bc9-4f9c-a49d-b8a36d2813c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705047061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3705047061
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.4258626158
Short name T536
Test name
Test status
Simulation time 537542742 ps
CPU time 1.2 seconds
Started Jul 26 06:45:26 PM PDT 24
Finished Jul 26 06:45:28 PM PDT 24
Peak memory 199864 kb
Host smart-d933f09e-b5c6-4741-bdb1-f794bd6a9578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258626158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4258626158
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4116197011
Short name T1100
Test name
Test status
Simulation time 902572948408 ps
CPU time 635.53 seconds
Started Jul 26 06:45:32 PM PDT 24
Finished Jul 26 06:56:08 PM PDT 24
Peak memory 200036 kb
Host smart-ecc27eef-50cb-4b40-a8a5-5e3863420a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116197011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4116197011
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1543042541
Short name T1176
Test name
Test status
Simulation time 96416160549 ps
CPU time 1581.2 seconds
Started Jul 26 06:45:26 PM PDT 24
Finished Jul 26 07:11:48 PM PDT 24
Peak memory 228076 kb
Host smart-ed54be26-45a3-4a2f-9e3e-0229256f65d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543042541 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1543042541
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.200069514
Short name T302
Test name
Test status
Simulation time 1066309729 ps
CPU time 4.39 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:45:35 PM PDT 24
Peak memory 199216 kb
Host smart-1894e7b5-30f5-4a51-b190-65e70d569045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200069514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.200069514
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3217317713
Short name T72
Test name
Test status
Simulation time 86367695290 ps
CPU time 48.59 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:46:16 PM PDT 24
Peak memory 200196 kb
Host smart-14c7507e-c102-4333-b611-40897feb2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217317713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3217317713
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.135867454
Short name T924
Test name
Test status
Simulation time 40571651 ps
CPU time 0.54 seconds
Started Jul 26 06:45:28 PM PDT 24
Finished Jul 26 06:45:29 PM PDT 24
Peak memory 194980 kb
Host smart-c235d256-bce6-473c-9794-fdd00c7c8ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135867454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.135867454
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1739852760
Short name T148
Test name
Test status
Simulation time 20705929263 ps
CPU time 28.96 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:45:56 PM PDT 24
Peak memory 200144 kb
Host smart-f03064c4-abb6-46bf-be94-212cd7188df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739852760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1739852760
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3737318164
Short name T1153
Test name
Test status
Simulation time 28499652484 ps
CPU time 48.71 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:46:19 PM PDT 24
Peak memory 200372 kb
Host smart-a99a0913-3cb3-45c5-81e2-32bfe1b16944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737318164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3737318164
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2004581620
Short name T849
Test name
Test status
Simulation time 99119241123 ps
CPU time 39 seconds
Started Jul 26 06:45:27 PM PDT 24
Finished Jul 26 06:46:07 PM PDT 24
Peak memory 200120 kb
Host smart-183b4728-b0da-4e7a-81c3-88e06a4851f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004581620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2004581620
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.24887492
Short name T612
Test name
Test status
Simulation time 38879136016 ps
CPU time 69.86 seconds
Started Jul 26 06:45:31 PM PDT 24
Finished Jul 26 06:46:41 PM PDT 24
Peak memory 200360 kb
Host smart-050404db-4db2-4979-9d91-5d7a74210202
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.24887492
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1835460890
Short name T1016
Test name
Test status
Simulation time 89305054431 ps
CPU time 317.14 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:50:48 PM PDT 24
Peak memory 200144 kb
Host smart-f82c84cb-0b4f-44f0-ae89-dab182f2ac4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835460890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1835460890
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3125749081
Short name T857
Test name
Test status
Simulation time 3224405076 ps
CPU time 5.92 seconds
Started Jul 26 06:45:29 PM PDT 24
Finished Jul 26 06:45:35 PM PDT 24
Peak memory 196256 kb
Host smart-86661fa7-f67e-4ea3-9398-495630294ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125749081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3125749081
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2436876803
Short name T790
Test name
Test status
Simulation time 15287276026 ps
CPU time 23.27 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:45:53 PM PDT 24
Peak memory 198504 kb
Host smart-fb2fcb8a-734d-467e-9175-1815867ec36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436876803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2436876803
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.505409872
Short name T580
Test name
Test status
Simulation time 11902764748 ps
CPU time 585.84 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:55:16 PM PDT 24
Peak memory 200232 kb
Host smart-43970730-2ae9-47af-bce2-40a2f47af1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505409872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.505409872
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1526611852
Short name T1040
Test name
Test status
Simulation time 4524393416 ps
CPU time 9.48 seconds
Started Jul 26 06:45:28 PM PDT 24
Finished Jul 26 06:45:37 PM PDT 24
Peak memory 199588 kb
Host smart-2f5c7d9f-8560-4da1-ba31-99b03ba3d6ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526611852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1526611852
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2335796555
Short name T154
Test name
Test status
Simulation time 24067762192 ps
CPU time 16.86 seconds
Started Jul 26 06:45:31 PM PDT 24
Finished Jul 26 06:45:48 PM PDT 24
Peak memory 200032 kb
Host smart-ef85ad6c-ce29-4aeb-91ef-2fe62ce9498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335796555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2335796555
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.445023461
Short name T610
Test name
Test status
Simulation time 2804269583 ps
CPU time 2.43 seconds
Started Jul 26 06:45:31 PM PDT 24
Finished Jul 26 06:45:33 PM PDT 24
Peak memory 196784 kb
Host smart-ceff2794-bfda-432f-a58a-4d2fc6641171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445023461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.445023461
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2167854164
Short name T711
Test name
Test status
Simulation time 5569337925 ps
CPU time 7.28 seconds
Started Jul 26 06:45:31 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 199720 kb
Host smart-6033e41d-2a79-49d3-94c7-db5f4f5ce8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167854164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2167854164
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.117189240
Short name T1024
Test name
Test status
Simulation time 43907204554 ps
CPU time 207.99 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:48:58 PM PDT 24
Peak memory 200332 kb
Host smart-b9f94b1b-1308-4e13-8889-ccfcc491c871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117189240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.117189240
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3636219277
Short name T330
Test name
Test status
Simulation time 1158999950997 ps
CPU time 964.8 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 07:01:35 PM PDT 24
Peak memory 224928 kb
Host smart-5ac8b7e7-cf0e-4306-9ef9-0f631245b502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636219277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3636219277
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3176856839
Short name T395
Test name
Test status
Simulation time 1207419995 ps
CPU time 3.77 seconds
Started Jul 26 06:45:30 PM PDT 24
Finished Jul 26 06:45:34 PM PDT 24
Peak memory 199236 kb
Host smart-e915c6ca-2349-4c6b-ac83-b04e8b72da94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176856839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3176856839
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1355857109
Short name T901
Test name
Test status
Simulation time 133310778284 ps
CPU time 12.48 seconds
Started Jul 26 06:45:26 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 197076 kb
Host smart-eb5e3248-8e13-4581-a139-1a12c6ccd434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355857109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1355857109
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.261240814
Short name T481
Test name
Test status
Simulation time 11777807 ps
CPU time 0.54 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:45:41 PM PDT 24
Peak memory 194956 kb
Host smart-b5dad6f1-e476-4e47-a94b-d97a55cc4eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261240814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.261240814
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3209185572
Short name T944
Test name
Test status
Simulation time 22017948515 ps
CPU time 34.81 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:46:12 PM PDT 24
Peak memory 200160 kb
Host smart-423f5db5-c681-487e-b4dd-4db779a51539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209185572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3209185572
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3946450560
Short name T1103
Test name
Test status
Simulation time 106491309424 ps
CPU time 159.07 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:48:18 PM PDT 24
Peak memory 200204 kb
Host smart-68e16534-a8b3-4057-ae4f-db2051b1784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946450560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3946450560
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1529980404
Short name T543
Test name
Test status
Simulation time 10331225270 ps
CPU time 16.34 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:45:57 PM PDT 24
Peak memory 200148 kb
Host smart-2e49a8b5-afd1-4f41-9294-ffe1588dcad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529980404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1529980404
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.410426706
Short name T1172
Test name
Test status
Simulation time 249999170473 ps
CPU time 421.31 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:52:38 PM PDT 24
Peak memory 200036 kb
Host smart-85b8d472-3c91-424f-881e-e78f2df95084
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410426706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.410426706
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3150604694
Short name T412
Test name
Test status
Simulation time 104318788258 ps
CPU time 736.15 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 200144 kb
Host smart-584b08cd-8d42-41c1-8483-d729bfd2c33d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150604694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3150604694
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2049432466
Short name T656
Test name
Test status
Simulation time 7566425396 ps
CPU time 2.88 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:45:43 PM PDT 24
Peak memory 199144 kb
Host smart-3ace33ef-9b63-4a5d-b038-a38303fb2177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049432466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2049432466
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2072085751
Short name T473
Test name
Test status
Simulation time 77504845747 ps
CPU time 164.07 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:48:26 PM PDT 24
Peak memory 200208 kb
Host smart-cb437638-9c4e-44c4-8781-1fef6970d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072085751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2072085751
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1826642326
Short name T455
Test name
Test status
Simulation time 7378685121 ps
CPU time 409.56 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 200108 kb
Host smart-58889f93-2ec8-43e3-a980-aef03f1f6ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826642326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1826642326
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1179501953
Short name T854
Test name
Test status
Simulation time 4794059082 ps
CPU time 19.36 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:46:00 PM PDT 24
Peak memory 199416 kb
Host smart-8c801020-339f-42d6-9e5b-d367f2f5032b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179501953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1179501953
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3428800788
Short name T1161
Test name
Test status
Simulation time 108096996096 ps
CPU time 213.53 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:49:12 PM PDT 24
Peak memory 200232 kb
Host smart-817a8d71-3be5-43a6-84c4-b803e942a259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428800788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3428800788
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2685386008
Short name T759
Test name
Test status
Simulation time 3110205905 ps
CPU time 1.33 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:45:40 PM PDT 24
Peak memory 196280 kb
Host smart-156a3c34-d196-4d03-8da4-4640fff678be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685386008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2685386008
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3787544366
Short name T764
Test name
Test status
Simulation time 149618325 ps
CPU time 0.82 seconds
Started Jul 26 06:45:29 PM PDT 24
Finished Jul 26 06:45:30 PM PDT 24
Peak memory 198272 kb
Host smart-06b28202-c5bb-4dd2-854b-22a664d7f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787544366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3787544366
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4011776220
Short name T276
Test name
Test status
Simulation time 137430160107 ps
CPU time 162.62 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:48:23 PM PDT 24
Peak memory 216448 kb
Host smart-ea28f0bb-ca20-4d39-9724-ef81d17520b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011776220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4011776220
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1923019612
Short name T62
Test name
Test status
Simulation time 69378575630 ps
CPU time 812.86 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:59:14 PM PDT 24
Peak memory 225148 kb
Host smart-9609f135-834e-4b63-8cb7-1789a812a9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923019612 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1923019612
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2416769819
Short name T530
Test name
Test status
Simulation time 8638066513 ps
CPU time 6.38 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:45:45 PM PDT 24
Peak memory 200064 kb
Host smart-06baf34e-641a-463a-86cc-ad22daa51d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416769819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2416769819
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.507819492
Short name T1123
Test name
Test status
Simulation time 92994542250 ps
CPU time 35.05 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:46:12 PM PDT 24
Peak memory 200104 kb
Host smart-6d72f9df-05ed-43a2-a4c3-e9826a6a4a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507819492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.507819492
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1827988155
Short name T535
Test name
Test status
Simulation time 12022648 ps
CPU time 0.56 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:45:42 PM PDT 24
Peak memory 195528 kb
Host smart-44a033ae-c339-4387-89c7-cd528eb3377f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827988155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1827988155
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3707015029
Short name T1142
Test name
Test status
Simulation time 76195733664 ps
CPU time 34.21 seconds
Started Jul 26 06:45:36 PM PDT 24
Finished Jul 26 06:46:10 PM PDT 24
Peak memory 200100 kb
Host smart-7e7a0c80-615a-4f40-8494-021fc2ef68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707015029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3707015029
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1475995723
Short name T915
Test name
Test status
Simulation time 41006371567 ps
CPU time 14.41 seconds
Started Jul 26 06:45:42 PM PDT 24
Finished Jul 26 06:45:57 PM PDT 24
Peak memory 200188 kb
Host smart-42d703a0-9fa9-4957-a3ed-46a2568347e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475995723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1475995723
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3346124058
Short name T938
Test name
Test status
Simulation time 22491836478 ps
CPU time 21.62 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:45:59 PM PDT 24
Peak memory 200088 kb
Host smart-f6065a83-1650-42f5-8867-5cfb3816954c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346124058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3346124058
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3955574311
Short name T911
Test name
Test status
Simulation time 99218656104 ps
CPU time 537.98 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:54:38 PM PDT 24
Peak memory 200180 kb
Host smart-e71df634-9458-4633-9098-6a788262522e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955574311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3955574311
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3075952007
Short name T534
Test name
Test status
Simulation time 3074079164 ps
CPU time 3.01 seconds
Started Jul 26 06:45:42 PM PDT 24
Finished Jul 26 06:45:45 PM PDT 24
Peak memory 199496 kb
Host smart-42884df0-52f5-42c4-b9b1-9902b1ce4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075952007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3075952007
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2197782702
Short name T636
Test name
Test status
Simulation time 9154950486 ps
CPU time 13.23 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:45:54 PM PDT 24
Peak memory 200036 kb
Host smart-dc1d71e8-1504-48be-9760-af975c8aa573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197782702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2197782702
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4045464241
Short name T671
Test name
Test status
Simulation time 15681050905 ps
CPU time 166.12 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:48:25 PM PDT 24
Peak memory 200236 kb
Host smart-90b5f37e-0661-4609-8563-7d9bba106f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045464241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4045464241
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1034719056
Short name T812
Test name
Test status
Simulation time 5525780542 ps
CPU time 47.39 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:46:29 PM PDT 24
Peak memory 199276 kb
Host smart-2e94221d-673d-44e9-af85-d551ef556174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034719056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1034719056
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4079454278
Short name T643
Test name
Test status
Simulation time 99326612156 ps
CPU time 26.77 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:46:04 PM PDT 24
Peak memory 200112 kb
Host smart-fbda9ceb-71f3-4902-8c4d-6a5dcd99ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079454278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4079454278
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3826806608
Short name T320
Test name
Test status
Simulation time 35087436606 ps
CPU time 12.29 seconds
Started Jul 26 06:45:37 PM PDT 24
Finished Jul 26 06:45:49 PM PDT 24
Peak memory 196272 kb
Host smart-91396081-4e60-4a16-99d7-66660d9b81f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826806608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3826806608
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.143465367
Short name T1020
Test name
Test status
Simulation time 487156323 ps
CPU time 2.37 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:45:43 PM PDT 24
Peak memory 198576 kb
Host smart-39a56d15-def7-432d-975c-044f4f851955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143465367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.143465367
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2117555088
Short name T805
Test name
Test status
Simulation time 175218889806 ps
CPU time 54.48 seconds
Started Jul 26 06:45:42 PM PDT 24
Finished Jul 26 06:46:36 PM PDT 24
Peak memory 200192 kb
Host smart-63adda9a-9555-4ec4-b724-b53ffb03d14c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117555088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2117555088
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.510728342
Short name T608
Test name
Test status
Simulation time 125835395344 ps
CPU time 356.09 seconds
Started Jul 26 06:45:44 PM PDT 24
Finished Jul 26 06:51:40 PM PDT 24
Peak memory 224984 kb
Host smart-dc0a17e1-7f63-416d-a78d-de6708d569e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510728342 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.510728342
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.526492138
Short name T442
Test name
Test status
Simulation time 771446193 ps
CPU time 3.47 seconds
Started Jul 26 06:45:42 PM PDT 24
Finished Jul 26 06:45:46 PM PDT 24
Peak memory 199228 kb
Host smart-ebdcdb32-e0dd-43bc-a3a4-f1a93fedef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526492138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.526492138
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2417793428
Short name T1177
Test name
Test status
Simulation time 145887086227 ps
CPU time 27.98 seconds
Started Jul 26 06:45:40 PM PDT 24
Finished Jul 26 06:46:08 PM PDT 24
Peak memory 200128 kb
Host smart-d4580369-2207-4b48-ad6d-9d2757b40695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417793428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2417793428
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.846420264
Short name T1073
Test name
Test status
Simulation time 32244964 ps
CPU time 0.56 seconds
Started Jul 26 06:45:45 PM PDT 24
Finished Jul 26 06:45:46 PM PDT 24
Peak memory 195572 kb
Host smart-8684c8e7-1643-4e95-af76-360c20bbb9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846420264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.846420264
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.553113433
Short name T448
Test name
Test status
Simulation time 28206494697 ps
CPU time 55.86 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:46:37 PM PDT 24
Peak memory 200180 kb
Host smart-87a5c474-b7f4-4e45-8c38-885aa665d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553113433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.553113433
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3948400802
Short name T967
Test name
Test status
Simulation time 35712274531 ps
CPU time 13.49 seconds
Started Jul 26 06:45:39 PM PDT 24
Finished Jul 26 06:45:52 PM PDT 24
Peak memory 200064 kb
Host smart-9616d087-ba06-478d-80c9-7257d86b3cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948400802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3948400802
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3026404575
Short name T807
Test name
Test status
Simulation time 12583550180 ps
CPU time 19.25 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:46:01 PM PDT 24
Peak memory 200180 kb
Host smart-0ad9ad55-2aa6-4a8d-b7d4-b8bebc65fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026404575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3026404575
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3960676655
Short name T468
Test name
Test status
Simulation time 155670774035 ps
CPU time 53.68 seconds
Started Jul 26 06:45:46 PM PDT 24
Finished Jul 26 06:46:39 PM PDT 24
Peak memory 197956 kb
Host smart-649f4ac9-e947-489a-b8f5-2ef3ea61403b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960676655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3960676655
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1985708516
Short name T544
Test name
Test status
Simulation time 60037588379 ps
CPU time 123.03 seconds
Started Jul 26 06:45:46 PM PDT 24
Finished Jul 26 06:47:49 PM PDT 24
Peak memory 200200 kb
Host smart-4695db25-6c02-42f5-a4a5-d29f3515d505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985708516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1985708516
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3900170067
Short name T968
Test name
Test status
Simulation time 8638790793 ps
CPU time 4.08 seconds
Started Jul 26 06:45:47 PM PDT 24
Finished Jul 26 06:45:51 PM PDT 24
Peak memory 200188 kb
Host smart-676b8cd1-e657-4c13-95fa-c6b2c5472870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900170067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3900170067
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.832863180
Short name T485
Test name
Test status
Simulation time 36789994783 ps
CPU time 55.56 seconds
Started Jul 26 06:45:45 PM PDT 24
Finished Jul 26 06:46:41 PM PDT 24
Peak memory 199636 kb
Host smart-6569c3c9-d2f9-4815-aa77-d9da525a38e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832863180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.832863180
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1529300439
Short name T1131
Test name
Test status
Simulation time 20160753375 ps
CPU time 123.19 seconds
Started Jul 26 06:45:45 PM PDT 24
Finished Jul 26 06:47:48 PM PDT 24
Peak memory 200088 kb
Host smart-03b02bfc-d47e-4b19-83f2-ec46146d4aa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529300439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1529300439
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4102757816
Short name T668
Test name
Test status
Simulation time 3919615029 ps
CPU time 32.06 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:46:13 PM PDT 24
Peak memory 198228 kb
Host smart-fb830af8-d658-4f7e-94af-50091b4f542b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102757816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4102757816
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.345448859
Short name T562
Test name
Test status
Simulation time 354026306750 ps
CPU time 59.6 seconds
Started Jul 26 06:45:43 PM PDT 24
Finished Jul 26 06:46:43 PM PDT 24
Peak memory 200212 kb
Host smart-07097780-6bab-4e19-a4af-15238d01380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345448859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.345448859
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2494631713
Short name T1038
Test name
Test status
Simulation time 33888646055 ps
CPU time 23.33 seconds
Started Jul 26 06:45:45 PM PDT 24
Finished Jul 26 06:46:09 PM PDT 24
Peak memory 196420 kb
Host smart-1d9c7107-0e5f-4731-8510-17a7f81896f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494631713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2494631713
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1397563805
Short name T422
Test name
Test status
Simulation time 5711685144 ps
CPU time 11.5 seconds
Started Jul 26 06:45:41 PM PDT 24
Finished Jul 26 06:45:53 PM PDT 24
Peak memory 199996 kb
Host smart-8d60ec31-0c94-4cf4-bef8-0230008dc3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397563805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1397563805
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.705676771
Short name T169
Test name
Test status
Simulation time 121769922760 ps
CPU time 506.27 seconds
Started Jul 26 06:45:43 PM PDT 24
Finished Jul 26 06:54:10 PM PDT 24
Peak memory 216700 kb
Host smart-7d7193c5-3b3c-4fe8-aac1-1080813163dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705676771 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.705676771
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4003134544
Short name T1127
Test name
Test status
Simulation time 2439102805 ps
CPU time 2.19 seconds
Started Jul 26 06:45:44 PM PDT 24
Finished Jul 26 06:45:46 PM PDT 24
Peak memory 200184 kb
Host smart-c38260b0-c000-4190-a372-ea488e0ea966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003134544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4003134544
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2304213629
Short name T1155
Test name
Test status
Simulation time 8093898873 ps
CPU time 12.49 seconds
Started Jul 26 06:45:42 PM PDT 24
Finished Jul 26 06:45:54 PM PDT 24
Peak memory 199968 kb
Host smart-96e69693-4a0a-4db2-90ef-cbdd9e1c4800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304213629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2304213629
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.237906212
Short name T1166
Test name
Test status
Simulation time 13758826 ps
CPU time 0.57 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:39:35 PM PDT 24
Peak memory 195504 kb
Host smart-bfbce8bd-71a0-4c62-9d10-6b468fa5c722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237906212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.237906212
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.872533525
Short name T122
Test name
Test status
Simulation time 67047597840 ps
CPU time 27.31 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:39:57 PM PDT 24
Peak memory 199968 kb
Host smart-7a380486-a968-404a-9f55-1745bd26bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872533525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.872533525
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2164990849
Short name T1076
Test name
Test status
Simulation time 30013062638 ps
CPU time 74.25 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:40:44 PM PDT 24
Peak memory 200108 kb
Host smart-927a48f9-afdf-4fc2-bf94-fbfef47efe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164990849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2164990849
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3068156050
Short name T545
Test name
Test status
Simulation time 54217933773 ps
CPU time 18.94 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:39:49 PM PDT 24
Peak memory 199236 kb
Host smart-4ccbec9d-246e-4fd7-942f-a225b8fed428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068156050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3068156050
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1126697790
Short name T1092
Test name
Test status
Simulation time 42629315436 ps
CPU time 17.99 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:39:50 PM PDT 24
Peak memory 200208 kb
Host smart-e11a1e71-3c0f-471a-82ce-f045756e2b22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126697790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1126697790
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3663683129
Short name T893
Test name
Test status
Simulation time 137938708413 ps
CPU time 285.71 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:44:14 PM PDT 24
Peak memory 200140 kb
Host smart-f33df86d-cf1d-481b-b5c9-71700cdd72dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663683129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3663683129
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.987077535
Short name T352
Test name
Test status
Simulation time 2386531721 ps
CPU time 2.68 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:39:35 PM PDT 24
Peak memory 197620 kb
Host smart-831c8b4e-810f-4593-acfd-ada23064ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987077535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.987077535
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.916359998
Short name T1065
Test name
Test status
Simulation time 69668277097 ps
CPU time 39.06 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:40:08 PM PDT 24
Peak memory 200196 kb
Host smart-99605976-f2f7-4a05-87ab-8510c88e93f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916359998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.916359998
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2136397667
Short name T1088
Test name
Test status
Simulation time 11039469204 ps
CPU time 665.98 seconds
Started Jul 26 06:39:30 PM PDT 24
Finished Jul 26 06:50:36 PM PDT 24
Peak memory 200112 kb
Host smart-f1f90997-02f2-4753-9f13-cbde55f7486a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136397667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2136397667
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1309412274
Short name T488
Test name
Test status
Simulation time 4297307400 ps
CPU time 27.23 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:39:55 PM PDT 24
Peak memory 198900 kb
Host smart-6a239837-12ac-4ff6-9b20-bc8950092a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309412274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1309412274
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1845151827
Short name T808
Test name
Test status
Simulation time 30593531956 ps
CPU time 44.22 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:40:18 PM PDT 24
Peak memory 200200 kb
Host smart-c374b462-dbe4-49f3-9e50-812acf8f2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845151827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1845151827
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4004662229
Short name T1098
Test name
Test status
Simulation time 5090891361 ps
CPU time 8.47 seconds
Started Jul 26 06:39:29 PM PDT 24
Finished Jul 26 06:39:38 PM PDT 24
Peak memory 196200 kb
Host smart-76e35d35-7cf0-405d-a645-5b1626232b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004662229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4004662229
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2951455617
Short name T296
Test name
Test status
Simulation time 489928482 ps
CPU time 2.53 seconds
Started Jul 26 06:39:27 PM PDT 24
Finished Jul 26 06:39:30 PM PDT 24
Peak memory 198876 kb
Host smart-b7c3c14f-7415-49b9-aadf-ae79c13a3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951455617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2951455617
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.4078169971
Short name T537
Test name
Test status
Simulation time 441808079840 ps
CPU time 169.62 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:42:24 PM PDT 24
Peak memory 200204 kb
Host smart-c2788324-7a32-463f-9949-34122dd0532a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078169971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4078169971
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1812182023
Short name T1110
Test name
Test status
Simulation time 6523484194 ps
CPU time 18.49 seconds
Started Jul 26 06:39:28 PM PDT 24
Finished Jul 26 06:39:46 PM PDT 24
Peak memory 199524 kb
Host smart-6f3ccfe0-0268-4734-a8c5-f6d8a34667a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812182023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1812182023
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.854533784
Short name T579
Test name
Test status
Simulation time 144992920353 ps
CPU time 19.03 seconds
Started Jul 26 06:39:32 PM PDT 24
Finished Jul 26 06:39:51 PM PDT 24
Peak memory 200168 kb
Host smart-a1e1ea3d-4790-4dd2-b35c-48efa95ff76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854533784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.854533784
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4132962462
Short name T737
Test name
Test status
Simulation time 35726821603 ps
CPU time 21.29 seconds
Started Jul 26 06:45:54 PM PDT 24
Finished Jul 26 06:46:16 PM PDT 24
Peak memory 200184 kb
Host smart-bcb9eecb-093a-46d1-baad-cfbf9d4e4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132962462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4132962462
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3936580942
Short name T1122
Test name
Test status
Simulation time 50707446519 ps
CPU time 565.82 seconds
Started Jul 26 06:45:51 PM PDT 24
Finished Jul 26 06:55:17 PM PDT 24
Peak memory 216728 kb
Host smart-79e0054c-49c6-47df-ab93-cf70eaf4c3d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936580942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3936580942
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1393911862
Short name T323
Test name
Test status
Simulation time 50582485018 ps
CPU time 97.67 seconds
Started Jul 26 06:45:53 PM PDT 24
Finished Jul 26 06:47:31 PM PDT 24
Peak memory 200108 kb
Host smart-acad3189-2874-4295-9159-d01ec5563e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393911862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1393911862
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.269727630
Short name T1035
Test name
Test status
Simulation time 29879158791 ps
CPU time 292.99 seconds
Started Jul 26 06:45:51 PM PDT 24
Finished Jul 26 06:50:44 PM PDT 24
Peak memory 215964 kb
Host smart-6a5479bd-450d-4b39-a39f-c7343507e227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269727630 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.269727630
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3708760997
Short name T314
Test name
Test status
Simulation time 40055355173 ps
CPU time 32.21 seconds
Started Jul 26 06:45:51 PM PDT 24
Finished Jul 26 06:46:23 PM PDT 24
Peak memory 200024 kb
Host smart-e91c4bb8-6617-4754-be40-226f3c1df190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708760997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3708760997
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.635379513
Short name T165
Test name
Test status
Simulation time 30627760916 ps
CPU time 12.3 seconds
Started Jul 26 06:45:52 PM PDT 24
Finished Jul 26 06:46:04 PM PDT 24
Peak memory 200108 kb
Host smart-7c9d3593-a059-44db-ba05-de8529179089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635379513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.635379513
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.671720079
Short name T168
Test name
Test status
Simulation time 620240492429 ps
CPU time 907.92 seconds
Started Jul 26 06:45:52 PM PDT 24
Finished Jul 26 07:01:00 PM PDT 24
Peak memory 224980 kb
Host smart-c8f13b2a-f04a-4d8c-9384-11fe7fb8fefd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671720079 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.671720079
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1042772820
Short name T763
Test name
Test status
Simulation time 16457056193 ps
CPU time 216.29 seconds
Started Jul 26 06:45:53 PM PDT 24
Finished Jul 26 06:49:30 PM PDT 24
Peak memory 210096 kb
Host smart-d0544263-77d2-46ef-9a4a-7d5bf6315da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042772820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1042772820
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1934995637
Short name T260
Test name
Test status
Simulation time 71826854130 ps
CPU time 33.07 seconds
Started Jul 26 06:45:53 PM PDT 24
Finished Jul 26 06:46:26 PM PDT 24
Peak memory 200180 kb
Host smart-40099424-8dc0-4488-9a32-c346a15bf820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934995637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1934995637
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.613327285
Short name T742
Test name
Test status
Simulation time 79534014685 ps
CPU time 349.24 seconds
Started Jul 26 06:45:52 PM PDT 24
Finished Jul 26 06:51:41 PM PDT 24
Peak memory 216836 kb
Host smart-ddfb6041-ca4b-472f-a3ff-dad0a38aa828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613327285 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.613327285
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.563426539
Short name T224
Test name
Test status
Simulation time 30217995265 ps
CPU time 10.8 seconds
Started Jul 26 06:45:52 PM PDT 24
Finished Jul 26 06:46:03 PM PDT 24
Peak memory 200180 kb
Host smart-0b8292d9-aaa9-4d59-98f4-41890825918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563426539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.563426539
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.578552816
Short name T1121
Test name
Test status
Simulation time 24484799573 ps
CPU time 212.46 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 06:49:34 PM PDT 24
Peak memory 216796 kb
Host smart-d9335b56-ccc0-490a-99b3-ea2b3bf9e90f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578552816 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.578552816
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.601499445
Short name T233
Test name
Test status
Simulation time 19862124532 ps
CPU time 19.07 seconds
Started Jul 26 06:46:00 PM PDT 24
Finished Jul 26 06:46:19 PM PDT 24
Peak memory 200180 kb
Host smart-bed8c124-5cde-4bd1-b2e7-80677f022b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601499445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.601499445
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.476358713
Short name T592
Test name
Test status
Simulation time 35238578385 ps
CPU time 28.99 seconds
Started Jul 26 06:46:00 PM PDT 24
Finished Jul 26 06:46:29 PM PDT 24
Peak memory 200112 kb
Host smart-a4b8c894-5f84-4438-b899-47b3dabcb2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476358713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.476358713
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3047503871
Short name T334
Test name
Test status
Simulation time 74571495411 ps
CPU time 619.88 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 06:56:22 PM PDT 24
Peak memory 228132 kb
Host smart-249dd706-9f1a-4ece-86cd-33bfa0191fd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047503871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3047503871
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3085278860
Short name T1101
Test name
Test status
Simulation time 62372214027 ps
CPU time 24.69 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 06:46:25 PM PDT 24
Peak memory 199976 kb
Host smart-ea18d252-12c9-4049-a582-44a98712dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085278860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3085278860
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4050274029
Short name T120
Test name
Test status
Simulation time 43735506939 ps
CPU time 295.18 seconds
Started Jul 26 06:46:00 PM PDT 24
Finished Jul 26 06:50:55 PM PDT 24
Peak memory 216924 kb
Host smart-3c9d9a6c-200b-417f-8508-d28e9dbeb69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050274029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4050274029
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2960333251
Short name T936
Test name
Test status
Simulation time 13570851 ps
CPU time 0.54 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:39:34 PM PDT 24
Peak memory 195560 kb
Host smart-e3fcb984-6395-4288-a577-332f8b19664f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960333251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2960333251
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.791398294
Short name T770
Test name
Test status
Simulation time 102677421389 ps
CPU time 139.67 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:41:54 PM PDT 24
Peak memory 200132 kb
Host smart-5206691f-ce50-439a-b778-70e24c959da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791398294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.791398294
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.556023477
Short name T299
Test name
Test status
Simulation time 94787254780 ps
CPU time 187.34 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:42:43 PM PDT 24
Peak memory 200180 kb
Host smart-53df1dcb-9eca-4978-ba13-25458647b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556023477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.556023477
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2269608932
Short name T215
Test name
Test status
Simulation time 132779523216 ps
CPU time 165.49 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:42:20 PM PDT 24
Peak memory 200068 kb
Host smart-ab98e1e6-afcd-4198-9622-d5730ad520e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269608932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2269608932
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.322492320
Short name T13
Test name
Test status
Simulation time 107169022670 ps
CPU time 279.16 seconds
Started Jul 26 06:39:38 PM PDT 24
Finished Jul 26 06:44:17 PM PDT 24
Peak memory 200208 kb
Host smart-c761bf9f-cc1a-4ca7-beba-6835dab1cb6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322492320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.322492320
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.12342438
Short name T471
Test name
Test status
Simulation time 119485477187 ps
CPU time 752.08 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:52:07 PM PDT 24
Peak memory 200200 kb
Host smart-5780c655-4750-46cf-8a2b-5c85712ea19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12342438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.12342438
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.883048560
Short name T1062
Test name
Test status
Simulation time 1400475803 ps
CPU time 1.44 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:39:36 PM PDT 24
Peak memory 198616 kb
Host smart-6e13ded4-47aa-4272-ba2f-82005a4a8104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883048560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.883048560
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1168447026
Short name T842
Test name
Test status
Simulation time 14871349234 ps
CPU time 23.38 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:39:59 PM PDT 24
Peak memory 198768 kb
Host smart-5524c315-ed9c-457b-89c0-8cd2d70dce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168447026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1168447026
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4119249386
Short name T620
Test name
Test status
Simulation time 15994979254 ps
CPU time 808.12 seconds
Started Jul 26 06:39:36 PM PDT 24
Finished Jul 26 06:53:04 PM PDT 24
Peak memory 200124 kb
Host smart-21e154e0-c3fd-421c-baf7-8a33f20a0d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119249386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4119249386
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3418284025
Short name T438
Test name
Test status
Simulation time 6647774869 ps
CPU time 15.44 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:39:50 PM PDT 24
Peak memory 198808 kb
Host smart-6060b2a6-b93a-43c0-bae8-a647f35de4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418284025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3418284025
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.936723094
Short name T1047
Test name
Test status
Simulation time 171366827488 ps
CPU time 58.61 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:40:34 PM PDT 24
Peak memory 200180 kb
Host smart-8006fb96-5fa5-498e-9648-cd4bc1dfdd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936723094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.936723094
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3200989794
Short name T315
Test name
Test status
Simulation time 1609587573 ps
CPU time 3.07 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:39:38 PM PDT 24
Peak memory 195664 kb
Host smart-c657bbba-2ebd-48fd-a266-1d6b9a1c08c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200989794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3200989794
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2956018672
Short name T781
Test name
Test status
Simulation time 5545669956 ps
CPU time 17.89 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:39:53 PM PDT 24
Peak memory 199940 kb
Host smart-8c1c7d93-2928-4281-a616-8369b749febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956018672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2956018672
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2333746346
Short name T655
Test name
Test status
Simulation time 204470067256 ps
CPU time 36.78 seconds
Started Jul 26 06:39:37 PM PDT 24
Finished Jul 26 06:40:14 PM PDT 24
Peak memory 200316 kb
Host smart-3f0655a9-5000-418d-a173-a25b15e302b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333746346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2333746346
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1816362827
Short name T222
Test name
Test status
Simulation time 128891620713 ps
CPU time 319.67 seconds
Started Jul 26 06:39:38 PM PDT 24
Finished Jul 26 06:44:57 PM PDT 24
Peak memory 215780 kb
Host smart-fa8c333f-4b9e-48c2-9070-39381bca27e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816362827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1816362827
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3101451754
Short name T111
Test name
Test status
Simulation time 6551542670 ps
CPU time 22.56 seconds
Started Jul 26 06:39:34 PM PDT 24
Finished Jul 26 06:39:57 PM PDT 24
Peak memory 200160 kb
Host smart-0a9bbced-61c8-44dd-b119-fb00a900e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101451754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3101451754
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.88155702
Short name T269
Test name
Test status
Simulation time 74683814936 ps
CPU time 66.97 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:40:42 PM PDT 24
Peak memory 200172 kb
Host smart-03bfc62c-d8c2-48d3-90de-49bce44a2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88155702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.88155702
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.416627523
Short name T484
Test name
Test status
Simulation time 22250983836 ps
CPU time 30.4 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 06:46:32 PM PDT 24
Peak memory 200176 kb
Host smart-2f308acd-7c73-43c0-a87c-3861a2fb247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416627523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.416627523
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2234077144
Short name T794
Test name
Test status
Simulation time 27126221196 ps
CPU time 166.38 seconds
Started Jul 26 06:45:59 PM PDT 24
Finished Jul 26 06:48:46 PM PDT 24
Peak memory 216212 kb
Host smart-97ea5c5e-ec1e-44bc-acd6-da87e44c5231
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234077144 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2234077144
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.768180805
Short name T282
Test name
Test status
Simulation time 61255996014 ps
CPU time 12.38 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 06:46:15 PM PDT 24
Peak memory 200184 kb
Host smart-8be1e226-0eaa-4e8b-a5ee-6a5c55d5dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768180805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.768180805
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.4053436241
Short name T659
Test name
Test status
Simulation time 72515426605 ps
CPU time 2089.19 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 07:20:51 PM PDT 24
Peak memory 216652 kb
Host smart-05a67cbd-1385-49e2-8519-27bc1b2cb7ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053436241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.4053436241
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.617128127
Short name T813
Test name
Test status
Simulation time 54424990837 ps
CPU time 22.24 seconds
Started Jul 26 06:46:00 PM PDT 24
Finished Jul 26 06:46:22 PM PDT 24
Peak memory 200196 kb
Host smart-22825970-2ba4-47a4-8ac9-0225dd59f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617128127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.617128127
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3635542652
Short name T263
Test name
Test status
Simulation time 160073363046 ps
CPU time 964.05 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 07:02:05 PM PDT 24
Peak memory 225384 kb
Host smart-1562b934-dea2-42b9-8a34-d83234786d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635542652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3635542652
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1297788301
Short name T859
Test name
Test status
Simulation time 78768162297 ps
CPU time 120.14 seconds
Started Jul 26 06:46:03 PM PDT 24
Finished Jul 26 06:48:03 PM PDT 24
Peak memory 200132 kb
Host smart-05638c34-d839-4e55-aff7-4e174befd179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297788301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1297788301
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3951850136
Short name T927
Test name
Test status
Simulation time 242085667586 ps
CPU time 693.35 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 06:57:35 PM PDT 24
Peak memory 225032 kb
Host smart-bb202153-6a07-4885-a024-2d17b1d9fe41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951850136 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3951850136
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.687426775
Short name T673
Test name
Test status
Simulation time 78850378422 ps
CPU time 593.72 seconds
Started Jul 26 06:46:03 PM PDT 24
Finished Jul 26 06:55:56 PM PDT 24
Peak memory 224900 kb
Host smart-3e3fd6a3-a055-4608-a58a-b2b733d60374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687426775 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.687426775
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.582877300
Short name T152
Test name
Test status
Simulation time 109702024967 ps
CPU time 166.5 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 06:48:48 PM PDT 24
Peak memory 200136 kb
Host smart-4e58e65d-ba74-4aa3-ad1b-9fb88d854c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582877300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.582877300
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1635623386
Short name T809
Test name
Test status
Simulation time 56933241573 ps
CPU time 41.9 seconds
Started Jul 26 06:46:01 PM PDT 24
Finished Jul 26 06:46:43 PM PDT 24
Peak memory 199948 kb
Host smart-8dc26b63-cff8-4487-af28-c66d0d661d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635623386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1635623386
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1425103059
Short name T35
Test name
Test status
Simulation time 88521001574 ps
CPU time 535.59 seconds
Started Jul 26 06:46:02 PM PDT 24
Finished Jul 26 06:54:58 PM PDT 24
Peak memory 213580 kb
Host smart-09d615bd-9af0-4607-b4f3-2290a6108e5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425103059 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1425103059
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.875793785
Short name T210
Test name
Test status
Simulation time 210547487021 ps
CPU time 93.86 seconds
Started Jul 26 06:46:00 PM PDT 24
Finished Jul 26 06:47:34 PM PDT 24
Peak memory 200088 kb
Host smart-66a050a0-cfe4-412a-bd33-5418d9fc6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875793785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.875793785
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1556198083
Short name T904
Test name
Test status
Simulation time 75501114822 ps
CPU time 446.77 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:53:38 PM PDT 24
Peak memory 227408 kb
Host smart-e68d956f-846d-400b-bd0b-1433fed64785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556198083 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1556198083
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2224558289
Short name T252
Test name
Test status
Simulation time 129437491813 ps
CPU time 179.32 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:49:11 PM PDT 24
Peak memory 200060 kb
Host smart-0f797bd9-64ef-4238-aa32-af555d9a76b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224558289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2224558289
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1912831237
Short name T240
Test name
Test status
Simulation time 101923959611 ps
CPU time 519.3 seconds
Started Jul 26 06:46:10 PM PDT 24
Finished Jul 26 06:54:50 PM PDT 24
Peak memory 225012 kb
Host smart-05ab2651-4058-46f9-a416-b7cac799c04e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912831237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1912831237
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4239655360
Short name T721
Test name
Test status
Simulation time 120943545233 ps
CPU time 68.21 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:47:20 PM PDT 24
Peak memory 200232 kb
Host smart-890c03f1-67f0-43cd-a2bb-74aaf02d0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239655360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4239655360
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3586918019
Short name T724
Test name
Test status
Simulation time 24526947240 ps
CPU time 272.57 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:50:43 PM PDT 24
Peak memory 216924 kb
Host smart-34eb9fc0-3e2b-4c36-844f-3f7e0fa630d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586918019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3586918019
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.912403094
Short name T1168
Test name
Test status
Simulation time 34789234 ps
CPU time 0.56 seconds
Started Jul 26 06:39:40 PM PDT 24
Finished Jul 26 06:39:41 PM PDT 24
Peak memory 195552 kb
Host smart-7a2a6a2a-98c1-479a-b9a3-6f61e9fda841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912403094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.912403094
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3368751105
Short name T2
Test name
Test status
Simulation time 9942856033 ps
CPU time 4 seconds
Started Jul 26 06:39:33 PM PDT 24
Finished Jul 26 06:39:37 PM PDT 24
Peak memory 200068 kb
Host smart-64c2a12d-fcd2-40c7-acea-82ed5381ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368751105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3368751105
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2173199068
Short name T309
Test name
Test status
Simulation time 22184604126 ps
CPU time 36.66 seconds
Started Jul 26 06:39:43 PM PDT 24
Finished Jul 26 06:40:20 PM PDT 24
Peak memory 200160 kb
Host smart-5d6fa0c1-0a33-445d-a45a-d23b3d7008b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173199068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2173199068
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2322005823
Short name T1086
Test name
Test status
Simulation time 104521867520 ps
CPU time 54.29 seconds
Started Jul 26 06:39:39 PM PDT 24
Finished Jul 26 06:40:34 PM PDT 24
Peak memory 200144 kb
Host smart-b76a3c10-b977-4328-a6a1-1cd19d5c8df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322005823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2322005823
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.373179057
Short name T575
Test name
Test status
Simulation time 13668146841 ps
CPU time 10.05 seconds
Started Jul 26 06:39:42 PM PDT 24
Finished Jul 26 06:39:53 PM PDT 24
Peak memory 197672 kb
Host smart-24a3d5ec-3621-4cb9-aa78-f5138054ab43
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373179057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.373179057
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1265445210
Short name T787
Test name
Test status
Simulation time 92495893358 ps
CPU time 133.66 seconds
Started Jul 26 06:39:41 PM PDT 24
Finished Jul 26 06:41:54 PM PDT 24
Peak memory 200160 kb
Host smart-f46dc0c2-a76e-4aa9-8322-6db1facef06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265445210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1265445210
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1746247649
Short name T367
Test name
Test status
Simulation time 2367539319 ps
CPU time 5.51 seconds
Started Jul 26 06:39:42 PM PDT 24
Finished Jul 26 06:39:48 PM PDT 24
Peak memory 199036 kb
Host smart-58973e83-5874-4ade-8006-3c5582546ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746247649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1746247649
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4280058941
Short name T84
Test name
Test status
Simulation time 25680874421 ps
CPU time 11.37 seconds
Started Jul 26 06:39:41 PM PDT 24
Finished Jul 26 06:39:52 PM PDT 24
Peak memory 198476 kb
Host smart-9f4657ea-69f3-42d5-a30b-ca327ee5c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280058941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4280058941
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1270784002
Short name T554
Test name
Test status
Simulation time 18853982089 ps
CPU time 870.35 seconds
Started Jul 26 06:39:43 PM PDT 24
Finished Jul 26 06:54:14 PM PDT 24
Peak memory 200116 kb
Host smart-97847950-754f-4aff-b936-fa1f8b203067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270784002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1270784002
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3067171718
Short name T80
Test name
Test status
Simulation time 3126497442 ps
CPU time 17.58 seconds
Started Jul 26 06:39:40 PM PDT 24
Finished Jul 26 06:39:58 PM PDT 24
Peak memory 200144 kb
Host smart-e23ea5aa-a6bf-449c-a2b5-e76248bec99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067171718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3067171718
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2333890275
Short name T824
Test name
Test status
Simulation time 12988894405 ps
CPU time 20.49 seconds
Started Jul 26 06:39:42 PM PDT 24
Finished Jul 26 06:40:03 PM PDT 24
Peak memory 200152 kb
Host smart-24b033f1-c2b7-404f-9775-ac3d00bf8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333890275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2333890275
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3497476444
Short name T1126
Test name
Test status
Simulation time 4659863937 ps
CPU time 2.36 seconds
Started Jul 26 06:39:43 PM PDT 24
Finished Jul 26 06:39:46 PM PDT 24
Peak memory 196668 kb
Host smart-9bb99e84-8a34-4af0-86ea-f3ccaff2d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497476444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3497476444
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3527834834
Short name T564
Test name
Test status
Simulation time 709865455 ps
CPU time 3.62 seconds
Started Jul 26 06:39:38 PM PDT 24
Finished Jul 26 06:39:41 PM PDT 24
Peak memory 198432 kb
Host smart-cb1d698f-3a04-457c-81c2-281a67f92dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527834834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3527834834
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2965647560
Short name T933
Test name
Test status
Simulation time 192525360112 ps
CPU time 358.84 seconds
Started Jul 26 06:39:40 PM PDT 24
Finished Jul 26 06:45:39 PM PDT 24
Peak memory 200188 kb
Host smart-95df6a74-1259-4b30-959f-d3bc62b48414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965647560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2965647560
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2115517334
Short name T57
Test name
Test status
Simulation time 166492913263 ps
CPU time 517.81 seconds
Started Jul 26 06:39:44 PM PDT 24
Finished Jul 26 06:48:21 PM PDT 24
Peak memory 216732 kb
Host smart-991301ca-5ebb-4380-bbe0-d0578122c4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115517334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2115517334
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3204600932
Short name T823
Test name
Test status
Simulation time 481811167 ps
CPU time 2.08 seconds
Started Jul 26 06:39:40 PM PDT 24
Finished Jul 26 06:39:42 PM PDT 24
Peak memory 199928 kb
Host smart-278f9ba1-9a4f-407c-9a40-7806b4fc33a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204600932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3204600932
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2363132356
Short name T342
Test name
Test status
Simulation time 91836933471 ps
CPU time 23.14 seconds
Started Jul 26 06:39:35 PM PDT 24
Finished Jul 26 06:39:58 PM PDT 24
Peak memory 200084 kb
Host smart-f94c0aad-acdb-4317-9062-3f1630def96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363132356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2363132356
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1058589612
Short name T614
Test name
Test status
Simulation time 32225620881 ps
CPU time 6.71 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:46:18 PM PDT 24
Peak memory 199136 kb
Host smart-e41fa896-2458-4783-9ee2-324dbc4401ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058589612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1058589612
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2750414909
Short name T1064
Test name
Test status
Simulation time 97482432550 ps
CPU time 621.52 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:56:33 PM PDT 24
Peak memory 229592 kb
Host smart-ee3b5c96-58b9-4ea9-b084-bcbfad651226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750414909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2750414909
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1652490752
Short name T583
Test name
Test status
Simulation time 51319187550 ps
CPU time 82.8 seconds
Started Jul 26 06:46:10 PM PDT 24
Finished Jul 26 06:47:33 PM PDT 24
Peak memory 200160 kb
Host smart-1934b4c7-b7da-4aa9-a0a2-b7907f282b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652490752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1652490752
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2633952201
Short name T242
Test name
Test status
Simulation time 280877307179 ps
CPU time 109.52 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:48:02 PM PDT 24
Peak memory 200212 kb
Host smart-0695a2fc-13b8-481e-9ac5-20ad1a732315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633952201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2633952201
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.569666749
Short name T648
Test name
Test status
Simulation time 20502473110 ps
CPU time 244.6 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:50:17 PM PDT 24
Peak memory 208648 kb
Host smart-fc2976b0-40c9-4789-8786-336329877c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569666749 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.569666749
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3717386798
Short name T238
Test name
Test status
Simulation time 91369701481 ps
CPU time 202.34 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:49:34 PM PDT 24
Peak memory 200108 kb
Host smart-bb13842a-8492-4076-ba29-3018d9951490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717386798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3717386798
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1783991878
Short name T797
Test name
Test status
Simulation time 88706387772 ps
CPU time 500.38 seconds
Started Jul 26 06:46:10 PM PDT 24
Finished Jul 26 06:54:30 PM PDT 24
Peak memory 216860 kb
Host smart-dd7374d2-504f-45e6-85fa-d34d9b7fbebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783991878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1783991878
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3126103014
Short name T281
Test name
Test status
Simulation time 15618529550 ps
CPU time 23.09 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:46:34 PM PDT 24
Peak memory 200092 kb
Host smart-fbee425f-c463-45b4-968a-16b30c204e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126103014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3126103014
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3123258678
Short name T651
Test name
Test status
Simulation time 101600562561 ps
CPU time 285.59 seconds
Started Jul 26 06:46:13 PM PDT 24
Finished Jul 26 06:50:58 PM PDT 24
Peak memory 216732 kb
Host smart-2be28d9b-96c3-43f0-9836-b6a74fbed559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123258678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3123258678
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2794479983
Short name T123
Test name
Test status
Simulation time 57486739622 ps
CPU time 167.88 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:49:00 PM PDT 24
Peak memory 200164 kb
Host smart-519845d0-d191-432f-ac70-b0ed06c41381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794479983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2794479983
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2149551603
Short name T965
Test name
Test status
Simulation time 132002597243 ps
CPU time 454.96 seconds
Started Jul 26 06:46:12 PM PDT 24
Finished Jul 26 06:53:47 PM PDT 24
Peak memory 216780 kb
Host smart-eec896c2-294b-4e96-9d7a-78105ba07708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149551603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2149551603
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3566960019
Short name T313
Test name
Test status
Simulation time 144669126371 ps
CPU time 253.75 seconds
Started Jul 26 06:46:11 PM PDT 24
Finished Jul 26 06:50:25 PM PDT 24
Peak memory 199836 kb
Host smart-af29d61b-c9d5-455c-a19c-8312ea2f6cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566960019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3566960019
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.954759371
Short name T25
Test name
Test status
Simulation time 93304285527 ps
CPU time 137.1 seconds
Started Jul 26 06:46:14 PM PDT 24
Finished Jul 26 06:48:31 PM PDT 24
Peak memory 215728 kb
Host smart-8c9b65f6-44e9-4938-b5ea-49538bbf8e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954759371 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.954759371
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1602352232
Short name T1070
Test name
Test status
Simulation time 26808263279 ps
CPU time 43.73 seconds
Started Jul 26 06:46:13 PM PDT 24
Finished Jul 26 06:46:57 PM PDT 24
Peak memory 200212 kb
Host smart-da8fc4af-ec8e-4836-b539-f9aa60d7d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602352232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1602352232
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1119608824
Short name T587
Test name
Test status
Simulation time 79709839856 ps
CPU time 57.73 seconds
Started Jul 26 06:46:23 PM PDT 24
Finished Jul 26 06:47:20 PM PDT 24
Peak memory 200152 kb
Host smart-2fb84e64-4c07-458c-b00a-6b3744063a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119608824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1119608824
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2879588282
Short name T1066
Test name
Test status
Simulation time 238228734933 ps
CPU time 464.41 seconds
Started Jul 26 06:46:20 PM PDT 24
Finished Jul 26 06:54:04 PM PDT 24
Peak memory 225824 kb
Host smart-6d5d21ab-7fd1-4fea-929f-e20e8889c8e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879588282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2879588282
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3908942129
Short name T151
Test name
Test status
Simulation time 86428153512 ps
CPU time 152.67 seconds
Started Jul 26 06:46:21 PM PDT 24
Finished Jul 26 06:48:54 PM PDT 24
Peak memory 200100 kb
Host smart-dec0e035-11b3-4961-a9aa-e7757fb5d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908942129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3908942129
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1230595717
Short name T58
Test name
Test status
Simulation time 76072007685 ps
CPU time 706.55 seconds
Started Jul 26 06:46:20 PM PDT 24
Finished Jul 26 06:58:07 PM PDT 24
Peak memory 216720 kb
Host smart-e2a3d441-dd0a-4d59-9f31-fbe9cdd4ead1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230595717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1230595717
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1828587282
Short name T716
Test name
Test status
Simulation time 14748814 ps
CPU time 0.58 seconds
Started Jul 26 06:39:53 PM PDT 24
Finished Jul 26 06:39:54 PM PDT 24
Peak memory 195560 kb
Host smart-0d80df7a-ee2b-4165-b76d-68e942e36e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828587282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1828587282
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1665680862
Short name T274
Test name
Test status
Simulation time 83431597498 ps
CPU time 151.35 seconds
Started Jul 26 06:39:47 PM PDT 24
Finished Jul 26 06:42:19 PM PDT 24
Peak memory 200120 kb
Host smart-757ba51b-e74d-4bcb-9d7c-7b062140f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665680862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1665680862
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.803031052
Short name T825
Test name
Test status
Simulation time 43383303213 ps
CPU time 21 seconds
Started Jul 26 06:39:48 PM PDT 24
Finished Jul 26 06:40:10 PM PDT 24
Peak memory 200140 kb
Host smart-72aeee0e-8273-49ce-9494-273d24a1a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803031052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.803031052
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.222139249
Short name T1165
Test name
Test status
Simulation time 137967028729 ps
CPU time 112.37 seconds
Started Jul 26 06:39:49 PM PDT 24
Finished Jul 26 06:41:42 PM PDT 24
Peak memory 200080 kb
Host smart-42518652-1476-411a-8fe5-3d5a1a9a6d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222139249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.222139249
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4081740027
Short name T1157
Test name
Test status
Simulation time 191274296626 ps
CPU time 296.54 seconds
Started Jul 26 06:39:49 PM PDT 24
Finished Jul 26 06:44:46 PM PDT 24
Peak memory 198012 kb
Host smart-99ec3d58-ecba-4d7a-aa88-5776299b1b55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081740027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4081740027
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1017076217
Short name T524
Test name
Test status
Simulation time 73757505235 ps
CPU time 72.61 seconds
Started Jul 26 06:39:54 PM PDT 24
Finished Jul 26 06:41:07 PM PDT 24
Peak memory 200148 kb
Host smart-15dfa594-5537-424d-9391-82d090d16e37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017076217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1017076217
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3469601343
Short name T817
Test name
Test status
Simulation time 4762765164 ps
CPU time 5.08 seconds
Started Jul 26 06:39:55 PM PDT 24
Finished Jul 26 06:40:00 PM PDT 24
Peak memory 199996 kb
Host smart-b2bf353a-6b29-4c35-8714-fce5905087a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469601343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3469601343
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3879859750
Short name T300
Test name
Test status
Simulation time 193489467627 ps
CPU time 99.32 seconds
Started Jul 26 06:39:50 PM PDT 24
Finished Jul 26 06:41:30 PM PDT 24
Peak memory 200252 kb
Host smart-5a8d05ee-9e58-49f9-91bd-cd2fd286013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879859750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3879859750
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2196641040
Short name T310
Test name
Test status
Simulation time 10487163407 ps
CPU time 600.36 seconds
Started Jul 26 06:39:53 PM PDT 24
Finished Jul 26 06:49:54 PM PDT 24
Peak memory 200196 kb
Host smart-372a5e77-ca19-4b8a-9950-64f8ee400543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196641040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2196641040
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2922599604
Short name T815
Test name
Test status
Simulation time 4765696388 ps
CPU time 12.08 seconds
Started Jul 26 06:39:49 PM PDT 24
Finished Jul 26 06:40:01 PM PDT 24
Peak memory 199452 kb
Host smart-c301dbb5-9858-4ab4-93b6-8c06eadfce62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922599604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2922599604
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2856391489
Short name T336
Test name
Test status
Simulation time 200626851686 ps
CPU time 245.28 seconds
Started Jul 26 06:39:47 PM PDT 24
Finished Jul 26 06:43:52 PM PDT 24
Peak memory 200184 kb
Host smart-988a8188-ee08-4975-9139-6491ac5323c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856391489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2856391489
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3307546312
Short name T286
Test name
Test status
Simulation time 36941299904 ps
CPU time 52.21 seconds
Started Jul 26 06:39:47 PM PDT 24
Finished Jul 26 06:40:39 PM PDT 24
Peak memory 196340 kb
Host smart-b5549602-01cd-4311-a20c-be48ae156eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307546312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3307546312
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3105433798
Short name T621
Test name
Test status
Simulation time 866786225 ps
CPU time 1.88 seconds
Started Jul 26 06:39:43 PM PDT 24
Finished Jul 26 06:39:45 PM PDT 24
Peak memory 198976 kb
Host smart-aa4faddf-67b7-4b38-8ffb-5d9fdc849cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105433798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3105433798
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3035958229
Short name T1009
Test name
Test status
Simulation time 348457116821 ps
CPU time 939.29 seconds
Started Jul 26 06:39:54 PM PDT 24
Finished Jul 26 06:55:34 PM PDT 24
Peak memory 216604 kb
Host smart-c791772b-ac98-4e73-8a27-dc4b5af13918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035958229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3035958229
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1279700790
Short name T39
Test name
Test status
Simulation time 50330455353 ps
CPU time 324.12 seconds
Started Jul 26 06:39:55 PM PDT 24
Finished Jul 26 06:45:20 PM PDT 24
Peak memory 213352 kb
Host smart-ac2817c3-914b-473e-bf5d-f043f38cd400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279700790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1279700790
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2773070226
Short name T70
Test name
Test status
Simulation time 888958460 ps
CPU time 1.31 seconds
Started Jul 26 06:39:51 PM PDT 24
Finished Jul 26 06:39:52 PM PDT 24
Peak memory 198444 kb
Host smart-fb979e18-fc40-4985-8488-39212dc214b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773070226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2773070226
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1895469594
Short name T695
Test name
Test status
Simulation time 107495376690 ps
CPU time 37.67 seconds
Started Jul 26 06:39:41 PM PDT 24
Finished Jul 26 06:40:19 PM PDT 24
Peak memory 200212 kb
Host smart-33bde313-269f-4eb1-bc5d-0fd59f306506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895469594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1895469594
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4000521776
Short name T138
Test name
Test status
Simulation time 27586004202 ps
CPU time 16.83 seconds
Started Jul 26 06:46:20 PM PDT 24
Finished Jul 26 06:46:37 PM PDT 24
Peak memory 200188 kb
Host smart-33b634c2-6f78-4363-9951-3d346274f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000521776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4000521776
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2090072552
Short name T119
Test name
Test status
Simulation time 166381121598 ps
CPU time 237.05 seconds
Started Jul 26 06:46:23 PM PDT 24
Finished Jul 26 06:50:20 PM PDT 24
Peak memory 216816 kb
Host smart-b593ef7f-11ed-42d9-acd8-0e265c2e61f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090072552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2090072552
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.919241579
Short name T483
Test name
Test status
Simulation time 83933055384 ps
CPU time 77.01 seconds
Started Jul 26 06:46:19 PM PDT 24
Finished Jul 26 06:47:36 PM PDT 24
Peak memory 200180 kb
Host smart-52b8575b-cc07-4dd1-9c13-66e160bd9b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919241579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.919241579
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2097827536
Short name T894
Test name
Test status
Simulation time 40536093995 ps
CPU time 582.4 seconds
Started Jul 26 06:46:19 PM PDT 24
Finished Jul 26 06:56:01 PM PDT 24
Peak memory 215296 kb
Host smart-891d424d-7ab1-4bde-988f-f678564e51ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097827536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2097827536
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.987209935
Short name T1107
Test name
Test status
Simulation time 103761029630 ps
CPU time 37.35 seconds
Started Jul 26 06:46:21 PM PDT 24
Finished Jul 26 06:46:58 PM PDT 24
Peak memory 200112 kb
Host smart-3efad445-a5ee-45a0-8f9a-97aefaed0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987209935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.987209935
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1784638129
Short name T431
Test name
Test status
Simulation time 94226048893 ps
CPU time 383.51 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:52:45 PM PDT 24
Peak memory 216728 kb
Host smart-1213ad7b-8d09-4afa-a863-2717a81f2f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784638129 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1784638129
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3714323506
Short name T1109
Test name
Test status
Simulation time 40807674709 ps
CPU time 21.7 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:46:44 PM PDT 24
Peak memory 200148 kb
Host smart-add12a8d-2c45-4bf5-a2b8-91b656180322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714323506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3714323506
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2825299291
Short name T762
Test name
Test status
Simulation time 23386045845 ps
CPU time 199.6 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:49:42 PM PDT 24
Peak memory 216772 kb
Host smart-bb0e6c1e-33e8-4d5f-b761-c5b8196352a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825299291 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2825299291
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1622719513
Short name T702
Test name
Test status
Simulation time 50700015914 ps
CPU time 110.13 seconds
Started Jul 26 06:46:19 PM PDT 24
Finished Jul 26 06:48:09 PM PDT 24
Peak memory 200176 kb
Host smart-d7fd7d05-88c9-4b24-b6c1-02729f66a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622719513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1622719513
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.216060753
Short name T868
Test name
Test status
Simulation time 7391205126 ps
CPU time 102.44 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:48:05 PM PDT 24
Peak memory 208456 kb
Host smart-a8e5bdda-24e3-4388-90ca-45692dadbd76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216060753 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.216060753
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3570483376
Short name T214
Test name
Test status
Simulation time 18609288673 ps
CPU time 28.27 seconds
Started Jul 26 06:46:21 PM PDT 24
Finished Jul 26 06:46:50 PM PDT 24
Peak memory 200088 kb
Host smart-fa98505e-0765-462e-89c8-20763d8c280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570483376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3570483376
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1467519512
Short name T191
Test name
Test status
Simulation time 58888897703 ps
CPU time 26.24 seconds
Started Jul 26 06:46:21 PM PDT 24
Finished Jul 26 06:46:47 PM PDT 24
Peak memory 200040 kb
Host smart-83380d1b-cdb9-4364-a7f6-82d46d94406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467519512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1467519512
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1742630960
Short name T782
Test name
Test status
Simulation time 135100801997 ps
CPU time 379.61 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:52:42 PM PDT 24
Peak memory 216668 kb
Host smart-94758b8b-ac7f-45e2-9db0-62501a8644f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742630960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1742630960
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3862229749
Short name T501
Test name
Test status
Simulation time 10469458705 ps
CPU time 16.08 seconds
Started Jul 26 06:46:21 PM PDT 24
Finished Jul 26 06:46:38 PM PDT 24
Peak memory 200208 kb
Host smart-b9ef1d72-dca4-492b-9c59-38ba3cfb0253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862229749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3862229749
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3563782801
Short name T995
Test name
Test status
Simulation time 13829515368 ps
CPU time 82.03 seconds
Started Jul 26 06:46:22 PM PDT 24
Finished Jul 26 06:47:44 PM PDT 24
Peak memory 208584 kb
Host smart-5ec84580-706d-4010-83dd-b9dc02b03167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563782801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3563782801
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3800026995
Short name T900
Test name
Test status
Simulation time 61736009215 ps
CPU time 35.59 seconds
Started Jul 26 06:46:28 PM PDT 24
Finished Jul 26 06:47:04 PM PDT 24
Peak memory 200120 kb
Host smart-fe318303-fb5e-4139-a838-072df33c554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800026995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3800026995
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.28095945
Short name T666
Test name
Test status
Simulation time 63993799294 ps
CPU time 544.37 seconds
Started Jul 26 06:46:29 PM PDT 24
Finished Jul 26 06:55:34 PM PDT 24
Peak memory 216792 kb
Host smart-652e5943-13ef-4ee1-adf3-3d5a354ff6b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28095945 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.28095945
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1066846447
Short name T60
Test name
Test status
Simulation time 22481716488 ps
CPU time 250.31 seconds
Started Jul 26 06:46:30 PM PDT 24
Finished Jul 26 06:50:40 PM PDT 24
Peak memory 208524 kb
Host smart-b5f9c8fa-e28a-40c4-a3be-d171819a22a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066846447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1066846447
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2143838418
Short name T436
Test name
Test status
Simulation time 34359223 ps
CPU time 0.55 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:40:08 PM PDT 24
Peak memory 195560 kb
Host smart-336e496a-24e6-4178-8a0c-d3c6ca5dab5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143838418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2143838418
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1947699728
Short name T576
Test name
Test status
Simulation time 114627520397 ps
CPU time 31.98 seconds
Started Jul 26 06:39:53 PM PDT 24
Finished Jul 26 06:40:26 PM PDT 24
Peak memory 200132 kb
Host smart-7de9c7c3-8216-448e-8646-04fe1220e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947699728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1947699728
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3971738393
Short name T1089
Test name
Test status
Simulation time 211519090192 ps
CPU time 72.34 seconds
Started Jul 26 06:40:03 PM PDT 24
Finished Jul 26 06:41:15 PM PDT 24
Peak memory 200084 kb
Host smart-9dd91c7a-70e5-4f8e-aa61-152053def55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971738393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3971738393
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2764549311
Short name T212
Test name
Test status
Simulation time 194644517192 ps
CPU time 112.8 seconds
Started Jul 26 06:39:59 PM PDT 24
Finished Jul 26 06:41:52 PM PDT 24
Peak memory 200084 kb
Host smart-e1a10cec-3780-403e-8cef-8281531ef574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764549311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2764549311
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4197728817
Short name T865
Test name
Test status
Simulation time 71756944041 ps
CPU time 124.44 seconds
Started Jul 26 06:40:00 PM PDT 24
Finished Jul 26 06:42:04 PM PDT 24
Peak memory 200128 kb
Host smart-db5fb405-02f0-4411-9e0d-123ef1b218ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197728817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4197728817
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3067065773
Short name T669
Test name
Test status
Simulation time 122455848218 ps
CPU time 164.08 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:42:52 PM PDT 24
Peak memory 200128 kb
Host smart-f5cde8d0-a381-44f5-8a82-2a04e5d5383b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067065773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3067065773
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4099875286
Short name T574
Test name
Test status
Simulation time 11264598304 ps
CPU time 12.29 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:40:19 PM PDT 24
Peak memory 200120 kb
Host smart-8d2ac53d-8389-4a0e-9afd-096713d8410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099875286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4099875286
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3537659883
Short name T346
Test name
Test status
Simulation time 64388861482 ps
CPU time 30.84 seconds
Started Jul 26 06:40:00 PM PDT 24
Finished Jul 26 06:40:31 PM PDT 24
Peak memory 208508 kb
Host smart-6008674a-16c4-4c9f-b95c-eb00093354ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537659883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3537659883
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2223005806
Short name T589
Test name
Test status
Simulation time 7244650311 ps
CPU time 320.02 seconds
Started Jul 26 06:40:07 PM PDT 24
Finished Jul 26 06:45:27 PM PDT 24
Peak memory 200192 kb
Host smart-a3fcc5a4-fa4b-4634-a16c-8e58d93785b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223005806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2223005806
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.325345950
Short name T689
Test name
Test status
Simulation time 3501447649 ps
CPU time 24.44 seconds
Started Jul 26 06:40:03 PM PDT 24
Finished Jul 26 06:40:27 PM PDT 24
Peak memory 198492 kb
Host smart-b2e71391-9190-4c0b-85c6-e314b7733171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325345950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.325345950
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3307412459
Short name T1081
Test name
Test status
Simulation time 17971177113 ps
CPU time 29.37 seconds
Started Jul 26 06:39:59 PM PDT 24
Finished Jul 26 06:40:29 PM PDT 24
Peak memory 200092 kb
Host smart-ebbdfa30-7385-4232-b5cf-28d441663882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307412459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3307412459
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.104447271
Short name T1097
Test name
Test status
Simulation time 36110617350 ps
CPU time 27.36 seconds
Started Jul 26 06:40:02 PM PDT 24
Finished Jul 26 06:40:30 PM PDT 24
Peak memory 196008 kb
Host smart-ba28ec7f-e3be-423c-83e0-0490a3a0b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104447271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.104447271
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3988872615
Short name T311
Test name
Test status
Simulation time 483571293 ps
CPU time 1.36 seconds
Started Jul 26 06:39:53 PM PDT 24
Finished Jul 26 06:39:54 PM PDT 24
Peak memory 199832 kb
Host smart-51849142-c565-4a3c-b279-2d29816572ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988872615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3988872615
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3221071929
Short name T176
Test name
Test status
Simulation time 106620731487 ps
CPU time 374.98 seconds
Started Jul 26 06:40:05 PM PDT 24
Finished Jul 26 06:46:21 PM PDT 24
Peak memory 216624 kb
Host smart-fc5d60fa-27b3-4574-b06e-455186f22c4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221071929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3221071929
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1418834161
Short name T16
Test name
Test status
Simulation time 824230742 ps
CPU time 2.39 seconds
Started Jul 26 06:40:00 PM PDT 24
Finished Jul 26 06:40:02 PM PDT 24
Peak memory 198968 kb
Host smart-afcfa548-0791-4e76-b285-dba08f820369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418834161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1418834161
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3551376431
Short name T283
Test name
Test status
Simulation time 228984988475 ps
CPU time 56.66 seconds
Started Jul 26 06:39:54 PM PDT 24
Finished Jul 26 06:40:51 PM PDT 24
Peak memory 200192 kb
Host smart-e612c406-5080-4505-9298-a47bbd0fbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551376431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3551376431
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3724377586
Short name T203
Test name
Test status
Simulation time 41677152564 ps
CPU time 8.37 seconds
Started Jul 26 06:46:29 PM PDT 24
Finished Jul 26 06:46:38 PM PDT 24
Peak memory 200156 kb
Host smart-4f3eb90e-7934-4132-96f2-67301828fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724377586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3724377586
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1600801032
Short name T1141
Test name
Test status
Simulation time 106131975042 ps
CPU time 552.83 seconds
Started Jul 26 06:46:28 PM PDT 24
Finished Jul 26 06:55:41 PM PDT 24
Peak memory 216716 kb
Host smart-e515fde3-cb30-4dab-acb8-fd36fdc0f30a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600801032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1600801032
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3633297997
Short name T79
Test name
Test status
Simulation time 36997184638 ps
CPU time 38.74 seconds
Started Jul 26 06:46:27 PM PDT 24
Finished Jul 26 06:47:06 PM PDT 24
Peak memory 200192 kb
Host smart-27fd6d73-0092-45d0-a4e6-db4b7e16c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633297997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3633297997
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.4042465387
Short name T686
Test name
Test status
Simulation time 36232940689 ps
CPU time 265.1 seconds
Started Jul 26 06:46:31 PM PDT 24
Finished Jul 26 06:50:56 PM PDT 24
Peak memory 208552 kb
Host smart-81f42dbe-f0cc-42e4-96fc-3e40f38d540b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042465387 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.4042465387
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2219318333
Short name T340
Test name
Test status
Simulation time 41949509133 ps
CPU time 20.09 seconds
Started Jul 26 06:46:30 PM PDT 24
Finished Jul 26 06:46:50 PM PDT 24
Peak memory 200148 kb
Host smart-1bb24c83-6870-405f-b5f1-ac75427f8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219318333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2219318333
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.993423847
Short name T913
Test name
Test status
Simulation time 21410428064 ps
CPU time 29.1 seconds
Started Jul 26 06:46:29 PM PDT 24
Finished Jul 26 06:46:58 PM PDT 24
Peak memory 200136 kb
Host smart-62ce3fff-492b-4b58-8c78-3a4474a9be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993423847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.993423847
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.823571536
Short name T333
Test name
Test status
Simulation time 46272429703 ps
CPU time 552.38 seconds
Started Jul 26 06:46:31 PM PDT 24
Finished Jul 26 06:55:43 PM PDT 24
Peak memory 216576 kb
Host smart-4c258b96-22f0-4058-a0ca-c263e1732aac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823571536 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.823571536
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.118772239
Short name T1067
Test name
Test status
Simulation time 63485154197 ps
CPU time 24.55 seconds
Started Jul 26 06:46:29 PM PDT 24
Finished Jul 26 06:46:54 PM PDT 24
Peak memory 200196 kb
Host smart-579d3298-d1ec-438e-abef-b17fc1eec571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118772239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.118772239
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3879499042
Short name T491
Test name
Test status
Simulation time 97014969522 ps
CPU time 22.13 seconds
Started Jul 26 06:46:28 PM PDT 24
Finished Jul 26 06:46:51 PM PDT 24
Peak memory 200092 kb
Host smart-33465835-aaa4-4189-840f-7960d86f7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879499042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3879499042
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2010005016
Short name T654
Test name
Test status
Simulation time 24322194707 ps
CPU time 280.6 seconds
Started Jul 26 06:46:31 PM PDT 24
Finished Jul 26 06:51:11 PM PDT 24
Peak memory 212132 kb
Host smart-67735876-3d71-43d1-ac5f-02422eef3e7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010005016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2010005016
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1676093327
Short name T617
Test name
Test status
Simulation time 97966910383 ps
CPU time 76.84 seconds
Started Jul 26 06:46:30 PM PDT 24
Finished Jul 26 06:47:47 PM PDT 24
Peak memory 200208 kb
Host smart-6b9f3d71-ffeb-49b2-b8e6-2199c424bb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676093327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1676093327
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2492559635
Short name T1059
Test name
Test status
Simulation time 65396771107 ps
CPU time 32.28 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:47:12 PM PDT 24
Peak memory 200152 kb
Host smart-10aa275e-75a6-4222-a36b-cc318f3adce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492559635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2492559635
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1996301125
Short name T705
Test name
Test status
Simulation time 157256515844 ps
CPU time 231.88 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:50:31 PM PDT 24
Peak memory 216648 kb
Host smart-791b2e91-f1fd-464c-9381-8d9854859681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996301125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1996301125
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1188295358
Short name T879
Test name
Test status
Simulation time 53802034445 ps
CPU time 72.45 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:47:52 PM PDT 24
Peak memory 200020 kb
Host smart-6b292eb7-2b48-4739-a550-f5b392b3c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188295358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1188295358
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1102054212
Short name T82
Test name
Test status
Simulation time 37251382578 ps
CPU time 505.9 seconds
Started Jul 26 06:46:40 PM PDT 24
Finished Jul 26 06:55:06 PM PDT 24
Peak memory 216480 kb
Host smart-dd4a3f02-0343-45fb-b62a-1cd73791428f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102054212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1102054212
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3502950315
Short name T157
Test name
Test status
Simulation time 168658759352 ps
CPU time 129.96 seconds
Started Jul 26 06:46:39 PM PDT 24
Finished Jul 26 06:48:49 PM PDT 24
Peak memory 200216 kb
Host smart-2394e7ed-5c69-47c5-bea9-3c18cb55f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502950315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3502950315
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1230208259
Short name T61
Test name
Test status
Simulation time 677501287283 ps
CPU time 1654.03 seconds
Started Jul 26 06:46:38 PM PDT 24
Finished Jul 26 07:14:12 PM PDT 24
Peak memory 225092 kb
Host smart-6c8a69c1-f113-4776-8f09-9b2375f7340b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230208259 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1230208259
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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