Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	112701	1			T1	76		T2	1		T3	1
all_values[1]	112701	1			T1	76		T2	1		T3	1
all_values[2]	112701	1			T1	76		T2	1		T3	1
all_values[3]	112701	1			T1	76		T2	1		T3	1
all_values[4]	112701	1			T1	76		T2	1		T3	1
all_values[5]	112701	1			T1	76		T2	1		T3	1
all_values[6]	112701	1			T1	76		T2	1		T3	1
all_values[7]	112701	1			T1	76		T2	1		T3	1
all_values[8]	112701	1			T1	76		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524719

1

T1

393

T2

8

T3

3

auto[1]

489590

1

T1

291

T2

1

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

917478

1

T1

614

T2

7

T3

7

auto[1]

96831

1

T1

70

T2

2

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31868	1			T1	32		T4	3		T5	92
all_values[0]	auto[0]	auto[1]	24505	1			T1	37		T2	1		T4	33
all_values[0]	auto[1]	auto[0]	32709	1			T1	4		T5	108		T6	3
all_values[0]	auto[1]	auto[1]	23619	1			T1	3		T3	1		T4	11
all_values[1]	auto[0]	auto[0]	55088	1			T1	69		T2	1		T4	44
all_values[1]	auto[0]	auto[1]	1830	1			T4	3		T5	24		T7	8
all_values[1]	auto[1]	auto[0]	54037	1			T1	7		T3	1		T5	187
all_values[1]	auto[1]	auto[1]	1746	1			T5	10		T7	1		T28	3
all_values[2]	auto[0]	auto[0]	57056	1			T1	10		T2	1		T4	33
all_values[2]	auto[0]	auto[1]	2970	1			T1	1		T5	16		T6	6
all_values[2]	auto[1]	auto[0]	50135	1			T1	60		T3	1		T4	12
all_values[2]	auto[1]	auto[1]	2540	1			T1	5		T4	2		T5	3
all_values[3]	auto[0]	auto[0]	60233	1			T1	17		T2	1		T4	13
all_values[3]	auto[0]	auto[1]	300	1			T1	2		T5	5		T7	1
all_values[3]	auto[1]	auto[0]	51847	1			T1	57		T3	1		T4	34
all_values[3]	auto[1]	auto[1]	321	1			T5	2		T14	4		T23	3
all_values[4]	auto[0]	auto[0]	60140	1			T1	23		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	475	1			T5	9		T14	2		T23	2
all_values[4]	auto[1]	auto[0]	51625	1			T1	53		T5	167		T6	60
all_values[4]	auto[1]	auto[1]	461	1			T5	13		T7	4		T14	2
all_values[5]	auto[0]	auto[0]	61213	1			T1	76		T3	1		T4	12
all_values[5]	auto[0]	auto[1]	194	1			T14	2		T23	1		T12	2
all_values[5]	auto[1]	auto[0]	51097	1			T2	1		T4	35		T5	215
all_values[5]	auto[1]	auto[1]	197	1			T14	1		T23	1		T15	1
all_values[6]	auto[0]	auto[0]	57695	1			T1	50		T2	1		T4	42
all_values[6]	auto[0]	auto[1]	216	1			T5	3		T7	2		T14	1
all_values[6]	auto[1]	auto[0]	54613	1			T1	26		T3	1		T4	5
all_values[6]	auto[1]	auto[1]	177	1			T5	1		T7	1		T14	4
all_values[7]	auto[0]	auto[0]	52976	1			T1	54		T2	1		T4	45
all_values[7]	auto[0]	auto[1]	394	1			T5	2		T7	2		T14	2
all_values[7]	auto[1]	auto[0]	58985	1			T1	22		T3	1		T4	2
all_values[7]	auto[1]	auto[1]	346	1			T5	4		T7	4		T9	1
all_values[8]	auto[0]	auto[0]	38106	1			T1	4		T4	3		T5	131
all_values[8]	auto[0]	auto[1]	19460	1			T1	18		T2	1		T3	1
all_values[8]	auto[1]	auto[0]	38055	1			T1	50		T5	79		T6	27
all_values[8]	auto[1]	auto[1]	17080	1			T1	4		T4	9		T5	134