Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2646

1

T1

1

T2

1

T3

1

auto[UartRx]

2646

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4667	1			T1	2		T2	2		T3	2
values[1]	47	1			T5	1		T24	2		T26	1
values[2]	54	1			T7	1		T24	1		T25	1
values[3]	53	1			T5	3		T24	1		T27	2
values[4]	61	1			T5	1		T7	1		T23	1
values[5]	58	1			T5	1		T7	1		T14	1
values[6]	63	1			T5	1		T13	2		T24	1
values[7]	63	1			T7	1		T24	1		T25	1
values[8]	63	1			T25	2		T15	3		T34	5
values[9]	67	1			T14	1		T23	1		T25	1
values[10]	69	1			T7	2		T14	2		T23	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2426	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	14	1			T5	1		T44	1		T147	1
auto[UartTx]	values[2]	13	1			T7	1		T15	2		T108	1
auto[UartTx]	values[3]	18	1			T24	1		T27	1		T34	1
auto[UartTx]	values[4]	17	1			T34	1		T251	1		T147	1
auto[UartTx]	values[5]	12	1			T5	1		T91	1		T321	1
auto[UartTx]	values[6]	30	1			T5	1		T34	1		T251	1
auto[UartTx]	values[7]	29	1			T26	2		T15	1		T34	1
auto[UartTx]	values[8]	20	1			T25	2		T34	1		T322	1
auto[UartTx]	values[9]	31	1			T23	1		T25	1		T15	1
auto[UartTx]	values[10]	24	1			T7	1		T14	1		T24	1
auto[UartRx]	values[0]	2241	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	33	1			T24	2		T26	1		T91	1
auto[UartRx]	values[2]	41	1			T24	1		T25	1		T34	1
auto[UartRx]	values[3]	35	1			T5	3		T27	1		T251	1
auto[UartRx]	values[4]	44	1			T5	1		T7	1		T23	1
auto[UartRx]	values[5]	46	1			T7	1		T14	1		T34	1
auto[UartRx]	values[6]	33	1			T13	2		T24	1		T25	1
auto[UartRx]	values[7]	34	1			T7	1		T24	1		T25	1
auto[UartRx]	values[8]	43	1			T15	3		T34	4		T323	1
auto[UartRx]	values[9]	36	1			T14	1		T26	2		T179	3
auto[UartRx]	values[10]	45	1			T7	1		T14	1		T23	1