Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2409	1			T1	2		T2	6		T3	6
auto[BaudRate115200]	2144	1			T1	1		T2	9		T4	1
auto[BaudRate230400]	2218	1			T1	2		T4	1		T5	20
auto[BaudRate128Kbps]	2180	1			T1	2		T2	15		T4	2
auto[BaudRate256Kbps]	2376	1			T1	2		T2	3		T4	1
auto[BaudRate1Mbps]	2031	1			T1	1		T2	6		T4	1
auto[BaudRate1p5Mbps]	1370	1			T2	9		T8	2		T11	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1385	1			T3	6		T14	95		T260	8
freqs[25]	1185	1			T324	21		T103	10		T15	34
freqs[48]	680	1			T1	10		T29	9		T245	5
freqs[50]	572	1			T2	48		T23	125		T242	2
freqs[100]	1243	1			T24	41		T102	7		T114	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	231	1			T3	6		T14	8		T260	3
auto[BaudRate9600]	freqs[25]	215	1			T324	3		T15	7		T250	1
auto[BaudRate9600]	freqs[48]	91	1			T1	2		T29	2		T31	2
auto[BaudRate9600]	freqs[50]	94	1			T2	6		T23	17		T173	2
auto[BaudRate9600]	freqs[100]	213	1			T24	4		T114	1		T38	1
auto[BaudRate115200]	freqs[24]	192	1			T14	22		T260	1		T141	2
auto[BaudRate115200]	freqs[25]	161	1			T324	6		T103	2		T15	4
auto[BaudRate115200]	freqs[48]	98	1			T1	1		T31	3		T149	1
auto[BaudRate115200]	freqs[50]	61	1			T2	9		T23	3		T242	1
auto[BaudRate115200]	freqs[100]	145	1			T24	3		T102	2		T114	2
auto[BaudRate230400]	freqs[24]	210	1			T14	11		T112	2		T127	1
auto[BaudRate230400]	freqs[25]	170	1			T103	2		T15	9		T250	5
auto[BaudRate230400]	freqs[48]	73	1			T1	2		T29	1		T31	2
auto[BaudRate230400]	freqs[50]	91	1			T23	37		T242	1		T173	2
auto[BaudRate230400]	freqs[100]	163	1			T24	4		T102	2		T268	1
auto[BaudRate128Kbps]	freqs[24]	204	1			T14	18		T260	2		T112	1
auto[BaudRate128Kbps]	freqs[25]	167	1			T103	2		T15	3		T250	2
auto[BaudRate128Kbps]	freqs[48]	94	1			T1	2		T29	2		T261	2
auto[BaudRate128Kbps]	freqs[50]	97	1			T2	15		T23	13		T173	1
auto[BaudRate128Kbps]	freqs[100]	158	1			T24	11		T102	2		T114	1
auto[BaudRate256Kbps]	freqs[24]	215	1			T14	14		T112	2		T141	2
auto[BaudRate256Kbps]	freqs[25]	179	1			T324	3		T103	1		T15	4
auto[BaudRate256Kbps]	freqs[48]	116	1			T1	2		T29	2		T245	1
auto[BaudRate256Kbps]	freqs[50]	78	1			T2	3		T23	20		T173	2
auto[BaudRate256Kbps]	freqs[100]	193	1			T24	8		T243	2		T268	3
auto[BaudRate1Mbps]	freqs[24]	219	1			T14	16		T260	1		T112	1
auto[BaudRate1Mbps]	freqs[25]	196	1			T324	6		T103	3		T15	7
auto[BaudRate1Mbps]	freqs[48]	108	1			T1	1		T29	1		T245	2
auto[BaudRate1Mbps]	freqs[50]	84	1			T2	6		T23	25		T117	2
auto[BaudRate1Mbps]	freqs[100]	194	1			T24	8		T243	1		T268	1
auto[BaudRate1p5Mbps]	freqs[25]	97	1			T324	3		T250	1		T293	1
auto[BaudRate1p5Mbps]	freqs[48]	100	1			T29	1		T245	2		T31	1
auto[BaudRate1p5Mbps]	freqs[50]	67	1			T2	9		T23	10		T173	2
auto[BaudRate1p5Mbps]	freqs[100]	177	1			T24	3		T102	1		T114	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded