Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31064145	1			T1	109		T2	9		T3	1
all_levels[1]	225041	1			T1	2		T5	515		T6	41
all_levels[2]	2821	1			T4	1		T6	5		T7	3
all_levels[3]	1207	1			T4	4		T6	1		T28	1
all_levels[4]	769	1			T4	1		T6	2		T28	2
all_levels[5]	621	1			T4	2		T6	2		T29	1
all_levels[6]	499	1			T5	1		T6	2		T9	1
all_levels[7]	378	1			T5	3		T6	3		T111	1
all_levels[8]	290	1			T6	1		T28	1		T29	1
all_levels[9]	239	1			T28	1		T111	2		T34	1
all_levels[10]	195	1			T1	1		T5	2		T28	2
all_levels[11]	205	1			T1	2		T6	1		T28	1
all_levels[12]	161	1			T4	1		T5	1		T111	2
all_levels[13]	149	1			T97	1		T112	1		T113	1
all_levels[14]	132	1			T5	1		T28	2		T104	1
all_levels[15]	137	1			T4	1		T6	1		T9	1
all_levels[16]	113	1			T9	1		T12	1		T104	1
all_levels[17]	111	1			T4	1		T12	1		T15	3
all_levels[18]	95	1			T1	1		T12	1		T24	1
all_levels[19]	87	1			T4	1		T5	1		T112	1
all_levels[20]	73	1			T114	1		T115	1		T35	2
all_levels[21]	45	1			T4	1		T104	1		T116	1
all_levels[22]	66	1			T5	1		T6	1		T97	1
all_levels[23]	68	1			T15	2		T117	1		T35	1
all_levels[24]	64	1			T1	3		T118	2		T119	1
all_levels[25]	53	1			T44	1		T105	1		T120	1
all_levels[26]	53	1			T9	1		T44	1		T121	1
all_levels[27]	59	1			T6	1		T40	2		T44	1
all_levels[28]	43	1			T29	1		T122	3		T123	1
all_levels[29]	33	1			T5	1		T35	1		T124	1
all_levels[30]	40	1			T23	1		T125	1		T91	1
all_levels[31]	33	1			T91	1		T116	1		T126	2
all_levels[32]	35	1			T12	1		T127	1		T128	1
all_levels[33]	25	1			T105	1		T129	1		T124	1
all_levels[34]	28	1			T97	1		T25	1		T130	1
all_levels[35]	30	1			T131	2		T116	1		T132	1
all_levels[36]	24	1			T113	1		T133	1		T134	1
all_levels[37]	26	1			T127	1		T40	1		T135	1
all_levels[38]	29	1			T26	1		T136	1		T137	1
all_levels[39]	17	1			T127	1		T117	1		T138	1
all_levels[40]	13	1			T34	2		T139	2		T140	1
all_levels[41]	19	1			T5	1		T23	1		T141	1
all_levels[42]	22	1			T23	1		T127	1		T38	1
all_levels[43]	22	1			T40	1		T142	1		T118	1
all_levels[44]	18	1			T127	1		T37	1		T143	2
all_levels[45]	19	1			T118	1		T129	2		T144	1
all_levels[46]	17	1			T5	1		T145	1		T146	1
all_levels[47]	12	1			T127	2		T147	1		T148	1
all_levels[48]	14	1			T103	3		T149	1		T143	1
all_levels[49]	9	1			T150	1		T151	1		T152	1
all_levels[50]	10	1			T153	2		T118	1		T154	1
all_levels[51]	7	1			T29	1		T155	1		T140	1
all_levels[52]	7	1			T102	1		T142	1		T156	2
all_levels[53]	10	1			T31	1		T129	1		T157	1
all_levels[54]	13	1			T31	1		T131	1		T132	1
all_levels[55]	8	1			T9	1		T147	1		T158	2
all_levels[56]	18	1			T9	1		T101	1		T159	1
all_levels[57]	17	1			T143	1		T159	1		T47	1
all_levels[58]	13	1			T34	1		T160	1		T161	1
all_levels[59]	11	1			T132	1		T162	1		T163	1
all_levels[60]	9	1			T159	4		T46	1		T164	1
all_levels[61]	10	1			T165	1		T166	1		T167	1
all_levels[62]	8	1			T45	1		T163	2		T168	1
all_levels[63]	10	1			T169	1		T170	1		T171	1
all_levels[64]	106	1			T12	1		T13	1		T26	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31293856

1

T1

110

T4

208

T5

114510

auto[1]

4805

1

T1

8

T2

9

T3

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[42] , all_levels[43]]	[auto[1]]	--	--	2
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31059822	1			T1	105		T4	195		T5	113983
all_levels[0]	auto[1]	4323	1			T1	4		T2	9		T3	1
all_levels[1]	auto[0]	224945	1			T1	1		T5	515		T6	41
all_levels[1]	auto[1]	96	1			T1	1		T8	2		T114	1
all_levels[2]	auto[0]	2796	1			T4	1		T6	5		T7	3
all_levels[2]	auto[1]	25	1			T28	1		T172	1		T40	1
all_levels[3]	auto[0]	1184	1			T4	4		T6	1		T28	1
all_levels[3]	auto[1]	23	1			T173	1		T133	2		T174	1
all_levels[4]	auto[0]	747	1			T4	1		T6	2		T28	2
all_levels[4]	auto[1]	22	1			T103	3		T175	1		T176	1
all_levels[5]	auto[0]	596	1			T4	2		T6	2		T29	1
all_levels[5]	auto[1]	25	1			T97	1		T133	2		T115	1
all_levels[6]	auto[0]	476	1			T5	1		T6	2		T9	1
all_levels[6]	auto[1]	23	1			T173	4		T104	2		T177	2
all_levels[7]	auto[0]	362	1			T5	2		T6	3		T111	1
all_levels[7]	auto[1]	16	1			T5	1		T97	1		T172	2
all_levels[8]	auto[0]	274	1			T6	1		T28	1		T29	1
all_levels[8]	auto[1]	16	1			T37	2		T153	3		T178	3
all_levels[9]	auto[0]	224	1			T28	1		T111	2		T34	1
all_levels[9]	auto[1]	15	1			T127	3		T40	1		T179	1
all_levels[10]	auto[0]	189	1			T1	1		T5	2		T28	2
all_levels[10]	auto[1]	6	1			T180	2		T181	1		T182	1
all_levels[11]	auto[0]	197	1			T1	1		T6	1		T28	1
all_levels[11]	auto[1]	8	1			T1	1		T160	1		T183	1
all_levels[12]	auto[0]	155	1			T4	1		T5	1		T111	2
all_levels[12]	auto[1]	6	1			T98	4		T184	1		T185	1
all_levels[13]	auto[0]	136	1			T97	1		T112	1		T113	1
all_levels[13]	auto[1]	13	1			T40	1		T160	1		T186	1
all_levels[14]	auto[0]	118	1			T5	1		T28	1		T104	1
all_levels[14]	auto[1]	14	1			T28	1		T187	1		T188	1
all_levels[15]	auto[0]	125	1			T4	1		T6	1		T9	1
all_levels[15]	auto[1]	12	1			T184	1		T171	1		T189	1
all_levels[16]	auto[0]	102	1			T9	1		T12	1		T104	1
all_levels[16]	auto[1]	11	1			T175	1		T190	1		T191	1
all_levels[17]	auto[0]	103	1			T4	1		T12	1		T15	1
all_levels[17]	auto[1]	8	1			T15	2		T192	1		T193	1
all_levels[18]	auto[0]	87	1			T1	1		T12	1		T24	1
all_levels[18]	auto[1]	8	1			T194	2		T195	1		T196	1
all_levels[19]	auto[0]	81	1			T4	1		T5	1		T112	1
all_levels[19]	auto[1]	6	1			T197	1		T181	1		T198	2
all_levels[20]	auto[0]	65	1			T114	1		T115	1		T35	1
all_levels[20]	auto[1]	8	1			T35	1		T136	1		T148	1
all_levels[21]	auto[0]	43	1			T4	1		T104	1		T116	1
all_levels[21]	auto[1]	2	1			T199	1		T200	1		-	-
all_levels[22]	auto[0]	59	1			T5	1		T6	1		T97	1
all_levels[22]	auto[1]	7	1			T156	2		T201	1		T202	2
all_levels[23]	auto[0]	64	1			T15	1		T117	1		T35	1
all_levels[23]	auto[1]	4	1			T15	1		T203	1		T159	1
all_levels[24]	auto[0]	56	1			T1	1		T118	2		T119	1
all_levels[24]	auto[1]	8	1			T1	2		T204	3		T196	1
all_levels[25]	auto[0]	42	1			T44	1		T105	1		T120	1
all_levels[25]	auto[1]	11	1			T205	1		T175	4		T206	3
all_levels[26]	auto[0]	49	1			T9	1		T44	1		T121	1
all_levels[26]	auto[1]	4	1			T207	2		T208	1		T209	1
all_levels[27]	auto[0]	54	1			T6	1		T40	1		T44	1
all_levels[27]	auto[1]	5	1			T40	1		T210	1		T211	2
all_levels[28]	auto[0]	39	1			T29	1		T122	1		T123	1
all_levels[28]	auto[1]	4	1			T122	2		T151	1		T212	1
all_levels[29]	auto[0]	29	1			T5	1		T35	1		T124	1
all_levels[29]	auto[1]	4	1			T213	1		T214	1		T50	1
all_levels[30]	auto[0]	34	1			T23	1		T125	1		T91	1
all_levels[30]	auto[1]	6	1			T119	1		T215	2		T216	2
all_levels[31]	auto[0]	31	1			T91	1		T116	1		T126	2
all_levels[31]	auto[1]	2	1			T217	2		-	-		-	-
all_levels[32]	auto[0]	33	1			T12	1		T127	1		T128	1
all_levels[32]	auto[1]	2	1			T218	1		T219	1		-	-
all_levels[33]	auto[0]	25	1			T105	1		T129	1		T124	1
all_levels[34]	auto[0]	24	1			T97	1		T25	1		T130	1
all_levels[34]	auto[1]	4	1			T220	1		T221	1		T222	1
all_levels[35]	auto[0]	27	1			T131	1		T116	1		T132	1
all_levels[35]	auto[1]	3	1			T131	1		T223	1		T224	1
all_levels[36]	auto[0]	24	1			T113	1		T133	1		T134	1
all_levels[37]	auto[0]	19	1			T127	1		T40	1		T135	1
all_levels[37]	auto[1]	7	1			T140	1		T225	3		T226	2
all_levels[38]	auto[0]	24	1			T26	1		T136	1		T137	1
all_levels[38]	auto[1]	5	1			T203	2		T227	1		T228	2
all_levels[39]	auto[0]	16	1			T127	1		T117	1		T138	1
all_levels[39]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[40]	auto[0]	11	1			T34	2		T139	1		T140	1
all_levels[40]	auto[1]	2	1			T139	1		T229	1		-	-
all_levels[41]	auto[0]	17	1			T5	1		T23	1		T141	1
all_levels[41]	auto[1]	2	1			T189	2		-	-		-	-
all_levels[42]	auto[0]	22	1			T23	1		T127	1		T38	1
all_levels[43]	auto[0]	22	1			T40	1		T142	1		T118	1
all_levels[44]	auto[0]	17	1			T127	1		T37	1		T143	1
all_levels[44]	auto[1]	1	1			T143	1		-	-		-	-
all_levels[45]	auto[0]	17	1			T118	1		T129	2		T144	1
all_levels[45]	auto[1]	2	1			T170	1		T213	1		-	-
all_levels[46]	auto[0]	14	1			T5	1		T145	1		T146	1
all_levels[46]	auto[1]	3	1			T230	1		T180	2		-	-
all_levels[47]	auto[0]	11	1			T127	2		T147	1		T148	1
all_levels[47]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[48]	auto[0]	12	1			T103	1		T149	1		T143	1
all_levels[48]	auto[1]	2	1			T103	2		-	-		-	-
all_levels[49]	auto[0]	9	1			T150	1		T151	1		T152	1
all_levels[50]	auto[0]	9	1			T153	1		T118	1		T154	1
all_levels[50]	auto[1]	1	1			T153	1		-	-		-	-
all_levels[51]	auto[0]	7	1			T29	1		T155	1		T140	1
all_levels[52]	auto[0]	6	1			T102	1		T142	1		T156	1
all_levels[52]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[53]	auto[0]	10	1			T31	1		T129	1		T157	1
all_levels[54]	auto[0]	12	1			T31	1		T131	1		T132	1
all_levels[54]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T9	1		T147	1		T158	1
all_levels[55]	auto[1]	1	1			T158	1		-	-		-	-
all_levels[56]	auto[0]	18	1			T9	1		T101	1		T159	1
all_levels[57]	auto[0]	12	1			T143	1		T159	1		T47	1
all_levels[57]	auto[1]	5	1			T233	2		T234	2		T235	1
all_levels[58]	auto[0]	12	1			T34	1		T160	1		T161	1
all_levels[58]	auto[1]	1	1			T49	1		-	-		-	-
all_levels[59]	auto[0]	11	1			T132	1		T162	1		T163	1
all_levels[60]	auto[0]	6	1			T159	1		T46	1		T164	1
all_levels[60]	auto[1]	3	1			T159	3		-	-		-	-
all_levels[61]	auto[0]	9	1			T165	1		T166	1		T167	1
all_levels[61]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[62]	auto[0]	7	1			T45	1		T163	1		T168	1
all_levels[62]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[63]	auto[0]	8	1			T169	1		T170	1		T171	1
all_levels[63]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[64]	auto[0]	94	1			T12	1		T13	1		T26	1
all_levels[64]	auto[1]	12	1			T37	2		T238	1		T46	1