Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	112701	1			T1	76		T2	1		T3	1
all_pins[1]	112701	1			T1	76		T2	1		T3	1
all_pins[2]	112701	1			T1	76		T2	1		T3	1
all_pins[3]	112701	1			T1	76		T2	1		T3	1
all_pins[4]	112701	1			T1	76		T2	1		T3	1
all_pins[5]	112701	1			T1	76		T2	1		T3	1
all_pins[6]	112701	1			T1	76		T2	1		T3	1
all_pins[7]	112701	1			T1	76		T2	1		T3	1
all_pins[8]	112701	1			T1	76		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	966793	1			T1	671		T2	9		T3	8
values[0x1]	47516	1			T1	13		T3	1		T4	22
transitions[0x0=>0x1]	38457	1			T1	13		T3	1		T4	14
transitions[0x1=>0x0]	38247	1			T1	13		T4	13		T5	197

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	88996	1			T1	73		T2	1		T4	36
all_pins[0]	values[0x1]	23705	1			T1	3		T3	1		T4	11
all_pins[0]	transitions[0x0=>0x1]	23178	1			T1	3		T3	1		T4	11
all_pins[0]	transitions[0x1=>0x0]	1212	1			T5	3		T239	1		T23	7
all_pins[1]	values[0x0]	110962	1			T1	76		T2	1		T3	1
all_pins[1]	values[0x1]	1739	1			T5	10		T7	1		T28	3
all_pins[1]	transitions[0x0=>0x1]	1639	1			T5	9		T7	1		T28	3
all_pins[1]	transitions[0x1=>0x0]	2492	1			T1	5		T4	2		T5	3
all_pins[2]	values[0x0]	110109	1			T1	71		T2	1		T3	1
all_pins[2]	values[0x1]	2592	1			T1	5		T4	2		T5	4
all_pins[2]	transitions[0x0=>0x1]	2527	1			T1	5		T4	2		T5	4
all_pins[2]	transitions[0x1=>0x0]	256	1			T5	2		T14	3		T23	3
all_pins[3]	values[0x0]	112380	1			T1	76		T2	1		T3	1
all_pins[3]	values[0x1]	321	1			T5	2		T14	4		T23	3
all_pins[3]	transitions[0x0=>0x1]	268	1			T5	2		T14	2		T23	1
all_pins[3]	transitions[0x1=>0x0]	408	1			T5	13		T7	4		T23	2
all_pins[4]	values[0x0]	112240	1			T1	76		T2	1		T3	1
all_pins[4]	values[0x1]	461	1			T5	13		T7	4		T14	2
all_pins[4]	transitions[0x0=>0x1]	387	1			T5	12		T7	3		T14	2
all_pins[4]	transitions[0x1=>0x0]	167	1			T14	1		T23	1		T15	1
all_pins[5]	values[0x0]	112460	1			T1	76		T2	1		T3	1
all_pins[5]	values[0x1]	241	1			T5	1		T7	1		T14	1
all_pins[5]	transitions[0x0=>0x1]	197	1			T5	1		T7	1		T23	1
all_pins[5]	transitions[0x1=>0x0]	915	1			T1	1		T5	6		T7	3
all_pins[6]	values[0x0]	111742	1			T1	75		T2	1		T3	1
all_pins[6]	values[0x1]	959	1			T1	1		T5	6		T7	3
all_pins[6]	transitions[0x0=>0x1]	921	1			T1	1		T5	6		T7	3
all_pins[6]	transitions[0x1=>0x0]	308	1			T5	4		T7	4		T9	1
all_pins[7]	values[0x0]	112355	1			T1	76		T2	1		T3	1
all_pins[7]	values[0x1]	346	1			T5	4		T7	4		T9	1
all_pins[7]	transitions[0x0=>0x1]	214	1			T5	3		T7	4		T9	1
all_pins[7]	transitions[0x1=>0x0]	17020	1			T1	4		T4	9		T5	133
all_pins[8]	values[0x0]	95549	1			T1	72		T2	1		T3	1
all_pins[8]	values[0x1]	17152	1			T1	4		T4	9		T5	134
all_pins[8]	transitions[0x0=>0x1]	9126	1			T1	4		T4	1		T5	87
all_pins[8]	transitions[0x1=>0x0]	15469	1			T1	3		T4	2		T5	33