Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8124259	1			T1	19		T4	193		T5	16387
all_levels[1]	1798017	1			T5	617		T6	14		T7	14281
all_levels[2]	545097	1			T5	614		T6	7		T7	15
all_levels[3]	230716	1			T1	3		T5	638		T6	12
all_levels[4]	276270	1			T5	820		T6	2		T7	12
all_levels[5]	239970	1			T1	15		T4	1		T5	571
all_levels[6]	270047	1			T1	3		T5	557		T6	2
all_levels[7]	232035	1			T1	1		T4	1		T5	432
all_levels[8]	398652	1			T1	7		T5	2735		T7	14
all_levels[9]	247348	1			T1	5		T4	1		T5	405
all_levels[10]	203113	1			T1	5		T5	442		T7	13
all_levels[11]	390270	1			T1	3		T4	3		T5	553
all_levels[12]	444695	1			T1	5		T4	3		T5	551
all_levels[13]	268385	1			T1	1		T5	550		T6	5
all_levels[14]	199045	1			T1	1		T4	1		T5	548
all_levels[15]	345706	1			T1	2		T4	2		T5	551
all_levels[16]	292833	1			T5	501		T7	10		T9	1
all_levels[17]	182037	1			T4	2		T5	427		T6	4
all_levels[18]	260491	1			T1	1		T5	342		T7	9
all_levels[19]	200298	1			T1	4		T4	1		T5	312
all_levels[20]	225747	1			T5	310		T7	12		T14	3
all_levels[21]	180853	1			T1	17		T5	473		T7	10
all_levels[22]	178855	1			T1	4		T5	551		T7	11
all_levels[23]	486211	1			T5	550		T7	12		T14	4
all_levels[24]	253829	1			T1	9		T4	1		T5	550
all_levels[25]	184169	1			T1	4		T5	549		T7	12
all_levels[26]	231735	1			T5	525		T6	111		T7	7
all_levels[27]	315856	1			T5	518		T7	9		T14	4
all_levels[28]	202657	1			T4	1		T5	521		T7	12
all_levels[29]	209697	1			T1	3		T5	518		T7	16
all_levels[30]	391841	1			T5	519		T7	13		T14	3
all_levels[31]	486193	1			T1	4		T4	3		T5	756
all_levels[32]	12801233	1			T1	1		T4	2		T5	79676

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31293856

1

T1

110

T4

208

T5

114510

auto[1]

4304

1

T1

7

T4

7

T5

59

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8121752	1			T1	15		T4	187		T5	16357
all_levels[0]	auto[1]	2507	1			T1	4		T4	6		T5	30
all_levels[1]	auto[0]	1797724	1			T5	617		T6	13		T7	14281
all_levels[1]	auto[1]	293	1			T6	1		T111	1		T241	2
all_levels[2]	auto[0]	545051	1			T5	614		T6	7		T7	15
all_levels[2]	auto[1]	46	1			T129	2		T326	3		T137	3
all_levels[3]	auto[0]	230579	1			T1	3		T5	611		T6	12
all_levels[3]	auto[1]	137	1			T5	27		T29	2		T26	12
all_levels[4]	auto[0]	276228	1			T5	820		T6	2		T7	12
all_levels[4]	auto[1]	42	1			T241	1		T172	1		T134	1
all_levels[5]	auto[0]	239941	1			T1	15		T4	1		T5	571
all_levels[5]	auto[1]	29	1			T112	1		T137	1		T327	1
all_levels[6]	auto[0]	270023	1			T1	3		T5	557		T6	2
all_levels[6]	auto[1]	24	1			T328	3		T319	1		T158	1
all_levels[7]	auto[0]	231889	1			T1	1		T4	1		T5	430
all_levels[7]	auto[1]	146	1			T5	2		T26	8		T114	1
all_levels[8]	auto[0]	398620	1			T1	7		T5	2735		T7	14
all_levels[8]	auto[1]	32	1			T12	1		T172	2		T115	1
all_levels[9]	auto[0]	247328	1			T1	5		T4	1		T5	405
all_levels[9]	auto[1]	20	1			T97	1		T175	1		T326	1
all_levels[10]	auto[0]	203090	1			T1	5		T5	442		T7	13
all_levels[10]	auto[1]	23	1			T29	3		T141	1		T131	3
all_levels[11]	auto[0]	390252	1			T1	3		T4	3		T5	553
all_levels[11]	auto[1]	18	1			T131	1		T301	1		T122	2
all_levels[12]	auto[0]	444664	1			T1	5		T4	3		T5	551
all_levels[12]	auto[1]	31	1			T244	2		T258	1		T105	3
all_levels[13]	auto[0]	268345	1			T1	1		T5	550		T6	5
all_levels[13]	auto[1]	40	1			T98	5		T120	1		T329	1
all_levels[14]	auto[0]	199015	1			T1	1		T4	1		T5	548
all_levels[14]	auto[1]	30	1			T280	1		T87	1		T330	1
all_levels[15]	auto[0]	345589	1			T1	2		T4	2		T5	551
all_levels[15]	auto[1]	117	1			T14	7		T246	1		T280	3
all_levels[16]	auto[0]	292814	1			T5	501		T7	10		T9	1
all_levels[16]	auto[1]	19	1			T331	3		T332	1		T333	1
all_levels[17]	auto[0]	182008	1			T4	2		T5	427		T6	4
all_levels[17]	auto[1]	29	1			T35	1		T147	1		T334	1
all_levels[18]	auto[0]	260476	1			T1	1		T5	342		T7	9
all_levels[18]	auto[1]	15	1			T115	1		T159	2		T238	2
all_levels[19]	auto[0]	200281	1			T1	4		T4	1		T5	312
all_levels[19]	auto[1]	17	1			T174	1		T122	1		T335	1
all_levels[20]	auto[0]	225723	1			T5	310		T7	12		T14	3
all_levels[20]	auto[1]	24	1			T133	1		T274	1		T336	3
all_levels[21]	auto[0]	180834	1			T1	16		T5	473		T7	10
all_levels[21]	auto[1]	19	1			T1	1		T98	2		T114	1
all_levels[22]	auto[0]	178843	1			T1	4		T5	551		T7	11
all_levels[22]	auto[1]	12	1			T174	1		T320	1		T337	2
all_levels[23]	auto[0]	486191	1			T5	550		T7	12		T14	4
all_levels[23]	auto[1]	20	1			T143	1		T330	2		T152	2
all_levels[24]	auto[0]	253815	1			T1	8		T4	1		T5	550
all_levels[24]	auto[1]	14	1			T1	1		T329	1		T318	1
all_levels[25]	auto[0]	184154	1			T1	4		T5	549		T7	12
all_levels[25]	auto[1]	15	1			T97	1		T119	1		T227	1
all_levels[26]	auto[0]	231715	1			T5	525		T6	111		T7	7
all_levels[26]	auto[1]	20	1			T128	2		T139	1		T338	1
all_levels[27]	auto[0]	315842	1			T5	518		T7	9		T14	4
all_levels[27]	auto[1]	14	1			T179	1		T339	4		T210	1
all_levels[28]	auto[0]	202645	1			T4	1		T5	521		T7	12
all_levels[28]	auto[1]	12	1			T301	2		T182	1		T215	2
all_levels[29]	auto[0]	209680	1			T1	3		T5	518		T7	16
all_levels[29]	auto[1]	17	1			T241	1		T150	1		T177	1
all_levels[30]	auto[0]	391826	1			T5	519		T7	13		T14	3
all_levels[30]	auto[1]	15	1			T37	2		T212	1		T340	1
all_levels[31]	auto[0]	486169	1			T1	3		T4	2		T5	756
all_levels[31]	auto[1]	24	1			T1	1		T4	1		T8	2
all_levels[32]	auto[0]	12800750	1			T1	1		T4	2		T5	79676
all_levels[32]	auto[1]	483	1			T8	4		T9	1		T28	1