Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	841	1			T5	4		T7	4		T14	7
all_values[1]	841	1			T5	4		T7	4		T14	7
all_values[2]	841	1			T5	4		T7	4		T14	7
all_values[3]	841	1			T5	4		T7	4		T14	7
all_values[4]	841	1			T5	4		T7	4		T14	7
all_values[5]	841	1			T5	4		T7	4		T14	7
all_values[6]	841	1			T5	4		T7	4		T14	7
all_values[7]	841	1			T5	4		T7	4		T14	7
all_values[8]	841	1			T5	4		T7	4		T14	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4064

1

T5

24

T7

24

T14

35

auto[1]

3505

1

T5

12

T7

12

T14

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2538

1

T5

12

T7

13

T14

17

auto[1]

5031

1

T5

24

T7

23

T14

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4505

1

T5

23

T7

21

T14

34

auto[1]

3064

1

T5

13

T7

15

T14

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	271	1			T5	1		T7	1		T14	1
all_values[0]	auto[0]	auto[1]	auto[1]	229	1			T5	2		T7	1		T14	3
all_values[0]	auto[1]	auto[0]	auto[1]	196	1			T5	1		T7	1		T14	1
all_values[0]	auto[1]	auto[1]	auto[1]	145	1			T7	1		T14	2		T23	2
all_values[1]	auto[0]	auto[0]	auto[0]	253	1			T5	1		T7	1		T14	3
all_values[1]	auto[0]	auto[1]	auto[0]	241	1			T5	1		T14	1		T23	4
all_values[1]	auto[1]	auto[0]	auto[1]	190	1			T7	3		T14	3		T23	3
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T5	2		T23	4		T12	3
all_values[2]	auto[0]	auto[0]	auto[0]	192	1			T5	3		T14	1		T23	4
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T14	1		T12	1		T26	1
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T5	1		T7	1		T14	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T7	1		T91	4		T108	3
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T7	1		T14	4		T23	5
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T7	1		T23	1		T12	1
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T23	3		T12	2		T26	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T5	1		T23	1		T26	1
all_values[3]	auto[0]	auto[1]	auto[0]	169	1			T5	1		T7	1		T14	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T7	1		T14	3		T23	1
all_values[3]	auto[1]	auto[0]	auto[1]	196	1			T5	2		T7	1		T23	6
all_values[3]	auto[1]	auto[1]	auto[1]	136	1			T7	1		T14	2		T23	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T5	2		T7	3		T14	2
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T5	1		T23	2		T12	1
all_values[4]	auto[0]	auto[1]	auto[0]	163	1			T7	1		T14	1		T23	2
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T23	1		T26	2		T15	4
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T5	1		T14	1		T23	2
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T14	3		T23	4		T12	1
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T5	3		T7	4		T14	1
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T14	1		T23	1		T12	1
all_values[5]	auto[0]	auto[1]	auto[0]	165	1			T14	1		T23	4		T12	4
all_values[5]	auto[0]	auto[1]	auto[1]	88	1			T14	1		T23	1		T34	2
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T5	1		T14	3		T23	2
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T23	1		T12	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T14	1		T23	4		T12	3
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T5	1		T7	1		T23	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T23	3		T12	1		T26	1
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T5	1		T14	2		T23	1
all_values[6]	auto[1]	auto[0]	auto[1]	195	1			T5	1		T7	3		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T5	1		T14	2		T23	3
all_values[7]	auto[0]	auto[0]	auto[0]	187	1			T7	2		T14	2		T23	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T7	1		T14	1		T23	1
all_values[7]	auto[0]	auto[1]	auto[0]	157	1			T14	1		T23	3		T26	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T5	1		T23	1		T26	1
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T5	2		T7	1		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T5	1		T14	1		T23	4
all_values[8]	auto[0]	auto[0]	auto[1]	274	1			T5	2		T14	4		T23	5
all_values[8]	auto[0]	auto[1]	auto[1]	234	1			T5	1		T7	2		T23	2
all_values[8]	auto[1]	auto[0]	auto[1]	183	1			T5	1		T7	1		T14	1
all_values[8]	auto[1]	auto[1]	auto[1]	150	1			T7	1		T14	2		T23	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal