Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1317
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T1257 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1150489940 Jul 27 06:19:29 PM PDT 24 Jul 27 06:19:31 PM PDT 24 28808398 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_intr_test.2836809733 Jul 27 06:18:58 PM PDT 24 Jul 27 06:18:59 PM PDT 24 15898489 ps
T1259 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3348473669 Jul 27 06:19:28 PM PDT 24 Jul 27 06:19:30 PM PDT 24 94489560 ps
T1260 /workspace/coverage/cover_reg_top/40.uart_intr_test.3509687657 Jul 27 06:19:39 PM PDT 24 Jul 27 06:19:40 PM PDT 24 199866960 ps
T77 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2137421569 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 52485099 ps
T1261 /workspace/coverage/cover_reg_top/3.uart_tl_errors.530257065 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:10 PM PDT 24 57154178 ps
T74 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3693238528 Jul 27 06:19:22 PM PDT 24 Jul 27 06:19:23 PM PDT 24 162742467 ps
T79 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2224395373 Jul 27 06:19:30 PM PDT 24 Jul 27 06:19:32 PM PDT 24 168107007 ps
T110 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3782608380 Jul 27 06:19:30 PM PDT 24 Jul 27 06:19:31 PM PDT 24 78115945 ps
T1262 /workspace/coverage/cover_reg_top/48.uart_intr_test.428269460 Jul 27 06:19:48 PM PDT 24 Jul 27 06:19:48 PM PDT 24 32118281 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1895364779 Jul 27 06:18:57 PM PDT 24 Jul 27 06:18:58 PM PDT 24 13590848 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2214119795 Jul 27 06:19:31 PM PDT 24 Jul 27 06:19:32 PM PDT 24 94368265 ps
T1265 /workspace/coverage/cover_reg_top/46.uart_intr_test.3445861431 Jul 27 06:19:49 PM PDT 24 Jul 27 06:19:50 PM PDT 24 42188187 ps
T1266 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3700010146 Jul 27 06:19:22 PM PDT 24 Jul 27 06:19:22 PM PDT 24 51643866 ps
T1267 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3776830272 Jul 27 06:19:05 PM PDT 24 Jul 27 06:19:06 PM PDT 24 70236905 ps
T1268 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2551429341 Jul 27 06:19:19 PM PDT 24 Jul 27 06:19:20 PM PDT 24 135641656 ps
T1269 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.882580675 Jul 27 06:19:37 PM PDT 24 Jul 27 06:19:38 PM PDT 24 26982220 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_tl_errors.1738236472 Jul 27 06:19:02 PM PDT 24 Jul 27 06:19:05 PM PDT 24 46724985 ps
T1271 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2224270822 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 270882437 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3124105658 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:09 PM PDT 24 13579744 ps
T1273 /workspace/coverage/cover_reg_top/9.uart_intr_test.1927837947 Jul 27 06:19:20 PM PDT 24 Jul 27 06:19:20 PM PDT 24 23851626 ps
T1274 /workspace/coverage/cover_reg_top/35.uart_intr_test.1653580602 Jul 27 06:19:41 PM PDT 24 Jul 27 06:19:41 PM PDT 24 42803872 ps
T1275 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3071216272 Jul 27 06:19:19 PM PDT 24 Jul 27 06:19:21 PM PDT 24 616347240 ps
T1276 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3666419956 Jul 27 06:19:20 PM PDT 24 Jul 27 06:19:21 PM PDT 24 55752165 ps
T1277 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2285485654 Jul 27 06:19:19 PM PDT 24 Jul 27 06:19:20 PM PDT 24 77336044 ps
T1278 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3776495553 Jul 27 06:19:29 PM PDT 24 Jul 27 06:19:31 PM PDT 24 368162079 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3858111236 Jul 27 06:18:58 PM PDT 24 Jul 27 06:19:00 PM PDT 24 779142704 ps
T1280 /workspace/coverage/cover_reg_top/22.uart_intr_test.1350058637 Jul 27 06:19:41 PM PDT 24 Jul 27 06:19:41 PM PDT 24 24447245 ps
T1281 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1538115094 Jul 27 06:19:11 PM PDT 24 Jul 27 06:19:11 PM PDT 24 63078716 ps
T1282 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1104646912 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 85619537 ps
T1283 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3069685069 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 27983634 ps
T1284 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2114065347 Jul 27 06:19:04 PM PDT 24 Jul 27 06:19:05 PM PDT 24 17914365 ps
T1285 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.498153595 Jul 27 06:18:58 PM PDT 24 Jul 27 06:18:59 PM PDT 24 58930510 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_intr_test.3422861821 Jul 27 06:19:06 PM PDT 24 Jul 27 06:19:07 PM PDT 24 47040748 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2014581707 Jul 27 06:19:07 PM PDT 24 Jul 27 06:19:08 PM PDT 24 19337951 ps
T1288 /workspace/coverage/cover_reg_top/42.uart_intr_test.1965530181 Jul 27 06:19:38 PM PDT 24 Jul 27 06:19:38 PM PDT 24 63246041 ps
T1289 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1606281898 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:09 PM PDT 24 401938321 ps
T1290 /workspace/coverage/cover_reg_top/5.uart_intr_test.3296180401 Jul 27 06:19:09 PM PDT 24 Jul 27 06:19:10 PM PDT 24 16133711 ps
T1291 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2932393841 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:29 PM PDT 24 32497361 ps
T1292 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4212517980 Jul 27 06:19:28 PM PDT 24 Jul 27 06:19:29 PM PDT 24 27587261 ps
T1293 /workspace/coverage/cover_reg_top/34.uart_intr_test.2244143954 Jul 27 06:19:38 PM PDT 24 Jul 27 06:19:38 PM PDT 24 39242530 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_csr_rw.475621817 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 47278544 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2648266630 Jul 27 06:19:31 PM PDT 24 Jul 27 06:19:32 PM PDT 24 49575238 ps
T1296 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2682836746 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:27 PM PDT 24 18299758 ps
T1297 /workspace/coverage/cover_reg_top/15.uart_intr_test.244969337 Jul 27 06:19:31 PM PDT 24 Jul 27 06:19:32 PM PDT 24 21387967 ps
T1298 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1979523875 Jul 27 06:19:18 PM PDT 24 Jul 27 06:19:18 PM PDT 24 21370673 ps
T1299 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1922496052 Jul 27 06:19:26 PM PDT 24 Jul 27 06:19:27 PM PDT 24 39351677 ps
T1300 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2277661283 Jul 27 06:19:38 PM PDT 24 Jul 27 06:19:39 PM PDT 24 37244288 ps
T1301 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4287997407 Jul 27 06:19:33 PM PDT 24 Jul 27 06:19:35 PM PDT 24 78629944 ps
T1302 /workspace/coverage/cover_reg_top/21.uart_intr_test.696407384 Jul 27 06:19:37 PM PDT 24 Jul 27 06:19:38 PM PDT 24 21978400 ps
T1303 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2961120418 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:28 PM PDT 24 65328249 ps
T1304 /workspace/coverage/cover_reg_top/5.uart_tl_errors.164590788 Jul 27 06:19:11 PM PDT 24 Jul 27 06:19:12 PM PDT 24 67400968 ps
T1305 /workspace/coverage/cover_reg_top/36.uart_intr_test.2688554342 Jul 27 06:19:36 PM PDT 24 Jul 27 06:19:36 PM PDT 24 13927465 ps
T1306 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3439490965 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:09 PM PDT 24 40324856 ps
T1307 /workspace/coverage/cover_reg_top/20.uart_intr_test.2396579538 Jul 27 06:19:37 PM PDT 24 Jul 27 06:19:37 PM PDT 24 11002050 ps
T1308 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3316154014 Jul 27 06:19:06 PM PDT 24 Jul 27 06:19:07 PM PDT 24 44217049 ps
T1309 /workspace/coverage/cover_reg_top/25.uart_intr_test.2491855584 Jul 27 06:19:37 PM PDT 24 Jul 27 06:19:38 PM PDT 24 13074015 ps
T1310 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3510577599 Jul 27 06:19:19 PM PDT 24 Jul 27 06:19:20 PM PDT 24 41530879 ps
T1311 /workspace/coverage/cover_reg_top/39.uart_intr_test.3066251596 Jul 27 06:19:40 PM PDT 24 Jul 27 06:19:40 PM PDT 24 42755491 ps
T1312 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3059167411 Jul 27 06:18:58 PM PDT 24 Jul 27 06:18:59 PM PDT 24 53383655 ps
T62 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3366908571 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:08 PM PDT 24 32894245 ps
T1313 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1332844958 Jul 27 06:18:57 PM PDT 24 Jul 27 06:18:58 PM PDT 24 58257601 ps
T1314 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.116313420 Jul 27 06:19:08 PM PDT 24 Jul 27 06:19:11 PM PDT 24 443997276 ps
T1315 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3843480500 Jul 27 06:19:29 PM PDT 24 Jul 27 06:19:30 PM PDT 24 110835333 ps
T1316 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2007570575 Jul 27 06:19:27 PM PDT 24 Jul 27 06:19:30 PM PDT 24 237485704 ps
T1317 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3769600846 Jul 27 06:18:58 PM PDT 24 Jul 27 06:19:00 PM PDT 24 96428350 ps
T57 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2445690306 Jul 27 06:19:09 PM PDT 24 Jul 27 06:19:10 PM PDT 24 16653632 ps

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2983493401
Short name T5
Test name
Test status
Simulation time 789166305822 ps
CPU time 730.3 seconds
Started Jul 27 06:30:51 PM PDT 24
Finished Jul 27 06:43:01 PM PDT 24
Peak memory 216756 kb
Host smart-18caea40-0f06-4bf6-bb13-fc4ae112c311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983493401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2983493401
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.376616061
Short name T245
Test name
Test status
Simulation time 61143816331 ps
CPU time 355.72 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200236 kb
Host smart-2803ccff-fd5e-467c-b858-352ba9c9048b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376616061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.376616061
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2787094993
Short name T35
Test name
Test status
Simulation time 181293644612 ps
CPU time 1588.17 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:50:18 PM PDT 24
Peak memory 216748 kb
Host smart-f4cb7ef1-cf63-4f38-be20-749b7345a388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787094993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2787094993
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.881961415
Short name T12
Test name
Test status
Simulation time 199338544141 ps
CPU time 159.6 seconds
Started Jul 27 06:25:35 PM PDT 24
Finished Jul 27 06:28:15 PM PDT 24
Peak memory 216712 kb
Host smart-dc1ba4a0-d863-4289-bf3f-6f31a9040f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881961415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.881961415
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1407805402
Short name T24
Test name
Test status
Simulation time 137693299089 ps
CPU time 3362.51 seconds
Started Jul 27 06:30:20 PM PDT 24
Finished Jul 27 07:26:23 PM PDT 24
Peak memory 233240 kb
Host smart-a2a9d3f2-b772-4f4e-b3f7-b46694addd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407805402 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1407805402
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.259743463
Short name T91
Test name
Test status
Simulation time 489270349612 ps
CPU time 520.48 seconds
Started Jul 27 06:30:12 PM PDT 24
Finished Jul 27 06:38:52 PM PDT 24
Peak memory 229184 kb
Host smart-ed33a536-61f7-4b20-83c1-8de5fadfaeec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259743463 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.259743463
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3275596054
Short name T20
Test name
Test status
Simulation time 481642556 ps
CPU time 0.84 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:11 PM PDT 24
Peak memory 218364 kb
Host smart-4afaca57-316e-47ef-a577-da73ed230ccd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275596054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3275596054
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1221440355
Short name T1
Test name
Test status
Simulation time 143932665477 ps
CPU time 455.88 seconds
Started Jul 27 06:30:35 PM PDT 24
Finished Jul 27 06:38:11 PM PDT 24
Peak memory 200228 kb
Host smart-bcb28c36-0907-4eec-9a7f-90031c2579d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221440355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1221440355
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.342111470
Short name T147
Test name
Test status
Simulation time 518659728673 ps
CPU time 853.04 seconds
Started Jul 27 06:28:56 PM PDT 24
Finished Jul 27 06:43:09 PM PDT 24
Peak memory 229792 kb
Host smart-526b2d3b-6dff-4006-a39f-a12e759598de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342111470 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.342111470
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3313876603
Short name T15
Test name
Test status
Simulation time 142479219350 ps
CPU time 315.69 seconds
Started Jul 27 06:26:31 PM PDT 24
Finished Jul 27 06:31:47 PM PDT 24
Peak memory 216864 kb
Host smart-57ea4c2b-d56b-459e-af3e-abeec1dbe678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313876603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3313876603
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1422950742
Short name T145
Test name
Test status
Simulation time 174333714223 ps
CPU time 188.62 seconds
Started Jul 27 06:27:07 PM PDT 24
Finished Jul 27 06:30:16 PM PDT 24
Peak memory 200148 kb
Host smart-b0fc13d4-5c40-4ec1-b2cf-87961828983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422950742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1422950742
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1572456290
Short name T260
Test name
Test status
Simulation time 143478513354 ps
CPU time 155.16 seconds
Started Jul 27 06:23:02 PM PDT 24
Finished Jul 27 06:25:37 PM PDT 24
Peak memory 200228 kb
Host smart-e41244f5-5e3a-49e1-9062-fc5eafe2f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572456290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1572456290
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1063897335
Short name T255
Test name
Test status
Simulation time 48212884930 ps
CPU time 249.06 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:29:53 PM PDT 24
Peak memory 200112 kb
Host smart-a1f68571-7062-4ddf-93c1-6ecb53077589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063897335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1063897335
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1538475929
Short name T179
Test name
Test status
Simulation time 235116136835 ps
CPU time 910.25 seconds
Started Jul 27 06:25:15 PM PDT 24
Finished Jul 27 06:40:25 PM PDT 24
Peak memory 224956 kb
Host smart-3d092ca5-dbb6-4311-a055-d8867fb44455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538475929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1538475929
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2192064922
Short name T267
Test name
Test status
Simulation time 233046921502 ps
CPU time 258.65 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:34:01 PM PDT 24
Peak memory 200200 kb
Host smart-f2ab2cc3-34ee-477d-bfd5-5cc42de48b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192064922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2192064922
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2232908098
Short name T70
Test name
Test status
Simulation time 390535550 ps
CPU time 1.41 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 200368 kb
Host smart-992fb3de-741d-4de6-8b11-79fa80cb712a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232908098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2232908098
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3554438152
Short name T46
Test name
Test status
Simulation time 393098508044 ps
CPU time 1446.04 seconds
Started Jul 27 06:30:16 PM PDT 24
Finished Jul 27 06:54:22 PM PDT 24
Peak memory 231332 kb
Host smart-7c133905-8101-420e-99d6-d81785c313d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554438152 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3554438152
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2152312255
Short name T23
Test name
Test status
Simulation time 138482330882 ps
CPU time 666.33 seconds
Started Jul 27 06:23:59 PM PDT 24
Finished Jul 27 06:35:06 PM PDT 24
Peak memory 216912 kb
Host smart-077da1ef-6c2a-41a1-be75-273117f190d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152312255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2152312255
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3714848745
Short name T412
Test name
Test status
Simulation time 17765106 ps
CPU time 0.55 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:10 PM PDT 24
Peak memory 195620 kb
Host smart-0a6f260d-7674-4f0d-9c94-7e83e33df624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714848745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3714848745
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3946199635
Short name T54
Test name
Test status
Simulation time 19155396 ps
CPU time 0.63 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 196588 kb
Host smart-28eb6a5a-7ae7-481e-95d4-64de167f7433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946199635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3946199635
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1146289599
Short name T26
Test name
Test status
Simulation time 250354269252 ps
CPU time 1091.75 seconds
Started Jul 27 06:30:22 PM PDT 24
Finished Jul 27 06:48:34 PM PDT 24
Peak memory 231780 kb
Host smart-89a7fbfa-1af8-48dc-827f-ff35e5f1f203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146289599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1146289599
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.600249913
Short name T102
Test name
Test status
Simulation time 22157187660 ps
CPU time 38.25 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:25 PM PDT 24
Peak memory 200172 kb
Host smart-06c99122-66fc-44ae-858c-dae11b01cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600249913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.600249913
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2536962636
Short name T132
Test name
Test status
Simulation time 497438598932 ps
CPU time 1184.37 seconds
Started Jul 27 06:28:36 PM PDT 24
Finished Jul 27 06:48:21 PM PDT 24
Peak memory 227548 kb
Host smart-63c6b746-1cf0-4c4a-beb5-11c3f33f02ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536962636 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2536962636
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_intr.475076733
Short name T249
Test name
Test status
Simulation time 203423195450 ps
CPU time 476.06 seconds
Started Jul 27 06:27:18 PM PDT 24
Finished Jul 27 06:35:14 PM PDT 24
Peak memory 200164 kb
Host smart-e35b8d3f-cee2-483d-bc7f-a4fe1be170de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475076733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.475076733
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1034496657
Short name T34
Test name
Test status
Simulation time 175438852871 ps
CPU time 462.5 seconds
Started Jul 27 06:30:23 PM PDT 24
Finished Jul 27 06:38:05 PM PDT 24
Peak memory 225092 kb
Host smart-99cfdfce-eaa6-4ac5-8454-129afd3ba40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034496657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1034496657
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3519169578
Short name T40
Test name
Test status
Simulation time 176697958753 ps
CPU time 76.26 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:28:42 PM PDT 24
Peak memory 200132 kb
Host smart-6ec2698a-c951-4ac6-a613-a5fbab941d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519169578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3519169578
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.846743738
Short name T265
Test name
Test status
Simulation time 19225766800 ps
CPU time 15.22 seconds
Started Jul 27 06:25:52 PM PDT 24
Finished Jul 27 06:26:07 PM PDT 24
Peak memory 200176 kb
Host smart-5eaaee45-0d1b-4438-94f0-78efa0d5d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846743738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.846743738
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1820134710
Short name T129
Test name
Test status
Simulation time 85900391043 ps
CPU time 210.76 seconds
Started Jul 27 06:32:51 PM PDT 24
Finished Jul 27 06:36:22 PM PDT 24
Peak memory 200260 kb
Host smart-dc397c8f-07e9-4ec3-be98-5495a5ebdbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820134710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1820134710
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1041296838
Short name T143
Test name
Test status
Simulation time 74564142278 ps
CPU time 105.99 seconds
Started Jul 27 06:30:52 PM PDT 24
Finished Jul 27 06:32:38 PM PDT 24
Peak memory 200132 kb
Host smart-60ce4bf5-e9da-48b7-8643-1ba19a5bcb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041296838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1041296838
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3226622351
Short name T131
Test name
Test status
Simulation time 46690080325 ps
CPU time 19.8 seconds
Started Jul 27 06:32:16 PM PDT 24
Finished Jul 27 06:32:36 PM PDT 24
Peak memory 200196 kb
Host smart-f0e723cd-68cd-42c0-8f3d-394baf07cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226622351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3226622351
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3689283729
Short name T75
Test name
Test status
Simulation time 71824320 ps
CPU time 1.28 seconds
Started Jul 27 06:19:07 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 200208 kb
Host smart-17b54414-2375-4b8c-84b5-cab4c6c157f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689283729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3689283729
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1895891405
Short name T133
Test name
Test status
Simulation time 131498790090 ps
CPU time 26.02 seconds
Started Jul 27 06:24:10 PM PDT 24
Finished Jul 27 06:24:36 PM PDT 24
Peak memory 199856 kb
Host smart-279de73b-624f-4e45-8281-5e74219e232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895891405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1895891405
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1805631941
Short name T212
Test name
Test status
Simulation time 72345791505 ps
CPU time 50 seconds
Started Jul 27 06:32:22 PM PDT 24
Finished Jul 27 06:33:12 PM PDT 24
Peak memory 200216 kb
Host smart-39855cb6-7b70-4039-9bc8-6ba5e5c3b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805631941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1805631941
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2803002864
Short name T87
Test name
Test status
Simulation time 70286750003 ps
CPU time 208.26 seconds
Started Jul 27 06:32:34 PM PDT 24
Finished Jul 27 06:36:03 PM PDT 24
Peak memory 200124 kb
Host smart-00c265b4-ebc8-47d4-a2a2-2eb29b78d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803002864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2803002864
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4259501181
Short name T984
Test name
Test status
Simulation time 58896293813 ps
CPU time 365.23 seconds
Started Jul 27 06:30:39 PM PDT 24
Finished Jul 27 06:36:45 PM PDT 24
Peak memory 216656 kb
Host smart-13616384-ee2a-4df1-b685-2b9760b962db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259501181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4259501181
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1469178244
Short name T29
Test name
Test status
Simulation time 174886577253 ps
CPU time 136.72 seconds
Started Jul 27 06:31:07 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200172 kb
Host smart-871ca832-b757-4d01-8d3b-2e657432cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469178244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1469178244
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2380262509
Short name T190
Test name
Test status
Simulation time 225250084910 ps
CPU time 1299.49 seconds
Started Jul 27 06:24:46 PM PDT 24
Finished Jul 27 06:46:26 PM PDT 24
Peak memory 228848 kb
Host smart-f88104b1-95c0-4366-8673-8e69c4798c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380262509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2380262509
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.4049884052
Short name T227
Test name
Test status
Simulation time 432188010380 ps
CPU time 332.1 seconds
Started Jul 27 06:25:04 PM PDT 24
Finished Jul 27 06:30:36 PM PDT 24
Peak memory 208496 kb
Host smart-83384c59-38a7-4cc4-87be-a546c7030a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049884052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4049884052
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4168191692
Short name T171
Test name
Test status
Simulation time 26564218488 ps
CPU time 44.11 seconds
Started Jul 27 06:31:53 PM PDT 24
Finished Jul 27 06:32:37 PM PDT 24
Peak memory 200152 kb
Host smart-b95c5694-94e6-42fd-b4e3-6971fa455470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168191692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4168191692
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2679037196
Short name T153
Test name
Test status
Simulation time 217672716224 ps
CPU time 88.31 seconds
Started Jul 27 06:32:34 PM PDT 24
Finished Jul 27 06:34:02 PM PDT 24
Peak memory 200212 kb
Host smart-5946940c-5ac5-48d8-a5bc-0b9de1e6b146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679037196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2679037196
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3652728487
Short name T292
Test name
Test status
Simulation time 90284038614 ps
CPU time 143.97 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:31:11 PM PDT 24
Peak memory 200252 kb
Host smart-5c678f9d-b002-41da-89cc-afdc8d936ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652728487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3652728487
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/11.uart_stress_all.16835102
Short name T158
Test name
Test status
Simulation time 463613590643 ps
CPU time 144.55 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:26:42 PM PDT 24
Peak memory 200160 kb
Host smart-bf5eb5c5-6a3c-4f03-a739-702136d4c6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16835102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.16835102
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3112334044
Short name T181
Test name
Test status
Simulation time 92238422817 ps
CPU time 307.87 seconds
Started Jul 27 06:32:14 PM PDT 24
Finished Jul 27 06:37:22 PM PDT 24
Peak memory 200256 kb
Host smart-cb128e61-5b54-4e2c-a0bd-cd4dd59c72d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112334044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3112334044
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1401747647
Short name T322
Test name
Test status
Simulation time 57664976401 ps
CPU time 1863.31 seconds
Started Jul 27 06:30:12 PM PDT 24
Finished Jul 27 07:01:16 PM PDT 24
Peak memory 216748 kb
Host smart-a1a942b1-3c56-409c-8cfb-913750983e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401747647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1401747647
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2666220315
Short name T200
Test name
Test status
Simulation time 196536466665 ps
CPU time 288.75 seconds
Started Jul 27 06:31:11 PM PDT 24
Finished Jul 27 06:36:00 PM PDT 24
Peak memory 200208 kb
Host smart-696f610c-b966-4749-b6f0-2ab28971bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666220315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2666220315
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2449120681
Short name T105
Test name
Test status
Simulation time 130854296767 ps
CPU time 41.81 seconds
Started Jul 27 06:31:08 PM PDT 24
Finished Jul 27 06:31:50 PM PDT 24
Peak memory 200176 kb
Host smart-d24d67e8-6023-4152-95c3-93b0d2a74c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449120681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2449120681
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1258562242
Short name T163
Test name
Test status
Simulation time 56274655665 ps
CPU time 12.96 seconds
Started Jul 27 06:32:23 PM PDT 24
Finished Jul 27 06:32:36 PM PDT 24
Peak memory 200136 kb
Host smart-165b7c26-eff6-4d73-b3f9-70f8f119afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258562242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1258562242
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1562961272
Short name T207
Test name
Test status
Simulation time 72624471833 ps
CPU time 163.82 seconds
Started Jul 27 06:32:22 PM PDT 24
Finished Jul 27 06:35:06 PM PDT 24
Peak memory 200212 kb
Host smart-7af6b4ac-f4ba-4141-8bd6-c1ed6e38c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562961272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1562961272
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1243227466
Short name T28
Test name
Test status
Simulation time 135448734071 ps
CPU time 32.66 seconds
Started Jul 27 06:32:59 PM PDT 24
Finished Jul 27 06:33:32 PM PDT 24
Peak memory 200196 kb
Host smart-baed4be1-6d59-4252-8000-bf3465b4c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243227466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1243227466
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1712399899
Short name T213
Test name
Test status
Simulation time 76658771114 ps
CPU time 47.19 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:24:08 PM PDT 24
Peak memory 200244 kb
Host smart-5c4c6a78-759a-4089-b3d4-f2016e0d3f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712399899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1712399899
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1505135574
Short name T156
Test name
Test status
Simulation time 99813004634 ps
CPU time 34.17 seconds
Started Jul 27 06:31:00 PM PDT 24
Finished Jul 27 06:31:34 PM PDT 24
Peak memory 200168 kb
Host smart-a6d3267a-0a28-4442-89dd-26b84a3d14fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505135574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1505135574
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_perf.739866600
Short name T288
Test name
Test status
Simulation time 21800727730 ps
CPU time 987.45 seconds
Started Jul 27 06:23:15 PM PDT 24
Finished Jul 27 06:39:42 PM PDT 24
Peak memory 200272 kb
Host smart-83851086-5543-4b5c-988a-eaef97573e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739866600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.739866600
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2023990750
Short name T215
Test name
Test status
Simulation time 71389034185 ps
CPU time 99.81 seconds
Started Jul 27 06:31:08 PM PDT 24
Finished Jul 27 06:32:48 PM PDT 24
Peak memory 200232 kb
Host smart-1caf65cc-24f5-41ba-927d-06b69a029864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023990750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2023990750
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.836590827
Short name T1094
Test name
Test status
Simulation time 135759835542 ps
CPU time 210.26 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:34:47 PM PDT 24
Peak memory 199984 kb
Host smart-394dc5f8-e7e0-4860-b303-50be10299be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836590827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.836590827
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.358702679
Short name T189
Test name
Test status
Simulation time 46019994788 ps
CPU time 20.17 seconds
Started Jul 27 06:31:18 PM PDT 24
Finished Jul 27 06:31:39 PM PDT 24
Peak memory 200144 kb
Host smart-e6a97a8f-3037-418b-84aa-5add57b31caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358702679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.358702679
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3938975557
Short name T139
Test name
Test status
Simulation time 132569551356 ps
CPU time 70 seconds
Started Jul 27 06:31:16 PM PDT 24
Finished Jul 27 06:32:26 PM PDT 24
Peak memory 200116 kb
Host smart-6959a5fb-ef5a-48cb-84f8-f639d70035fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938975557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3938975557
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3996376547
Short name T394
Test name
Test status
Simulation time 23628393936 ps
CPU time 29.91 seconds
Started Jul 27 06:24:26 PM PDT 24
Finished Jul 27 06:24:56 PM PDT 24
Peak memory 200216 kb
Host smart-05e9c0a0-44c9-4f32-8b96-52461bd1cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996376547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3996376547
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1774692317
Short name T218
Test name
Test status
Simulation time 58914585939 ps
CPU time 25.7 seconds
Started Jul 27 06:31:26 PM PDT 24
Finished Jul 27 06:31:52 PM PDT 24
Peak memory 200160 kb
Host smart-ee1445bf-aaf6-45d3-af3e-951f6c3fea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774692317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1774692317
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.830293027
Short name T185
Test name
Test status
Simulation time 217403527879 ps
CPU time 358.72 seconds
Started Jul 27 06:31:28 PM PDT 24
Finished Jul 27 06:37:27 PM PDT 24
Peak memory 200100 kb
Host smart-b8c5e176-a7a9-4551-a85e-5bf4105aaf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830293027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.830293027
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1395833088
Short name T1118
Test name
Test status
Simulation time 83308839020 ps
CPU time 34.34 seconds
Started Jul 27 06:31:37 PM PDT 24
Finished Jul 27 06:32:11 PM PDT 24
Peak memory 200168 kb
Host smart-2ff930b1-19b7-42d8-8bf6-c1b5a748c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395833088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1395833088
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.311032828
Short name T222
Test name
Test status
Simulation time 98014636482 ps
CPU time 101.23 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:26:25 PM PDT 24
Peak memory 200228 kb
Host smart-37ee957c-bc9f-405c-a209-3d3ea7d66c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311032828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.311032828
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3789584644
Short name T233
Test name
Test status
Simulation time 56978033648 ps
CPU time 25.98 seconds
Started Jul 27 06:31:53 PM PDT 24
Finished Jul 27 06:32:19 PM PDT 24
Peak memory 200140 kb
Host smart-dc4abdd7-cb7e-48bc-8693-7b799672e12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789584644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3789584644
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2069335641
Short name T230
Test name
Test status
Simulation time 203852049333 ps
CPU time 89.02 seconds
Started Jul 27 06:32:01 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 200216 kb
Host smart-7a49e597-12df-443a-ab57-2ffa1f525104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069335641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2069335641
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3002614978
Short name T159
Test name
Test status
Simulation time 71082402377 ps
CPU time 28.84 seconds
Started Jul 27 06:32:16 PM PDT 24
Finished Jul 27 06:32:45 PM PDT 24
Peak memory 200152 kb
Host smart-cac3a576-1b2f-4b66-b1da-81b4e417f7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002614978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3002614978
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.319246006
Short name T232
Test name
Test status
Simulation time 25730890284 ps
CPU time 24.14 seconds
Started Jul 27 06:32:19 PM PDT 24
Finished Jul 27 06:32:43 PM PDT 24
Peak memory 200188 kb
Host smart-fe3ca186-6f31-4426-8ff1-c59c90ab96c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319246006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.319246006
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3246246909
Short name T103
Test name
Test status
Simulation time 89711702777 ps
CPU time 34.27 seconds
Started Jul 27 06:32:22 PM PDT 24
Finished Jul 27 06:32:57 PM PDT 24
Peak memory 200044 kb
Host smart-e07acbcd-26c3-4253-a742-523114f9f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246246909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3246246909
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2050464845
Short name T320
Test name
Test status
Simulation time 82976472180 ps
CPU time 38.4 seconds
Started Jul 27 06:32:23 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 200240 kb
Host smart-ab72ea17-1e3b-4de1-b659-c8b191f896f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050464845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2050464845
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.638250987
Short name T236
Test name
Test status
Simulation time 110446444625 ps
CPU time 138.54 seconds
Started Jul 27 06:32:34 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 200184 kb
Host smart-91e1ab90-a803-4858-a37f-74733fc72d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638250987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.638250987
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3981314478
Short name T876
Test name
Test status
Simulation time 63586967421 ps
CPU time 88.52 seconds
Started Jul 27 06:32:41 PM PDT 24
Finished Jul 27 06:34:09 PM PDT 24
Peak memory 200232 kb
Host smart-ee3831bc-5fd9-4f36-9368-c1da884c9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981314478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3981314478
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4133543311
Short name T237
Test name
Test status
Simulation time 37057792917 ps
CPU time 29.4 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:22 PM PDT 24
Peak memory 200176 kb
Host smart-acdb3983-3d10-476a-a935-b1a69d17b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133543311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4133543311
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2637285402
Short name T231
Test name
Test status
Simulation time 23424326691 ps
CPU time 50.1 seconds
Started Jul 27 06:32:50 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 200228 kb
Host smart-3aeb98f6-4a46-4574-b0b4-f4ec7c255e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637285402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2637285402
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.391465050
Short name T217
Test name
Test status
Simulation time 43945479067 ps
CPU time 67.48 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:31:29 PM PDT 24
Peak memory 200104 kb
Host smart-ba0ed3d1-bbce-4dc8-a0b2-2fba973513a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391465050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.391465050
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1935519770
Short name T49
Test name
Test status
Simulation time 219578766864 ps
CPU time 564.52 seconds
Started Jul 27 06:30:42 PM PDT 24
Finished Jul 27 06:40:06 PM PDT 24
Peak memory 212864 kb
Host smart-ae48e2d8-cae2-4eec-9494-2174a4a40a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935519770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1935519770
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1216694828
Short name T61
Test name
Test status
Simulation time 33113409 ps
CPU time 0.75 seconds
Started Jul 27 06:18:57 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 197244 kb
Host smart-8daea67c-f140-4447-88f4-29cb4756a9ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216694828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1216694828
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2050080107
Short name T1209
Test name
Test status
Simulation time 127425160 ps
CPU time 1.35 seconds
Started Jul 27 06:19:00 PM PDT 24
Finished Jul 27 06:19:01 PM PDT 24
Peak memory 198384 kb
Host smart-ecb5c591-0a5b-43da-9249-b36ddd2af42f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050080107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2050080107
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3316154014
Short name T1308
Test name
Test status
Simulation time 44217049 ps
CPU time 0.56 seconds
Started Jul 27 06:19:06 PM PDT 24
Finished Jul 27 06:19:07 PM PDT 24
Peak memory 196304 kb
Host smart-e6e1231b-dce8-4837-a462-9f9ac4d364bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316154014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3316154014
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3776830272
Short name T1267
Test name
Test status
Simulation time 70236905 ps
CPU time 1.05 seconds
Started Jul 27 06:19:05 PM PDT 24
Finished Jul 27 06:19:06 PM PDT 24
Peak memory 200704 kb
Host smart-f96321f7-c9fc-4f10-9433-33dab38cab31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776830272 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3776830272
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2824236829
Short name T1182
Test name
Test status
Simulation time 142203353 ps
CPU time 0.58 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:02 PM PDT 24
Peak memory 196292 kb
Host smart-aa06ab9a-a586-4340-be68-cec6d22edc37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824236829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2824236829
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3845873313
Short name T1254
Test name
Test status
Simulation time 20548410 ps
CPU time 0.56 seconds
Started Jul 27 06:19:01 PM PDT 24
Finished Jul 27 06:19:02 PM PDT 24
Peak memory 195304 kb
Host smart-4e0c304b-460c-4c4e-b88a-bb804fb70671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845873313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3845873313
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2867107813
Short name T1244
Test name
Test status
Simulation time 14821907 ps
CPU time 0.68 seconds
Started Jul 27 06:18:59 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 196852 kb
Host smart-c9e18df2-2233-453d-b14b-8d3840a9c387
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867107813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2867107813
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3769600846
Short name T1317
Test name
Test status
Simulation time 96428350 ps
CPU time 1.71 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:19:00 PM PDT 24
Peak memory 200932 kb
Host smart-29e17d8b-fce6-4870-aa20-9b02179800a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769600846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3769600846
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.611590466
Short name T73
Test name
Test status
Simulation time 335603984 ps
CPU time 1.29 seconds
Started Jul 27 06:18:59 PM PDT 24
Finished Jul 27 06:19:01 PM PDT 24
Peak memory 200040 kb
Host smart-e619851b-af4d-4959-a689-5e38125c0d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611590466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.611590466
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1369850403
Short name T1206
Test name
Test status
Simulation time 21779737 ps
CPU time 0.7 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:02 PM PDT 24
Peak memory 196472 kb
Host smart-8359806c-274b-45f1-aa2e-5d75cbae00f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369850403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1369850403
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3858111236
Short name T1279
Test name
Test status
Simulation time 779142704 ps
CPU time 1.59 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:19:00 PM PDT 24
Peak memory 199020 kb
Host smart-f4085561-7588-42d8-87a1-646e5309a204
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858111236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3858111236
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1895364779
Short name T1263
Test name
Test status
Simulation time 13590848 ps
CPU time 0.63 seconds
Started Jul 27 06:18:57 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 196328 kb
Host smart-afd87ac4-897d-4fa9-aafd-01e27ae0bb20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895364779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1895364779
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2114065347
Short name T1284
Test name
Test status
Simulation time 17914365 ps
CPU time 0.66 seconds
Started Jul 27 06:19:04 PM PDT 24
Finished Jul 27 06:19:05 PM PDT 24
Peak memory 197996 kb
Host smart-13e3760b-24fc-4069-b9ec-64302f7626eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114065347 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2114065347
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3730541097
Short name T1214
Test name
Test status
Simulation time 32703694 ps
CPU time 0.62 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 196368 kb
Host smart-3c8bafb1-e902-4fa7-ab03-2b1c0fb0c915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730541097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3730541097
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2340349023
Short name T1202
Test name
Test status
Simulation time 15108346 ps
CPU time 0.57 seconds
Started Jul 27 06:19:00 PM PDT 24
Finished Jul 27 06:19:01 PM PDT 24
Peak memory 195220 kb
Host smart-70ff9d25-9a9b-4458-a008-28566eb67019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340349023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2340349023
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2397667427
Short name T68
Test name
Test status
Simulation time 147767247 ps
CPU time 0.64 seconds
Started Jul 27 06:18:57 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 195376 kb
Host smart-ba49cd86-e7e4-44fc-8d4d-0898cba3176b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397667427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2397667427
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.334713618
Short name T1252
Test name
Test status
Simulation time 259817745 ps
CPU time 1.71 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:19:00 PM PDT 24
Peak memory 200904 kb
Host smart-833fe19f-3536-4634-a13b-450c18000c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334713618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.334713618
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.715256608
Short name T1256
Test name
Test status
Simulation time 126301979 ps
CPU time 0.92 seconds
Started Jul 27 06:18:59 PM PDT 24
Finished Jul 27 06:19:00 PM PDT 24
Peak memory 199852 kb
Host smart-fbbcfaa7-8818-4a18-a289-79aaed1667d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715256608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.715256608
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2648266630
Short name T1295
Test name
Test status
Simulation time 49575238 ps
CPU time 0.81 seconds
Started Jul 27 06:19:31 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 199904 kb
Host smart-e367b733-18ee-4bd0-b625-f17c52f2ed7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648266630 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2648266630
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4230792824
Short name T1231
Test name
Test status
Simulation time 15634659 ps
CPU time 0.58 seconds
Started Jul 27 06:19:17 PM PDT 24
Finished Jul 27 06:19:18 PM PDT 24
Peak memory 196296 kb
Host smart-fb6482d2-e5b8-4358-87ce-e7b206b0ca09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230792824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4230792824
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2206370672
Short name T1255
Test name
Test status
Simulation time 42091792 ps
CPU time 0.58 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 195288 kb
Host smart-68e47b2e-56d7-4be9-b298-c4478d09fadf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206370672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2206370672
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3312387217
Short name T1210
Test name
Test status
Simulation time 52678102 ps
CPU time 0.66 seconds
Started Jul 27 06:19:30 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 196304 kb
Host smart-43fce673-d238-4ee1-9acb-6a7280c95b27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312387217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3312387217
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1289870883
Short name T1199
Test name
Test status
Simulation time 405394918 ps
CPU time 2.31 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:21 PM PDT 24
Peak memory 200908 kb
Host smart-e9d18540-113c-4414-9614-80156da7a20d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289870883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1289870883
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3071216272
Short name T1275
Test name
Test status
Simulation time 616347240 ps
CPU time 1.27 seconds
Started Jul 27 06:19:19 PM PDT 24
Finished Jul 27 06:19:21 PM PDT 24
Peak memory 200088 kb
Host smart-1d62ec50-e112-4141-8382-76c97640b464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071216272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3071216272
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2389970349
Short name T1212
Test name
Test status
Simulation time 41044897 ps
CPU time 0.94 seconds
Started Jul 27 06:19:30 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 200688 kb
Host smart-de153efb-b752-4b7f-82c5-b39ecb92c55c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389970349 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2389970349
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3906594413
Short name T69
Test name
Test status
Simulation time 48937093 ps
CPU time 0.62 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 196372 kb
Host smart-229a9147-bf1d-48b0-8baa-c5da66e621d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906594413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3906594413
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1358486523
Short name T1226
Test name
Test status
Simulation time 44240614 ps
CPU time 0.57 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 195184 kb
Host smart-350bba37-3a1c-4991-a7e1-c6005bde8f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358486523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1358486523
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4212517980
Short name T1292
Test name
Test status
Simulation time 27587261 ps
CPU time 0.73 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 196836 kb
Host smart-891dc0b4-21aa-4cd0-b668-dd8f34900dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212517980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.4212517980
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1104646912
Short name T1282
Test name
Test status
Simulation time 85619537 ps
CPU time 1.39 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 200944 kb
Host smart-70a8ea81-ef60-4973-b9fe-e6836fa1a2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104646912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1104646912
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3348473669
Short name T1259
Test name
Test status
Simulation time 94489560 ps
CPU time 1.26 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 200264 kb
Host smart-3b748160-e40c-413b-a054-55a8c767bfa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348473669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3348473669
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3653491065
Short name T1235
Test name
Test status
Simulation time 118229502 ps
CPU time 0.92 seconds
Started Jul 27 06:19:26 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 200672 kb
Host smart-0b554601-defa-4d54-9073-0e47e8962280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653491065 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3653491065
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2380500900
Short name T64
Test name
Test status
Simulation time 20471104 ps
CPU time 0.59 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 196316 kb
Host smart-e495c6c0-6951-42e8-9c9b-0d639b6ad521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380500900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2380500900
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1820016360
Short name T1219
Test name
Test status
Simulation time 24593527 ps
CPU time 0.57 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 195216 kb
Host smart-60191888-d31e-437d-bc25-fccbf47b12ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820016360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1820016360
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3069685069
Short name T1283
Test name
Test status
Simulation time 27983634 ps
CPU time 0.7 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 197216 kb
Host smart-b1cc5430-a3a6-4fb1-afef-85d3ac4ddda6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069685069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3069685069
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.692857553
Short name T1195
Test name
Test status
Simulation time 197249314 ps
CPU time 1.21 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 200860 kb
Host smart-dbe75f21-3b23-4814-84e6-e8ef92eeedf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692857553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.692857553
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.69952282
Short name T1238
Test name
Test status
Simulation time 142995672 ps
CPU time 0.89 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 199848 kb
Host smart-415b6ac6-e638-4350-a4e1-d40025010b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69952282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.69952282
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.508643762
Short name T1234
Test name
Test status
Simulation time 73579882 ps
CPU time 0.74 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 200252 kb
Host smart-b32dfaae-6eb4-41b1-bc56-a55aa0a6253c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508643762 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.508643762
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3669246964
Short name T58
Test name
Test status
Simulation time 14403234 ps
CPU time 0.59 seconds
Started Jul 27 06:19:30 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 196316 kb
Host smart-04c8f76d-874d-4989-b53e-fd9afa34deab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669246964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3669246964
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.553275280
Short name T1236
Test name
Test status
Simulation time 49727424 ps
CPU time 0.59 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 195296 kb
Host smart-ba0b9cf8-724c-403c-97d6-2c6f5b4ca9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553275280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.553275280
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1922496052
Short name T1299
Test name
Test status
Simulation time 39351677 ps
CPU time 0.63 seconds
Started Jul 27 06:19:26 PM PDT 24
Finished Jul 27 06:19:27 PM PDT 24
Peak memory 196420 kb
Host smart-5524ecc7-ce0f-4576-b199-72a067e49d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922496052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1922496052
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3776495553
Short name T1278
Test name
Test status
Simulation time 368162079 ps
CPU time 1.35 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 200932 kb
Host smart-b7588ba0-b53a-4e0f-b99c-5d71b4a0fe86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776495553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3776495553
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2137421569
Short name T77
Test name
Test status
Simulation time 52485099 ps
CPU time 0.98 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 199580 kb
Host smart-21aa893c-36a0-4373-ae59-4b42bc9e1386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137421569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2137421569
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2049540238
Short name T1201
Test name
Test status
Simulation time 119844593 ps
CPU time 0.7 seconds
Started Jul 27 06:19:31 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 198888 kb
Host smart-2cae1bd6-0c8d-4165-8eb1-8d7f90b83ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049540238 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2049540238
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3490092875
Short name T1184
Test name
Test status
Simulation time 24452983 ps
CPU time 0.57 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 195272 kb
Host smart-f52e8381-dc6e-46ef-9850-59253cd696f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490092875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3490092875
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2224270822
Short name T1271
Test name
Test status
Simulation time 270882437 ps
CPU time 0.65 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 197336 kb
Host smart-fbd8c7c0-7060-4308-aa1e-e4b8e6e940bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224270822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2224270822
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1150489940
Short name T1257
Test name
Test status
Simulation time 28808398 ps
CPU time 1.51 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 200920 kb
Host smart-bce47fbf-16da-4324-9caf-9780714de6a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150489940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1150489940
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.316727736
Short name T1246
Test name
Test status
Simulation time 788256311 ps
CPU time 0.92 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 199820 kb
Host smart-80a65f39-e17f-45a0-9650-409280a4b72b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316727736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.316727736
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2961120418
Short name T1303
Test name
Test status
Simulation time 65328249 ps
CPU time 0.69 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 199288 kb
Host smart-1edffb9f-dbce-4087-80ab-7860a0eb1a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961120418 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2961120418
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3472032999
Short name T65
Test name
Test status
Simulation time 23770691 ps
CPU time 0.61 seconds
Started Jul 27 06:19:31 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 196476 kb
Host smart-206aa929-4951-4933-9a35-3c24d2dbc904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472032999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3472032999
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.244969337
Short name T1297
Test name
Test status
Simulation time 21387967 ps
CPU time 0.57 seconds
Started Jul 27 06:19:31 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 195308 kb
Host smart-a31b41f2-3944-4aa4-bdd1-3345fb47099d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244969337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.244969337
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2214119795
Short name T1264
Test name
Test status
Simulation time 94368265 ps
CPU time 0.74 seconds
Started Jul 27 06:19:31 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 197832 kb
Host smart-15dc29ef-2a88-4831-9de2-6a2864bc0555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214119795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2214119795
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3594366810
Short name T1211
Test name
Test status
Simulation time 107781345 ps
CPU time 0.93 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 200704 kb
Host smart-ce5a97c5-0626-4c54-9b24-6e3e734e317e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594366810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3594366810
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3782608380
Short name T110
Test name
Test status
Simulation time 78115945 ps
CPU time 1.28 seconds
Started Jul 27 06:19:30 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 200160 kb
Host smart-7a15ce1e-fdb3-4a20-883c-579109f4ed45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782608380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3782608380
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2932393841
Short name T1291
Test name
Test status
Simulation time 32497361 ps
CPU time 1.41 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 200944 kb
Host smart-7b3f4019-a608-4c3f-86d8-32017bf926a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932393841 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2932393841
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.475621817
Short name T1294
Test name
Test status
Simulation time 47278544 ps
CPU time 0.6 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 196384 kb
Host smart-032ce859-43a7-4650-89c1-c92abe9cda7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475621817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.475621817
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3400026486
Short name T1224
Test name
Test status
Simulation time 34368931 ps
CPU time 0.55 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 195168 kb
Host smart-7cc6d231-6537-462b-bd2f-b74f163fb8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400026486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3400026486
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.338352025
Short name T1217
Test name
Test status
Simulation time 22042473 ps
CPU time 0.65 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 195816 kb
Host smart-60e7fcc3-ca2d-49f2-8309-217e7314c78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338352025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.338352025
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2448446349
Short name T1221
Test name
Test status
Simulation time 58700291 ps
CPU time 1.53 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:31 PM PDT 24
Peak memory 200952 kb
Host smart-b233af88-343e-48a8-bd1a-22959b6bc566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448446349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2448446349
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4287997407
Short name T1301
Test name
Test status
Simulation time 78629944 ps
CPU time 1.34 seconds
Started Jul 27 06:19:33 PM PDT 24
Finished Jul 27 06:19:35 PM PDT 24
Peak memory 200320 kb
Host smart-c73f7086-bd84-4782-8412-5e7e7b8bcbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287997407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4287997407
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2682836746
Short name T1296
Test name
Test status
Simulation time 18299758 ps
CPU time 0.68 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:27 PM PDT 24
Peak memory 198760 kb
Host smart-9c9ee7c2-f9da-4b3e-8211-cc3d85ab63bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682836746 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2682836746
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1378656792
Short name T1239
Test name
Test status
Simulation time 17486629 ps
CPU time 0.63 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 196372 kb
Host smart-6763b566-5e90-4786-919a-89057d2be460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378656792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1378656792
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.81067945
Short name T1229
Test name
Test status
Simulation time 81733884 ps
CPU time 0.58 seconds
Started Jul 27 06:19:32 PM PDT 24
Finished Jul 27 06:19:33 PM PDT 24
Peak memory 195204 kb
Host smart-edb70227-0c7b-4b05-a50f-d3a159be52ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81067945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.81067945
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.627628524
Short name T67
Test name
Test status
Simulation time 22482018 ps
CPU time 0.76 seconds
Started Jul 27 06:19:32 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 197332 kb
Host smart-6208c3df-f890-4ca5-926c-62ad8dc3c389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627628524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.627628524
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2007570575
Short name T1316
Test name
Test status
Simulation time 237485704 ps
CPU time 2.48 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 200960 kb
Host smart-c7edad0f-fbe9-449a-b329-193f2e06a6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007570575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2007570575
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.167591859
Short name T71
Test name
Test status
Simulation time 94366831 ps
CPU time 0.97 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 199852 kb
Host smart-996467b1-1d5a-4ec1-9200-b7636ee1e78c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167591859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.167591859
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3843480500
Short name T1315
Test name
Test status
Simulation time 110835333 ps
CPU time 0.86 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 200712 kb
Host smart-6872ff5a-ef53-44f6-b4e0-64b1ca065d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843480500 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3843480500
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4135504891
Short name T1253
Test name
Test status
Simulation time 16845618 ps
CPU time 0.63 seconds
Started Jul 27 06:19:29 PM PDT 24
Finished Jul 27 06:19:30 PM PDT 24
Peak memory 196360 kb
Host smart-52040c9c-2b32-4253-8eb6-6f1d4a39d325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135504891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4135504891
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2619713537
Short name T1248
Test name
Test status
Simulation time 12449580 ps
CPU time 0.59 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 195272 kb
Host smart-e985f1c8-969a-4b33-84b8-936d2f8ddeab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619713537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2619713537
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2075529377
Short name T1208
Test name
Test status
Simulation time 28433805 ps
CPU time 0.75 seconds
Started Jul 27 06:19:27 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 196968 kb
Host smart-aad57a77-e9ca-47a2-afbb-639085082aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075529377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2075529377
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.970104171
Short name T1189
Test name
Test status
Simulation time 24961312 ps
CPU time 1.22 seconds
Started Jul 27 06:19:28 PM PDT 24
Finished Jul 27 06:19:29 PM PDT 24
Peak memory 200968 kb
Host smart-99034af1-c3ec-4768-be47-02ba0f2e4997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970104171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.970104171
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2224395373
Short name T79
Test name
Test status
Simulation time 168107007 ps
CPU time 1.34 seconds
Started Jul 27 06:19:30 PM PDT 24
Finished Jul 27 06:19:32 PM PDT 24
Peak memory 200304 kb
Host smart-cfbde2ff-d175-4ecd-8d29-fe829c6eeab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224395373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2224395373
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2277661283
Short name T1300
Test name
Test status
Simulation time 37244288 ps
CPU time 0.68 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:39 PM PDT 24
Peak memory 198796 kb
Host smart-2c22a7cb-8d9a-4e38-8240-32f7c254cf39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277661283 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2277661283
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2569702386
Short name T63
Test name
Test status
Simulation time 40647228 ps
CPU time 0.62 seconds
Started Jul 27 06:19:43 PM PDT 24
Finished Jul 27 06:19:43 PM PDT 24
Peak memory 196332 kb
Host smart-93b94be2-1bf3-4678-9338-7b3874386bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569702386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2569702386
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1982306804
Short name T1188
Test name
Test status
Simulation time 13877040 ps
CPU time 0.55 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195276 kb
Host smart-5f1c1872-f909-4a81-8a8b-3b86e8fc0bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982306804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1982306804
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.882580675
Short name T1269
Test name
Test status
Simulation time 26982220 ps
CPU time 0.61 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 196424 kb
Host smart-6e26132b-4e37-4e51-a70a-33e4b9d3fa32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882580675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.882580675
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2413145247
Short name T1240
Test name
Test status
Simulation time 57630889 ps
CPU time 1.37 seconds
Started Jul 27 06:19:43 PM PDT 24
Finished Jul 27 06:19:44 PM PDT 24
Peak memory 200972 kb
Host smart-9c9e6bce-ed1a-4954-98c6-5b5557f1f962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413145247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2413145247
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1844468132
Short name T72
Test name
Test status
Simulation time 821868963 ps
CPU time 1.38 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:39 PM PDT 24
Peak memory 200236 kb
Host smart-08fddc9d-824e-4ac5-a298-c55d6a268fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844468132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1844468132
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1332844958
Short name T1313
Test name
Test status
Simulation time 58257601 ps
CPU time 0.74 seconds
Started Jul 27 06:18:57 PM PDT 24
Finished Jul 27 06:18:58 PM PDT 24
Peak memory 197296 kb
Host smart-b21487a6-3748-48b2-b4eb-ccaa323190d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332844958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1332844958
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1220034435
Short name T56
Test name
Test status
Simulation time 104594542 ps
CPU time 2.33 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:05 PM PDT 24
Peak memory 198700 kb
Host smart-d5ab5984-8deb-4757-9a21-2ee4b3b90c61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220034435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1220034435
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3600121475
Short name T1242
Test name
Test status
Simulation time 56384757 ps
CPU time 0.59 seconds
Started Jul 27 06:19:01 PM PDT 24
Finished Jul 27 06:19:02 PM PDT 24
Peak memory 196320 kb
Host smart-7bfc23b8-9732-440c-9482-0b6633a10a9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600121475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3600121475
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.498153595
Short name T1285
Test name
Test status
Simulation time 58930510 ps
CPU time 0.66 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 198740 kb
Host smart-7758c206-183a-4976-8a66-d012d5f4871d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498153595 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.498153595
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3059167411
Short name T1312
Test name
Test status
Simulation time 53383655 ps
CPU time 0.62 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 196348 kb
Host smart-5b35bad3-c92e-4db3-b89f-9f2b5753056f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059167411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3059167411
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2836809733
Short name T1258
Test name
Test status
Simulation time 15898489 ps
CPU time 0.58 seconds
Started Jul 27 06:18:58 PM PDT 24
Finished Jul 27 06:18:59 PM PDT 24
Peak memory 195300 kb
Host smart-7378f6f0-01b3-4fdc-9901-9e7c1007d1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836809733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2836809733
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2171744494
Short name T1207
Test name
Test status
Simulation time 51006343 ps
CPU time 0.74 seconds
Started Jul 27 06:19:05 PM PDT 24
Finished Jul 27 06:19:06 PM PDT 24
Peak memory 197956 kb
Host smart-054af887-09a4-4f7e-9dd9-878de4f7cc41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171744494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2171744494
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1738236472
Short name T1270
Test name
Test status
Simulation time 46724985 ps
CPU time 2.41 seconds
Started Jul 27 06:19:02 PM PDT 24
Finished Jul 27 06:19:05 PM PDT 24
Peak memory 200936 kb
Host smart-93292d3f-cc40-498e-9058-3603137be29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738236472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1738236472
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.519065060
Short name T109
Test name
Test status
Simulation time 329557523 ps
CPU time 1.43 seconds
Started Jul 27 06:19:03 PM PDT 24
Finished Jul 27 06:19:04 PM PDT 24
Peak memory 200228 kb
Host smart-cdbb03a3-b33b-4210-ac38-9afc4a80ff6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519065060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.519065060
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2396579538
Short name T1307
Test name
Test status
Simulation time 11002050 ps
CPU time 0.6 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:37 PM PDT 24
Peak memory 195292 kb
Host smart-c8c0de10-9cdb-48ba-abaf-bc72eab9b0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396579538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2396579538
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.696407384
Short name T1302
Test name
Test status
Simulation time 21978400 ps
CPU time 0.59 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195256 kb
Host smart-a29c3c77-0809-4773-9819-e26bff746f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696407384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.696407384
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1350058637
Short name T1280
Test name
Test status
Simulation time 24447245 ps
CPU time 0.57 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:41 PM PDT 24
Peak memory 195268 kb
Host smart-c5805566-cf85-41fa-895c-e6fbe96d92ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350058637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1350058637
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2132859384
Short name T1197
Test name
Test status
Simulation time 46790415 ps
CPU time 0.58 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195276 kb
Host smart-9f8b783e-2376-46e2-a32e-9de1a59be127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132859384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2132859384
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.80841279
Short name T1193
Test name
Test status
Simulation time 22294468 ps
CPU time 0.59 seconds
Started Jul 27 06:19:39 PM PDT 24
Finished Jul 27 06:19:40 PM PDT 24
Peak memory 195236 kb
Host smart-dbcab413-ce38-4abb-886f-cd96ff55eef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80841279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.80841279
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2491855584
Short name T1309
Test name
Test status
Simulation time 13074015 ps
CPU time 0.57 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195276 kb
Host smart-67d04375-19ce-403a-a65d-53175b378dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491855584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2491855584
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1708229765
Short name T1200
Test name
Test status
Simulation time 161355637 ps
CPU time 0.54 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:42 PM PDT 24
Peak memory 195256 kb
Host smart-e60f40b2-d416-4d6e-a5b5-4e72ca2b0955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708229765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1708229765
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.554388755
Short name T1215
Test name
Test status
Simulation time 66133697 ps
CPU time 0.6 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195272 kb
Host smart-16878f90-64b7-42bf-bc0d-1680f549b3df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554388755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.554388755
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3531840876
Short name T1241
Test name
Test status
Simulation time 13931866 ps
CPU time 0.57 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:37 PM PDT 24
Peak memory 195288 kb
Host smart-f592fa33-8f66-42a6-a7af-0cd05801342a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531840876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3531840876
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3242518980
Short name T1251
Test name
Test status
Simulation time 95158195 ps
CPU time 0.59 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:42 PM PDT 24
Peak memory 195276 kb
Host smart-763ae44c-1558-4178-bb20-0c4d44738b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242518980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3242518980
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3439490965
Short name T1306
Test name
Test status
Simulation time 40324856 ps
CPU time 0.68 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 195796 kb
Host smart-afe6391e-912d-4dc0-bdf5-0c4e31b11e87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439490965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3439490965
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.116313420
Short name T1314
Test name
Test status
Simulation time 443997276 ps
CPU time 2.48 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 198224 kb
Host smart-87bf570c-26f2-48f3-a139-da90f4312407
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116313420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.116313420
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2445690306
Short name T57
Test name
Test status
Simulation time 16653632 ps
CPU time 0.64 seconds
Started Jul 27 06:19:09 PM PDT 24
Finished Jul 27 06:19:10 PM PDT 24
Peak memory 196276 kb
Host smart-5c768c2f-48a1-46a3-9f02-ddaf3520ca93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445690306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2445690306
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3498865369
Short name T1249
Test name
Test status
Simulation time 344032605 ps
CPU time 0.88 seconds
Started Jul 27 06:19:07 PM PDT 24
Finished Jul 27 06:19:08 PM PDT 24
Peak memory 200700 kb
Host smart-e0886054-40e1-4000-876a-bc33ab7ee3cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498865369 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3498865369
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3335298183
Short name T59
Test name
Test status
Simulation time 21126291 ps
CPU time 0.61 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 196424 kb
Host smart-1ac95773-de7f-41f4-be9a-b2bc9e0b53b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335298183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3335298183
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3422861821
Short name T1286
Test name
Test status
Simulation time 47040748 ps
CPU time 0.57 seconds
Started Jul 27 06:19:06 PM PDT 24
Finished Jul 27 06:19:07 PM PDT 24
Peak memory 195488 kb
Host smart-337fb115-ecc7-4256-8ff6-7fae4b702d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422861821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3422861821
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1538115094
Short name T1281
Test name
Test status
Simulation time 63078716 ps
CPU time 0.61 seconds
Started Jul 27 06:19:11 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 196332 kb
Host smart-a75424e5-c5aa-4ee0-bbf1-7f8c01f78e57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538115094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1538115094
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.530257065
Short name T1261
Test name
Test status
Simulation time 57154178 ps
CPU time 1.55 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:10 PM PDT 24
Peak memory 200968 kb
Host smart-9601beac-43f2-4595-a7b2-3e76066449b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530257065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.530257065
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2690630647
Short name T76
Test name
Test status
Simulation time 91551977 ps
CPU time 1.46 seconds
Started Jul 27 06:19:10 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 200020 kb
Host smart-f34c87b9-c2a8-43ee-a88a-101cd95f2002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690630647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2690630647
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3663569897
Short name T1196
Test name
Test status
Simulation time 33081701 ps
CPU time 0.61 seconds
Started Jul 27 06:19:36 PM PDT 24
Finished Jul 27 06:19:37 PM PDT 24
Peak memory 195280 kb
Host smart-aea1b238-0c46-47a0-b533-916f39495f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663569897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3663569897
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3473202144
Short name T1205
Test name
Test status
Simulation time 47567900 ps
CPU time 0.58 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:42 PM PDT 24
Peak memory 195284 kb
Host smart-313d4a62-abff-4826-bdb2-b040da186367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473202144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3473202144
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2387000041
Short name T1181
Test name
Test status
Simulation time 44610853 ps
CPU time 0.6 seconds
Started Jul 27 06:19:37 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195200 kb
Host smart-6637de27-ed46-40aa-8404-1db20168581e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387000041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2387000041
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4091425800
Short name T1204
Test name
Test status
Simulation time 14125408 ps
CPU time 0.58 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:39 PM PDT 24
Peak memory 195212 kb
Host smart-36eca455-4bf3-4b79-bfc3-d76dacc69c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091425800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4091425800
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2244143954
Short name T1293
Test name
Test status
Simulation time 39242530 ps
CPU time 0.57 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195224 kb
Host smart-ebc517a4-696a-47e3-8426-3c82c07f3c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244143954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2244143954
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1653580602
Short name T1274
Test name
Test status
Simulation time 42803872 ps
CPU time 0.59 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:41 PM PDT 24
Peak memory 195300 kb
Host smart-31381b61-5ff7-421f-a2ff-f51f4754ef11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653580602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1653580602
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2688554342
Short name T1305
Test name
Test status
Simulation time 13927465 ps
CPU time 0.56 seconds
Started Jul 27 06:19:36 PM PDT 24
Finished Jul 27 06:19:36 PM PDT 24
Peak memory 195312 kb
Host smart-47db98fb-51c4-4f98-b892-0367b0747717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688554342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2688554342
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1450151752
Short name T1247
Test name
Test status
Simulation time 11386996 ps
CPU time 0.56 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195228 kb
Host smart-40813765-85fb-49c1-9f7c-b045c7c39553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450151752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1450151752
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3686545186
Short name T1220
Test name
Test status
Simulation time 12170452 ps
CPU time 0.58 seconds
Started Jul 27 06:19:36 PM PDT 24
Finished Jul 27 06:19:37 PM PDT 24
Peak memory 195292 kb
Host smart-a01a25b6-324a-4db0-b5fc-1fa9686f446f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686545186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3686545186
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3066251596
Short name T1311
Test name
Test status
Simulation time 42755491 ps
CPU time 0.57 seconds
Started Jul 27 06:19:40 PM PDT 24
Finished Jul 27 06:19:40 PM PDT 24
Peak memory 195300 kb
Host smart-5284668d-5bdd-4f6b-9454-6477943ba950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066251596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3066251596
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.912628654
Short name T55
Test name
Test status
Simulation time 30272952 ps
CPU time 0.81 seconds
Started Jul 27 06:19:10 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 197640 kb
Host smart-19b7263a-96a9-4c03-b7eb-5dd05f02b47c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912628654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.912628654
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3903005626
Short name T1203
Test name
Test status
Simulation time 93584987 ps
CPU time 1.48 seconds
Started Jul 27 06:19:09 PM PDT 24
Finished Jul 27 06:19:10 PM PDT 24
Peak memory 198648 kb
Host smart-25b426f6-d116-4190-a8a4-d0304ccebe74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903005626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3903005626
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1642957551
Short name T1183
Test name
Test status
Simulation time 244223904 ps
CPU time 0.59 seconds
Started Jul 27 06:19:10 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 196300 kb
Host smart-8d325bcc-b922-4d78-8c2f-871f100d0583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642957551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1642957551
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2094508090
Short name T1228
Test name
Test status
Simulation time 28410027 ps
CPU time 0.78 seconds
Started Jul 27 06:19:09 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 199368 kb
Host smart-3184b2a1-0e83-4f1b-949e-5d4c41b8e77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094508090 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2094508090
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3366908571
Short name T62
Test name
Test status
Simulation time 32894245 ps
CPU time 0.62 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:08 PM PDT 24
Peak memory 196468 kb
Host smart-d758720e-a5c2-4cf8-acb0-3d4b6e52e8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366908571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3366908571
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2414436528
Short name T1237
Test name
Test status
Simulation time 31883485 ps
CPU time 0.6 seconds
Started Jul 27 06:19:10 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 195288 kb
Host smart-11f69601-f761-4bcb-b5d7-64647097bf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414436528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2414436528
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2014581707
Short name T1287
Test name
Test status
Simulation time 19337951 ps
CPU time 0.67 seconds
Started Jul 27 06:19:07 PM PDT 24
Finished Jul 27 06:19:08 PM PDT 24
Peak memory 196560 kb
Host smart-fe128004-3efc-4cc1-81df-c6b38336ea72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014581707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2014581707
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.221890366
Short name T1198
Test name
Test status
Simulation time 95483792 ps
CPU time 1.44 seconds
Started Jul 27 06:19:09 PM PDT 24
Finished Jul 27 06:19:11 PM PDT 24
Peak memory 200968 kb
Host smart-e9b60bf6-2cf5-4f8c-b8b7-31836f866ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221890366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.221890366
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1606281898
Short name T1289
Test name
Test status
Simulation time 401938321 ps
CPU time 1.32 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 200164 kb
Host smart-79cb83f6-0e54-4907-803b-2c86c4acd808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606281898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1606281898
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3509687657
Short name T1260
Test name
Test status
Simulation time 199866960 ps
CPU time 0.59 seconds
Started Jul 27 06:19:39 PM PDT 24
Finished Jul 27 06:19:40 PM PDT 24
Peak memory 195292 kb
Host smart-407863aa-ddd8-477b-b408-4890bacaf0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509687657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3509687657
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3036938681
Short name T1245
Test name
Test status
Simulation time 14715186 ps
CPU time 0.58 seconds
Started Jul 27 06:19:41 PM PDT 24
Finished Jul 27 06:19:41 PM PDT 24
Peak memory 195228 kb
Host smart-4b31a695-fba8-4613-b079-b4f4f81e3f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036938681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3036938681
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1965530181
Short name T1288
Test name
Test status
Simulation time 63246041 ps
CPU time 0.57 seconds
Started Jul 27 06:19:38 PM PDT 24
Finished Jul 27 06:19:38 PM PDT 24
Peak memory 195304 kb
Host smart-1aa5f6b1-bb63-4ad6-8c96-6f9be285615b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965530181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1965530181
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1411593337
Short name T1187
Test name
Test status
Simulation time 16712834 ps
CPU time 0.56 seconds
Started Jul 27 06:19:36 PM PDT 24
Finished Jul 27 06:19:37 PM PDT 24
Peak memory 195220 kb
Host smart-457dec32-d937-4d1a-8278-fd19c5beb844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411593337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1411593337
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2020489163
Short name T1186
Test name
Test status
Simulation time 20237388 ps
CPU time 0.6 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 195276 kb
Host smart-d8861c68-1878-49ff-a7af-6af3161c117e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020489163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2020489163
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3414273997
Short name T1227
Test name
Test status
Simulation time 12387947 ps
CPU time 0.55 seconds
Started Jul 27 06:19:47 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 195284 kb
Host smart-867a5478-9710-4402-9440-6bb540dedce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414273997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3414273997
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3445861431
Short name T1265
Test name
Test status
Simulation time 42188187 ps
CPU time 0.58 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195300 kb
Host smart-d0945c1b-213e-4b63-a53e-679947d561a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445861431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3445861431
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.827738040
Short name T1194
Test name
Test status
Simulation time 16743854 ps
CPU time 0.58 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195412 kb
Host smart-f60742aa-9e21-4085-ae27-ac5495bb607c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827738040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.827738040
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.428269460
Short name T1262
Test name
Test status
Simulation time 32118281 ps
CPU time 0.53 seconds
Started Jul 27 06:19:48 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 195144 kb
Host smart-5f9bbf28-2911-40ff-8060-ceb3d6c9f878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428269460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.428269460
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.108061695
Short name T1250
Test name
Test status
Simulation time 15775379 ps
CPU time 0.56 seconds
Started Jul 27 06:19:49 PM PDT 24
Finished Jul 27 06:19:50 PM PDT 24
Peak memory 195324 kb
Host smart-44b46e5a-6ecb-450f-ac16-bb4546a8b7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108061695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.108061695
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3666419956
Short name T1276
Test name
Test status
Simulation time 55752165 ps
CPU time 0.69 seconds
Started Jul 27 06:19:20 PM PDT 24
Finished Jul 27 06:19:21 PM PDT 24
Peak memory 199588 kb
Host smart-746a581a-abdf-40dc-9364-6f0f0ebbb85b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666419956 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3666419956
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3124105658
Short name T1272
Test name
Test status
Simulation time 13579744 ps
CPU time 0.65 seconds
Started Jul 27 06:19:08 PM PDT 24
Finished Jul 27 06:19:09 PM PDT 24
Peak memory 196320 kb
Host smart-79edd206-1eb4-430b-8d03-0d5e225dc4b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124105658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3124105658
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3296180401
Short name T1290
Test name
Test status
Simulation time 16133711 ps
CPU time 0.6 seconds
Started Jul 27 06:19:09 PM PDT 24
Finished Jul 27 06:19:10 PM PDT 24
Peak memory 195296 kb
Host smart-5cfa9c32-0600-4d40-9ce3-e2213d49b4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296180401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3296180401
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2683115650
Short name T1230
Test name
Test status
Simulation time 59846798 ps
CPU time 0.76 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:19 PM PDT 24
Peak memory 197892 kb
Host smart-a3fc0576-3ad4-48b9-b905-ed15bfa3b350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683115650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2683115650
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.164590788
Short name T1304
Test name
Test status
Simulation time 67400968 ps
CPU time 1.05 seconds
Started Jul 27 06:19:11 PM PDT 24
Finished Jul 27 06:19:12 PM PDT 24
Peak memory 200712 kb
Host smart-ccb7b8b5-a817-4ea7-a1f4-b2bda89fdffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164590788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.164590788
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2285485654
Short name T1277
Test name
Test status
Simulation time 77336044 ps
CPU time 1.02 seconds
Started Jul 27 06:19:19 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 200696 kb
Host smart-d2f3729f-bd21-40e1-80ec-f91cd360384b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285485654 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2285485654
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3700010146
Short name T1266
Test name
Test status
Simulation time 51643866 ps
CPU time 0.59 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:22 PM PDT 24
Peak memory 196320 kb
Host smart-1b555f40-d3c4-4949-8bae-f196466af11f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700010146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3700010146
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2331982988
Short name T1191
Test name
Test status
Simulation time 10625676 ps
CPU time 0.55 seconds
Started Jul 27 06:19:20 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 195200 kb
Host smart-8721d39a-eb37-4b60-940c-f8f28da4a48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331982988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2331982988
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1979523875
Short name T1298
Test name
Test status
Simulation time 21370673 ps
CPU time 0.65 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:18 PM PDT 24
Peak memory 195668 kb
Host smart-5d9c70ef-499f-4285-8428-beb71d252624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979523875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1979523875
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.979127247
Short name T1192
Test name
Test status
Simulation time 133709649 ps
CPU time 1.9 seconds
Started Jul 27 06:19:21 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 200940 kb
Host smart-0f8c2c8b-613a-414c-8215-9f40914af8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979127247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.979127247
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1908543283
Short name T1185
Test name
Test status
Simulation time 31859112 ps
CPU time 0.92 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 200736 kb
Host smart-937e5ca2-ef90-41ee-8ab0-374fd4b55a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908543283 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1908543283
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.845360038
Short name T1218
Test name
Test status
Simulation time 34113818 ps
CPU time 0.59 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:19 PM PDT 24
Peak memory 196284 kb
Host smart-ede85da5-9cdd-4d65-858c-27f6af78c3a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845360038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.845360038
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4071877865
Short name T1243
Test name
Test status
Simulation time 54334793 ps
CPU time 0.6 seconds
Started Jul 27 06:19:20 PM PDT 24
Finished Jul 27 06:19:21 PM PDT 24
Peak memory 195200 kb
Host smart-87f7a1d8-3ae5-48e8-bbbc-180946059d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071877865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4071877865
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1879701305
Short name T1222
Test name
Test status
Simulation time 120425082 ps
CPU time 0.73 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:19 PM PDT 24
Peak memory 197836 kb
Host smart-e878e56e-29e3-4ba0-8fa2-7673b6ec3809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879701305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1879701305
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3536381015
Short name T1213
Test name
Test status
Simulation time 374909182 ps
CPU time 1.52 seconds
Started Jul 27 06:19:23 PM PDT 24
Finished Jul 27 06:19:25 PM PDT 24
Peak memory 200924 kb
Host smart-c7ccbc9b-10b6-4b45-882b-ab08f8eaa072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536381015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3536381015
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2862080541
Short name T78
Test name
Test status
Simulation time 801201236 ps
CPU time 1.29 seconds
Started Jul 27 06:19:21 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 200156 kb
Host smart-c02cbbd6-6d14-4f67-9ee2-94368988263d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862080541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2862080541
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2551429341
Short name T1268
Test name
Test status
Simulation time 135641656 ps
CPU time 0.74 seconds
Started Jul 27 06:19:19 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 199768 kb
Host smart-d6059957-dde0-435e-b45d-b4adafd26fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551429341 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2551429341
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.734562246
Short name T60
Test name
Test status
Simulation time 11175008 ps
CPU time 0.61 seconds
Started Jul 27 06:19:23 PM PDT 24
Finished Jul 27 06:19:24 PM PDT 24
Peak memory 196224 kb
Host smart-e8895b9d-fbed-44d3-98ec-08a6870e56a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734562246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.734562246
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1772878343
Short name T1225
Test name
Test status
Simulation time 37059869 ps
CPU time 0.58 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 195212 kb
Host smart-7dc7b2a5-7585-48b1-9846-e2f0c5c7e12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772878343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1772878343
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1367953652
Short name T1223
Test name
Test status
Simulation time 71294290 ps
CPU time 0.65 seconds
Started Jul 27 06:19:17 PM PDT 24
Finished Jul 27 06:19:18 PM PDT 24
Peak memory 196772 kb
Host smart-dc1273f0-1b9c-4fdc-8043-63dcd7788775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367953652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1367953652
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3446296412
Short name T1190
Test name
Test status
Simulation time 540487374 ps
CPU time 2.55 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:24 PM PDT 24
Peak memory 200860 kb
Host smart-c432ac9d-a2f0-464e-a594-5d1de1ca1b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446296412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3446296412
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3510577599
Short name T1310
Test name
Test status
Simulation time 41530879 ps
CPU time 0.9 seconds
Started Jul 27 06:19:19 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 199964 kb
Host smart-264ad2c0-1174-4d8d-acfe-65d92621cd1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510577599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3510577599
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1675754271
Short name T1216
Test name
Test status
Simulation time 111976139 ps
CPU time 1.27 seconds
Started Jul 27 06:19:18 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 200940 kb
Host smart-7e11e3d0-f636-4b86-b070-d8224063cb33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675754271 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1675754271
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3037433969
Short name T1233
Test name
Test status
Simulation time 39842206 ps
CPU time 0.58 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 196304 kb
Host smart-21f48be2-dea1-4b07-b6b2-6f6c94994b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037433969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3037433969
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1927837947
Short name T1273
Test name
Test status
Simulation time 23851626 ps
CPU time 0.56 seconds
Started Jul 27 06:19:20 PM PDT 24
Finished Jul 27 06:19:20 PM PDT 24
Peak memory 195192 kb
Host smart-79fa1cd9-3b53-4e34-8d85-5b07b5c012cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927837947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1927837947
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4141732726
Short name T66
Test name
Test status
Simulation time 27201446 ps
CPU time 0.64 seconds
Started Jul 27 06:19:19 PM PDT 24
Finished Jul 27 06:19:19 PM PDT 24
Peak memory 196428 kb
Host smart-4ab4a812-7638-4283-aa26-ac905de64ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141732726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4141732726
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1252577523
Short name T1232
Test name
Test status
Simulation time 144552367 ps
CPU time 2.49 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:24 PM PDT 24
Peak memory 200968 kb
Host smart-ab7681bc-1e02-4949-a128-85cfe4e902a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252577523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1252577523
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3693238528
Short name T74
Test name
Test status
Simulation time 162742467 ps
CPU time 1.4 seconds
Started Jul 27 06:19:22 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 200276 kb
Host smart-99a18d37-9120-427f-9483-0d66ae1b72ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693238528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3693238528
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.731954150
Short name T1120
Test name
Test status
Simulation time 80721192 ps
CPU time 0.56 seconds
Started Jul 27 06:23:00 PM PDT 24
Finished Jul 27 06:23:00 PM PDT 24
Peak memory 195528 kb
Host smart-387190b6-a216-420a-81ff-81bf658b1459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731954150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.731954150
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.326136254
Short name T1061
Test name
Test status
Simulation time 80655666696 ps
CPU time 24.05 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:23:15 PM PDT 24
Peak memory 200172 kb
Host smart-31d5e49b-3bee-45a8-8f66-563c7976809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326136254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.326136254
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2944920605
Short name T118
Test name
Test status
Simulation time 101460422859 ps
CPU time 18.4 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:23:12 PM PDT 24
Peak memory 199952 kb
Host smart-c83d3df3-16da-49d1-9ffd-981ba04b67c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944920605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2944920605
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3865040505
Short name T689
Test name
Test status
Simulation time 10002659942 ps
CPU time 14.62 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:23:07 PM PDT 24
Peak memory 200176 kb
Host smart-983ce961-8aa0-4a38-8b04-8b67ff72db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865040505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3865040505
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3394210427
Short name T495
Test name
Test status
Simulation time 32964918174 ps
CPU time 57.07 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:23:48 PM PDT 24
Peak memory 200240 kb
Host smart-ca7be286-586f-4397-a7b0-80d406e4f7a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394210427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3394210427
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1140082546
Short name T486
Test name
Test status
Simulation time 63284163903 ps
CPU time 536.31 seconds
Started Jul 27 06:22:52 PM PDT 24
Finished Jul 27 06:31:48 PM PDT 24
Peak memory 200228 kb
Host smart-10e0befa-fea6-4191-854e-abc213f44362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140082546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1140082546
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2204117377
Short name T1133
Test name
Test status
Simulation time 177613484 ps
CPU time 0.63 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:53 PM PDT 24
Peak memory 196276 kb
Host smart-d10b73fd-a665-4204-9e3b-7b448753e3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204117377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2204117377
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1785759175
Short name T999
Test name
Test status
Simulation time 76362719109 ps
CPU time 85.86 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:24:17 PM PDT 24
Peak memory 199848 kb
Host smart-c6fa23c8-2d3d-4871-8923-434663a57c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785759175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1785759175
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1988721701
Short name T678
Test name
Test status
Simulation time 10575541283 ps
CPU time 57.69 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:23:48 PM PDT 24
Peak memory 200108 kb
Host smart-27cc27bc-07c6-413a-b1de-0f2de5b4f1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988721701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1988721701
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.772242017
Short name T3
Test name
Test status
Simulation time 2875598917 ps
CPU time 6.22 seconds
Started Jul 27 06:22:54 PM PDT 24
Finished Jul 27 06:23:01 PM PDT 24
Peak memory 198628 kb
Host smart-5839f4c7-393f-423c-bfe1-3ecae52d63d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772242017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.772242017
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.131515100
Short name T620
Test name
Test status
Simulation time 29212789223 ps
CPU time 39.91 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:23:33 PM PDT 24
Peak memory 200128 kb
Host smart-16493c2c-d403-4852-9466-0262c8df1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131515100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.131515100
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3576431377
Short name T1056
Test name
Test status
Simulation time 39636653576 ps
CPU time 10.07 seconds
Started Jul 27 06:22:52 PM PDT 24
Finished Jul 27 06:23:03 PM PDT 24
Peak memory 196296 kb
Host smart-764edf0b-b3ed-4ff6-b9ad-fda168c33182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576431377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3576431377
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2618465389
Short name T21
Test name
Test status
Simulation time 395809223 ps
CPU time 0.75 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:23:02 PM PDT 24
Peak memory 218456 kb
Host smart-bf05b6e5-19ec-4632-b0af-c502b140ec97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618465389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2618465389
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3205162008
Short name T638
Test name
Test status
Simulation time 256371421 ps
CPU time 1.1 seconds
Started Jul 27 06:22:55 PM PDT 24
Finished Jul 27 06:22:56 PM PDT 24
Peak memory 198724 kb
Host smart-182d8012-6512-4c65-9f16-43b52aa85e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205162008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3205162008
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2914108238
Short name T805
Test name
Test status
Simulation time 3650258050 ps
CPU time 3.09 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:23:04 PM PDT 24
Peak memory 200232 kb
Host smart-fb095ac2-a48e-4066-983d-d3b63b772742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914108238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2914108238
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3528430679
Short name T895
Test name
Test status
Simulation time 94560872252 ps
CPU time 426.99 seconds
Started Jul 27 06:23:00 PM PDT 24
Finished Jul 27 06:30:07 PM PDT 24
Peak memory 216360 kb
Host smart-90033089-80ee-4bba-9856-79d6e5cef41e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528430679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3528430679
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3157816712
Short name T578
Test name
Test status
Simulation time 1325313031 ps
CPU time 2.3 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:56 PM PDT 24
Peak memory 198988 kb
Host smart-172874a2-c46c-4aa5-ad2a-c3a5848dd9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157816712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3157816712
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1262126441
Short name T787
Test name
Test status
Simulation time 147632573282 ps
CPU time 15.74 seconds
Started Jul 27 06:22:52 PM PDT 24
Finished Jul 27 06:23:08 PM PDT 24
Peak memory 199140 kb
Host smart-4658b292-cc94-4bab-b6f3-fbab87364f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262126441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1262126441
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3301798936
Short name T1158
Test name
Test status
Simulation time 25651905 ps
CPU time 0.55 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:10 PM PDT 24
Peak memory 195608 kb
Host smart-d42559b0-386b-41a5-a8e5-b93070218ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301798936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3301798936
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1797121228
Short name T268
Test name
Test status
Simulation time 54608528767 ps
CPU time 85.58 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:24:27 PM PDT 24
Peak memory 200168 kb
Host smart-74893189-0019-4b86-ba3a-c43ad9b35ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797121228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1797121228
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2465171067
Short name T318
Test name
Test status
Simulation time 112358615498 ps
CPU time 170.68 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 200236 kb
Host smart-f1e8c602-aafb-4dd3-b06e-6a37f1e58e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465171067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2465171067
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.347658930
Short name T565
Test name
Test status
Simulation time 197289851743 ps
CPU time 310.03 seconds
Started Jul 27 06:23:03 PM PDT 24
Finished Jul 27 06:28:13 PM PDT 24
Peak memory 200276 kb
Host smart-6430a3fa-d7cb-4694-a728-0862444d9e12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347658930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.347658930
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.360996151
Short name T30
Test name
Test status
Simulation time 342612039996 ps
CPU time 274.64 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:27:44 PM PDT 24
Peak memory 200236 kb
Host smart-64a079b5-24f1-41f1-b90f-b1b09e81bc37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360996151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.360996151
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1640885204
Short name T1099
Test name
Test status
Simulation time 791594554 ps
CPU time 1.13 seconds
Started Jul 27 06:23:03 PM PDT 24
Finished Jul 27 06:23:04 PM PDT 24
Peak memory 195720 kb
Host smart-029e1293-8910-4985-a98e-ce15c234ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640885204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1640885204
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2860336515
Short name T432
Test name
Test status
Simulation time 285237827765 ps
CPU time 43.73 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:23:45 PM PDT 24
Peak memory 200356 kb
Host smart-b3629ff7-3cdc-47db-81e1-f0779d83d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860336515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2860336515
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3808774768
Short name T1142
Test name
Test status
Simulation time 2113503956 ps
CPU time 12.42 seconds
Started Jul 27 06:23:00 PM PDT 24
Finished Jul 27 06:23:12 PM PDT 24
Peak memory 198788 kb
Host smart-9bb8c6dd-8e57-4c35-81de-ba6f82f920ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808774768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3808774768
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2965499292
Short name T498
Test name
Test status
Simulation time 31866588498 ps
CPU time 24.28 seconds
Started Jul 27 06:22:59 PM PDT 24
Finished Jul 27 06:23:24 PM PDT 24
Peak memory 200196 kb
Host smart-57ebe59d-34f1-4347-8e96-6c25defa2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965499292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2965499292
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1578079574
Short name T760
Test name
Test status
Simulation time 40195220510 ps
CPU time 65.55 seconds
Started Jul 27 06:22:59 PM PDT 24
Finished Jul 27 06:24:05 PM PDT 24
Peak memory 196764 kb
Host smart-b1a6c992-fa4a-4224-aad8-974c250d5e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578079574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1578079574
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3129017334
Short name T22
Test name
Test status
Simulation time 577465259 ps
CPU time 0.93 seconds
Started Jul 27 06:23:08 PM PDT 24
Finished Jul 27 06:23:10 PM PDT 24
Peak memory 218556 kb
Host smart-eba3c071-fb2e-4367-ade5-411676556633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129017334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3129017334
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1520871807
Short name T709
Test name
Test status
Simulation time 714233504 ps
CPU time 3.89 seconds
Started Jul 27 06:23:01 PM PDT 24
Finished Jul 27 06:23:05 PM PDT 24
Peak memory 198496 kb
Host smart-0ebd5ea3-68a9-4d3b-aea4-1337ad71b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520871807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1520871807
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3146881839
Short name T833
Test name
Test status
Simulation time 397448395476 ps
CPU time 184.3 seconds
Started Jul 27 06:23:08 PM PDT 24
Finished Jul 27 06:26:13 PM PDT 24
Peak memory 200212 kb
Host smart-ba74d299-5a07-4e28-9570-a9dbf12f91dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146881839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3146881839
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3397967634
Short name T598
Test name
Test status
Simulation time 129476721229 ps
CPU time 524.6 seconds
Started Jul 27 06:23:12 PM PDT 24
Finished Jul 27 06:31:56 PM PDT 24
Peak memory 227896 kb
Host smart-0a3b6440-92a6-459b-86fb-a55373a26848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397967634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3397967634
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1856435983
Short name T1078
Test name
Test status
Simulation time 203156643 ps
CPU time 1.15 seconds
Started Jul 27 06:23:02 PM PDT 24
Finished Jul 27 06:23:03 PM PDT 24
Peak memory 198128 kb
Host smart-581b0e87-2f19-4a5e-b4a6-7df81543b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856435983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1856435983
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3957094413
Short name T701
Test name
Test status
Simulation time 96102651071 ps
CPU time 96.33 seconds
Started Jul 27 06:23:00 PM PDT 24
Finished Jul 27 06:24:37 PM PDT 24
Peak memory 200200 kb
Host smart-ce2d2fc9-8547-4147-bbdd-0a6ec6eb14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957094413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3957094413
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3153345531
Short name T1007
Test name
Test status
Simulation time 13873326 ps
CPU time 0.56 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:23:57 PM PDT 24
Peak memory 195612 kb
Host smart-c66d8dec-1748-4307-9613-032b2161bf21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153345531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3153345531
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2624037791
Short name T651
Test name
Test status
Simulation time 222873175075 ps
CPU time 34.19 seconds
Started Jul 27 06:23:59 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 200172 kb
Host smart-31489188-2346-432b-ac95-b57cc2cb172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624037791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2624037791
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.461846470
Short name T502
Test name
Test status
Simulation time 43016091385 ps
CPU time 20.15 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:18 PM PDT 24
Peak memory 200208 kb
Host smart-a3c2e37b-7cda-4853-a414-781270916717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461846470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.461846470
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2258178355
Short name T128
Test name
Test status
Simulation time 17271812241 ps
CPU time 24.84 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:23 PM PDT 24
Peak memory 200252 kb
Host smart-94a4a6a6-e733-4c24-8790-25e726eab21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258178355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2258178355
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3051065591
Short name T946
Test name
Test status
Simulation time 21186991158 ps
CPU time 35.98 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 200224 kb
Host smart-254c42e6-fea6-4a5c-97e3-375fedcef709
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051065591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3051065591
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4157775954
Short name T957
Test name
Test status
Simulation time 51038312264 ps
CPU time 240.66 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:27:57 PM PDT 24
Peak memory 200152 kb
Host smart-3acaef43-5734-44f9-8209-c0ef3a19ad2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157775954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4157775954
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3418527818
Short name T440
Test name
Test status
Simulation time 1753253856 ps
CPU time 2 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:23:59 PM PDT 24
Peak memory 195932 kb
Host smart-30ac7eea-7171-485c-b9f9-c253c637be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418527818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3418527818
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3926784687
Short name T1129
Test name
Test status
Simulation time 129921999070 ps
CPU time 52.5 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:50 PM PDT 24
Peak memory 200240 kb
Host smart-e61b0510-a3dc-476b-b693-7df69c623ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926784687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3926784687
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1742668564
Short name T313
Test name
Test status
Simulation time 20526650870 ps
CPU time 73.79 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:25:11 PM PDT 24
Peak memory 200216 kb
Host smart-166684ef-c314-473f-830e-4383c5671f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742668564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1742668564
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3277803476
Short name T1028
Test name
Test status
Simulation time 1480198805 ps
CPU time 5.48 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:24:03 PM PDT 24
Peak memory 198252 kb
Host smart-d34548a8-ce1c-4016-9750-214a49081306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277803476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3277803476
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4184526464
Short name T1104
Test name
Test status
Simulation time 112654570469 ps
CPU time 42.76 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:41 PM PDT 24
Peak memory 200116 kb
Host smart-81975bb4-9983-472e-88ee-aa4e57df1283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184526464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4184526464
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1494736230
Short name T1082
Test name
Test status
Simulation time 2531233182 ps
CPU time 4.3 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:24:02 PM PDT 24
Peak memory 195972 kb
Host smart-4d980a9b-c943-44e0-8fbc-4f5c5ad0df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494736230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1494736230
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.116138034
Short name T628
Test name
Test status
Simulation time 741249608 ps
CPU time 2.28 seconds
Started Jul 27 06:23:57 PM PDT 24
Finished Jul 27 06:24:00 PM PDT 24
Peak memory 199664 kb
Host smart-a47088f6-d041-4178-9d47-615f24e00b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116138034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.116138034
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.592330174
Short name T568
Test name
Test status
Simulation time 81457518151 ps
CPU time 127.81 seconds
Started Jul 27 06:23:59 PM PDT 24
Finished Jul 27 06:26:07 PM PDT 24
Peak memory 200176 kb
Host smart-ac9d764e-c2d9-40b0-96d0-bc149aa48ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592330174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.592330174
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1257925034
Short name T311
Test name
Test status
Simulation time 1426568156 ps
CPU time 5 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:03 PM PDT 24
Peak memory 199884 kb
Host smart-2ace31fb-aa41-4a60-a8e5-058bd477f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257925034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1257925034
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1179044478
Short name T511
Test name
Test status
Simulation time 26056034404 ps
CPU time 41.23 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:24:39 PM PDT 24
Peak memory 200236 kb
Host smart-c03f9565-e893-4d86-9b45-061803fe1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179044478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1179044478
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3988996004
Short name T301
Test name
Test status
Simulation time 108518979389 ps
CPU time 235.04 seconds
Started Jul 27 06:31:07 PM PDT 24
Finished Jul 27 06:35:02 PM PDT 24
Peak memory 200096 kb
Host smart-9a027dd3-c1a7-4630-a9fd-c4217fad1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988996004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3988996004
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1679156973
Short name T1108
Test name
Test status
Simulation time 40857566022 ps
CPU time 69.16 seconds
Started Jul 27 06:31:10 PM PDT 24
Finished Jul 27 06:32:19 PM PDT 24
Peak memory 200248 kb
Host smart-7fcf9cbb-e6ee-4079-8b00-614d05be2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679156973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1679156973
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1452903262
Short name T1166
Test name
Test status
Simulation time 167193664337 ps
CPU time 14.15 seconds
Started Jul 27 06:31:06 PM PDT 24
Finished Jul 27 06:31:21 PM PDT 24
Peak memory 199844 kb
Host smart-9564d5e0-6afc-4970-9293-a12202a36642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452903262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1452903262
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1959936039
Short name T228
Test name
Test status
Simulation time 153130696572 ps
CPU time 55.26 seconds
Started Jul 27 06:31:10 PM PDT 24
Finished Jul 27 06:32:06 PM PDT 24
Peak memory 200196 kb
Host smart-9551d7d6-972f-43b8-8b46-97c990801e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959936039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1959936039
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2634476443
Short name T197
Test name
Test status
Simulation time 214103041051 ps
CPU time 103.81 seconds
Started Jul 27 06:31:08 PM PDT 24
Finished Jul 27 06:32:52 PM PDT 24
Peak memory 199988 kb
Host smart-6a9aef82-2c45-4bf4-9a7e-a3aada9eff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634476443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2634476443
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1095349985
Short name T330
Test name
Test status
Simulation time 24501100089 ps
CPU time 20.56 seconds
Started Jul 27 06:31:09 PM PDT 24
Finished Jul 27 06:31:30 PM PDT 24
Peak memory 200108 kb
Host smart-096602eb-766c-42bd-a2ab-d4fe35c5bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095349985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1095349985
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.425636281
Short name T794
Test name
Test status
Simulation time 22836977 ps
CPU time 0.57 seconds
Started Jul 27 06:24:16 PM PDT 24
Finished Jul 27 06:24:17 PM PDT 24
Peak memory 195564 kb
Host smart-202f32c9-1552-4c09-9b5b-d9ded8a624c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425636281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.425636281
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2806748074
Short name T1040
Test name
Test status
Simulation time 20559352115 ps
CPU time 29.89 seconds
Started Jul 27 06:24:08 PM PDT 24
Finished Jul 27 06:24:38 PM PDT 24
Peak memory 200440 kb
Host smart-9ffe3c4a-63fc-4c78-ae5e-6e3069696659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806748074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2806748074
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4178926106
Short name T907
Test name
Test status
Simulation time 9412374514 ps
CPU time 15.46 seconds
Started Jul 27 06:24:10 PM PDT 24
Finished Jul 27 06:24:25 PM PDT 24
Peak memory 199852 kb
Host smart-dfa9bbaf-6ee4-4ac3-85f7-ca374da31af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178926106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4178926106
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.183507799
Short name T960
Test name
Test status
Simulation time 39109232145 ps
CPU time 9.39 seconds
Started Jul 27 06:24:07 PM PDT 24
Finished Jul 27 06:24:16 PM PDT 24
Peak memory 200156 kb
Host smart-87512d78-a9e3-4de0-ac0e-5b3f0915b42f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183507799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.183507799
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2388839481
Short name T416
Test name
Test status
Simulation time 92506395093 ps
CPU time 257.09 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:28:35 PM PDT 24
Peak memory 200248 kb
Host smart-e189a118-01b4-4f34-b163-ff17a8279a90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388839481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2388839481
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.771013150
Short name T537
Test name
Test status
Simulation time 3320856326 ps
CPU time 1.46 seconds
Started Jul 27 06:24:10 PM PDT 24
Finished Jul 27 06:24:11 PM PDT 24
Peak memory 197548 kb
Host smart-faf6b33b-e80e-4402-87cf-3b8ca146363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771013150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.771013150
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.757754368
Short name T413
Test name
Test status
Simulation time 86470469765 ps
CPU time 159.44 seconds
Started Jul 27 06:24:07 PM PDT 24
Finished Jul 27 06:26:46 PM PDT 24
Peak memory 200324 kb
Host smart-1296838f-8439-4411-8445-6d7488677a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757754368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.757754368
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1605917095
Short name T275
Test name
Test status
Simulation time 10314286725 ps
CPU time 239.5 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:28:18 PM PDT 24
Peak memory 200184 kb
Host smart-93a6614c-bdc8-4a2f-a60c-5a9da7f4d850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605917095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1605917095
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1345692095
Short name T1125
Test name
Test status
Simulation time 3645125591 ps
CPU time 6.11 seconds
Started Jul 27 06:24:06 PM PDT 24
Finished Jul 27 06:24:12 PM PDT 24
Peak memory 198384 kb
Host smart-38c63cbf-9553-436d-8b31-d733906a6078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345692095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1345692095
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3841509532
Short name T625
Test name
Test status
Simulation time 13331040140 ps
CPU time 20.91 seconds
Started Jul 27 06:24:06 PM PDT 24
Finished Jul 27 06:24:27 PM PDT 24
Peak memory 200260 kb
Host smart-b596e7de-a653-4e6d-92d1-a0d67274cf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841509532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3841509532
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1463462825
Short name T597
Test name
Test status
Simulation time 1474387767 ps
CPU time 1.18 seconds
Started Jul 27 06:24:09 PM PDT 24
Finished Jul 27 06:24:11 PM PDT 24
Peak memory 195720 kb
Host smart-e52e0e63-203e-442a-bfb2-f0b7668327c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463462825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1463462825
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4288590519
Short name T1046
Test name
Test status
Simulation time 501215964 ps
CPU time 1.89 seconds
Started Jul 27 06:24:08 PM PDT 24
Finished Jul 27 06:24:10 PM PDT 24
Peak memory 199192 kb
Host smart-ea83388b-3de0-4f90-9af2-41c4159ef79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288590519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4288590519
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3873432621
Short name T25
Test name
Test status
Simulation time 56485176500 ps
CPU time 693.77 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:35:52 PM PDT 24
Peak memory 216360 kb
Host smart-1f09f768-6f5d-4ace-9507-229085021969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873432621 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3873432621
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3346626560
Short name T444
Test name
Test status
Simulation time 13063931126 ps
CPU time 21.88 seconds
Started Jul 27 06:24:10 PM PDT 24
Finished Jul 27 06:24:32 PM PDT 24
Peak memory 200184 kb
Host smart-b7bf9671-d7e4-42fd-a6f9-dfa19c382f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346626560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3346626560
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1884151768
Short name T315
Test name
Test status
Simulation time 50765827406 ps
CPU time 41.93 seconds
Started Jul 27 06:24:09 PM PDT 24
Finished Jul 27 06:24:51 PM PDT 24
Peak memory 200256 kb
Host smart-5c61efb1-ead9-4d70-b51c-5a488182b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884151768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1884151768
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3278340436
Short name T773
Test name
Test status
Simulation time 58926782027 ps
CPU time 75.86 seconds
Started Jul 27 06:31:09 PM PDT 24
Finished Jul 27 06:32:25 PM PDT 24
Peak memory 200216 kb
Host smart-d6b55275-56a8-4aa4-a28a-cb7de667c0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278340436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3278340436
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3627092810
Short name T176
Test name
Test status
Simulation time 32668505547 ps
CPU time 28.36 seconds
Started Jul 27 06:31:09 PM PDT 24
Finished Jul 27 06:31:37 PM PDT 24
Peak memory 200216 kb
Host smart-b9bd0f17-d730-42d5-a094-3f5ea03f64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627092810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3627092810
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1332565569
Short name T1170
Test name
Test status
Simulation time 17018242886 ps
CPU time 12.29 seconds
Started Jul 27 06:31:16 PM PDT 24
Finished Jul 27 06:31:28 PM PDT 24
Peak memory 200020 kb
Host smart-7bc81455-c51c-4172-9c89-56af33cb7376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332565569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1332565569
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1269745127
Short name T493
Test name
Test status
Simulation time 104155547776 ps
CPU time 246.83 seconds
Started Jul 27 06:31:16 PM PDT 24
Finished Jul 27 06:35:23 PM PDT 24
Peak memory 200132 kb
Host smart-39a6d906-5d54-4352-84ec-562e544855ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269745127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1269745127
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2759211303
Short name T1003
Test name
Test status
Simulation time 170177599824 ps
CPU time 126.07 seconds
Started Jul 27 06:31:18 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200120 kb
Host smart-1d6383e8-ed78-4bdf-a595-c4394f4764c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759211303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2759211303
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.521149172
Short name T839
Test name
Test status
Simulation time 13118636834 ps
CPU time 18.61 seconds
Started Jul 27 06:31:25 PM PDT 24
Finished Jul 27 06:31:44 PM PDT 24
Peak memory 200244 kb
Host smart-f5f3912a-46c8-4215-bc69-47867415c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521149172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.521149172
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.93731048
Short name T1179
Test name
Test status
Simulation time 10770056406 ps
CPU time 14.32 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:31:31 PM PDT 24
Peak memory 200192 kb
Host smart-c19552e5-762b-40d0-9f3d-0ab451531fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93731048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.93731048
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1324701548
Short name T898
Test name
Test status
Simulation time 85075455103 ps
CPU time 111.79 seconds
Started Jul 27 06:31:19 PM PDT 24
Finished Jul 27 06:33:11 PM PDT 24
Peak memory 200236 kb
Host smart-a5b40823-c612-46ec-a052-fe25829fe883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324701548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1324701548
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1083912272
Short name T878
Test name
Test status
Simulation time 144836029484 ps
CPU time 21.58 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:31:39 PM PDT 24
Peak memory 198888 kb
Host smart-8f76247c-f316-4bd3-a26e-50b383286a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083912272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1083912272
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3096105240
Short name T97
Test name
Test status
Simulation time 8514411101 ps
CPU time 16.19 seconds
Started Jul 27 06:31:19 PM PDT 24
Finished Jul 27 06:31:36 PM PDT 24
Peak memory 200216 kb
Host smart-5f03d792-7fc2-4501-a54b-8a2827eea737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096105240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3096105240
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3182353866
Short name T610
Test name
Test status
Simulation time 22351113 ps
CPU time 0.56 seconds
Started Jul 27 06:24:19 PM PDT 24
Finished Jul 27 06:24:19 PM PDT 24
Peak memory 195620 kb
Host smart-ded0554d-0355-4bde-975f-3d7b82a02666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182353866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3182353866
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3293312480
Short name T938
Test name
Test status
Simulation time 36748174625 ps
CPU time 71.68 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:25:29 PM PDT 24
Peak memory 200180 kb
Host smart-f9a35000-c306-44b6-821d-b17789493917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293312480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3293312480
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1213067664
Short name T923
Test name
Test status
Simulation time 249691079724 ps
CPU time 61.95 seconds
Started Jul 27 06:24:16 PM PDT 24
Finished Jul 27 06:25:18 PM PDT 24
Peak memory 200252 kb
Host smart-c76f45a6-5ccc-4837-90ef-c18c32d1e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213067664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1213067664
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2877066595
Short name T1052
Test name
Test status
Simulation time 63872457388 ps
CPU time 95.09 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 200260 kb
Host smart-c4f45953-e77f-4844-a4ab-09661fafe063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877066595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2877066595
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1567935416
Short name T36
Test name
Test status
Simulation time 47225575530 ps
CPU time 23.2 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:24:41 PM PDT 24
Peak memory 200240 kb
Host smart-d0a28b22-763a-46d6-939d-3f844441717c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567935416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1567935416
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.584750933
Short name T256
Test name
Test status
Simulation time 104713107388 ps
CPU time 484.74 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:32:22 PM PDT 24
Peak memory 200112 kb
Host smart-eb33839d-ff7e-4739-bb7e-2d45b0aabbd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584750933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.584750933
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3373004769
Short name T548
Test name
Test status
Simulation time 1910756842 ps
CPU time 2.88 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:24:20 PM PDT 24
Peak memory 198744 kb
Host smart-947d4295-795c-44ae-ae12-4c1f5c0e891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373004769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3373004769
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2420381590
Short name T1114
Test name
Test status
Simulation time 52361211327 ps
CPU time 64.52 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:25:22 PM PDT 24
Peak memory 208460 kb
Host smart-88c7f418-0eed-47e0-a950-48198deb724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420381590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2420381590
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3049642544
Short name T949
Test name
Test status
Simulation time 10171648676 ps
CPU time 520.69 seconds
Started Jul 27 06:24:16 PM PDT 24
Finished Jul 27 06:32:57 PM PDT 24
Peak memory 200248 kb
Host smart-98030d2f-d5b9-4bb8-b9e1-f230d1013205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049642544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3049642544
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2002825839
Short name T464
Test name
Test status
Simulation time 1985304744 ps
CPU time 11.21 seconds
Started Jul 27 06:24:16 PM PDT 24
Finished Jul 27 06:24:27 PM PDT 24
Peak memory 198284 kb
Host smart-123bc944-8517-4ff7-ba3e-ae1b9731b7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002825839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2002825839
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3122204655
Short name T944
Test name
Test status
Simulation time 221532372367 ps
CPU time 44.62 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:25:02 PM PDT 24
Peak memory 200240 kb
Host smart-e0930ece-f023-4533-a18f-19cb3cb37a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122204655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3122204655
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4276966132
Short name T811
Test name
Test status
Simulation time 2712431828 ps
CPU time 4.54 seconds
Started Jul 27 06:24:20 PM PDT 24
Finished Jul 27 06:24:24 PM PDT 24
Peak memory 196784 kb
Host smart-90153930-6277-4ae8-a564-2349865a61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276966132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4276966132
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3352890852
Short name T299
Test name
Test status
Simulation time 305675091 ps
CPU time 1.45 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:24:19 PM PDT 24
Peak memory 200056 kb
Host smart-9fe31c13-74b9-4d47-b136-aa8fe439e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352890852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3352890852
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.4041839756
Short name T813
Test name
Test status
Simulation time 103480678581 ps
CPU time 92.11 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:25:50 PM PDT 24
Peak memory 215632 kb
Host smart-d5f57fce-2a0a-454f-8b14-038a5c7f8082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041839756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4041839756
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4290573946
Short name T870
Test name
Test status
Simulation time 82259199027 ps
CPU time 561.49 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 225088 kb
Host smart-9a4b239e-5cc2-44c4-a459-1b6820bf633b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290573946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4290573946
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3484026840
Short name T294
Test name
Test status
Simulation time 13883019938 ps
CPU time 10.86 seconds
Started Jul 27 06:24:18 PM PDT 24
Finished Jul 27 06:24:29 PM PDT 24
Peak memory 200148 kb
Host smart-4ddfc300-3391-4d68-9126-6dd1eafa6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484026840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3484026840
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.143488700
Short name T488
Test name
Test status
Simulation time 40777861184 ps
CPU time 33.93 seconds
Started Jul 27 06:24:16 PM PDT 24
Finished Jul 27 06:24:50 PM PDT 24
Peak memory 200224 kb
Host smart-7a990e6c-c518-4f61-b8df-67bc26e6159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143488700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.143488700
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2616051941
Short name T1033
Test name
Test status
Simulation time 118016221189 ps
CPU time 44.55 seconds
Started Jul 27 06:31:16 PM PDT 24
Finished Jul 27 06:32:01 PM PDT 24
Peak memory 200188 kb
Host smart-c8a1b6b1-832a-4fc1-912c-721f0233a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616051941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2616051941
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1887274584
Short name T1134
Test name
Test status
Simulation time 11578528571 ps
CPU time 46.46 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:32:03 PM PDT 24
Peak memory 200196 kb
Host smart-48211af8-038f-49a4-8f9b-22c009d2ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887274584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1887274584
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.262672450
Short name T696
Test name
Test status
Simulation time 85685860215 ps
CPU time 136.68 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:33:33 PM PDT 24
Peak memory 200212 kb
Host smart-1395fb50-3b3e-42e8-a09e-b00b43b718dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262672450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.262672450
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3014480422
Short name T791
Test name
Test status
Simulation time 152586219875 ps
CPU time 142.15 seconds
Started Jul 27 06:31:18 PM PDT 24
Finished Jul 27 06:33:40 PM PDT 24
Peak memory 200224 kb
Host smart-c9eb0004-a0ea-4cd3-ac1e-18e566c9fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014480422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3014480422
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3356735221
Short name T328
Test name
Test status
Simulation time 98280298018 ps
CPU time 32.14 seconds
Started Jul 27 06:31:16 PM PDT 24
Finished Jul 27 06:31:49 PM PDT 24
Peak memory 200136 kb
Host smart-2ead38e4-311d-4a63-a843-236c1440845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356735221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3356735221
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.68361459
Short name T679
Test name
Test status
Simulation time 182135547596 ps
CPU time 127.2 seconds
Started Jul 27 06:31:18 PM PDT 24
Finished Jul 27 06:33:26 PM PDT 24
Peak memory 200152 kb
Host smart-2c65af30-ed7c-4d3c-a1ed-46cefd21a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68361459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.68361459
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2821234373
Short name T173
Test name
Test status
Simulation time 134784129739 ps
CPU time 102.65 seconds
Started Jul 27 06:31:17 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200204 kb
Host smart-0e32d0b4-d764-476c-8084-a2444c939a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821234373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2821234373
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3022170718
Short name T858
Test name
Test status
Simulation time 24778470 ps
CPU time 0.58 seconds
Started Jul 27 06:24:38 PM PDT 24
Finished Jul 27 06:24:39 PM PDT 24
Peak memory 195904 kb
Host smart-907b94bd-bcf3-43e6-885a-14ec4c24d8f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022170718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3022170718
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1785294812
Short name T807
Test name
Test status
Simulation time 33886477164 ps
CPU time 13.45 seconds
Started Jul 27 06:24:17 PM PDT 24
Finished Jul 27 06:24:31 PM PDT 24
Peak memory 200256 kb
Host smart-7a00b5bc-ef72-4535-a29c-72e8e128c2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785294812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1785294812
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3094807508
Short name T687
Test name
Test status
Simulation time 19502111879 ps
CPU time 4.19 seconds
Started Jul 27 06:24:29 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 200188 kb
Host smart-65b50bb0-08af-4100-9945-1dfd0b467208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094807508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3094807508
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2927414288
Short name T848
Test name
Test status
Simulation time 13584850915 ps
CPU time 5.16 seconds
Started Jul 27 06:24:27 PM PDT 24
Finished Jul 27 06:24:32 PM PDT 24
Peak memory 197184 kb
Host smart-04b1a005-bfdd-4760-8cac-3b6e7b55fcd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927414288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2927414288
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3936598583
Short name T383
Test name
Test status
Simulation time 99608323930 ps
CPU time 364.65 seconds
Started Jul 27 06:24:28 PM PDT 24
Finished Jul 27 06:30:33 PM PDT 24
Peak memory 200200 kb
Host smart-0775dc6f-408e-4f2e-8a3a-b7b22b744ae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936598583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3936598583
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1726308853
Short name T397
Test name
Test status
Simulation time 253155084 ps
CPU time 1.06 seconds
Started Jul 27 06:24:30 PM PDT 24
Finished Jul 27 06:24:31 PM PDT 24
Peak memory 198132 kb
Host smart-aa61b40c-f66a-4ef2-8544-6825471bd6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726308853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1726308853
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2273728416
Short name T266
Test name
Test status
Simulation time 43387296420 ps
CPU time 69.64 seconds
Started Jul 27 06:24:26 PM PDT 24
Finished Jul 27 06:25:35 PM PDT 24
Peak memory 199324 kb
Host smart-48653f85-6c3d-4d28-9201-e783c855fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273728416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2273728416
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.202801515
Short name T1001
Test name
Test status
Simulation time 13395357764 ps
CPU time 70.65 seconds
Started Jul 27 06:24:27 PM PDT 24
Finished Jul 27 06:25:37 PM PDT 24
Peak memory 200176 kb
Host smart-03cf174f-285c-4300-ba8e-deb204c183b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202801515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.202801515
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3859991586
Short name T401
Test name
Test status
Simulation time 3081082935 ps
CPU time 5.98 seconds
Started Jul 27 06:24:27 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 198248 kb
Host smart-998317da-0f23-4e6c-b801-eb6920149cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859991586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3859991586
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1646249788
Short name T912
Test name
Test status
Simulation time 67300983663 ps
CPU time 121.74 seconds
Started Jul 27 06:24:27 PM PDT 24
Finished Jul 27 06:26:28 PM PDT 24
Peak memory 200188 kb
Host smart-7583e4eb-b6c5-454c-941d-d8be29505bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646249788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1646249788
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1074266846
Short name T784
Test name
Test status
Simulation time 5726388817 ps
CPU time 2.78 seconds
Started Jul 27 06:24:26 PM PDT 24
Finished Jul 27 06:24:29 PM PDT 24
Peak memory 197108 kb
Host smart-8d67d75d-b941-4cef-8681-6c55f9efe2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074266846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1074266846
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3979846269
Short name T856
Test name
Test status
Simulation time 933330253 ps
CPU time 3.3 seconds
Started Jul 27 06:24:19 PM PDT 24
Finished Jul 27 06:24:22 PM PDT 24
Peak memory 199920 kb
Host smart-faae7bfc-dac4-4b3b-92e5-bbd30d14bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979846269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3979846269
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.769162351
Short name T845
Test name
Test status
Simulation time 336218201945 ps
CPU time 582.02 seconds
Started Jul 27 06:24:28 PM PDT 24
Finished Jul 27 06:34:10 PM PDT 24
Peak memory 200140 kb
Host smart-f0f63aca-24fd-4aa9-b8bb-8aa532e96d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769162351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.769162351
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3354856931
Short name T707
Test name
Test status
Simulation time 210772314064 ps
CPU time 565.87 seconds
Started Jul 27 06:24:25 PM PDT 24
Finished Jul 27 06:33:51 PM PDT 24
Peak memory 213596 kb
Host smart-6cb85cff-5732-4cfa-99c5-52d313e8c489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354856931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3354856931
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4027715379
Short name T892
Test name
Test status
Simulation time 993520552 ps
CPU time 4.4 seconds
Started Jul 27 06:24:26 PM PDT 24
Finished Jul 27 06:24:31 PM PDT 24
Peak memory 198868 kb
Host smart-0de285ed-9e82-40a4-9774-2d6b6a3130ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027715379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4027715379
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3134820741
Short name T478
Test name
Test status
Simulation time 35014819667 ps
CPU time 26.04 seconds
Started Jul 27 06:24:20 PM PDT 24
Finished Jul 27 06:24:46 PM PDT 24
Peak memory 200264 kb
Host smart-476f5de9-a7cc-4eae-af54-fcf1f64a2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134820741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3134820741
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.209047927
Short name T423
Test name
Test status
Simulation time 50984429386 ps
CPU time 26.42 seconds
Started Jul 27 06:31:29 PM PDT 24
Finished Jul 27 06:31:56 PM PDT 24
Peak memory 199976 kb
Host smart-b94dd657-ec55-4ade-a192-69cf1ec26694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209047927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.209047927
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1605198368
Short name T624
Test name
Test status
Simulation time 30077349980 ps
CPU time 48.97 seconds
Started Jul 27 06:31:26 PM PDT 24
Finished Jul 27 06:32:15 PM PDT 24
Peak memory 200232 kb
Host smart-917789e9-0fb8-49a5-8e5d-b0442b01a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605198368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1605198368
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3423700831
Short name T1130
Test name
Test status
Simulation time 57817911427 ps
CPU time 32.18 seconds
Started Jul 27 06:31:25 PM PDT 24
Finished Jul 27 06:31:58 PM PDT 24
Peak memory 200112 kb
Host smart-6c9618f8-9f20-4879-bc55-53dcbc24ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423700831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3423700831
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.412963274
Short name T439
Test name
Test status
Simulation time 189391902350 ps
CPU time 28.69 seconds
Started Jul 27 06:31:25 PM PDT 24
Finished Jul 27 06:31:54 PM PDT 24
Peak memory 200184 kb
Host smart-cd5ef112-3f6f-4f3d-a5e3-b853cd41eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412963274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.412963274
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3264096843
Short name T1115
Test name
Test status
Simulation time 10801178737 ps
CPU time 20.06 seconds
Started Jul 27 06:31:27 PM PDT 24
Finished Jul 27 06:31:47 PM PDT 24
Peak memory 200196 kb
Host smart-eddaadc1-3b66-4f92-a474-0708fdfb64f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264096843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3264096843
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3817713639
Short name T1168
Test name
Test status
Simulation time 157869326068 ps
CPU time 98.82 seconds
Started Jul 27 06:31:25 PM PDT 24
Finished Jul 27 06:33:04 PM PDT 24
Peak memory 200176 kb
Host smart-99f475de-d61b-4029-a0a9-9ebab5d344fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817713639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3817713639
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1272910886
Short name T334
Test name
Test status
Simulation time 39232542477 ps
CPU time 37.1 seconds
Started Jul 27 06:31:27 PM PDT 24
Finished Jul 27 06:32:04 PM PDT 24
Peak memory 200204 kb
Host smart-ac0be9c3-e560-4b3f-8673-1535000f9c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272910886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1272910886
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4033679636
Short name T210
Test name
Test status
Simulation time 31872173249 ps
CPU time 52.58 seconds
Started Jul 27 06:31:29 PM PDT 24
Finished Jul 27 06:32:22 PM PDT 24
Peak memory 200160 kb
Host smart-626d98d8-8086-4895-a7de-12168d377b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033679636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4033679636
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3364946430
Short name T497
Test name
Test status
Simulation time 71378244199 ps
CPU time 7.17 seconds
Started Jul 27 06:31:26 PM PDT 24
Finished Jul 27 06:31:33 PM PDT 24
Peak memory 200236 kb
Host smart-2030d228-f456-48d5-b535-a641e3496441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364946430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3364946430
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4109911091
Short name T37
Test name
Test status
Simulation time 112597687501 ps
CPU time 39.93 seconds
Started Jul 27 06:31:24 PM PDT 24
Finished Jul 27 06:32:04 PM PDT 24
Peak memory 199976 kb
Host smart-6530777c-b218-4ecb-804f-e6df79abbf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109911091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4109911091
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4218736917
Short name T482
Test name
Test status
Simulation time 31644456 ps
CPU time 0.54 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:24:44 PM PDT 24
Peak memory 194976 kb
Host smart-1a0b38fb-b974-4666-a6a1-cb3fc945afae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218736917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4218736917
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.346661264
Short name T373
Test name
Test status
Simulation time 73905338931 ps
CPU time 39.25 seconds
Started Jul 27 06:24:35 PM PDT 24
Finished Jul 27 06:25:15 PM PDT 24
Peak memory 200244 kb
Host smart-6fc65597-150e-45b2-8f99-0d91843e0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346661264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.346661264
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3438161606
Short name T316
Test name
Test status
Simulation time 139547447479 ps
CPU time 38.63 seconds
Started Jul 27 06:24:38 PM PDT 24
Finished Jul 27 06:25:17 PM PDT 24
Peak memory 200216 kb
Host smart-067691bd-30cd-4d24-a3b7-a3167f3344a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438161606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3438161606
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1807917611
Short name T1127
Test name
Test status
Simulation time 119523233808 ps
CPU time 30.44 seconds
Started Jul 27 06:24:35 PM PDT 24
Finished Jul 27 06:25:06 PM PDT 24
Peak memory 200252 kb
Host smart-80a4a289-9efe-4e0e-bcd1-32e9b910c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807917611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1807917611
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3108756833
Short name T796
Test name
Test status
Simulation time 68939031419 ps
CPU time 54.23 seconds
Started Jul 27 06:24:35 PM PDT 24
Finished Jul 27 06:25:29 PM PDT 24
Peak memory 200232 kb
Host smart-1303a3b1-1255-4fd4-85c1-75a5265f4209
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108756833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3108756833
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1852850474
Short name T407
Test name
Test status
Simulation time 105323438822 ps
CPU time 644.8 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:35:29 PM PDT 24
Peak memory 200204 kb
Host smart-358d69a2-4471-43a1-9976-3120e140c722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852850474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1852850474
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.167338750
Short name T43
Test name
Test status
Simulation time 3050023022 ps
CPU time 1.56 seconds
Started Jul 27 06:24:34 PM PDT 24
Finished Jul 27 06:24:36 PM PDT 24
Peak memory 196048 kb
Host smart-6af19eb7-9b91-40f5-834b-7e5970d02079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167338750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.167338750
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3033012138
Short name T1010
Test name
Test status
Simulation time 115143766123 ps
CPU time 155.81 seconds
Started Jul 27 06:24:38 PM PDT 24
Finished Jul 27 06:27:13 PM PDT 24
Peak memory 200312 kb
Host smart-c33819a8-e11b-44a2-beda-e97b9bdbd59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033012138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3033012138
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.713168830
Short name T566
Test name
Test status
Simulation time 21726508287 ps
CPU time 308.8 seconds
Started Jul 27 06:24:46 PM PDT 24
Finished Jul 27 06:29:55 PM PDT 24
Peak memory 200228 kb
Host smart-8aa63567-0da2-4440-b722-7be22387d1bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713168830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.713168830
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2192359776
Short name T356
Test name
Test status
Simulation time 2446778426 ps
CPU time 3.69 seconds
Started Jul 27 06:24:34 PM PDT 24
Finished Jul 27 06:24:38 PM PDT 24
Peak memory 198376 kb
Host smart-2e2a1d33-339e-4507-88ff-8c5674a9eb55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192359776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2192359776
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3621669280
Short name T843
Test name
Test status
Simulation time 121568191994 ps
CPU time 85.43 seconds
Started Jul 27 06:24:35 PM PDT 24
Finished Jul 27 06:26:01 PM PDT 24
Peak memory 200116 kb
Host smart-8dca9822-b2d9-457a-9eb0-b90c6c9e0fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621669280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3621669280
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.631038395
Short name T455
Test name
Test status
Simulation time 1769076327 ps
CPU time 1.36 seconds
Started Jul 27 06:24:36 PM PDT 24
Finished Jul 27 06:24:37 PM PDT 24
Peak memory 195680 kb
Host smart-9987fcf5-6cb5-4d36-b379-60edcec01e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631038395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.631038395
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1652402196
Short name T779
Test name
Test status
Simulation time 644492251 ps
CPU time 2.35 seconds
Started Jul 27 06:24:36 PM PDT 24
Finished Jul 27 06:24:38 PM PDT 24
Peak memory 199900 kb
Host smart-8ce1e183-d685-454e-b27d-f60ea08e5fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652402196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1652402196
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3973806568
Short name T599
Test name
Test status
Simulation time 727492512653 ps
CPU time 185.29 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:27:49 PM PDT 24
Peak memory 200156 kb
Host smart-3bb01a2b-f81f-4694-a9e3-905aa7ba0c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973806568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3973806568
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.867719685
Short name T899
Test name
Test status
Simulation time 1646685605 ps
CPU time 1.75 seconds
Started Jul 27 06:24:37 PM PDT 24
Finished Jul 27 06:24:39 PM PDT 24
Peak memory 198640 kb
Host smart-ce2ad785-a869-4bd7-b2c2-9de4816ff83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867719685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.867719685
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.881363251
Short name T1027
Test name
Test status
Simulation time 4212362271 ps
CPU time 7.35 seconds
Started Jul 27 06:24:34 PM PDT 24
Finished Jul 27 06:24:42 PM PDT 24
Peak memory 199604 kb
Host smart-1c9db157-439b-401c-96c0-3eea3b7696cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881363251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.881363251
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.84600447
Short name T1169
Test name
Test status
Simulation time 51917239450 ps
CPU time 75.9 seconds
Started Jul 27 06:31:27 PM PDT 24
Finished Jul 27 06:32:43 PM PDT 24
Peak memory 200228 kb
Host smart-6c5586f0-0b06-4f08-ac8f-ca76e3810584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84600447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.84600447
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2434084821
Short name T753
Test name
Test status
Simulation time 44477162054 ps
CPU time 17.75 seconds
Started Jul 27 06:31:25 PM PDT 24
Finished Jul 27 06:31:43 PM PDT 24
Peak memory 200144 kb
Host smart-40cb96dc-dbd5-43c8-8d0d-6666b1d1004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434084821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2434084821
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.868166328
Short name T202
Test name
Test status
Simulation time 36428343440 ps
CPU time 63.33 seconds
Started Jul 27 06:31:29 PM PDT 24
Finished Jul 27 06:32:33 PM PDT 24
Peak memory 200212 kb
Host smart-80065f12-a89e-4c79-adc8-938406ba3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868166328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.868166328
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2796038384
Short name T438
Test name
Test status
Simulation time 33127549838 ps
CPU time 49.7 seconds
Started Jul 27 06:31:24 PM PDT 24
Finished Jul 27 06:32:14 PM PDT 24
Peak memory 199856 kb
Host smart-57ee87a1-f4e6-43d9-ba76-057d4a8e25ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796038384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2796038384
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2972198280
Short name T442
Test name
Test status
Simulation time 6211023030 ps
CPU time 10.4 seconds
Started Jul 27 06:31:36 PM PDT 24
Finished Jul 27 06:31:47 PM PDT 24
Peak memory 199844 kb
Host smart-ba9ad9db-e0ea-4fea-b3b9-59ac2ad922ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972198280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2972198280
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.634549983
Short name T278
Test name
Test status
Simulation time 29749268167 ps
CPU time 44.67 seconds
Started Jul 27 06:31:34 PM PDT 24
Finished Jul 27 06:32:19 PM PDT 24
Peak memory 200252 kb
Host smart-7dbdfd83-9a05-4c93-8d89-c3350821ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634549983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.634549983
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2703543266
Short name T614
Test name
Test status
Simulation time 183900021493 ps
CPU time 201.28 seconds
Started Jul 27 06:31:36 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 200220 kb
Host smart-3c89758b-bca9-4efd-ace1-3a2c1787561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703543266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2703543266
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1451337114
Short name T542
Test name
Test status
Simulation time 22449894 ps
CPU time 0.55 seconds
Started Jul 27 06:24:52 PM PDT 24
Finished Jul 27 06:24:52 PM PDT 24
Peak memory 194540 kb
Host smart-61ccc425-d33a-4700-9fc6-f99521759f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451337114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1451337114
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2157470056
Short name T392
Test name
Test status
Simulation time 176917472750 ps
CPU time 173.17 seconds
Started Jul 27 06:24:45 PM PDT 24
Finished Jul 27 06:27:39 PM PDT 24
Peak memory 200192 kb
Host smart-606a2ff8-df7c-4db7-8721-89691b32862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157470056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2157470056
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1314356293
Short name T552
Test name
Test status
Simulation time 149698343143 ps
CPU time 105.37 seconds
Started Jul 27 06:24:45 PM PDT 24
Finished Jul 27 06:26:30 PM PDT 24
Peak memory 200220 kb
Host smart-d1b3edb8-2864-4dab-9ccf-ff53741197e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314356293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1314356293
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.2389393955
Short name T729
Test name
Test status
Simulation time 2867940852 ps
CPU time 2.65 seconds
Started Jul 27 06:24:46 PM PDT 24
Finished Jul 27 06:24:49 PM PDT 24
Peak memory 199860 kb
Host smart-4aa1b4b2-4ae3-4052-bd47-af40b7defb6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389393955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2389393955
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2533950080
Short name T1059
Test name
Test status
Simulation time 77124079305 ps
CPU time 177.56 seconds
Started Jul 27 06:24:56 PM PDT 24
Finished Jul 27 06:27:54 PM PDT 24
Peak memory 200200 kb
Host smart-da7a7c6b-19cc-4828-a04a-a65ac8766848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533950080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2533950080
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.483001402
Short name T550
Test name
Test status
Simulation time 6377333321 ps
CPU time 10.21 seconds
Started Jul 27 06:24:43 PM PDT 24
Finished Jul 27 06:24:53 PM PDT 24
Peak memory 200024 kb
Host smart-f57dcd27-8a6a-4f1d-85a5-4f894ec07c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483001402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.483001402
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.794590746
Short name T646
Test name
Test status
Simulation time 48982666669 ps
CPU time 13.53 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:24:58 PM PDT 24
Peak memory 196164 kb
Host smart-a2d70e7a-1384-4d97-aee9-966f09119598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794590746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.794590746
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2489821930
Short name T539
Test name
Test status
Simulation time 18791210863 ps
CPU time 230.2 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:28:35 PM PDT 24
Peak memory 200224 kb
Host smart-b33e2954-b7c9-4ba5-8a71-a047b00351d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489821930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2489821930
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2345216811
Short name T937
Test name
Test status
Simulation time 7450297860 ps
CPU time 17.24 seconds
Started Jul 27 06:24:47 PM PDT 24
Finished Jul 27 06:25:04 PM PDT 24
Peak memory 199524 kb
Host smart-e77a3b68-6f98-40af-8d19-f75fc4a2e7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345216811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2345216811
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3771156294
Short name T767
Test name
Test status
Simulation time 177925504042 ps
CPU time 119.1 seconds
Started Jul 27 06:24:43 PM PDT 24
Finished Jul 27 06:26:43 PM PDT 24
Peak memory 200028 kb
Host smart-02d08d4e-270c-41a6-9821-549ec6a0db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771156294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3771156294
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1499488287
Short name T10
Test name
Test status
Simulation time 41242699311 ps
CPU time 7.89 seconds
Started Jul 27 06:24:46 PM PDT 24
Finished Jul 27 06:24:54 PM PDT 24
Peak memory 196360 kb
Host smart-aafdfbf4-39b3-4585-a1ce-7bb2e3c3633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499488287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1499488287
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2000381906
Short name T287
Test name
Test status
Simulation time 317199676 ps
CPU time 0.94 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:24:45 PM PDT 24
Peak memory 199944 kb
Host smart-f4789274-7462-4ac6-9cbb-28b148053eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000381906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2000381906
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3557441449
Short name T562
Test name
Test status
Simulation time 99546416885 ps
CPU time 400.25 seconds
Started Jul 27 06:24:52 PM PDT 24
Finished Jul 27 06:31:32 PM PDT 24
Peak memory 200196 kb
Host smart-99367d48-5792-4ad8-bfaf-264b4d208061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557441449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3557441449
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3417887052
Short name T795
Test name
Test status
Simulation time 332625135532 ps
CPU time 683.22 seconds
Started Jul 27 06:24:52 PM PDT 24
Finished Jul 27 06:36:16 PM PDT 24
Peak memory 225032 kb
Host smart-ba8cd0c5-b50b-4471-a9af-aab43d88f4c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417887052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3417887052
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3054597961
Short name T1016
Test name
Test status
Simulation time 8549213382 ps
CPU time 6.96 seconds
Started Jul 27 06:24:44 PM PDT 24
Finished Jul 27 06:24:51 PM PDT 24
Peak memory 200136 kb
Host smart-0abe8cb2-2599-4f9f-9196-80ffe406197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054597961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3054597961
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.773708610
Short name T708
Test name
Test status
Simulation time 45086616250 ps
CPU time 66.05 seconds
Started Jul 27 06:24:46 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 200208 kb
Host smart-131d5581-7220-4d26-a86a-4c270aeaaac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773708610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.773708610
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3005162734
Short name T916
Test name
Test status
Simulation time 26262418015 ps
CPU time 40.45 seconds
Started Jul 27 06:31:34 PM PDT 24
Finished Jul 27 06:32:15 PM PDT 24
Peak memory 200256 kb
Host smart-b0a74b80-18fb-461e-9494-ffe9d37efc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005162734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3005162734
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.487486738
Short name T785
Test name
Test status
Simulation time 32630723933 ps
CPU time 47.62 seconds
Started Jul 27 06:31:35 PM PDT 24
Finished Jul 27 06:32:23 PM PDT 24
Peak memory 200228 kb
Host smart-c46a8ea9-7ea6-4911-a519-4cc35a9d7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487486738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.487486738
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1947550044
Short name T326
Test name
Test status
Simulation time 36453118985 ps
CPU time 33.77 seconds
Started Jul 27 06:31:35 PM PDT 24
Finished Jul 27 06:32:09 PM PDT 24
Peak memory 200136 kb
Host smart-94faeb94-b286-4d03-8e41-7f7c9e253975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947550044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1947550044
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.935598042
Short name T812
Test name
Test status
Simulation time 30108374599 ps
CPU time 14.41 seconds
Started Jul 27 06:31:34 PM PDT 24
Finished Jul 27 06:31:49 PM PDT 24
Peak memory 200224 kb
Host smart-60428934-7ff6-42ba-8b18-372dda62ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935598042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.935598042
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2447558096
Short name T956
Test name
Test status
Simulation time 60851489940 ps
CPU time 24.7 seconds
Started Jul 27 06:31:37 PM PDT 24
Finished Jul 27 06:32:02 PM PDT 24
Peak memory 200180 kb
Host smart-a697c428-fe7f-4e39-953b-5a790c38d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447558096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2447558096
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4116965294
Short name T219
Test name
Test status
Simulation time 24310389142 ps
CPU time 37.62 seconds
Started Jul 27 06:31:37 PM PDT 24
Finished Jul 27 06:32:15 PM PDT 24
Peak memory 200180 kb
Host smart-7c76608f-bea4-412a-94a6-3226dd55de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116965294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4116965294
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.340490132
Short name T238
Test name
Test status
Simulation time 171721796150 ps
CPU time 28.62 seconds
Started Jul 27 06:31:35 PM PDT 24
Finished Jul 27 06:32:04 PM PDT 24
Peak memory 200288 kb
Host smart-bd337ab3-32ad-408b-b6df-edb85ec19e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340490132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.340490132
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.372912639
Short name T188
Test name
Test status
Simulation time 70569071798 ps
CPU time 26.93 seconds
Started Jul 27 06:31:37 PM PDT 24
Finished Jul 27 06:32:04 PM PDT 24
Peak memory 200160 kb
Host smart-86835405-f3e0-4540-a71b-4a35e6214e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372912639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.372912639
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.719179593
Short name T332
Test name
Test status
Simulation time 75198398331 ps
CPU time 33.21 seconds
Started Jul 27 06:31:35 PM PDT 24
Finished Jul 27 06:32:08 PM PDT 24
Peak memory 200240 kb
Host smart-83607634-8179-4e5a-984d-087ca5cb605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719179593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.719179593
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3094526254
Short name T1041
Test name
Test status
Simulation time 111369321691 ps
CPU time 73.16 seconds
Started Jul 27 06:31:43 PM PDT 24
Finished Jul 27 06:32:56 PM PDT 24
Peak memory 200236 kb
Host smart-22b62e9d-a82d-42ae-aa15-6b49d6afbe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094526254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3094526254
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1185914623
Short name T724
Test name
Test status
Simulation time 13011182 ps
CPU time 0.58 seconds
Started Jul 27 06:25:01 PM PDT 24
Finished Jul 27 06:25:01 PM PDT 24
Peak memory 195624 kb
Host smart-e06cdbb4-9230-4f8b-9356-88e5473bdb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185914623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1185914623
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3081123806
Short name T144
Test name
Test status
Simulation time 144937569030 ps
CPU time 40.6 seconds
Started Jul 27 06:24:52 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 200204 kb
Host smart-142abded-6cd4-4f59-aff6-f9f955383b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081123806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3081123806
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1779518968
Short name T1165
Test name
Test status
Simulation time 28165537709 ps
CPU time 27.8 seconds
Started Jul 27 06:24:51 PM PDT 24
Finished Jul 27 06:25:19 PM PDT 24
Peak memory 199876 kb
Host smart-01369c88-c3a8-4eae-9595-2c533f78bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779518968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1779518968
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3249697416
Short name T441
Test name
Test status
Simulation time 192381595882 ps
CPU time 31.92 seconds
Started Jul 27 06:24:55 PM PDT 24
Finished Jul 27 06:25:27 PM PDT 24
Peak memory 200176 kb
Host smart-58b43de2-fc85-4f31-88f2-9c0a5209e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249697416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3249697416
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1540278438
Short name T1140
Test name
Test status
Simulation time 11704269606 ps
CPU time 9.61 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:25:03 PM PDT 24
Peak memory 198560 kb
Host smart-6e6a792c-c0a8-43fe-9445-aaa1b9777041
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540278438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1540278438
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3543443896
Short name T685
Test name
Test status
Simulation time 169606834542 ps
CPU time 454.47 seconds
Started Jul 27 06:25:02 PM PDT 24
Finished Jul 27 06:32:36 PM PDT 24
Peak memory 200132 kb
Host smart-c9c41f61-9c64-4de9-a2ce-c16cc4493301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543443896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3543443896
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.97100487
Short name T384
Test name
Test status
Simulation time 9528145093 ps
CPU time 7.88 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:25:01 PM PDT 24
Peak memory 200128 kb
Host smart-26e984e0-3a0d-4117-94cc-328ba5fb8359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97100487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.97100487
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4081127405
Short name T517
Test name
Test status
Simulation time 156673916185 ps
CPU time 81.18 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:26:14 PM PDT 24
Peak memory 199136 kb
Host smart-07ffdca0-250b-4e02-866c-e099e0a5c7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081127405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4081127405
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4113450871
Short name T783
Test name
Test status
Simulation time 21806924703 ps
CPU time 57.99 seconds
Started Jul 27 06:24:56 PM PDT 24
Finished Jul 27 06:25:54 PM PDT 24
Peak memory 200216 kb
Host smart-f55c0775-6a8e-4fc9-8d4e-e2ea0fa24ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113450871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4113450871
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2155960482
Short name T370
Test name
Test status
Simulation time 4416815804 ps
CPU time 32.07 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:25:25 PM PDT 24
Peak memory 199524 kb
Host smart-df9a64b7-f7eb-4834-b78b-a12cf2c477dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155960482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2155960482
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1281725835
Short name T285
Test name
Test status
Simulation time 119529843890 ps
CPU time 18.81 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:25:12 PM PDT 24
Peak memory 200072 kb
Host smart-1fdbdd1a-f7e7-4e3a-ad26-af34809e1723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281725835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1281725835
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1104022056
Short name T445
Test name
Test status
Simulation time 40876631731 ps
CPU time 9.95 seconds
Started Jul 27 06:24:52 PM PDT 24
Finished Jul 27 06:25:02 PM PDT 24
Peak memory 196648 kb
Host smart-527bf48f-3b7e-4511-a8b1-7d10745cff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104022056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1104022056
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.349781617
Short name T967
Test name
Test status
Simulation time 91923269 ps
CPU time 0.82 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:24:54 PM PDT 24
Peak memory 197248 kb
Host smart-6b80c3e1-bcd1-4cf2-be4c-feff25cd0663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349781617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.349781617
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.855231933
Short name T509
Test name
Test status
Simulation time 94761591988 ps
CPU time 366.22 seconds
Started Jul 27 06:25:03 PM PDT 24
Finished Jul 27 06:31:10 PM PDT 24
Peak memory 216836 kb
Host smart-8e67cf0a-803c-4952-a24c-2ce8a88a98f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855231933 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.855231933
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4157600418
Short name T272
Test name
Test status
Simulation time 7636408039 ps
CPU time 9.09 seconds
Started Jul 27 06:24:54 PM PDT 24
Finished Jul 27 06:25:03 PM PDT 24
Peak memory 200024 kb
Host smart-9e1ccf39-9759-4e21-99ce-33c3fd9b5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157600418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4157600418
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3374172719
Short name T361
Test name
Test status
Simulation time 9088556237 ps
CPU time 7.67 seconds
Started Jul 27 06:24:53 PM PDT 24
Finished Jul 27 06:25:01 PM PDT 24
Peak memory 197968 kb
Host smart-be907eaf-a90a-4727-b1fa-174d5f5dc91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374172719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3374172719
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1629487501
Short name T815
Test name
Test status
Simulation time 14060021317 ps
CPU time 16.13 seconds
Started Jul 27 06:31:44 PM PDT 24
Finished Jul 27 06:32:01 PM PDT 24
Peak memory 200168 kb
Host smart-582e0f02-0025-4cef-b357-e48fa7bfc3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629487501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1629487501
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.751789578
Short name T206
Test name
Test status
Simulation time 18449077415 ps
CPU time 30.89 seconds
Started Jul 27 06:31:45 PM PDT 24
Finished Jul 27 06:32:16 PM PDT 24
Peak memory 200204 kb
Host smart-3638b91f-e107-4130-b202-b80cfab88814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751789578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.751789578
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2563774755
Short name T141
Test name
Test status
Simulation time 10032592921 ps
CPU time 5.1 seconds
Started Jul 27 06:31:47 PM PDT 24
Finished Jul 27 06:31:52 PM PDT 24
Peak memory 200160 kb
Host smart-8446ab52-1193-48d9-96d3-3c0c70520dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563774755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2563774755
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1013531738
Short name T557
Test name
Test status
Simulation time 133133331266 ps
CPU time 102.93 seconds
Started Jul 27 06:31:44 PM PDT 24
Finished Jul 27 06:33:27 PM PDT 24
Peak memory 200240 kb
Host smart-73ee97c8-6302-43f3-bd98-859dff032d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013531738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1013531738
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2159815770
Short name T717
Test name
Test status
Simulation time 163723652316 ps
CPU time 222.6 seconds
Started Jul 27 06:31:45 PM PDT 24
Finished Jul 27 06:35:28 PM PDT 24
Peak memory 200200 kb
Host smart-2a5392bd-7a92-4327-b7a8-ea576d7baf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159815770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2159815770
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1029053440
Short name T182
Test name
Test status
Simulation time 11281379113 ps
CPU time 18.56 seconds
Started Jul 27 06:31:44 PM PDT 24
Finished Jul 27 06:32:02 PM PDT 24
Peak memory 200180 kb
Host smart-5e5c3474-3452-4ebd-9b5a-f3e4e52560a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029053440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1029053440
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.635773124
Short name T150
Test name
Test status
Simulation time 152629288679 ps
CPU time 38.89 seconds
Started Jul 27 06:31:44 PM PDT 24
Finished Jul 27 06:32:23 PM PDT 24
Peak memory 200184 kb
Host smart-5c41992e-3579-4384-9f5f-5e17a24a550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635773124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.635773124
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.753254936
Short name T122
Test name
Test status
Simulation time 121699458123 ps
CPU time 87.98 seconds
Started Jul 27 06:31:43 PM PDT 24
Finished Jul 27 06:33:11 PM PDT 24
Peak memory 200376 kb
Host smart-8de44d8f-386e-4b9e-a2a9-4ad5e29a81b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753254936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.753254936
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.203699526
Short name T8
Test name
Test status
Simulation time 22273690192 ps
CPU time 24.12 seconds
Started Jul 27 06:31:45 PM PDT 24
Finished Jul 27 06:32:09 PM PDT 24
Peak memory 200208 kb
Host smart-1d44cedf-6b5b-470f-bf31-62a32937fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203699526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.203699526
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2672962131
Short name T985
Test name
Test status
Simulation time 25903259932 ps
CPU time 27.98 seconds
Started Jul 27 06:31:51 PM PDT 24
Finished Jul 27 06:32:19 PM PDT 24
Peak memory 200224 kb
Host smart-5dcfb9dd-eb7b-4f38-b71a-a6bc7f0d41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672962131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2672962131
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4136596952
Short name T698
Test name
Test status
Simulation time 23196823 ps
CPU time 0.58 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:25:12 PM PDT 24
Peak memory 195592 kb
Host smart-22ad380d-206b-4c13-8e01-1311f089b25d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136596952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4136596952
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1462455972
Short name T987
Test name
Test status
Simulation time 78523565042 ps
CPU time 31.06 seconds
Started Jul 27 06:25:03 PM PDT 24
Finished Jul 27 06:25:35 PM PDT 24
Peak memory 200204 kb
Host smart-f5e0283e-d949-4100-b9f1-1f0c05fea2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462455972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1462455972
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1572996311
Short name T576
Test name
Test status
Simulation time 103106913272 ps
CPU time 23.88 seconds
Started Jul 27 06:25:04 PM PDT 24
Finished Jul 27 06:25:28 PM PDT 24
Peak memory 200188 kb
Host smart-59c5851f-7208-4191-9c2a-7d85d9be9a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572996311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1572996311
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2201302390
Short name T1045
Test name
Test status
Simulation time 44975827352 ps
CPU time 16.34 seconds
Started Jul 27 06:25:04 PM PDT 24
Finished Jul 27 06:25:21 PM PDT 24
Peak memory 199844 kb
Host smart-e365582f-8590-41ff-a68e-dae4b8049e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201302390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2201302390
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3651210400
Short name T595
Test name
Test status
Simulation time 17950199297 ps
CPU time 11.49 seconds
Started Jul 27 06:25:04 PM PDT 24
Finished Jul 27 06:25:16 PM PDT 24
Peak memory 197132 kb
Host smart-79e0ab0d-5be1-4605-9f20-a1724dee58cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651210400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3651210400
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2050850360
Short name T393
Test name
Test status
Simulation time 119886831431 ps
CPU time 884.83 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:39:57 PM PDT 24
Peak memory 200208 kb
Host smart-5965a4bd-e4a7-4202-a9b3-5528f7210451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050850360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2050850360
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1053882565
Short name T436
Test name
Test status
Simulation time 5417859319 ps
CPU time 10.15 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:25:22 PM PDT 24
Peak memory 199840 kb
Host smart-a3719491-b78a-4139-b739-0b089f86205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053882565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1053882565
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1806877411
Short name T788
Test name
Test status
Simulation time 56906610091 ps
CPU time 24.29 seconds
Started Jul 27 06:25:02 PM PDT 24
Finished Jul 27 06:25:26 PM PDT 24
Peak memory 199828 kb
Host smart-0572b35c-683a-4060-8f4f-96ad4cb38a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806877411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1806877411
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4202231902
Short name T243
Test name
Test status
Simulation time 11203352269 ps
CPU time 583.8 seconds
Started Jul 27 06:25:16 PM PDT 24
Finished Jul 27 06:35:00 PM PDT 24
Peak memory 200160 kb
Host smart-f0d0880c-3996-4c9c-b4e1-b1630c4fee4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202231902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4202231902
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1299776528
Short name T667
Test name
Test status
Simulation time 1584524232 ps
CPU time 4.85 seconds
Started Jul 27 06:25:03 PM PDT 24
Finished Jul 27 06:25:08 PM PDT 24
Peak memory 198196 kb
Host smart-e0433c10-0088-4fa7-86a7-59b3e96416f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299776528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1299776528
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1615873706
Short name T161
Test name
Test status
Simulation time 59359422501 ps
CPU time 50.35 seconds
Started Jul 27 06:25:02 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 200156 kb
Host smart-3f95d03f-95fb-4f8e-a4e2-dd89f67e8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615873706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1615873706
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1817882058
Short name T837
Test name
Test status
Simulation time 3785029388 ps
CPU time 3.54 seconds
Started Jul 27 06:25:01 PM PDT 24
Finished Jul 27 06:25:04 PM PDT 24
Peak memory 196300 kb
Host smart-337e8d0d-3bac-4305-ba73-a1dd63ae78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817882058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1817882058
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.942727397
Short name T670
Test name
Test status
Simulation time 6300744405 ps
CPU time 6.84 seconds
Started Jul 27 06:25:02 PM PDT 24
Finished Jul 27 06:25:09 PM PDT 24
Peak memory 200060 kb
Host smart-33779869-0d32-434d-8df1-eccfcdcf6b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942727397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.942727397
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2945094444
Short name T446
Test name
Test status
Simulation time 304686445841 ps
CPU time 583.04 seconds
Started Jul 27 06:25:14 PM PDT 24
Finished Jul 27 06:34:57 PM PDT 24
Peak memory 200180 kb
Host smart-e3c9ab43-591e-49b7-8f20-03cbd5ce981f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945094444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2945094444
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2853771248
Short name T752
Test name
Test status
Simulation time 458880197174 ps
CPU time 872.97 seconds
Started Jul 27 06:25:13 PM PDT 24
Finished Jul 27 06:39:46 PM PDT 24
Peak memory 225032 kb
Host smart-6464b02a-1267-4610-bb5c-f8f32dd31fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853771248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2853771248
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1883327236
Short name T1161
Test name
Test status
Simulation time 1886506933 ps
CPU time 2.52 seconds
Started Jul 27 06:25:13 PM PDT 24
Finished Jul 27 06:25:15 PM PDT 24
Peak memory 200020 kb
Host smart-103ab79c-23bc-4d04-beef-1d82166f01ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883327236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1883327236
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.379198771
Short name T302
Test name
Test status
Simulation time 74100179501 ps
CPU time 29.16 seconds
Started Jul 27 06:25:02 PM PDT 24
Finished Jul 27 06:25:31 PM PDT 24
Peak memory 200140 kb
Host smart-9e729552-e963-4266-b338-85a40ff27250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379198771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.379198771
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1846630307
Short name T199
Test name
Test status
Simulation time 53649473004 ps
CPU time 37.79 seconds
Started Jul 27 06:31:51 PM PDT 24
Finished Jul 27 06:32:29 PM PDT 24
Peak memory 200116 kb
Host smart-bab18b8b-1051-413c-85d0-7bc5164b2f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846630307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1846630307
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1756730999
Short name T259
Test name
Test status
Simulation time 46639609532 ps
CPU time 67.41 seconds
Started Jul 27 06:31:54 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 200160 kb
Host smart-f60422a0-4bfb-41cd-9c96-c00b1cd5d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756730999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1756730999
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3193986855
Short name T123
Test name
Test status
Simulation time 69820137170 ps
CPU time 96.2 seconds
Started Jul 27 06:31:53 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 200256 kb
Host smart-a6175ebb-c5e0-4ac4-8935-31f2cdf2caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193986855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3193986855
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2194912760
Short name T244
Test name
Test status
Simulation time 111910382820 ps
CPU time 189.51 seconds
Started Jul 27 06:31:55 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 200156 kb
Host smart-338abeb8-9f18-4359-b549-5afee36b1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194912760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2194912760
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1064664577
Short name T1105
Test name
Test status
Simulation time 89575228156 ps
CPU time 112.99 seconds
Started Jul 27 06:31:52 PM PDT 24
Finished Jul 27 06:33:45 PM PDT 24
Peak memory 200048 kb
Host smart-d94bbda5-df33-4bd5-b2c4-ea74484f9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064664577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1064664577
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3122714560
Short name T862
Test name
Test status
Simulation time 180170291055 ps
CPU time 75.45 seconds
Started Jul 27 06:31:54 PM PDT 24
Finished Jul 27 06:33:09 PM PDT 24
Peak memory 200116 kb
Host smart-3f1f460a-3c38-4324-a363-d77e20539b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122714560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3122714560
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2017081277
Short name T4
Test name
Test status
Simulation time 86365134926 ps
CPU time 103.6 seconds
Started Jul 27 06:31:52 PM PDT 24
Finished Jul 27 06:33:35 PM PDT 24
Peak memory 200232 kb
Host smart-c2eab658-2fe0-46a0-af04-ad5f78584d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017081277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2017081277
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.258126614
Short name T201
Test name
Test status
Simulation time 35500385097 ps
CPU time 14.29 seconds
Started Jul 27 06:31:55 PM PDT 24
Finished Jul 27 06:32:10 PM PDT 24
Peak memory 200244 kb
Host smart-53c1ccc5-60be-4bd7-9cf1-bdc740618d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258126614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.258126614
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2175672607
Short name T880
Test name
Test status
Simulation time 17407895 ps
CPU time 0.55 seconds
Started Jul 27 06:25:30 PM PDT 24
Finished Jul 27 06:25:31 PM PDT 24
Peak memory 195864 kb
Host smart-c2122a8b-cfce-4f42-9341-349faf461903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175672607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2175672607
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.178157883
Short name T117
Test name
Test status
Simulation time 11600544877 ps
CPU time 11.05 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:25:23 PM PDT 24
Peak memory 200204 kb
Host smart-ddf783cb-7b7c-4b24-8d3e-710139ebc374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178157883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.178157883
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2661556099
Short name T1044
Test name
Test status
Simulation time 117780276519 ps
CPU time 176.13 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:28:08 PM PDT 24
Peak memory 200252 kb
Host smart-5c05d865-d14b-4f35-af3c-b44524a70326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661556099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2661556099
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2296914074
Short name T551
Test name
Test status
Simulation time 12104048915 ps
CPU time 20.86 seconds
Started Jul 27 06:25:15 PM PDT 24
Finished Jul 27 06:25:36 PM PDT 24
Peak memory 200152 kb
Host smart-8b90e231-3f82-443f-94fb-fee06afb305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296914074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2296914074
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2993158028
Short name T612
Test name
Test status
Simulation time 32254080127 ps
CPU time 44.44 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:25:55 PM PDT 24
Peak memory 199872 kb
Host smart-318948ad-ad1d-4736-a864-c1c8dd48ea35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993158028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2993158028
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2387647348
Short name T749
Test name
Test status
Simulation time 47476553870 ps
CPU time 161.82 seconds
Started Jul 27 06:25:14 PM PDT 24
Finished Jul 27 06:27:56 PM PDT 24
Peak memory 200256 kb
Host smart-a22a46d6-af39-4fbc-858b-3eebef85fde5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387647348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2387647348
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2045769052
Short name T1024
Test name
Test status
Simulation time 11969005734 ps
CPU time 24.57 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:25:36 PM PDT 24
Peak memory 200220 kb
Host smart-d0a4e3a6-a4b4-47e3-a299-2ab568ed51f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045769052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2045769052
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.104494499
Short name T922
Test name
Test status
Simulation time 76746121760 ps
CPU time 152.71 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:27:45 PM PDT 24
Peak memory 208496 kb
Host smart-bf198989-e867-4375-977d-bbd6e5910639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104494499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.104494499
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3384146113
Short name T522
Test name
Test status
Simulation time 9175625288 ps
CPU time 252.04 seconds
Started Jul 27 06:25:15 PM PDT 24
Finished Jul 27 06:29:27 PM PDT 24
Peak memory 200276 kb
Host smart-97ab35f1-3c19-4751-bd12-07f0011ee271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384146113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3384146113
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3435136618
Short name T376
Test name
Test status
Simulation time 7295701666 ps
CPU time 64.4 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:26:15 PM PDT 24
Peak memory 199260 kb
Host smart-311b07d4-1ca0-4914-b0a5-b28873fd4280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435136618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3435136618
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2039620888
Short name T697
Test name
Test status
Simulation time 173479377693 ps
CPU time 93.37 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:26:45 PM PDT 24
Peak memory 200232 kb
Host smart-9964ea54-25d4-4277-bcdc-04bce8323e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039620888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2039620888
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4291278841
Short name T581
Test name
Test status
Simulation time 4977884855 ps
CPU time 2.06 seconds
Started Jul 27 06:25:12 PM PDT 24
Finished Jul 27 06:25:14 PM PDT 24
Peak memory 196292 kb
Host smart-123ec2ae-094a-405b-b3e4-e9c335937fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291278841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4291278841
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1945609777
Short name T389
Test name
Test status
Simulation time 6028216192 ps
CPU time 11.45 seconds
Started Jul 27 06:25:11 PM PDT 24
Finished Jul 27 06:25:22 PM PDT 24
Peak memory 200224 kb
Host smart-2c5637d9-e674-47c0-86ba-f6fe0898c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945609777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1945609777
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2406717871
Short name T1006
Test name
Test status
Simulation time 215522383563 ps
CPU time 308 seconds
Started Jul 27 06:25:16 PM PDT 24
Finished Jul 27 06:30:24 PM PDT 24
Peak memory 200236 kb
Host smart-d36d78b8-973f-445d-bc8e-999681bf95e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406717871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2406717871
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1057996842
Short name T1014
Test name
Test status
Simulation time 866533249 ps
CPU time 3.38 seconds
Started Jul 27 06:25:14 PM PDT 24
Finished Jul 27 06:25:17 PM PDT 24
Peak memory 199080 kb
Host smart-e43e1d12-6e6a-4226-8c12-2e6f6af28706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057996842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1057996842
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.400603951
Short name T854
Test name
Test status
Simulation time 28422597276 ps
CPU time 27.47 seconds
Started Jul 27 06:25:15 PM PDT 24
Finished Jul 27 06:25:43 PM PDT 24
Peak memory 200200 kb
Host smart-db283a0d-e786-4c3b-90e5-8ce9a914fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400603951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.400603951
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.283816967
Short name T885
Test name
Test status
Simulation time 61475344303 ps
CPU time 53.28 seconds
Started Jul 27 06:31:53 PM PDT 24
Finished Jul 27 06:32:46 PM PDT 24
Peak memory 200168 kb
Host smart-1c1b9160-3b01-4d96-9970-af6b31d1dbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283816967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.283816967
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.20983145
Short name T1122
Test name
Test status
Simulation time 33889126795 ps
CPU time 27.42 seconds
Started Jul 27 06:31:55 PM PDT 24
Finished Jul 27 06:32:23 PM PDT 24
Peak memory 200076 kb
Host smart-d345a4d8-3dd9-4c20-b5ed-164bdcefeb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20983145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.20983145
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1414489364
Short name T136
Test name
Test status
Simulation time 75435481239 ps
CPU time 30.83 seconds
Started Jul 27 06:31:52 PM PDT 24
Finished Jul 27 06:32:23 PM PDT 24
Peak memory 200136 kb
Host smart-825fc47f-5ae1-46be-ab93-bc06f7272f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414489364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1414489364
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1363397692
Short name T1035
Test name
Test status
Simulation time 47798169615 ps
CPU time 34.56 seconds
Started Jul 27 06:32:02 PM PDT 24
Finished Jul 27 06:32:37 PM PDT 24
Peak memory 200172 kb
Host smart-10500588-339e-4e04-b69f-0cdbece0e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363397692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1363397692
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.828853293
Short name T738
Test name
Test status
Simulation time 17005326492 ps
CPU time 5.97 seconds
Started Jul 27 06:32:02 PM PDT 24
Finished Jul 27 06:32:08 PM PDT 24
Peak memory 200004 kb
Host smart-acb161b0-e1fc-4458-bf8d-e194c63d521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828853293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.828853293
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1166733071
Short name T1143
Test name
Test status
Simulation time 201923145838 ps
CPU time 71.14 seconds
Started Jul 27 06:32:01 PM PDT 24
Finished Jul 27 06:33:12 PM PDT 24
Peak memory 200116 kb
Host smart-8de9bff8-842d-4482-84fd-c6156c4fe1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166733071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1166733071
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.34370834
Short name T910
Test name
Test status
Simulation time 145427259962 ps
CPU time 239.62 seconds
Started Jul 27 06:32:06 PM PDT 24
Finished Jul 27 06:36:06 PM PDT 24
Peak memory 200236 kb
Host smart-b797a904-8c12-430c-be90-6c812c2fe650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34370834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.34370834
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3977373826
Short name T1075
Test name
Test status
Simulation time 65221160504 ps
CPU time 29.19 seconds
Started Jul 27 06:32:02 PM PDT 24
Finished Jul 27 06:32:31 PM PDT 24
Peak memory 200280 kb
Host smart-1cb0e1b5-7064-4f08-b8da-31263210c468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977373826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3977373826
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2784904832
Short name T510
Test name
Test status
Simulation time 28979537992 ps
CPU time 45.4 seconds
Started Jul 27 06:32:04 PM PDT 24
Finished Jul 27 06:32:49 PM PDT 24
Peak memory 200208 kb
Host smart-6b2f284b-9a53-41ed-9ed2-7b9879f7989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784904832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2784904832
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.970040745
Short name T873
Test name
Test status
Simulation time 13352055 ps
CPU time 0.58 seconds
Started Jul 27 06:25:28 PM PDT 24
Finished Jul 27 06:25:28 PM PDT 24
Peak memory 195536 kb
Host smart-50f101ef-a35c-4c3d-b181-99b1d245261a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970040745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.970040745
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.613052083
Short name T126
Test name
Test status
Simulation time 85004950438 ps
CPU time 128.87 seconds
Started Jul 27 06:25:22 PM PDT 24
Finished Jul 27 06:27:31 PM PDT 24
Peak memory 200216 kb
Host smart-33105609-b514-40ad-8ea7-7875210a53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613052083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.613052083
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3892164560
Short name T583
Test name
Test status
Simulation time 116331656628 ps
CPU time 17.37 seconds
Started Jul 27 06:25:21 PM PDT 24
Finished Jul 27 06:25:39 PM PDT 24
Peak memory 200240 kb
Host smart-ca1be396-6cbb-484b-a0a8-287df2503e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892164560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3892164560
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.4059219487
Short name T648
Test name
Test status
Simulation time 54066169815 ps
CPU time 41.8 seconds
Started Jul 27 06:25:22 PM PDT 24
Finished Jul 27 06:26:04 PM PDT 24
Peak memory 200232 kb
Host smart-952c1661-9f39-4d8a-81ce-238bb325d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059219487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4059219487
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.349742377
Short name T1151
Test name
Test status
Simulation time 57445036055 ps
CPU time 22.96 seconds
Started Jul 27 06:25:28 PM PDT 24
Finished Jul 27 06:25:51 PM PDT 24
Peak memory 200100 kb
Host smart-7063a788-8758-4362-93fa-052417decc65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349742377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.349742377
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1015269291
Short name T989
Test name
Test status
Simulation time 130076521392 ps
CPU time 270.73 seconds
Started Jul 27 06:25:29 PM PDT 24
Finished Jul 27 06:30:00 PM PDT 24
Peak memory 200156 kb
Host smart-e09dacac-6e12-4e39-8455-20e27715ec57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015269291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1015269291
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4144416266
Short name T641
Test name
Test status
Simulation time 5080937208 ps
CPU time 7.89 seconds
Started Jul 27 06:25:30 PM PDT 24
Finished Jul 27 06:25:38 PM PDT 24
Peak memory 199940 kb
Host smart-87eeec7e-005d-44c1-a89b-3376d60693c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144416266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4144416266
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.848498080
Short name T875
Test name
Test status
Simulation time 128460266731 ps
CPU time 289.77 seconds
Started Jul 27 06:25:30 PM PDT 24
Finished Jul 27 06:30:20 PM PDT 24
Peak memory 200376 kb
Host smart-3f1e67ff-b9bd-421a-9ec1-6beadf4a5c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848498080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.848498080
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.532167898
Short name T973
Test name
Test status
Simulation time 35440464763 ps
CPU time 254.29 seconds
Started Jul 27 06:25:29 PM PDT 24
Finished Jul 27 06:29:44 PM PDT 24
Peak memory 200216 kb
Host smart-3fc63d62-7639-4436-9832-3af95eeb6af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532167898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.532167898
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1215609205
Short name T782
Test name
Test status
Simulation time 2255998605 ps
CPU time 1.78 seconds
Started Jul 27 06:25:21 PM PDT 24
Finished Jul 27 06:25:23 PM PDT 24
Peak memory 198388 kb
Host smart-85b911c6-a16f-48f2-a82e-f5058e27e5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215609205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1215609205
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3131310100
Short name T338
Test name
Test status
Simulation time 38976445193 ps
CPU time 16.14 seconds
Started Jul 27 06:25:26 PM PDT 24
Finished Jul 27 06:25:42 PM PDT 24
Peak memory 200076 kb
Host smart-3d171748-bfb9-450b-a957-7e68a76f88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131310100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3131310100
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.620898764
Short name T879
Test name
Test status
Simulation time 1856997053 ps
CPU time 3.59 seconds
Started Jul 27 06:25:22 PM PDT 24
Finished Jul 27 06:25:26 PM PDT 24
Peak memory 195672 kb
Host smart-820df2e4-6b33-4374-bb6b-a13872302f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620898764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.620898764
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1732167134
Short name T481
Test name
Test status
Simulation time 663362437 ps
CPU time 1.46 seconds
Started Jul 27 06:25:21 PM PDT 24
Finished Jul 27 06:25:23 PM PDT 24
Peak memory 198932 kb
Host smart-90018826-88e8-44de-875a-2034413df070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732167134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1732167134
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1895759342
Short name T325
Test name
Test status
Simulation time 397597948587 ps
CPU time 217.07 seconds
Started Jul 27 06:25:23 PM PDT 24
Finished Jul 27 06:29:01 PM PDT 24
Peak memory 208576 kb
Host smart-f831ce9f-c5dd-450a-8b9d-ee6170b97f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895759342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1895759342
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3626783195
Short name T936
Test name
Test status
Simulation time 88439979405 ps
CPU time 642.99 seconds
Started Jul 27 06:25:22 PM PDT 24
Finished Jul 27 06:36:05 PM PDT 24
Peak memory 216876 kb
Host smart-8bb0b68e-879b-47e2-ac71-d34605225d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626783195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3626783195
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1939612473
Short name T425
Test name
Test status
Simulation time 910393438 ps
CPU time 3.26 seconds
Started Jul 27 06:25:23 PM PDT 24
Finished Jul 27 06:25:26 PM PDT 24
Peak memory 200016 kb
Host smart-c7dad2ab-3913-47ab-b226-1d55a44faff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939612473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1939612473
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3179544558
Short name T408
Test name
Test status
Simulation time 56149276097 ps
CPU time 69.1 seconds
Started Jul 27 06:25:21 PM PDT 24
Finished Jul 27 06:26:31 PM PDT 24
Peak memory 200260 kb
Host smart-0c6f5f7b-b48b-4ec3-a05f-cd0ffade1b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179544558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3179544558
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3685036308
Short name T886
Test name
Test status
Simulation time 86432377538 ps
CPU time 140.06 seconds
Started Jul 27 06:32:01 PM PDT 24
Finished Jul 27 06:34:21 PM PDT 24
Peak memory 200232 kb
Host smart-9affadf9-14db-4794-86cb-7442a520fd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685036308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3685036308
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3861063091
Short name T180
Test name
Test status
Simulation time 164886130933 ps
CPU time 904.76 seconds
Started Jul 27 06:32:04 PM PDT 24
Finished Jul 27 06:47:09 PM PDT 24
Peak memory 200192 kb
Host smart-adce921d-0411-4c46-a1b5-3e3824879192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861063091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3861063091
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2498082707
Short name T203
Test name
Test status
Simulation time 127778229717 ps
CPU time 98.69 seconds
Started Jul 27 06:32:02 PM PDT 24
Finished Jul 27 06:33:41 PM PDT 24
Peak memory 200196 kb
Host smart-d3c69f70-45ec-4186-9b1e-7c9fe992e77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498082707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2498082707
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2160010171
Short name T1164
Test name
Test status
Simulation time 45389966424 ps
CPU time 80.63 seconds
Started Jul 27 06:32:18 PM PDT 24
Finished Jul 27 06:33:39 PM PDT 24
Peak memory 200196 kb
Host smart-43acb378-0478-4718-a858-797b2ad88d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160010171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2160010171
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2639543723
Short name T655
Test name
Test status
Simulation time 131171802073 ps
CPU time 49.65 seconds
Started Jul 27 06:32:19 PM PDT 24
Finished Jul 27 06:33:08 PM PDT 24
Peak memory 200196 kb
Host smart-87386115-d50c-45f4-9d2b-d0bd0d6ab4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639543723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2639543723
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.606132212
Short name T743
Test name
Test status
Simulation time 177135434403 ps
CPU time 294.06 seconds
Started Jul 27 06:32:16 PM PDT 24
Finished Jul 27 06:37:10 PM PDT 24
Peak memory 200040 kb
Host smart-ac084428-a4bc-451b-ae7e-1aa490a7a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606132212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.606132212
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3649892476
Short name T677
Test name
Test status
Simulation time 27917873181 ps
CPU time 9.79 seconds
Started Jul 27 06:32:16 PM PDT 24
Finished Jul 27 06:32:26 PM PDT 24
Peak memory 200176 kb
Host smart-eff6be3f-78ef-4ed9-8312-13a8ac965054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649892476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3649892476
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2132974478
Short name T647
Test name
Test status
Simulation time 57440103046 ps
CPU time 13.34 seconds
Started Jul 27 06:32:14 PM PDT 24
Finished Jul 27 06:32:28 PM PDT 24
Peak memory 200228 kb
Host smart-b7384e4c-c475-432f-95fe-d0e39f2d88de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132974478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2132974478
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2380378035
Short name T1048
Test name
Test status
Simulation time 23360835401 ps
CPU time 9.11 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:19 PM PDT 24
Peak memory 200224 kb
Host smart-8dbb2070-0bba-4f2a-b428-6eb06a0fe839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380378035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2380378035
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2621925329
Short name T859
Test name
Test status
Simulation time 36769851382 ps
CPU time 55.43 seconds
Started Jul 27 06:23:09 PM PDT 24
Finished Jul 27 06:24:04 PM PDT 24
Peak memory 200160 kb
Host smart-eff2dafe-52c9-4cbc-b2c8-172b42c810f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621925329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2621925329
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2469802341
Short name T809
Test name
Test status
Simulation time 21317306109 ps
CPU time 35.77 seconds
Started Jul 27 06:23:08 PM PDT 24
Finished Jul 27 06:23:44 PM PDT 24
Peak memory 200168 kb
Host smart-ee30c2c6-f549-43fe-ab61-f250d78c5472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469802341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2469802341
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2053952623
Short name T496
Test name
Test status
Simulation time 33796547341 ps
CPU time 6.42 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:16 PM PDT 24
Peak memory 200208 kb
Host smart-22f687c0-f739-4a48-8144-7ea4886163f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053952623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2053952623
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2264964511
Short name T563
Test name
Test status
Simulation time 90955463433 ps
CPU time 1069.54 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:40:59 PM PDT 24
Peak memory 200308 kb
Host smart-e5b60b7a-52a0-4572-9e9f-ac03d6a5edec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264964511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2264964511
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1169607112
Short name T99
Test name
Test status
Simulation time 8383997861 ps
CPU time 8.52 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:19 PM PDT 24
Peak memory 200112 kb
Host smart-d25458b4-c0e2-4241-825b-204bc20dd20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169607112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1169607112
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2485658800
Short name T297
Test name
Test status
Simulation time 139865662935 ps
CPU time 76.14 seconds
Started Jul 27 06:23:14 PM PDT 24
Finished Jul 27 06:24:30 PM PDT 24
Peak memory 208344 kb
Host smart-529e3e2d-5e38-40f3-a84d-91a86ca486f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485658800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2485658800
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2814657129
Short name T980
Test name
Test status
Simulation time 17724757865 ps
CPU time 143.39 seconds
Started Jul 27 06:23:12 PM PDT 24
Finished Jul 27 06:25:36 PM PDT 24
Peak memory 200208 kb
Host smart-82735c63-3194-41ae-8684-4de2ba429a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814657129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2814657129
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1051578604
Short name T821
Test name
Test status
Simulation time 6396198787 ps
CPU time 14 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:24 PM PDT 24
Peak memory 198572 kb
Host smart-9b59ed45-94e2-4063-91f5-5b414c82dda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051578604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1051578604
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1507925774
Short name T116
Test name
Test status
Simulation time 8901829747 ps
CPU time 15.39 seconds
Started Jul 27 06:23:11 PM PDT 24
Finished Jul 27 06:23:27 PM PDT 24
Peak memory 200424 kb
Host smart-2a546334-70d5-4e2b-9ce3-430bf76b5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507925774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1507925774
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1293392647
Short name T1111
Test name
Test status
Simulation time 3993179895 ps
CPU time 7.02 seconds
Started Jul 27 06:23:11 PM PDT 24
Finished Jul 27 06:23:18 PM PDT 24
Peak memory 196800 kb
Host smart-2eebba0d-4389-48f1-b5d2-a1d928376c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293392647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1293392647
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.4052831495
Short name T364
Test name
Test status
Simulation time 5645057998 ps
CPU time 12.78 seconds
Started Jul 27 06:23:12 PM PDT 24
Finished Jul 27 06:23:25 PM PDT 24
Peak memory 200188 kb
Host smart-a65276b7-c4d7-4cb7-b55f-5e63469f1599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052831495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4052831495
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3767923239
Short name T661
Test name
Test status
Simulation time 122489854900 ps
CPU time 657.84 seconds
Started Jul 27 06:23:09 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 200272 kb
Host smart-a8b6a398-c79c-4d8b-8e7e-d262c69776b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767923239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3767923239
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1941055111
Short name T634
Test name
Test status
Simulation time 1331707257881 ps
CPU time 1067.5 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:40:58 PM PDT 24
Peak memory 226176 kb
Host smart-c8968d0f-7e32-460e-b367-edb12519dfd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941055111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1941055111
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3620790804
Short name T958
Test name
Test status
Simulation time 1091889765 ps
CPU time 3.32 seconds
Started Jul 27 06:23:11 PM PDT 24
Finished Jul 27 06:23:15 PM PDT 24
Peak memory 199316 kb
Host smart-94fa9aaf-2a51-4b62-9321-083e80d94c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620790804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3620790804
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1960812361
Short name T693
Test name
Test status
Simulation time 45588016376 ps
CPU time 21.54 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:31 PM PDT 24
Peak memory 200168 kb
Host smart-64877121-5d5d-47d8-8d5c-b0966e1d0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960812361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1960812361
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.784129303
Short name T19
Test name
Test status
Simulation time 29452613 ps
CPU time 0.53 seconds
Started Jul 27 06:25:34 PM PDT 24
Finished Jul 27 06:25:34 PM PDT 24
Peak memory 194540 kb
Host smart-ef7e13c5-5547-45c1-94dc-6687003623e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784129303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.784129303
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.569858271
Short name T906
Test name
Test status
Simulation time 30918609598 ps
CPU time 25.59 seconds
Started Jul 27 06:25:36 PM PDT 24
Finished Jul 27 06:26:02 PM PDT 24
Peak memory 200240 kb
Host smart-d2846276-c4a6-4a7a-8c83-6c9bf13d78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569858271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.569858271
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1565320173
Short name T991
Test name
Test status
Simulation time 129003446426 ps
CPU time 39.99 seconds
Started Jul 27 06:25:36 PM PDT 24
Finished Jul 27 06:26:17 PM PDT 24
Peak memory 200224 kb
Host smart-1d0cc685-db9b-4dad-aeca-bf6165396ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565320173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1565320173
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1730568774
Short name T499
Test name
Test status
Simulation time 168707793421 ps
CPU time 74.61 seconds
Started Jul 27 06:25:35 PM PDT 24
Finished Jul 27 06:26:50 PM PDT 24
Peak memory 200192 kb
Host smart-d1f84a9f-02e9-4e00-a2a0-b1ea8107a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730568774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1730568774
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1315293306
Short name T890
Test name
Test status
Simulation time 40659454076 ps
CPU time 38.35 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:26:22 PM PDT 24
Peak memory 200156 kb
Host smart-7c7ed0b8-860d-40d7-8590-cc9f4dec3b4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315293306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1315293306
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_loopback.2662628183
Short name T375
Test name
Test status
Simulation time 4960495427 ps
CPU time 4.75 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:25:49 PM PDT 24
Peak memory 199244 kb
Host smart-87e0047e-e2db-430c-9ffa-e69383402452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662628183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2662628183
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.893388408
Short name T1047
Test name
Test status
Simulation time 83885264064 ps
CPU time 83.25 seconds
Started Jul 27 06:25:35 PM PDT 24
Finished Jul 27 06:26:58 PM PDT 24
Peak memory 200252 kb
Host smart-228cc9bd-e571-458d-802a-5e3ea0dc25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893388408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.893388408
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2219452408
Short name T491
Test name
Test status
Simulation time 15269332723 ps
CPU time 401.95 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:32:26 PM PDT 24
Peak memory 200176 kb
Host smart-b1edb09c-0911-424b-b9fe-34e7d80a4711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219452408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2219452408
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3321341719
Short name T902
Test name
Test status
Simulation time 3159030139 ps
CPU time 6.57 seconds
Started Jul 27 06:25:35 PM PDT 24
Finished Jul 27 06:25:41 PM PDT 24
Peak memory 199416 kb
Host smart-b03221b6-f276-4312-a115-64fbeede66f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321341719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3321341719
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1501100185
Short name T121
Test name
Test status
Simulation time 156055069970 ps
CPU time 113.98 seconds
Started Jul 27 06:25:34 PM PDT 24
Finished Jul 27 06:27:28 PM PDT 24
Peak memory 200208 kb
Host smart-b976bc3a-d372-4712-a00b-72cdceb9ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501100185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1501100185
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4082420127
Short name T453
Test name
Test status
Simulation time 35312497526 ps
CPU time 46.45 seconds
Started Jul 27 06:25:34 PM PDT 24
Finished Jul 27 06:26:21 PM PDT 24
Peak memory 197020 kb
Host smart-e84e8440-e3e7-44cc-a2a2-5dba4dd3ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082420127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4082420127
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.118844742
Short name T719
Test name
Test status
Simulation time 847534560 ps
CPU time 2.64 seconds
Started Jul 27 06:25:29 PM PDT 24
Finished Jul 27 06:25:32 PM PDT 24
Peak memory 199764 kb
Host smart-adbb73d5-5ed2-4ddd-a210-bc251d9b1093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118844742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.118844742
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1345255761
Short name T933
Test name
Test status
Simulation time 75649077987 ps
CPU time 709.16 seconds
Started Jul 27 06:25:35 PM PDT 24
Finished Jul 27 06:37:24 PM PDT 24
Peak memory 228444 kb
Host smart-76038dec-a9a5-4d8c-b2ec-22bf75e8c824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345255761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1345255761
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2348690579
Short name T777
Test name
Test status
Simulation time 14127610831 ps
CPU time 11.5 seconds
Started Jul 27 06:25:33 PM PDT 24
Finished Jul 27 06:25:45 PM PDT 24
Peak memory 200156 kb
Host smart-45c47ea8-ed41-4368-8bec-f00568c603d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348690579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2348690579
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2649560216
Short name T713
Test name
Test status
Simulation time 9485995000 ps
CPU time 15.78 seconds
Started Jul 27 06:25:22 PM PDT 24
Finished Jul 27 06:25:37 PM PDT 24
Peak memory 200260 kb
Host smart-42efcaef-e847-4e14-afa2-acdd8dbf018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649560216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2649560216
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3256861402
Short name T983
Test name
Test status
Simulation time 42087319014 ps
CPU time 47.75 seconds
Started Jul 27 06:32:15 PM PDT 24
Finished Jul 27 06:33:03 PM PDT 24
Peak memory 200232 kb
Host smart-bdc894c3-41a3-413c-8bb7-61805fa39576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256861402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3256861402
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.704834723
Short name T134
Test name
Test status
Simulation time 124722955507 ps
CPU time 182.95 seconds
Started Jul 27 06:32:14 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 200128 kb
Host smart-204f95b8-2122-4ba6-a568-c3618999b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704834723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.704834723
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.712849181
Short name T977
Test name
Test status
Simulation time 156976445215 ps
CPU time 66.78 seconds
Started Jul 27 06:32:14 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200164 kb
Host smart-cfcfe2f0-3730-46ef-9082-436466b890d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712849181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.712849181
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3136006373
Short name T1112
Test name
Test status
Simulation time 137977351405 ps
CPU time 92.9 seconds
Started Jul 27 06:32:17 PM PDT 24
Finished Jul 27 06:33:50 PM PDT 24
Peak memory 200092 kb
Host smart-870fe765-60f4-4bb3-a8b2-a8d580296b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136006373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3136006373
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2186448260
Short name T1062
Test name
Test status
Simulation time 57896983449 ps
CPU time 23.52 seconds
Started Jul 27 06:32:19 PM PDT 24
Finished Jul 27 06:32:43 PM PDT 24
Peak memory 200240 kb
Host smart-aa5bde80-0b8b-443b-b210-fb19313c5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186448260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2186448260
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.588793142
Short name T247
Test name
Test status
Simulation time 142802791332 ps
CPU time 182.01 seconds
Started Jul 27 06:32:17 PM PDT 24
Finished Jul 27 06:35:19 PM PDT 24
Peak memory 200252 kb
Host smart-39796f87-197a-4a0d-9fff-3e817daefa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588793142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.588793142
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3530315456
Short name T593
Test name
Test status
Simulation time 29335988207 ps
CPU time 40.73 seconds
Started Jul 27 06:32:15 PM PDT 24
Finished Jul 27 06:32:56 PM PDT 24
Peak memory 200216 kb
Host smart-6d118fdf-7151-4f63-b8dc-64174fb1fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530315456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3530315456
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.9898331
Short name T196
Test name
Test status
Simulation time 81335815505 ps
CPU time 21.14 seconds
Started Jul 27 06:32:14 PM PDT 24
Finished Jul 27 06:32:36 PM PDT 24
Peak memory 200236 kb
Host smart-c4c64796-06a4-487f-bd29-3529875b8688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9898331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.9898331
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2305022575
Short name T577
Test name
Test status
Simulation time 48678721483 ps
CPU time 35.82 seconds
Started Jul 27 06:32:19 PM PDT 24
Finished Jul 27 06:32:55 PM PDT 24
Peak memory 200240 kb
Host smart-d14b1350-5e36-4931-bf35-39bf7bee1284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305022575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2305022575
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2387720325
Short name T659
Test name
Test status
Simulation time 22084930 ps
CPU time 0.55 seconds
Started Jul 27 06:25:52 PM PDT 24
Finished Jul 27 06:25:53 PM PDT 24
Peak memory 195656 kb
Host smart-6ed47750-0d13-46fc-a346-eb275a008651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387720325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2387720325
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3401324782
Short name T409
Test name
Test status
Simulation time 192201975785 ps
CPU time 73.86 seconds
Started Jul 27 06:25:43 PM PDT 24
Finished Jul 27 06:26:57 PM PDT 24
Peak memory 200252 kb
Host smart-c5b9dc50-0d37-4b60-8cf6-dcb5fee06088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401324782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3401324782
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1072827003
Short name T111
Test name
Test status
Simulation time 210999870995 ps
CPU time 53.65 seconds
Started Jul 27 06:25:46 PM PDT 24
Finished Jul 27 06:26:40 PM PDT 24
Peak memory 200168 kb
Host smart-1740eb75-1341-4f39-a522-df00b54ac044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072827003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1072827003
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4165864607
Short name T127
Test name
Test status
Simulation time 37503001906 ps
CPU time 14.72 seconds
Started Jul 27 06:25:43 PM PDT 24
Finished Jul 27 06:25:58 PM PDT 24
Peak memory 200132 kb
Host smart-fcc6f4db-8f84-484d-ab85-4834af5907cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165864607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4165864607
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.897740105
Short name T754
Test name
Test status
Simulation time 60826652593 ps
CPU time 43.73 seconds
Started Jul 27 06:25:48 PM PDT 24
Finished Jul 27 06:26:32 PM PDT 24
Peak memory 199964 kb
Host smart-59ced864-f717-4a95-9af3-accce4f3028f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897740105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.897740105
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1290125342
Short name T656
Test name
Test status
Simulation time 145668872577 ps
CPU time 664.31 seconds
Started Jul 27 06:25:46 PM PDT 24
Finished Jul 27 06:36:51 PM PDT 24
Peak memory 200160 kb
Host smart-82faf431-b4d3-45ab-8dd8-dceaabf49bab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290125342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1290125342
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2779808386
Short name T1148
Test name
Test status
Simulation time 10786921492 ps
CPU time 5.01 seconds
Started Jul 27 06:25:43 PM PDT 24
Finished Jul 27 06:25:48 PM PDT 24
Peak memory 198584 kb
Host smart-10345940-d7df-4c1a-bb0c-19bd591de3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779808386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2779808386
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2015524531
Short name T748
Test name
Test status
Simulation time 100761054244 ps
CPU time 102.77 seconds
Started Jul 27 06:25:45 PM PDT 24
Finished Jul 27 06:27:28 PM PDT 24
Peak memory 208588 kb
Host smart-36992dd9-a4ed-4387-a693-471cef4be0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015524531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2015524531
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.215566124
Short name T273
Test name
Test status
Simulation time 13291826442 ps
CPU time 191.07 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:28:55 PM PDT 24
Peak memory 200252 kb
Host smart-fe07ca33-a2eb-4e00-aa3f-22f135154d64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=215566124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.215566124
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.20771631
Short name T357
Test name
Test status
Simulation time 2325727013 ps
CPU time 9.29 seconds
Started Jul 27 06:25:43 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 198472 kb
Host smart-a285910b-f496-4534-9859-1a43cc6a0054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20771631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.20771631
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.188299096
Short name T532
Test name
Test status
Simulation time 30833855595 ps
CPU time 51.37 seconds
Started Jul 27 06:25:48 PM PDT 24
Finished Jul 27 06:26:40 PM PDT 24
Peak memory 200192 kb
Host smart-515ec3de-ea12-4e64-b0f3-487d03b9e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188299096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.188299096
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3903783669
Short name T806
Test name
Test status
Simulation time 5941918935 ps
CPU time 9.82 seconds
Started Jul 27 06:25:48 PM PDT 24
Finished Jul 27 06:25:58 PM PDT 24
Peak memory 196424 kb
Host smart-8cffaa4f-fcb0-4d49-8142-10ffd0a89bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903783669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3903783669
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3528503223
Short name T868
Test name
Test status
Simulation time 460101038 ps
CPU time 1.39 seconds
Started Jul 27 06:25:44 PM PDT 24
Finished Jul 27 06:25:45 PM PDT 24
Peak memory 198688 kb
Host smart-461800e6-06d4-4934-a0e0-ab2883401b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528503223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3528503223
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.4220248371
Short name T607
Test name
Test status
Simulation time 170172863057 ps
CPU time 69.37 seconds
Started Jul 27 06:25:47 PM PDT 24
Finished Jul 27 06:26:56 PM PDT 24
Peak memory 200176 kb
Host smart-16f7dd16-b3c7-46cd-99cb-207f8d3f7ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220248371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4220248371
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1848093498
Short name T53
Test name
Test status
Simulation time 42542336073 ps
CPU time 328.04 seconds
Started Jul 27 06:25:48 PM PDT 24
Finished Jul 27 06:31:16 PM PDT 24
Peak memory 216636 kb
Host smart-9d56af90-1de8-4d99-b3bc-93a9f801e05a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848093498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1848093498
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.139822994
Short name T908
Test name
Test status
Simulation time 1053978724 ps
CPU time 2.92 seconds
Started Jul 27 06:25:45 PM PDT 24
Finished Jul 27 06:25:48 PM PDT 24
Peak memory 199024 kb
Host smart-9a3ecbe6-cf13-48e7-af51-c205da4bd436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139822994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.139822994
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3691544328
Short name T472
Test name
Test status
Simulation time 6812442413 ps
CPU time 11.85 seconds
Started Jul 27 06:25:34 PM PDT 24
Finished Jul 27 06:25:46 PM PDT 24
Peak memory 200204 kb
Host smart-31681005-bd38-4806-a70a-dadba4a8d83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691544328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3691544328
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2849425690
Short name T1093
Test name
Test status
Simulation time 32462169259 ps
CPU time 66.01 seconds
Started Jul 27 06:32:15 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200168 kb
Host smart-d5b83c74-52cf-4ea8-a41e-e55bde0ead8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849425690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2849425690
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1703161039
Short name T312
Test name
Test status
Simulation time 39045088972 ps
CPU time 15.3 seconds
Started Jul 27 06:32:15 PM PDT 24
Finished Jul 27 06:32:30 PM PDT 24
Peak memory 200236 kb
Host smart-dbe3515f-1995-403e-8a8d-4cefee300a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703161039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1703161039
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2290815752
Short name T1070
Test name
Test status
Simulation time 175484010164 ps
CPU time 188.17 seconds
Started Jul 27 06:32:18 PM PDT 24
Finished Jul 27 06:35:26 PM PDT 24
Peak memory 200196 kb
Host smart-e2d40f72-0f20-4d6b-8af1-b081c0b0ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290815752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2290815752
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.430171246
Short name T209
Test name
Test status
Simulation time 87852252593 ps
CPU time 66.13 seconds
Started Jul 27 06:32:15 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200092 kb
Host smart-048bbbe1-8757-4592-8e09-eed68c79afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430171246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.430171246
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2962326141
Short name T208
Test name
Test status
Simulation time 162025263429 ps
CPU time 64.28 seconds
Started Jul 27 06:32:24 PM PDT 24
Finished Jul 27 06:33:29 PM PDT 24
Peak memory 200144 kb
Host smart-ec54a0b7-584d-45c2-a930-edc13a503eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962326141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2962326141
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4154860634
Short name T901
Test name
Test status
Simulation time 29944645844 ps
CPU time 45.64 seconds
Started Jul 27 06:32:25 PM PDT 24
Finished Jul 27 06:33:11 PM PDT 24
Peak memory 200268 kb
Host smart-fec32252-91b4-4bd6-b235-b8af7bb8308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154860634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4154860634
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2867428799
Short name T567
Test name
Test status
Simulation time 8808464251 ps
CPU time 15.73 seconds
Started Jul 27 06:32:23 PM PDT 24
Finished Jul 27 06:32:39 PM PDT 24
Peak memory 199900 kb
Host smart-3741aa4e-bef1-4881-a2cc-871385666d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867428799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2867428799
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2749071350
Short name T883
Test name
Test status
Simulation time 26231744 ps
CPU time 0.57 seconds
Started Jul 27 06:26:02 PM PDT 24
Finished Jul 27 06:26:02 PM PDT 24
Peak memory 195580 kb
Host smart-ec4f6961-e9fa-457b-b283-9993e5c382c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749071350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2749071350
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4125397249
Short name T571
Test name
Test status
Simulation time 107185586231 ps
CPU time 14.37 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:26:08 PM PDT 24
Peak memory 200204 kb
Host smart-c6e82861-e07b-4525-91b4-04a13c7a230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125397249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4125397249
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.106793305
Short name T152
Test name
Test status
Simulation time 29786671809 ps
CPU time 32.9 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:26:26 PM PDT 24
Peak memory 200112 kb
Host smart-47574012-d578-4cb7-bb36-5d5e335eaa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106793305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.106793305
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.354616551
Short name T1146
Test name
Test status
Simulation time 30962927336 ps
CPU time 54.31 seconds
Started Jul 27 06:25:56 PM PDT 24
Finished Jul 27 06:26:50 PM PDT 24
Peak memory 200164 kb
Host smart-c0c2543c-9ada-49f6-a668-620ee8c57624
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354616551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.354616551
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.818394484
Short name T831
Test name
Test status
Simulation time 85275058267 ps
CPU time 539.34 seconds
Started Jul 27 06:25:54 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 200232 kb
Host smart-2f937c3a-5d9e-47b9-b4c8-af765020a63d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818394484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.818394484
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2397438260
Short name T2
Test name
Test status
Simulation time 8958881166 ps
CPU time 8.34 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:26:01 PM PDT 24
Peak memory 198780 kb
Host smart-aa14fe52-5f70-4ae5-844a-9f4782a598c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397438260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2397438260
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3755233110
Short name T250
Test name
Test status
Simulation time 193586560057 ps
CPU time 78.23 seconds
Started Jul 27 06:25:54 PM PDT 24
Finished Jul 27 06:27:13 PM PDT 24
Peak memory 199996 kb
Host smart-6112c7c6-4b86-4f36-a78b-70dd2b9388c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755233110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3755233110
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1845772899
Short name T284
Test name
Test status
Simulation time 28109338842 ps
CPU time 139.18 seconds
Started Jul 27 06:25:52 PM PDT 24
Finished Jul 27 06:28:12 PM PDT 24
Peak memory 200244 kb
Host smart-0ef3ee2f-7db4-44b9-b56b-4726ee74a208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845772899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1845772899
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.651810979
Short name T616
Test name
Test status
Simulation time 6078167708 ps
CPU time 43.42 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:26:37 PM PDT 24
Peak memory 200124 kb
Host smart-001f6261-22c7-4eca-bcb4-75ba7b9c6f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651810979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.651810979
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2385166665
Short name T130
Test name
Test status
Simulation time 134059294545 ps
CPU time 253.55 seconds
Started Jul 27 06:25:51 PM PDT 24
Finished Jul 27 06:30:05 PM PDT 24
Peak memory 200252 kb
Host smart-5975a509-214e-4708-b105-64d5cc06f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385166665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2385166665
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.574945322
Short name T399
Test name
Test status
Simulation time 803919489 ps
CPU time 1.77 seconds
Started Jul 27 06:25:54 PM PDT 24
Finished Jul 27 06:25:56 PM PDT 24
Peak memory 195724 kb
Host smart-2a531a14-7e24-455f-8b6a-4dd7f8b0c6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574945322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.574945322
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.501614734
Short name T968
Test name
Test status
Simulation time 295432654 ps
CPU time 2.24 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:25:55 PM PDT 24
Peak memory 199020 kb
Host smart-7ce7b692-bf7a-4d2a-8ce3-c81aac9389dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501614734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.501614734
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.186158759
Short name T650
Test name
Test status
Simulation time 459338037883 ps
CPU time 532.22 seconds
Started Jul 27 06:26:01 PM PDT 24
Finished Jul 27 06:34:53 PM PDT 24
Peak memory 215820 kb
Host smart-943e27ba-b200-4050-b95a-0d92929e9c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186158759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.186158759
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2446545728
Short name T13
Test name
Test status
Simulation time 57704431300 ps
CPU time 374.43 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:32:08 PM PDT 24
Peak memory 208592 kb
Host smart-c61c3985-8b22-477a-a253-2f1e6fa8c47d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446545728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2446545728
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.913551045
Short name T686
Test name
Test status
Simulation time 1472899859 ps
CPU time 3.21 seconds
Started Jul 27 06:25:54 PM PDT 24
Finished Jul 27 06:25:58 PM PDT 24
Peak memory 200008 kb
Host smart-ed543e9d-ec3d-4a29-89c9-94e619d6405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913551045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.913551045
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3992781235
Short name T959
Test name
Test status
Simulation time 180179476641 ps
CPU time 80.08 seconds
Started Jul 27 06:25:53 PM PDT 24
Finished Jul 27 06:27:13 PM PDT 24
Peak memory 200172 kb
Host smart-49818f87-9e72-4a3d-b244-6263287b61f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992781235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3992781235
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3984753779
Short name T939
Test name
Test status
Simulation time 63963771643 ps
CPU time 20.39 seconds
Started Jul 27 06:32:22 PM PDT 24
Finished Jul 27 06:32:43 PM PDT 24
Peak memory 200268 kb
Host smart-19ea7a70-cfd0-478c-8b88-fb0a938e15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984753779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3984753779
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3829324649
Short name T492
Test name
Test status
Simulation time 71036250033 ps
CPU time 28.32 seconds
Started Jul 27 06:32:26 PM PDT 24
Finished Jul 27 06:32:55 PM PDT 24
Peak memory 199972 kb
Host smart-a440476f-063d-4bd1-a8b7-a31bbac5a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829324649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3829324649
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3357179827
Short name T494
Test name
Test status
Simulation time 59229478011 ps
CPU time 26.57 seconds
Started Jul 27 06:32:26 PM PDT 24
Finished Jul 27 06:32:52 PM PDT 24
Peak memory 200140 kb
Host smart-c2b9cbb4-0326-4fa4-878a-1a6bbb538457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357179827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3357179827
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.434256300
Short name T162
Test name
Test status
Simulation time 53367884555 ps
CPU time 13.37 seconds
Started Jul 27 06:32:24 PM PDT 24
Finished Jul 27 06:32:37 PM PDT 24
Peak memory 200172 kb
Host smart-3569fd5b-8e72-4971-b0b0-3183ed58309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434256300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.434256300
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2017212930
Short name T175
Test name
Test status
Simulation time 88107761222 ps
CPU time 34.56 seconds
Started Jul 27 06:32:25 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200112 kb
Host smart-3d8a7c9e-8c3b-4fe7-8b47-9ac56a0ff035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017212930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2017212930
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1853678897
Short name T465
Test name
Test status
Simulation time 11555730837 ps
CPU time 10.36 seconds
Started Jul 27 06:32:24 PM PDT 24
Finished Jul 27 06:32:34 PM PDT 24
Peak memory 199076 kb
Host smart-dafb60c3-8557-4d8a-a317-094c18a71312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853678897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1853678897
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3429059245
Short name T882
Test name
Test status
Simulation time 41299801951 ps
CPU time 10.86 seconds
Started Jul 27 06:32:24 PM PDT 24
Finished Jul 27 06:32:35 PM PDT 24
Peak memory 200208 kb
Host smart-82c128d5-c98c-4f53-8d18-6dbb6d4fefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429059245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3429059245
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3837724105
Short name T746
Test name
Test status
Simulation time 9104919380 ps
CPU time 17.32 seconds
Started Jul 27 06:32:25 PM PDT 24
Finished Jul 27 06:32:42 PM PDT 24
Peak memory 200204 kb
Host smart-5fa51c48-be04-4de0-b821-8ab1ceffb768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837724105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3837724105
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3305560859
Short name T534
Test name
Test status
Simulation time 54712523 ps
CPU time 0.54 seconds
Started Jul 27 06:26:02 PM PDT 24
Finished Jul 27 06:26:02 PM PDT 24
Peak memory 195624 kb
Host smart-c020fec3-2070-46d0-bb01-0031f8af4b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305560859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3305560859
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3840786971
Short name T1021
Test name
Test status
Simulation time 116036477176 ps
CPU time 49.39 seconds
Started Jul 27 06:26:04 PM PDT 24
Finished Jul 27 06:26:54 PM PDT 24
Peak memory 200240 kb
Host smart-63394731-b090-40ee-a5e2-a108528a19cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840786971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3840786971
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3440682765
Short name T640
Test name
Test status
Simulation time 210718884839 ps
CPU time 37.59 seconds
Started Jul 27 06:26:05 PM PDT 24
Finished Jul 27 06:26:42 PM PDT 24
Peak memory 200236 kb
Host smart-0428d400-c160-4751-a423-64f3bc8a3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440682765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3440682765
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2307446885
Short name T177
Test name
Test status
Simulation time 95043142798 ps
CPU time 40.21 seconds
Started Jul 27 06:26:03 PM PDT 24
Finished Jul 27 06:26:44 PM PDT 24
Peak memory 200108 kb
Host smart-b7417237-c291-4bf3-a219-2c4c20036dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307446885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2307446885
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2288533935
Short name T1049
Test name
Test status
Simulation time 5815007467 ps
CPU time 3.3 seconds
Started Jul 27 06:26:02 PM PDT 24
Finished Jul 27 06:26:06 PM PDT 24
Peak memory 200232 kb
Host smart-50979340-c427-454c-a134-e86caf6cc4e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288533935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2288533935
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1635959182
Short name T422
Test name
Test status
Simulation time 66978080517 ps
CPU time 277.57 seconds
Started Jul 27 06:26:03 PM PDT 24
Finished Jul 27 06:30:40 PM PDT 24
Peak memory 200172 kb
Host smart-a9146a2e-c7c3-41a6-8d07-279923c7c18e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635959182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1635959182
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.272260513
Short name T391
Test name
Test status
Simulation time 2869267377 ps
CPU time 5.65 seconds
Started Jul 27 06:26:01 PM PDT 24
Finished Jul 27 06:26:07 PM PDT 24
Peak memory 200168 kb
Host smart-53e3fc65-4b94-4b78-b22f-3ce97de779e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272260513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.272260513
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.855764248
Short name T1013
Test name
Test status
Simulation time 10767673100 ps
CPU time 18.44 seconds
Started Jul 27 06:26:02 PM PDT 24
Finished Jul 27 06:26:20 PM PDT 24
Peak memory 198696 kb
Host smart-06cf2de3-3e05-4f4e-82dd-b76326b9d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855764248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.855764248
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.33475722
Short name T887
Test name
Test status
Simulation time 7841122375 ps
CPU time 120.42 seconds
Started Jul 27 06:26:03 PM PDT 24
Finished Jul 27 06:28:04 PM PDT 24
Peak memory 200256 kb
Host smart-96b7f09d-c5c1-4325-8740-004db51ebc08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33475722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.33475722
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.684444945
Short name T347
Test name
Test status
Simulation time 2538623978 ps
CPU time 9.94 seconds
Started Jul 27 06:26:01 PM PDT 24
Finished Jul 27 06:26:12 PM PDT 24
Peak memory 198492 kb
Host smart-0687d8db-f648-4982-a0f8-79301d16bad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684444945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.684444945
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.471757268
Short name T286
Test name
Test status
Simulation time 62458172469 ps
CPU time 85.73 seconds
Started Jul 27 06:26:04 PM PDT 24
Finished Jul 27 06:27:29 PM PDT 24
Peak memory 200156 kb
Host smart-e7fbc243-0d64-49f6-9b11-e778f21ee711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471757268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.471757268
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2770706275
Short name T538
Test name
Test status
Simulation time 4038503572 ps
CPU time 6.55 seconds
Started Jul 27 06:26:01 PM PDT 24
Finished Jul 27 06:26:08 PM PDT 24
Peak memory 197012 kb
Host smart-f29685fc-2f83-462c-b177-d95c22b2da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770706275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2770706275
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.455482234
Short name T457
Test name
Test status
Simulation time 499188106 ps
CPU time 3.55 seconds
Started Jul 27 06:26:02 PM PDT 24
Finished Jul 27 06:26:05 PM PDT 24
Peak memory 198844 kb
Host smart-c7de8b4b-dbd4-40e7-a491-ffa7996b2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455482234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.455482234
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1390237745
Short name T1037
Test name
Test status
Simulation time 153644574689 ps
CPU time 632.85 seconds
Started Jul 27 06:26:04 PM PDT 24
Finished Jul 27 06:36:37 PM PDT 24
Peak memory 200208 kb
Host smart-f66f66e1-b4bd-46b0-9370-1096273398fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390237745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1390237745
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3825636721
Short name T570
Test name
Test status
Simulation time 294302521967 ps
CPU time 935.29 seconds
Started Jul 27 06:26:04 PM PDT 24
Finished Jul 27 06:41:40 PM PDT 24
Peak memory 225068 kb
Host smart-67d56495-8c40-4043-afb5-29187ed38148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825636721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3825636721
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2523932866
Short name T953
Test name
Test status
Simulation time 1477200005 ps
CPU time 1.65 seconds
Started Jul 27 06:26:03 PM PDT 24
Finished Jul 27 06:26:05 PM PDT 24
Peak memory 198692 kb
Host smart-bf8fe94a-07e5-498c-a0be-a9908e0c51c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523932866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2523932866
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.474027257
Short name T282
Test name
Test status
Simulation time 3407525822 ps
CPU time 7.04 seconds
Started Jul 27 06:26:03 PM PDT 24
Finished Jul 27 06:26:10 PM PDT 24
Peak memory 200164 kb
Host smart-bc5fe36d-b22a-4b08-8317-509a98cdeb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474027257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.474027257
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3656506499
Short name T160
Test name
Test status
Simulation time 25253534358 ps
CPU time 38.24 seconds
Started Jul 27 06:32:24 PM PDT 24
Finished Jul 27 06:33:03 PM PDT 24
Peak memory 200216 kb
Host smart-fd5f2e96-09a9-41c2-8965-537f5dce68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656506499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3656506499
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3219227348
Short name T742
Test name
Test status
Simulation time 8343219384 ps
CPU time 7.48 seconds
Started Jul 27 06:32:26 PM PDT 24
Finished Jul 27 06:32:34 PM PDT 24
Peak memory 200172 kb
Host smart-f8edbd1a-2ce2-4526-98c2-72c655196a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219227348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3219227348
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1913808137
Short name T211
Test name
Test status
Simulation time 18612034027 ps
CPU time 16.47 seconds
Started Jul 27 06:32:25 PM PDT 24
Finished Jul 27 06:32:42 PM PDT 24
Peak memory 200164 kb
Host smart-084be73d-d03a-4fca-823b-74ed076606c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913808137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1913808137
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3974073742
Short name T115
Test name
Test status
Simulation time 26302465814 ps
CPU time 40.47 seconds
Started Jul 27 06:32:22 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 200180 kb
Host smart-0a1f4d50-45f6-4b2a-b9b6-ce5ce31f96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974073742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3974073742
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3991973447
Short name T771
Test name
Test status
Simulation time 48263452534 ps
CPU time 74.06 seconds
Started Jul 27 06:32:25 PM PDT 24
Finished Jul 27 06:33:39 PM PDT 24
Peak memory 200192 kb
Host smart-8e97849f-8767-4cfc-ab33-1ddc605e8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991973447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3991973447
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.705363217
Short name T333
Test name
Test status
Simulation time 9053635555 ps
CPU time 17.05 seconds
Started Jul 27 06:32:33 PM PDT 24
Finished Jul 27 06:32:50 PM PDT 24
Peak memory 200084 kb
Host smart-4ced45a3-eabc-4c8a-b282-8699dcc02c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705363217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.705363217
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2338785177
Short name T337
Test name
Test status
Simulation time 12019968947 ps
CPU time 22.81 seconds
Started Jul 27 06:32:34 PM PDT 24
Finished Jul 27 06:32:56 PM PDT 24
Peak memory 200232 kb
Host smart-9d0a22ed-ba3e-4470-a136-8c1e62a69be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338785177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2338785177
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.832630320
Short name T1058
Test name
Test status
Simulation time 45011600 ps
CPU time 0.56 seconds
Started Jul 27 06:26:14 PM PDT 24
Finished Jul 27 06:26:14 PM PDT 24
Peak memory 195624 kb
Host smart-3a06d52e-2e2d-4065-bfa0-74efb19a5b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832630320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.832630320
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3182533242
Short name T1117
Test name
Test status
Simulation time 18072110206 ps
CPU time 28.43 seconds
Started Jul 27 06:26:14 PM PDT 24
Finished Jul 27 06:26:43 PM PDT 24
Peak memory 200112 kb
Host smart-1579786d-ab50-494a-b8fc-8798c56d62dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182533242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3182533242
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3331468046
Short name T1022
Test name
Test status
Simulation time 27705751354 ps
CPU time 10.16 seconds
Started Jul 27 06:26:11 PM PDT 24
Finished Jul 27 06:26:22 PM PDT 24
Peak memory 199596 kb
Host smart-d670efa1-e7c7-4324-85f8-864d35f6793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331468046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3331468046
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3553707440
Short name T1175
Test name
Test status
Simulation time 10726035784 ps
CPU time 19.84 seconds
Started Jul 27 06:26:10 PM PDT 24
Finished Jul 27 06:26:30 PM PDT 24
Peak memory 200140 kb
Host smart-35b1cdad-998f-4bfe-adcc-b290f474df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553707440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3553707440
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4002707046
Short name T516
Test name
Test status
Simulation time 75088574755 ps
CPU time 32.61 seconds
Started Jul 27 06:26:11 PM PDT 24
Finished Jul 27 06:26:44 PM PDT 24
Peak memory 199980 kb
Host smart-d0844cbe-df27-4bae-b726-e4b74879b744
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002707046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4002707046
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3149467193
Short name T1109
Test name
Test status
Simulation time 77469635038 ps
CPU time 231.04 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:30:03 PM PDT 24
Peak memory 200236 kb
Host smart-b1a1b0be-57a3-4eba-bcf7-e3743e6d25d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149467193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3149467193
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3128746705
Short name T1119
Test name
Test status
Simulation time 2665542687 ps
CPU time 3.13 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:26:16 PM PDT 24
Peak memory 198088 kb
Host smart-4abf0c0e-2a6c-4ffe-87a9-c0a2d473f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128746705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3128746705
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1523436487
Short name T747
Test name
Test status
Simulation time 99217722383 ps
CPU time 190.1 seconds
Started Jul 27 06:26:14 PM PDT 24
Finished Jul 27 06:29:24 PM PDT 24
Peak memory 200156 kb
Host smart-e47c4c78-d58e-4045-8954-4e16052db589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523436487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1523436487
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3199081591
Short name T387
Test name
Test status
Simulation time 25411194242 ps
CPU time 218.38 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:29:51 PM PDT 24
Peak memory 200224 kb
Host smart-a95d17ef-81e3-4ce3-ab03-8d6a3091901e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199081591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3199081591
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3860096674
Short name T673
Test name
Test status
Simulation time 5642077886 ps
CPU time 45.08 seconds
Started Jul 27 06:26:10 PM PDT 24
Finished Jul 27 06:26:55 PM PDT 24
Peak memory 199080 kb
Host smart-a3061b81-ad01-44aa-9ebf-8e5a699df6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860096674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3860096674
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1174394554
Short name T579
Test name
Test status
Simulation time 143073363400 ps
CPU time 213.25 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:29:46 PM PDT 24
Peak memory 200244 kb
Host smart-ac484207-960c-474a-9090-251fa7224358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174394554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1174394554
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1689448561
Short name T851
Test name
Test status
Simulation time 48740880283 ps
CPU time 35.92 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:26:48 PM PDT 24
Peak memory 196104 kb
Host smart-e966d40e-a40c-43e5-9ab5-04e1802a8a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689448561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1689448561
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2328010350
Short name T731
Test name
Test status
Simulation time 318566373 ps
CPU time 1.11 seconds
Started Jul 27 06:26:10 PM PDT 24
Finished Jul 27 06:26:11 PM PDT 24
Peak memory 198404 kb
Host smart-38323620-18d4-47a4-9d2d-ba68146aad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328010350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2328010350
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.994668336
Short name T1095
Test name
Test status
Simulation time 102491855633 ps
CPU time 186.91 seconds
Started Jul 27 06:26:11 PM PDT 24
Finished Jul 27 06:29:18 PM PDT 24
Peak memory 200196 kb
Host smart-99940e47-94d4-46e4-ada4-74cf77f0fb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994668336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.994668336
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.81421180
Short name T580
Test name
Test status
Simulation time 49468644633 ps
CPU time 346.99 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:32:00 PM PDT 24
Peak memory 216324 kb
Host smart-7b35f1fb-543a-4001-abe2-ffde9b21e1cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81421180 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.81421180
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3544659535
Short name T360
Test name
Test status
Simulation time 1048812686 ps
CPU time 3.9 seconds
Started Jul 27 06:26:11 PM PDT 24
Finished Jul 27 06:26:15 PM PDT 24
Peak memory 199108 kb
Host smart-5302ab28-6466-4bd7-851e-9f738d7f7056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544659535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3544659535
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2785982506
Short name T85
Test name
Test status
Simulation time 50631671594 ps
CPU time 12.18 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:26:24 PM PDT 24
Peak memory 200188 kb
Host smart-5ace6211-1743-4c55-842f-112114983a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785982506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2785982506
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2807002367
Short name T174
Test name
Test status
Simulation time 172171991552 ps
CPU time 284.58 seconds
Started Jul 27 06:32:30 PM PDT 24
Finished Jul 27 06:37:15 PM PDT 24
Peak memory 200196 kb
Host smart-0b03363e-1101-4a53-ad08-4d9a94fc69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807002367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2807002367
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4041763375
Short name T818
Test name
Test status
Simulation time 178033030689 ps
CPU time 182.06 seconds
Started Jul 27 06:32:30 PM PDT 24
Finished Jul 27 06:35:33 PM PDT 24
Peak memory 200232 kb
Host smart-0c93d53e-16ae-43b9-a7bc-5ef492ea92e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041763375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4041763375
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4083093265
Short name T844
Test name
Test status
Simulation time 171216183638 ps
CPU time 87.72 seconds
Started Jul 27 06:32:33 PM PDT 24
Finished Jul 27 06:34:01 PM PDT 24
Peak memory 200224 kb
Host smart-cb95060d-ea5c-4c69-8c1a-1ce2c54bb606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083093265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4083093265
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2761518795
Short name T1162
Test name
Test status
Simulation time 155179234558 ps
CPU time 79.56 seconds
Started Jul 27 06:32:33 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 200196 kb
Host smart-a12c026d-442f-4ee6-8975-3c06ee37c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761518795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2761518795
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.284976350
Short name T556
Test name
Test status
Simulation time 43811460878 ps
CPU time 93.91 seconds
Started Jul 27 06:32:31 PM PDT 24
Finished Jul 27 06:34:05 PM PDT 24
Peak memory 200156 kb
Host smart-77db568d-bf8c-4630-9615-c89ef194e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284976350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.284976350
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.895376199
Short name T836
Test name
Test status
Simulation time 98028400918 ps
CPU time 40.8 seconds
Started Jul 27 06:32:33 PM PDT 24
Finished Jul 27 06:33:14 PM PDT 24
Peak memory 200132 kb
Host smart-8201ade0-66d3-4dbc-b054-98834da24d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895376199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.895376199
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2846581912
Short name T745
Test name
Test status
Simulation time 171176764755 ps
CPU time 189.07 seconds
Started Jul 27 06:32:32 PM PDT 24
Finished Jul 27 06:35:41 PM PDT 24
Peak memory 200184 kb
Host smart-7d8db135-5d98-421e-856e-eab74c00745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846581912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2846581912
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.8897125
Short name T186
Test name
Test status
Simulation time 151429656087 ps
CPU time 209.12 seconds
Started Jul 27 06:32:35 PM PDT 24
Finished Jul 27 06:36:04 PM PDT 24
Peak memory 199948 kb
Host smart-c3a17cc0-8296-4cd6-8a89-047af1abba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8897125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.8897125
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3507901590
Short name T718
Test name
Test status
Simulation time 253464880822 ps
CPU time 32.12 seconds
Started Jul 27 06:32:33 PM PDT 24
Finished Jul 27 06:33:05 PM PDT 24
Peak memory 200216 kb
Host smart-4031bed8-967e-4e7a-85df-7e03e2edc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507901590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3507901590
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.666162924
Short name T527
Test name
Test status
Simulation time 14985480 ps
CPU time 0.57 seconds
Started Jul 27 06:26:20 PM PDT 24
Finished Jul 27 06:26:21 PM PDT 24
Peak memory 195532 kb
Host smart-5f71e99f-7c2d-4528-b47d-3640006183d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666162924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.666162924
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1692698927
Short name T853
Test name
Test status
Simulation time 261877417968 ps
CPU time 53.95 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:27:06 PM PDT 24
Peak memory 200244 kb
Host smart-04ba899d-5a21-4d68-8bc0-3e06261b4c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692698927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1692698927
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2241842576
Short name T1160
Test name
Test status
Simulation time 19816705914 ps
CPU time 29.02 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:26:42 PM PDT 24
Peak memory 200200 kb
Host smart-fcbc7003-99e8-48e2-8b2f-38fdea475f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241842576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2241842576
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1608742027
Short name T178
Test name
Test status
Simulation time 13522562146 ps
CPU time 14.18 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:26:27 PM PDT 24
Peak memory 200228 kb
Host smart-7b9c256d-ff39-4c50-b4ea-cbf62f89db30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608742027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1608742027
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1029000441
Short name T691
Test name
Test status
Simulation time 17159440707 ps
CPU time 7.41 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:26:20 PM PDT 24
Peak memory 197508 kb
Host smart-55118b62-fdb0-44b8-a96d-a55f29a6f51c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029000441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1029000441
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4032059893
Short name T475
Test name
Test status
Simulation time 126539092222 ps
CPU time 296.52 seconds
Started Jul 27 06:26:20 PM PDT 24
Finished Jul 27 06:31:16 PM PDT 24
Peak memory 200060 kb
Host smart-5045e21c-3eec-434a-b927-a5ccf37c81ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032059893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4032059893
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2199926978
Short name T426
Test name
Test status
Simulation time 7905415157 ps
CPU time 4.58 seconds
Started Jul 27 06:26:23 PM PDT 24
Finished Jul 27 06:26:28 PM PDT 24
Peak memory 198248 kb
Host smart-a502d512-ff45-41e5-a7ce-b55ecf2c47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199926978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2199926978
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2988502271
Short name T1042
Test name
Test status
Simulation time 76963679549 ps
CPU time 130.11 seconds
Started Jul 27 06:26:14 PM PDT 24
Finished Jul 27 06:28:24 PM PDT 24
Peak memory 199708 kb
Host smart-afe0d488-ad25-4331-ba81-643bdc7ec2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988502271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2988502271
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1892448336
Short name T834
Test name
Test status
Simulation time 19836278843 ps
CPU time 178.29 seconds
Started Jul 27 06:26:23 PM PDT 24
Finished Jul 27 06:29:22 PM PDT 24
Peak memory 200176 kb
Host smart-ad5b18c9-be44-4f34-83d6-7917e7713349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892448336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1892448336
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.354580929
Short name T1025
Test name
Test status
Simulation time 3611276759 ps
CPU time 2.48 seconds
Started Jul 27 06:26:14 PM PDT 24
Finished Jul 27 06:26:17 PM PDT 24
Peak memory 198284 kb
Host smart-267c3e34-2894-4b24-b86e-3a6f63cb061c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354580929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.354580929
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.700927580
Short name T142
Test name
Test status
Simulation time 25585182294 ps
CPU time 13.45 seconds
Started Jul 27 06:26:21 PM PDT 24
Finished Jul 27 06:26:35 PM PDT 24
Peak memory 200200 kb
Host smart-7f0055b5-3d5c-4255-8f7a-c70476d97900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700927580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.700927580
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4272995405
Short name T755
Test name
Test status
Simulation time 661035288 ps
CPU time 1.61 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:26:14 PM PDT 24
Peak memory 195716 kb
Host smart-f446677a-eba5-4b9d-afa4-963518dd914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272995405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4272995405
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3099322500
Short name T503
Test name
Test status
Simulation time 672358469 ps
CPU time 2.41 seconds
Started Jul 27 06:26:13 PM PDT 24
Finished Jul 27 06:26:16 PM PDT 24
Peak memory 198984 kb
Host smart-d9641ea4-4143-4d05-9035-fc030f457be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099322500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3099322500
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1250766252
Short name T1153
Test name
Test status
Simulation time 132294942173 ps
CPU time 54.2 seconds
Started Jul 27 06:26:21 PM PDT 24
Finished Jul 27 06:27:16 PM PDT 24
Peak memory 215772 kb
Host smart-b82fb9a0-4022-47c2-b543-becc163617d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250766252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1250766252
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.436495339
Short name T582
Test name
Test status
Simulation time 118552576958 ps
CPU time 655.24 seconds
Started Jul 27 06:26:21 PM PDT 24
Finished Jul 27 06:37:17 PM PDT 24
Peak memory 225136 kb
Host smart-4bf8c314-6514-404c-8c0d-e8dbc3df4c3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436495339 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.436495339
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4270600760
Short name T381
Test name
Test status
Simulation time 1766943624 ps
CPU time 1.87 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:26:31 PM PDT 24
Peak memory 199968 kb
Host smart-467bc977-9533-49e3-8b29-6b6944b52c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270600760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4270600760
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.857293634
Short name T547
Test name
Test status
Simulation time 46149693341 ps
CPU time 41.11 seconds
Started Jul 27 06:26:12 PM PDT 24
Finished Jul 27 06:26:53 PM PDT 24
Peak memory 200188 kb
Host smart-fb2ef97c-0fc5-494a-963d-2cbf19d931c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857293634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.857293634
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2932502277
Short name T584
Test name
Test status
Simulation time 98834890316 ps
CPU time 36.9 seconds
Started Jul 27 06:32:44 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200192 kb
Host smart-d5bd7835-dc73-496b-96e8-47e33e7c3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932502277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2932502277
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2895134430
Short name T665
Test name
Test status
Simulation time 42856300281 ps
CPU time 19.44 seconds
Started Jul 27 06:32:42 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 200264 kb
Host smart-4da0939c-2116-4423-b6c0-d54ed7626ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895134430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2895134430
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3504776547
Short name T992
Test name
Test status
Simulation time 160389823978 ps
CPU time 39.48 seconds
Started Jul 27 06:32:40 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 200092 kb
Host smart-32442a84-8bfb-4b08-84ca-e8c3734c47e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504776547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3504776547
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1218442049
Short name T104
Test name
Test status
Simulation time 27625347083 ps
CPU time 43.22 seconds
Started Jul 27 06:32:41 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200208 kb
Host smart-f0c86db6-1bfa-49a7-a941-f8eb6f34799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218442049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1218442049
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.596061223
Short name T120
Test name
Test status
Simulation time 30982774707 ps
CPU time 12.32 seconds
Started Jul 27 06:32:40 PM PDT 24
Finished Jul 27 06:32:52 PM PDT 24
Peak memory 199820 kb
Host smart-eb66cee6-11dd-4046-9337-f7de23169880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596061223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.596061223
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1507949720
Short name T1102
Test name
Test status
Simulation time 10634942676 ps
CPU time 18.43 seconds
Started Jul 27 06:32:41 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200180 kb
Host smart-cd897d7f-c9df-4e66-abad-ad6371432457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507949720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1507949720
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2160733318
Short name T38
Test name
Test status
Simulation time 41553388031 ps
CPU time 68.07 seconds
Started Jul 27 06:32:45 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 199844 kb
Host smart-83b46714-b946-40d1-916c-036d17f34bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160733318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2160733318
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.36364978
Short name T198
Test name
Test status
Simulation time 65093680002 ps
CPU time 17.45 seconds
Started Jul 27 06:32:43 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200208 kb
Host smart-c56b5d2b-2778-4f07-ab8f-51967d5774f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36364978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.36364978
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.729450978
Short name T759
Test name
Test status
Simulation time 46738544142 ps
CPU time 18.86 seconds
Started Jul 27 06:32:43 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 199048 kb
Host smart-9300eb0e-8177-4915-abf9-17e5d25ae35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729450978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.729450978
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.306144138
Short name T1057
Test name
Test status
Simulation time 31393765155 ps
CPU time 17.99 seconds
Started Jul 27 06:32:41 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200232 kb
Host smart-53bc8335-0e08-4d93-8e4d-2f4810f62c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306144138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.306144138
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2284851497
Short name T1100
Test name
Test status
Simulation time 12926227 ps
CPU time 0.57 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:26:29 PM PDT 24
Peak memory 195620 kb
Host smart-5632ed7d-16d2-4971-82b3-6813f0a598f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284851497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2284851497
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.114218727
Short name T149
Test name
Test status
Simulation time 33436751080 ps
CPU time 27.5 seconds
Started Jul 27 06:26:21 PM PDT 24
Finished Jul 27 06:26:48 PM PDT 24
Peak memory 200160 kb
Host smart-d109a6cc-9e43-40fa-8c07-47406e28edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114218727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.114218727
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3267063141
Short name T881
Test name
Test status
Simulation time 43527415856 ps
CPU time 34.44 seconds
Started Jul 27 06:26:22 PM PDT 24
Finished Jul 27 06:26:57 PM PDT 24
Peak memory 200180 kb
Host smart-5cb966f5-3e84-4c6b-abfb-e24277a5916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267063141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3267063141
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.4246353054
Short name T1011
Test name
Test status
Simulation time 58432268550 ps
CPU time 33.25 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:27:02 PM PDT 24
Peak memory 200172 kb
Host smart-2cc200bd-c831-4ad6-8a3a-5e27695d3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246353054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4246353054
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.642916476
Short name T507
Test name
Test status
Simulation time 31574476222 ps
CPU time 10.37 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:26:40 PM PDT 24
Peak memory 199700 kb
Host smart-49a4c347-286f-4e49-91aa-4fed0371c3a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642916476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.642916476
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1166780000
Short name T964
Test name
Test status
Simulation time 131804963102 ps
CPU time 468.22 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 200280 kb
Host smart-93a35904-a2c6-4292-8e7a-2bbcb23ba5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166780000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1166780000
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3012338355
Short name T429
Test name
Test status
Simulation time 10736087497 ps
CPU time 2.29 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:26:32 PM PDT 24
Peak memory 199292 kb
Host smart-d4106b47-fd8d-45ab-bdfe-b3cfbae2b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012338355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3012338355
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1565516957
Short name T703
Test name
Test status
Simulation time 99032389700 ps
CPU time 168.52 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:29:18 PM PDT 24
Peak memory 208484 kb
Host smart-3146b4e6-05f3-468b-9cad-f73cb0b920ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565516957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1565516957
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4165639658
Short name T996
Test name
Test status
Simulation time 7611998945 ps
CPU time 380.9 seconds
Started Jul 27 06:26:33 PM PDT 24
Finished Jul 27 06:32:54 PM PDT 24
Peak memory 200248 kb
Host smart-e63c6b8b-5c65-452e-a817-d128ee51457c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165639658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4165639658
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3079287062
Short name T554
Test name
Test status
Simulation time 4234192332 ps
CPU time 33.54 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:27:03 PM PDT 24
Peak memory 198376 kb
Host smart-f1abffe6-d987-4582-ad7b-b37691390939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079287062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3079287062
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.930835038
Short name T736
Test name
Test status
Simulation time 17568712548 ps
CPU time 8.48 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:26:38 PM PDT 24
Peak memory 199780 kb
Host smart-5cfb1a3d-468e-46ea-9087-7916fc793fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930835038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.930835038
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.724329944
Short name T242
Test name
Test status
Simulation time 4744130438 ps
CPU time 3.96 seconds
Started Jul 27 06:26:31 PM PDT 24
Finished Jul 27 06:26:35 PM PDT 24
Peak memory 196352 kb
Host smart-f40e1015-c418-4f13-9bca-57a0f30b8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724329944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.724329944
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4270510271
Short name T447
Test name
Test status
Simulation time 735796124 ps
CPU time 2.19 seconds
Started Jul 27 06:26:22 PM PDT 24
Finished Jul 27 06:26:24 PM PDT 24
Peak memory 198584 kb
Host smart-25ce5e92-c2ed-45fa-90ef-8a6f977de2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270510271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4270510271
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1915842671
Short name T613
Test name
Test status
Simulation time 163843487852 ps
CPU time 66.52 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:27:36 PM PDT 24
Peak memory 215916 kb
Host smart-41aebaa3-b340-4e01-ba1c-26498f08ac0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915842671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1915842671
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3005727926
Short name T728
Test name
Test status
Simulation time 474837982 ps
CPU time 1.9 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:26:32 PM PDT 24
Peak memory 199636 kb
Host smart-2a700855-e789-49f6-9191-48890a56d752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005727926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3005727926
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.533107150
Short name T716
Test name
Test status
Simulation time 109418321136 ps
CPU time 462.91 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:34:13 PM PDT 24
Peak memory 200164 kb
Host smart-be809cbf-2239-476f-b41e-b6fb07af7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533107150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.533107150
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3416552251
Short name T1135
Test name
Test status
Simulation time 110414630761 ps
CPU time 174.38 seconds
Started Jul 27 06:32:43 PM PDT 24
Finished Jul 27 06:35:37 PM PDT 24
Peak memory 200176 kb
Host smart-5b05ccc3-7d73-405c-b9c7-462c9979af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416552251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3416552251
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2552251638
Short name T235
Test name
Test status
Simulation time 18135271225 ps
CPU time 31.32 seconds
Started Jul 27 06:32:41 PM PDT 24
Finished Jul 27 06:33:13 PM PDT 24
Peak memory 200180 kb
Host smart-38244833-8c1b-4aca-b023-7c0723341c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552251638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2552251638
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.293170329
Short name T657
Test name
Test status
Simulation time 101476295282 ps
CPU time 274.59 seconds
Started Jul 27 06:32:51 PM PDT 24
Finished Jul 27 06:37:26 PM PDT 24
Peak memory 200192 kb
Host smart-4e652a16-9897-4345-8ff0-32f3bf5b32ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293170329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.293170329
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3148556258
Short name T627
Test name
Test status
Simulation time 36484387242 ps
CPU time 53.69 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:46 PM PDT 24
Peak memory 200204 kb
Host smart-ead34a56-6ed5-4fd1-970c-bf4a90eff6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148556258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3148556258
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.627657768
Short name T172
Test name
Test status
Simulation time 57130588151 ps
CPU time 15.92 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:08 PM PDT 24
Peak memory 200176 kb
Host smart-2bd81d4f-afd6-49cd-985b-194bc13c9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627657768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.627657768
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1846237155
Short name T947
Test name
Test status
Simulation time 101788880807 ps
CPU time 144.23 seconds
Started Jul 27 06:32:50 PM PDT 24
Finished Jul 27 06:35:14 PM PDT 24
Peak memory 200100 kb
Host smart-d31ac353-71cd-40f8-8add-7760ce033ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846237155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1846237155
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.850419301
Short name T664
Test name
Test status
Simulation time 110351570631 ps
CPU time 47.67 seconds
Started Jul 27 06:32:51 PM PDT 24
Finished Jul 27 06:33:39 PM PDT 24
Peak memory 200196 kb
Host smart-c53e8e18-67ea-450f-a223-c1c14e621321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850419301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.850419301
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1046738722
Short name T529
Test name
Test status
Simulation time 30854924920 ps
CPU time 39.76 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:32 PM PDT 24
Peak memory 200268 kb
Host smart-c6e2dfbb-2e48-4327-9f28-ff8b9a343f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046738722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1046738722
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4014029507
Short name T772
Test name
Test status
Simulation time 232276568102 ps
CPU time 74.75 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:34:07 PM PDT 24
Peak memory 200220 kb
Host smart-dff0070c-20c4-467f-a2e9-faf824365e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014029507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4014029507
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3452111009
Short name T653
Test name
Test status
Simulation time 33581436 ps
CPU time 0.56 seconds
Started Jul 27 06:26:40 PM PDT 24
Finished Jul 27 06:26:41 PM PDT 24
Peak memory 195820 kb
Host smart-0e89c381-a4d8-4ed6-8dbc-e926b19d0a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452111009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3452111009
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3442015796
Short name T676
Test name
Test status
Simulation time 204339883211 ps
CPU time 179.35 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:29:28 PM PDT 24
Peak memory 200184 kb
Host smart-ef02efce-99dd-4025-b5ad-b9e1d9567447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442015796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3442015796
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4217818965
Short name T730
Test name
Test status
Simulation time 29916413801 ps
CPU time 67.35 seconds
Started Jul 27 06:26:31 PM PDT 24
Finished Jul 27 06:27:38 PM PDT 24
Peak memory 200120 kb
Host smart-744ee82b-048a-458f-808e-e851e3f2d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217818965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4217818965
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.182119829
Short name T889
Test name
Test status
Simulation time 27224119911 ps
CPU time 46.65 seconds
Started Jul 27 06:26:33 PM PDT 24
Finished Jul 27 06:27:19 PM PDT 24
Peak memory 200236 kb
Host smart-732e613a-d519-4c6d-bd75-13a9bc047be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182119829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.182119829
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1537057318
Short name T986
Test name
Test status
Simulation time 99201320229 ps
CPU time 156.49 seconds
Started Jul 27 06:26:32 PM PDT 24
Finished Jul 27 06:29:08 PM PDT 24
Peak memory 200196 kb
Host smart-7c75126f-b6ba-43fa-adb1-ee5f946b7565
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537057318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1537057318
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2442334823
Short name T1067
Test name
Test status
Simulation time 50758820927 ps
CPU time 335.96 seconds
Started Jul 27 06:26:38 PM PDT 24
Finished Jul 27 06:32:14 PM PDT 24
Peak memory 200232 kb
Host smart-d9946419-ad31-4d0e-bdb7-ca04fbcbc2a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442334823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2442334823
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2848486855
Short name T343
Test name
Test status
Simulation time 3392475378 ps
CPU time 5.49 seconds
Started Jul 27 06:26:39 PM PDT 24
Finished Jul 27 06:26:44 PM PDT 24
Peak memory 198172 kb
Host smart-9b2a8481-0ce5-469c-ba7d-2210e7e28f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848486855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2848486855
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2329986109
Short name T1092
Test name
Test status
Simulation time 150665622407 ps
CPU time 49.15 seconds
Started Jul 27 06:26:30 PM PDT 24
Finished Jul 27 06:27:19 PM PDT 24
Peak memory 200320 kb
Host smart-b38b7d86-432b-4819-81ae-b776ee0e8648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329986109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2329986109
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3384995316
Short name T688
Test name
Test status
Simulation time 11897752438 ps
CPU time 123.77 seconds
Started Jul 27 06:26:38 PM PDT 24
Finished Jul 27 06:28:42 PM PDT 24
Peak memory 200180 kb
Host smart-ed346a64-6740-4eac-bb33-0c2d1e585eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384995316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3384995316
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4229769586
Short name T712
Test name
Test status
Simulation time 4753502755 ps
CPU time 4.22 seconds
Started Jul 27 06:26:31 PM PDT 24
Finished Jul 27 06:26:35 PM PDT 24
Peak memory 198372 kb
Host smart-f1df2570-5328-474d-b875-29d38a938aa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229769586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4229769586
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1168965673
Short name T629
Test name
Test status
Simulation time 95905567377 ps
CPU time 35.39 seconds
Started Jul 27 06:26:39 PM PDT 24
Finished Jul 27 06:27:15 PM PDT 24
Peak memory 200220 kb
Host smart-a8f2f2ad-dd5c-4ec0-8ab5-97a54ba94ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168965673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1168965673
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3371150587
Short name T530
Test name
Test status
Simulation time 3341526521 ps
CPU time 1.85 seconds
Started Jul 27 06:26:29 PM PDT 24
Finished Jul 27 06:26:31 PM PDT 24
Peak memory 196260 kb
Host smart-e93f7ab8-9364-4384-84ae-78cd392c6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371150587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3371150587
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2492789367
Short name T32
Test name
Test status
Simulation time 509720194 ps
CPU time 1.2 seconds
Started Jul 27 06:26:32 PM PDT 24
Finished Jul 27 06:26:33 PM PDT 24
Peak memory 198956 kb
Host smart-a8f7a1f3-de81-4f54-9e5b-3887dd97bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492789367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2492789367
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3461636892
Short name T917
Test name
Test status
Simulation time 322202075319 ps
CPU time 724.18 seconds
Started Jul 27 06:26:38 PM PDT 24
Finished Jul 27 06:38:43 PM PDT 24
Peak memory 200352 kb
Host smart-2cf1417d-7f57-40e6-86f9-e22947a1167c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461636892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3461636892
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4215403302
Short name T663
Test name
Test status
Simulation time 27989850025 ps
CPU time 300.69 seconds
Started Jul 27 06:26:39 PM PDT 24
Finished Jul 27 06:31:39 PM PDT 24
Peak memory 209568 kb
Host smart-a70e4c3e-b82f-4b80-8055-ee995890d2f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215403302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4215403302
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2313807493
Short name T254
Test name
Test status
Simulation time 1337826823 ps
CPU time 2.29 seconds
Started Jul 27 06:26:41 PM PDT 24
Finished Jul 27 06:26:43 PM PDT 24
Peak memory 198672 kb
Host smart-6445d34e-092c-4811-bee7-52ad95feb0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313807493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2313807493
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2977401981
Short name T473
Test name
Test status
Simulation time 29911710230 ps
CPU time 40.11 seconds
Started Jul 27 06:32:50 PM PDT 24
Finished Jul 27 06:33:30 PM PDT 24
Peak memory 200076 kb
Host smart-de11952e-d5dd-44e0-a51c-685aceec1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977401981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2977401981
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4255668057
Short name T518
Test name
Test status
Simulation time 125453779221 ps
CPU time 168.53 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:35:41 PM PDT 24
Peak memory 200156 kb
Host smart-c21a6596-02e7-468b-ad4f-b45a2844ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255668057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4255668057
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1609383746
Short name T751
Test name
Test status
Simulation time 63038971483 ps
CPU time 27.55 seconds
Started Jul 27 06:32:51 PM PDT 24
Finished Jul 27 06:33:19 PM PDT 24
Peak memory 200208 kb
Host smart-24b56557-2fc3-4dd8-880f-ec8ed052eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609383746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1609383746
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1240574317
Short name T403
Test name
Test status
Simulation time 27199507500 ps
CPU time 17.73 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:10 PM PDT 24
Peak memory 200240 kb
Host smart-bd21e7d9-5c94-4d30-a423-a4a12f336226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240574317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1240574317
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1375852739
Short name T1128
Test name
Test status
Simulation time 29642155086 ps
CPU time 10.29 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 198904 kb
Host smart-b54ddc67-fedd-41dc-bfaf-cafa4499e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375852739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1375852739
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1015996746
Short name T974
Test name
Test status
Simulation time 91358574696 ps
CPU time 124.96 seconds
Started Jul 27 06:32:51 PM PDT 24
Finished Jul 27 06:34:56 PM PDT 24
Peak memory 200140 kb
Host smart-2587e0ee-5ea4-4821-bf82-dd0ce452eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015996746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1015996746
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3865887924
Short name T1086
Test name
Test status
Simulation time 105519335106 ps
CPU time 62.05 seconds
Started Jul 27 06:32:49 PM PDT 24
Finished Jul 27 06:33:52 PM PDT 24
Peak memory 200212 kb
Host smart-4d63235e-88ce-49e5-b16e-4e7ac440d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865887924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3865887924
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3545782813
Short name T761
Test name
Test status
Simulation time 76955592366 ps
CPU time 32.04 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200228 kb
Host smart-4b7bf8fa-b2c3-46ac-87df-90d2fbf3f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545782813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3545782813
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1209909373
Short name T18
Test name
Test status
Simulation time 13347421 ps
CPU time 0.56 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:26:48 PM PDT 24
Peak memory 195600 kb
Host smart-0df58c6c-993a-4754-ad58-c329922ce37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209909373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1209909373
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.357344395
Short name T1123
Test name
Test status
Simulation time 20975309875 ps
CPU time 24.79 seconds
Started Jul 27 06:26:38 PM PDT 24
Finished Jul 27 06:27:03 PM PDT 24
Peak memory 200228 kb
Host smart-e69c68b1-86f4-4d35-8752-7167df61914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357344395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.357344395
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3300739018
Short name T819
Test name
Test status
Simulation time 109831300763 ps
CPU time 42.69 seconds
Started Jul 27 06:26:38 PM PDT 24
Finished Jul 27 06:27:21 PM PDT 24
Peak memory 199988 kb
Host smart-3533de4e-e166-4fea-977e-45385bcbc6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300739018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3300739018
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.539901589
Short name T192
Test name
Test status
Simulation time 82914870530 ps
CPU time 72.32 seconds
Started Jul 27 06:26:40 PM PDT 24
Finished Jul 27 06:27:52 PM PDT 24
Peak memory 200100 kb
Host smart-36036f61-be10-423a-8f6e-1c217c93af5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539901589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.539901589
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.962655170
Short name T675
Test name
Test status
Simulation time 363092553439 ps
CPU time 31.23 seconds
Started Jul 27 06:26:40 PM PDT 24
Finished Jul 27 06:27:11 PM PDT 24
Peak memory 200168 kb
Host smart-48e2680c-5183-4d35-9007-f0251e3ca26a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962655170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.962655170
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3138239125
Short name T1147
Test name
Test status
Simulation time 71197450254 ps
CPU time 270.88 seconds
Started Jul 27 06:26:49 PM PDT 24
Finished Jul 27 06:31:20 PM PDT 24
Peak memory 200236 kb
Host smart-6d2e029f-085b-47bf-9978-46d4a99136af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138239125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3138239125
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.995208844
Short name T341
Test name
Test status
Simulation time 5608061697 ps
CPU time 5.64 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:26:54 PM PDT 24
Peak memory 198916 kb
Host smart-0ca308f0-fe77-439a-96d1-6581c4fa2ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995208844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.995208844
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.631922038
Short name T274
Test name
Test status
Simulation time 170443183422 ps
CPU time 70.68 seconds
Started Jul 27 06:26:47 PM PDT 24
Finished Jul 27 06:27:58 PM PDT 24
Peak memory 200320 kb
Host smart-43e65fbf-915b-4345-9743-fe491b0c824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631922038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.631922038
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3420077967
Short name T461
Test name
Test status
Simulation time 5049537398 ps
CPU time 295.53 seconds
Started Jul 27 06:26:47 PM PDT 24
Finished Jul 27 06:31:43 PM PDT 24
Peak memory 200180 kb
Host smart-20ce345a-c7e7-41ee-8106-3647684415be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420077967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3420077967
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2656822032
Short name T733
Test name
Test status
Simulation time 3496743916 ps
CPU time 7.24 seconds
Started Jul 27 06:26:41 PM PDT 24
Finished Jul 27 06:26:48 PM PDT 24
Peak memory 199148 kb
Host smart-972645a8-fc59-456b-9a7d-e6c048897757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656822032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2656822032
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1084830045
Short name T817
Test name
Test status
Simulation time 37705043802 ps
CPU time 15.34 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:27:03 PM PDT 24
Peak memory 199884 kb
Host smart-8c8dd030-fead-4558-9462-e2ac53d7f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084830045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1084830045
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4223439540
Short name T828
Test name
Test status
Simulation time 1839258453 ps
CPU time 1.39 seconds
Started Jul 27 06:26:49 PM PDT 24
Finished Jul 27 06:26:50 PM PDT 24
Peak memory 195812 kb
Host smart-be81f3bd-85a6-4307-873c-dcf1fba68a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223439540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4223439540
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.446867180
Short name T427
Test name
Test status
Simulation time 934528878 ps
CPU time 3.11 seconds
Started Jul 27 06:26:39 PM PDT 24
Finished Jul 27 06:26:42 PM PDT 24
Peak memory 200048 kb
Host smart-39df6eb3-947a-4773-948f-41b12d9774e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446867180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.446867180
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.848627985
Short name T1088
Test name
Test status
Simulation time 345171760191 ps
CPU time 1624.73 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:53:53 PM PDT 24
Peak memory 200204 kb
Host smart-4dce2b60-fb7c-43e0-90a7-e8aaf14c7cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848627985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.848627985
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2704028492
Short name T847
Test name
Test status
Simulation time 9732442633 ps
CPU time 113.68 seconds
Started Jul 27 06:26:46 PM PDT 24
Finished Jul 27 06:28:40 PM PDT 24
Peak memory 209856 kb
Host smart-ce2b5134-d942-4e83-acbc-9b9e0922b282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704028492 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2704028492
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.661977535
Short name T353
Test name
Test status
Simulation time 2288741368 ps
CPU time 2.51 seconds
Started Jul 27 06:26:47 PM PDT 24
Finished Jul 27 06:26:50 PM PDT 24
Peak memory 200104 kb
Host smart-4015c4bd-5eca-496b-bca1-f048a1cca0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661977535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.661977535
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2609465463
Short name T852
Test name
Test status
Simulation time 51711149892 ps
CPU time 83.24 seconds
Started Jul 27 06:26:39 PM PDT 24
Finished Jul 27 06:28:02 PM PDT 24
Peak memory 200220 kb
Host smart-b494f345-cb95-4751-a5aa-159097483639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609465463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2609465463
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3785202250
Short name T660
Test name
Test status
Simulation time 124170253624 ps
CPU time 89.99 seconds
Started Jul 27 06:32:52 PM PDT 24
Finished Jul 27 06:34:22 PM PDT 24
Peak memory 200140 kb
Host smart-4523a1c7-ce23-4ebc-b4e4-115893a6bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785202250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3785202250
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1728547110
Short name T226
Test name
Test status
Simulation time 13531184433 ps
CPU time 22.51 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:33:23 PM PDT 24
Peak memory 200264 kb
Host smart-4a2b0e1e-0aef-480f-9113-8ca05b4c36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728547110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1728547110
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3440862721
Short name T340
Test name
Test status
Simulation time 44296227674 ps
CPU time 51.34 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:33:52 PM PDT 24
Peak memory 200236 kb
Host smart-a0838a4b-cba1-4069-be3e-f1c549ed9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440862721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3440862721
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1986860621
Short name T1157
Test name
Test status
Simulation time 66206259148 ps
CPU time 95.33 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:34:35 PM PDT 24
Peak memory 200096 kb
Host smart-677ad88c-b486-47b8-8cdc-465da2f67502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986860621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1986860621
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2487734415
Short name T193
Test name
Test status
Simulation time 164690334631 ps
CPU time 138.94 seconds
Started Jul 27 06:32:59 PM PDT 24
Finished Jul 27 06:35:18 PM PDT 24
Peak memory 200116 kb
Host smart-c0c4fad1-61e7-4080-8bd2-7cec1ddf10c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487734415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2487734415
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3041901556
Short name T195
Test name
Test status
Simulation time 14288601761 ps
CPU time 24.56 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200176 kb
Host smart-d968cb88-d9e5-4bf1-8d54-1126050edf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041901556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3041901556
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.45467033
Short name T336
Test name
Test status
Simulation time 99626876676 ps
CPU time 16.03 seconds
Started Jul 27 06:33:02 PM PDT 24
Finished Jul 27 06:33:18 PM PDT 24
Peak memory 200172 kb
Host smart-a347b6b4-470a-426f-86ec-e7fe733ce745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45467033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.45467033
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.689790353
Short name T98
Test name
Test status
Simulation time 13110280997 ps
CPU time 17.46 seconds
Started Jul 27 06:32:59 PM PDT 24
Finished Jul 27 06:33:17 PM PDT 24
Peak memory 200228 kb
Host smart-adc03e10-d752-4c93-92f2-2617ce974476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689790353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.689790353
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2053998946
Short name T184
Test name
Test status
Simulation time 37704388015 ps
CPU time 45.36 seconds
Started Jul 27 06:33:01 PM PDT 24
Finished Jul 27 06:33:46 PM PDT 24
Peak memory 200192 kb
Host smart-d6cc6088-fcfe-400d-ad57-056d2484f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053998946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2053998946
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3349118958
Short name T623
Test name
Test status
Simulation time 41931677 ps
CPU time 0.54 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:26:58 PM PDT 24
Peak memory 195552 kb
Host smart-4b77cbe4-3c97-4820-a749-660f4ec0470e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349118958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3349118958
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1758730190
Short name T799
Test name
Test status
Simulation time 29928508700 ps
CPU time 15.75 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:27:04 PM PDT 24
Peak memory 200248 kb
Host smart-3ec0f9a8-fc52-4fc7-a194-935304b309d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758730190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1758730190
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4190213042
Short name T617
Test name
Test status
Simulation time 92090524224 ps
CPU time 68.71 seconds
Started Jul 27 06:26:47 PM PDT 24
Finished Jul 27 06:27:56 PM PDT 24
Peak memory 200040 kb
Host smart-9248fd54-2fc8-4e7b-b99f-0ff8342c349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190213042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4190213042
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3428271418
Short name T183
Test name
Test status
Simulation time 26592363297 ps
CPU time 43.59 seconds
Started Jul 27 06:26:46 PM PDT 24
Finished Jul 27 06:27:30 PM PDT 24
Peak memory 200144 kb
Host smart-4ae7e596-741e-4041-a32b-ae8b0cb4d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428271418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3428271418
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3805648210
Short name T1066
Test name
Test status
Simulation time 11909000606 ps
CPU time 2.42 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:27:01 PM PDT 24
Peak memory 198060 kb
Host smart-13aa684e-6354-4618-975f-a660b1e79425
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805648210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3805648210
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.697008305
Short name T252
Test name
Test status
Simulation time 89545616660 ps
CPU time 256.07 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:31:15 PM PDT 24
Peak memory 200164 kb
Host smart-6c67a110-043f-4b7d-903f-9a11a10033d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697008305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.697008305
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4245593150
Short name T1069
Test name
Test status
Simulation time 695221532 ps
CPU time 1.12 seconds
Started Jul 27 06:26:57 PM PDT 24
Finished Jul 27 06:26:59 PM PDT 24
Peak memory 195688 kb
Host smart-051188b0-72c7-4a13-8ea8-db54fc1b2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245593150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4245593150
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.210333322
Short name T1000
Test name
Test status
Simulation time 50740393259 ps
CPU time 75.04 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:28:14 PM PDT 24
Peak memory 198716 kb
Host smart-0845aa1a-ff2c-48c5-88de-4c6b065f3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210333322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.210333322
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2025977353
Short name T994
Test name
Test status
Simulation time 14405045218 ps
CPU time 703.35 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:38:42 PM PDT 24
Peak memory 200220 kb
Host smart-aa459c15-ac0f-4792-82c9-30db66c4d880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025977353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2025977353
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1596200569
Short name T388
Test name
Test status
Simulation time 5382582442 ps
CPU time 21.81 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:27:20 PM PDT 24
Peak memory 199316 kb
Host smart-87a807a6-b192-4d8a-83dd-5e4fae669c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596200569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1596200569
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1193790641
Short name T290
Test name
Test status
Simulation time 112907523009 ps
CPU time 178.37 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:29:56 PM PDT 24
Peak memory 200152 kb
Host smart-4e253e03-5bed-4f4a-aada-c52e9399ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193790641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1193790641
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2830765312
Short name T270
Test name
Test status
Simulation time 4080330312 ps
CPU time 4.76 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:27:03 PM PDT 24
Peak memory 197232 kb
Host smart-1ab7d269-f695-4238-8086-1acd320e6472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830765312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2830765312
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.570315232
Short name T515
Test name
Test status
Simulation time 1034762182 ps
CPU time 1.51 seconds
Started Jul 27 06:26:47 PM PDT 24
Finished Jul 27 06:26:49 PM PDT 24
Peak memory 199848 kb
Host smart-db6b182a-aa96-42d9-82d6-5070a5e32e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570315232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.570315232
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2200263718
Short name T1097
Test name
Test status
Simulation time 25173187077 ps
CPU time 724.93 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:39:04 PM PDT 24
Peak memory 200384 kb
Host smart-a0a9dd42-fea6-4b2e-a443-7f07d046f25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200263718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2200263718
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2149994029
Short name T1098
Test name
Test status
Simulation time 155458925227 ps
CPU time 457.26 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:34:36 PM PDT 24
Peak memory 225088 kb
Host smart-fbe43c0a-886c-411d-8643-6ba185f3551b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149994029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2149994029
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3616273317
Short name T1081
Test name
Test status
Simulation time 6753594984 ps
CPU time 12.75 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:27:12 PM PDT 24
Peak memory 200056 kb
Host smart-7a1fa7e7-055d-4f8d-afe5-e2c33e445b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616273317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3616273317
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2743933246
Short name T540
Test name
Test status
Simulation time 91679321486 ps
CPU time 92.18 seconds
Started Jul 27 06:26:48 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 200256 kb
Host smart-ddda5a91-7baa-4950-9e77-e7b97cf2f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743933246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2743933246
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1275443804
Short name T223
Test name
Test status
Simulation time 104834394853 ps
CPU time 45.81 seconds
Started Jul 27 06:33:01 PM PDT 24
Finished Jul 27 06:33:47 PM PDT 24
Peak memory 200164 kb
Host smart-858313d7-b2c0-49df-9ac7-8fcdeb448e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275443804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1275443804
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.23353065
Short name T216
Test name
Test status
Simulation time 72579779724 ps
CPU time 30.29 seconds
Started Jul 27 06:32:58 PM PDT 24
Finished Jul 27 06:33:28 PM PDT 24
Peak memory 200220 kb
Host smart-a1a0c642-5b1c-4bf5-969a-35625a67128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23353065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.23353065
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.880555158
Short name T594
Test name
Test status
Simulation time 141790449501 ps
CPU time 60.76 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:34:01 PM PDT 24
Peak memory 200312 kb
Host smart-02711aec-fde2-4974-a46a-f3cc5b550cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880555158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.880555158
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2843595640
Short name T778
Test name
Test status
Simulation time 22715775401 ps
CPU time 38.15 seconds
Started Jul 27 06:32:58 PM PDT 24
Finished Jul 27 06:33:36 PM PDT 24
Peak memory 200192 kb
Host smart-bbcec57d-5d12-4ba4-a0de-2d9cb43780ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843595640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2843595640
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.479065191
Short name T148
Test name
Test status
Simulation time 92636067196 ps
CPU time 119.15 seconds
Started Jul 27 06:32:59 PM PDT 24
Finished Jul 27 06:34:58 PM PDT 24
Peak memory 200132 kb
Host smart-6ab15769-1699-4770-9d85-60ea31a9aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479065191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.479065191
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4052149378
Short name T702
Test name
Test status
Simulation time 34745698315 ps
CPU time 12.26 seconds
Started Jul 27 06:33:00 PM PDT 24
Finished Jul 27 06:33:13 PM PDT 24
Peak memory 199948 kb
Host smart-4a8886b2-aae9-4482-9e67-d045b4afd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052149378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4052149378
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2488917854
Short name T214
Test name
Test status
Simulation time 173753400202 ps
CPU time 38.37 seconds
Started Jul 27 06:33:08 PM PDT 24
Finished Jul 27 06:33:46 PM PDT 24
Peak memory 200068 kb
Host smart-7f489e4a-4fcc-4563-a25d-ea59f1ea34a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488917854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2488917854
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2839592108
Short name T386
Test name
Test status
Simulation time 12352096157 ps
CPU time 5.44 seconds
Started Jul 27 06:33:08 PM PDT 24
Finished Jul 27 06:33:14 PM PDT 24
Peak memory 200112 kb
Host smart-f5bda0f4-ffae-45ba-bc44-ce4dd257b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839592108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2839592108
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2241390639
Short name T114
Test name
Test status
Simulation time 27980411338 ps
CPU time 69.86 seconds
Started Jul 27 06:33:07 PM PDT 24
Finished Jul 27 06:34:17 PM PDT 24
Peak memory 200440 kb
Host smart-0e745ddd-3e98-4776-854c-1a29fcd78b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241390639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2241390639
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1561555598
Short name T652
Test name
Test status
Simulation time 46854700 ps
CPU time 0.56 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:23:22 PM PDT 24
Peak memory 195908 kb
Host smart-ad0e31b9-7077-49c0-939a-6680afb33f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561555598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1561555598
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.160160763
Short name T601
Test name
Test status
Simulation time 32197390577 ps
CPU time 26.4 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:37 PM PDT 24
Peak memory 200196 kb
Host smart-b4a5f37e-5851-4093-88d0-409ac0c0daab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160160763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.160160763
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.4207800053
Short name T913
Test name
Test status
Simulation time 43103090854 ps
CPU time 18.21 seconds
Started Jul 27 06:23:12 PM PDT 24
Finished Jul 27 06:23:30 PM PDT 24
Peak memory 200068 kb
Host smart-d39fc704-eaa7-4465-978e-0c2d78c7d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207800053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4207800053
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4101481025
Short name T221
Test name
Test status
Simulation time 24962164416 ps
CPU time 43.5 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:54 PM PDT 24
Peak memory 200208 kb
Host smart-a1f047b4-c1e2-4835-9db0-9579e8629aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101481025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4101481025
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.843084747
Short name T452
Test name
Test status
Simulation time 15282215750 ps
CPU time 28.1 seconds
Started Jul 27 06:23:09 PM PDT 24
Finished Jul 27 06:23:37 PM PDT 24
Peak memory 199748 kb
Host smart-1831c3a4-30f5-4774-8343-07042c045eb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843084747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.843084747
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3052080263
Short name T891
Test name
Test status
Simulation time 80363395647 ps
CPU time 446.44 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:30:47 PM PDT 24
Peak memory 200168 kb
Host smart-b9fac8d4-4b27-4a6d-abfb-ca51d5b99794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052080263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3052080263
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1430067485
Short name T474
Test name
Test status
Simulation time 10083732316 ps
CPU time 18.04 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:23:39 PM PDT 24
Peak memory 198000 kb
Host smart-ed213179-c675-48b7-b076-cd79af56f5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430067485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1430067485
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2910263290
Short name T309
Test name
Test status
Simulation time 172940430216 ps
CPU time 89.24 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:24:40 PM PDT 24
Peak memory 200028 kb
Host smart-13e709ea-bb9e-47d1-863d-76b826601b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910263290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2910263290
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1498630903
Short name T239
Test name
Test status
Simulation time 11928690144 ps
CPU time 449.89 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:30:51 PM PDT 24
Peak memory 200200 kb
Host smart-2cd1ace9-b0e5-4154-9cd0-5f4ce596c86c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498630903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1498630903
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3017182276
Short name T948
Test name
Test status
Simulation time 2885496853 ps
CPU time 3.76 seconds
Started Jul 27 06:23:12 PM PDT 24
Finished Jul 27 06:23:15 PM PDT 24
Peak memory 199476 kb
Host smart-f8e90890-78aa-4639-86ba-c5b773a24cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017182276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3017182276
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3628550372
Short name T896
Test name
Test status
Simulation time 65543668062 ps
CPU time 23.77 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:33 PM PDT 24
Peak memory 200140 kb
Host smart-8aab6732-cddd-4ea1-a3f6-4b8975fe02fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628550372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3628550372
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1114404133
Short name T398
Test name
Test status
Simulation time 2635734908 ps
CPU time 2.95 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:23:13 PM PDT 24
Peak memory 196280 kb
Host smart-d4ca1ac3-97e0-4b6b-8012-a5ac9e372339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114404133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1114404133
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.542113711
Short name T80
Test name
Test status
Simulation time 31283771 ps
CPU time 0.75 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:23:22 PM PDT 24
Peak memory 218532 kb
Host smart-9a1fb78c-31b4-41f5-aab3-01c7a37b2169
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542113711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.542113711
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1821504029
Short name T797
Test name
Test status
Simulation time 5311996427 ps
CPU time 9.43 seconds
Started Jul 27 06:23:09 PM PDT 24
Finished Jul 27 06:23:19 PM PDT 24
Peak memory 199472 kb
Host smart-60e1f16a-8475-4519-9b2d-c280c27fe955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821504029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1821504029
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1142611676
Short name T1087
Test name
Test status
Simulation time 240520998204 ps
CPU time 447.89 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:30:50 PM PDT 24
Peak memory 200232 kb
Host smart-3047b1f7-fed8-4259-96a2-342fb07c64bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142611676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1142611676
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1797721583
Short name T7
Test name
Test status
Simulation time 112242250430 ps
CPU time 528.5 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:32:09 PM PDT 24
Peak memory 216900 kb
Host smart-c56e3895-5359-4c55-8dd3-ea9906bfb818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797721583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1797721583
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1139696251
Short name T869
Test name
Test status
Simulation time 1501072666 ps
CPU time 1.57 seconds
Started Jul 27 06:23:11 PM PDT 24
Finished Jul 27 06:23:12 PM PDT 24
Peak memory 199800 kb
Host smart-57c6d05f-37e6-44cb-a27c-bde1026796f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139696251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1139696251
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1416140999
Short name T246
Test name
Test status
Simulation time 78902880166 ps
CPU time 60.5 seconds
Started Jul 27 06:23:10 PM PDT 24
Finished Jul 27 06:24:10 PM PDT 24
Peak memory 200228 kb
Host smart-30c1cc64-e1a7-4a7e-9302-3ca9766fb583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416140999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1416140999
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2046418573
Short name T605
Test name
Test status
Simulation time 43231568 ps
CPU time 0.57 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:27:07 PM PDT 24
Peak memory 195904 kb
Host smart-d7c4a3f8-5824-41c5-850e-dba755a1608d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046418573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2046418573
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.725055867
Short name T154
Test name
Test status
Simulation time 94448420326 ps
CPU time 44.51 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:27:44 PM PDT 24
Peak memory 200208 kb
Host smart-c66c7011-49df-44c3-98b8-ec7be38c3a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725055867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.725055867
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2524713670
Short name T490
Test name
Test status
Simulation time 61316273886 ps
CPU time 162.28 seconds
Started Jul 27 06:27:07 PM PDT 24
Finished Jul 27 06:29:49 PM PDT 24
Peak memory 200248 kb
Host smart-d1331ec0-9226-458e-b97f-eebbfade216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524713670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2524713670
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1492117422
Short name T241
Test name
Test status
Simulation time 22249813340 ps
CPU time 59.87 seconds
Started Jul 27 06:27:07 PM PDT 24
Finished Jul 27 06:28:07 PM PDT 24
Peak memory 200376 kb
Host smart-ead3798e-8301-4492-9119-2dcea00393d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492117422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1492117422
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2220664968
Short name T711
Test name
Test status
Simulation time 41355624411 ps
CPU time 60.12 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:28:07 PM PDT 24
Peak memory 200228 kb
Host smart-0cb0ef53-f907-435d-a730-0b00ecdaf567
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220664968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2220664968
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3302683205
Short name T257
Test name
Test status
Simulation time 87767838996 ps
CPU time 707.32 seconds
Started Jul 27 06:27:11 PM PDT 24
Finished Jul 27 06:38:58 PM PDT 24
Peak memory 200184 kb
Host smart-94d08820-b427-4603-adbd-a3fe64788ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302683205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3302683205
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2418862049
Short name T1144
Test name
Test status
Simulation time 7496180946 ps
CPU time 14.44 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:27:21 PM PDT 24
Peak memory 199064 kb
Host smart-6d1b4f48-8937-4e9a-8f66-6ec163480a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418862049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2418862049
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.9213240
Short name T520
Test name
Test status
Simulation time 196624431586 ps
CPU time 41.72 seconds
Started Jul 27 06:27:10 PM PDT 24
Finished Jul 27 06:27:52 PM PDT 24
Peak memory 200292 kb
Host smart-90024850-161e-4c87-809c-ac7321c7e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9213240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.9213240
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.738175937
Short name T528
Test name
Test status
Simulation time 19968692509 ps
CPU time 1120.62 seconds
Started Jul 27 06:27:03 PM PDT 24
Finished Jul 27 06:45:44 PM PDT 24
Peak memory 200244 kb
Host smart-7da2bf95-f5bc-472d-8f41-251add7444fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738175937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.738175937
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.694553998
Short name T928
Test name
Test status
Simulation time 6867315881 ps
CPU time 8.5 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:27:14 PM PDT 24
Peak memory 199444 kb
Host smart-4f1f45d0-1e51-429d-91fc-a1b87b40d130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694553998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.694553998
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1298640293
Short name T298
Test name
Test status
Simulation time 37791799496 ps
CPU time 62.35 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:28:09 PM PDT 24
Peak memory 200180 kb
Host smart-d3860762-72d9-4000-a4ae-6a76aac4e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298640293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1298640293
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.822465244
Short name T596
Test name
Test status
Simulation time 3848568451 ps
CPU time 3.2 seconds
Started Jul 27 06:27:11 PM PDT 24
Finished Jul 27 06:27:14 PM PDT 24
Peak memory 196352 kb
Host smart-57118f03-206d-4b86-af1d-664777391da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822465244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.822465244
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3167485705
Short name T283
Test name
Test status
Simulation time 489720117 ps
CPU time 2.51 seconds
Started Jul 27 06:26:59 PM PDT 24
Finished Jul 27 06:27:01 PM PDT 24
Peak memory 199896 kb
Host smart-965fde63-2e7c-40f1-864f-cfd6573b6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167485705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3167485705
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.32679461
Short name T695
Test name
Test status
Simulation time 333737899631 ps
CPU time 209.64 seconds
Started Jul 27 06:27:08 PM PDT 24
Finished Jul 27 06:30:38 PM PDT 24
Peak memory 200204 kb
Host smart-6c53d7de-1961-45f3-8896-407e8cba5193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32679461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.32679461
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3732349925
Short name T804
Test name
Test status
Simulation time 275297885853 ps
CPU time 984.17 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:43:31 PM PDT 24
Peak memory 227376 kb
Host smart-888229e0-70e3-469d-9768-1840db5f1fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732349925 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3732349925
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2589111496
Short name T1113
Test name
Test status
Simulation time 502753364 ps
CPU time 2.31 seconds
Started Jul 27 06:27:05 PM PDT 24
Finished Jul 27 06:27:07 PM PDT 24
Peak memory 199132 kb
Host smart-7faeb6ac-e9d9-48db-a282-c59a32fd9caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589111496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2589111496
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1125184979
Short name T1017
Test name
Test status
Simulation time 3865643696 ps
CPU time 8.01 seconds
Started Jul 27 06:26:58 PM PDT 24
Finished Jul 27 06:27:07 PM PDT 24
Peak memory 200216 kb
Host smart-9a477f72-13fe-48b5-bb3d-ed3336dc8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125184979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1125184979
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1785840815
Short name T649
Test name
Test status
Simulation time 120124194 ps
CPU time 0.52 seconds
Started Jul 27 06:27:17 PM PDT 24
Finished Jul 27 06:27:18 PM PDT 24
Peak memory 195016 kb
Host smart-cf1655f1-b9be-44f8-82f3-c465f8873315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785840815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1785840815
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.528129085
Short name T469
Test name
Test status
Simulation time 177502630061 ps
CPU time 112.32 seconds
Started Jul 27 06:27:05 PM PDT 24
Finished Jul 27 06:28:58 PM PDT 24
Peak memory 200212 kb
Host smart-6ee185b2-5281-457f-ba5a-2f2c19aa5970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528129085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.528129085
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3708258076
Short name T1131
Test name
Test status
Simulation time 21543433193 ps
CPU time 33.4 seconds
Started Jul 27 06:27:17 PM PDT 24
Finished Jul 27 06:27:50 PM PDT 24
Peak memory 200072 kb
Host smart-4b5d0427-6a60-43ca-99ba-7e9e52986b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708258076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3708258076
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4270645096
Short name T585
Test name
Test status
Simulation time 199119461399 ps
CPU time 202.29 seconds
Started Jul 27 06:27:17 PM PDT 24
Finished Jul 27 06:30:39 PM PDT 24
Peak memory 200112 kb
Host smart-93b6f88a-71b8-4560-a17e-af21a4c869b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270645096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4270645096
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2338920064
Short name T480
Test name
Test status
Simulation time 10422786035 ps
CPU time 4.03 seconds
Started Jul 27 06:27:16 PM PDT 24
Finished Jul 27 06:27:20 PM PDT 24
Peak memory 199816 kb
Host smart-dda3dc55-5564-4a02-bd26-e70b16cb8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338920064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2338920064
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.4221211149
Short name T979
Test name
Test status
Simulation time 100057542281 ps
CPU time 86.43 seconds
Started Jul 27 06:27:18 PM PDT 24
Finished Jul 27 06:28:44 PM PDT 24
Peak memory 199072 kb
Host smart-13e23644-445a-4c14-af3e-11f9bc449913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221211149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4221211149
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1453794168
Short name T763
Test name
Test status
Simulation time 16286991024 ps
CPU time 222.8 seconds
Started Jul 27 06:27:15 PM PDT 24
Finished Jul 27 06:30:59 PM PDT 24
Peak memory 200200 kb
Host smart-57e31cb2-0f85-4e40-8fa1-6f5a01f40318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453794168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1453794168
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2673948812
Short name T559
Test name
Test status
Simulation time 3598557743 ps
CPU time 12.35 seconds
Started Jul 27 06:27:15 PM PDT 24
Finished Jul 27 06:27:27 PM PDT 24
Peak memory 198696 kb
Host smart-e26166d9-58d3-4377-b820-7f2df5f00921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673948812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2673948812
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2340151803
Short name T1116
Test name
Test status
Simulation time 125380217997 ps
CPU time 48.47 seconds
Started Jul 27 06:27:17 PM PDT 24
Finished Jul 27 06:28:05 PM PDT 24
Peak memory 200260 kb
Host smart-7d3b91b9-c48a-443c-963f-86a1685e68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340151803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2340151803
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.656992264
Short name T380
Test name
Test status
Simulation time 3661470319 ps
CPU time 1.77 seconds
Started Jul 27 06:27:19 PM PDT 24
Finished Jul 27 06:27:20 PM PDT 24
Peak memory 196472 kb
Host smart-0438761f-1d19-42da-8b06-7cc15ace6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656992264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.656992264
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.929534759
Short name T417
Test name
Test status
Simulation time 764543394 ps
CPU time 1 seconds
Started Jul 27 06:27:06 PM PDT 24
Finished Jul 27 06:27:08 PM PDT 24
Peak memory 199820 kb
Host smart-a84802e1-54d0-4aff-82e3-81871d48301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929534759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.929534759
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2281376977
Short name T781
Test name
Test status
Simulation time 148253239346 ps
CPU time 301.27 seconds
Started Jul 27 06:27:16 PM PDT 24
Finished Jul 27 06:32:18 PM PDT 24
Peak memory 200280 kb
Host smart-65410e82-379d-4ac6-9bd7-d8208fe29ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281376977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2281376977
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3515567773
Short name T94
Test name
Test status
Simulation time 63435193577 ps
CPU time 153.28 seconds
Started Jul 27 06:27:14 PM PDT 24
Finished Jul 27 06:29:47 PM PDT 24
Peak memory 208568 kb
Host smart-cec36bae-6a52-4316-83ba-b35928c19439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515567773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3515567773
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1441421074
Short name T1034
Test name
Test status
Simulation time 1228983735 ps
CPU time 2.1 seconds
Started Jul 27 06:27:16 PM PDT 24
Finished Jul 27 06:27:18 PM PDT 24
Peak memory 198720 kb
Host smart-a4da58eb-7c5e-4dd3-a0da-1298012bde53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441421074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1441421074
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1561022762
Short name T555
Test name
Test status
Simulation time 38726713887 ps
CPU time 10.81 seconds
Started Jul 27 06:27:12 PM PDT 24
Finished Jul 27 06:27:23 PM PDT 24
Peak memory 200140 kb
Host smart-6f3034ba-9deb-4482-80a4-1dd97acd6a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561022762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1561022762
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.184434900
Short name T1073
Test name
Test status
Simulation time 23225106 ps
CPU time 0.58 seconds
Started Jul 27 06:27:24 PM PDT 24
Finished Jul 27 06:27:25 PM PDT 24
Peak memory 195904 kb
Host smart-75b768b0-318a-4934-ab1e-714fe6c05163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184434900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.184434900
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1370229001
Short name T569
Test name
Test status
Simulation time 241214826738 ps
CPU time 541.64 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:36:27 PM PDT 24
Peak memory 200076 kb
Host smart-f8b7a2d1-b8d4-4197-9017-7965448d8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370229001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1370229001
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2734795836
Short name T308
Test name
Test status
Simulation time 101164745462 ps
CPU time 214.2 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:31:00 PM PDT 24
Peak memory 200308 kb
Host smart-b3f71bef-e70c-4e68-b8d2-9a7b01bc1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734795836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2734795836
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.3517508220
Short name T976
Test name
Test status
Simulation time 232113406953 ps
CPU time 141.73 seconds
Started Jul 27 06:27:30 PM PDT 24
Finished Jul 27 06:29:52 PM PDT 24
Peak memory 198332 kb
Host smart-0272e579-80de-4634-b1a8-3ff04291fd75
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517508220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3517508220
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_loopback.3997370938
Short name T505
Test name
Test status
Simulation time 2977446960 ps
CPU time 5.4 seconds
Started Jul 27 06:27:27 PM PDT 24
Finished Jul 27 06:27:32 PM PDT 24
Peak memory 197624 kb
Host smart-410087f0-6a14-4401-a403-d9ca183b2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997370938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3997370938
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3222211619
Short name T289
Test name
Test status
Simulation time 43425854097 ps
CPU time 40.39 seconds
Started Jul 27 06:27:27 PM PDT 24
Finished Jul 27 06:28:08 PM PDT 24
Peak memory 200268 kb
Host smart-f4a08677-e417-4558-a922-0f893bf7fa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222211619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3222211619
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2099223028
Short name T296
Test name
Test status
Simulation time 10081837364 ps
CPU time 481 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:35:27 PM PDT 24
Peak memory 200252 kb
Host smart-746b3b1e-8838-4c86-a421-71b7d402d91e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099223028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2099223028
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2819806046
Short name T801
Test name
Test status
Simulation time 6570221183 ps
CPU time 15.59 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:27:42 PM PDT 24
Peak memory 199648 kb
Host smart-62212098-79f0-474b-ba67-26c0dff2298b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819806046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2819806046
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2747339588
Short name T31
Test name
Test status
Simulation time 85361147603 ps
CPU time 87.47 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:28:54 PM PDT 24
Peak memory 200120 kb
Host smart-6e1d5fc4-f0f4-4401-9422-65ee59830186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747339588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2747339588
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.674374157
Short name T372
Test name
Test status
Simulation time 504264877 ps
CPU time 1.39 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:27:27 PM PDT 24
Peak memory 195740 kb
Host smart-af9de5dc-af0e-4b7d-a0ec-b61005fee1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674374157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.674374157
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.685124873
Short name T932
Test name
Test status
Simulation time 953038337 ps
CPU time 1.93 seconds
Started Jul 27 06:27:15 PM PDT 24
Finished Jul 27 06:27:17 PM PDT 24
Peak memory 199604 kb
Host smart-14da9837-e32f-445f-b4c6-5d67d6ae0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685124873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.685124873
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1436343230
Short name T1068
Test name
Test status
Simulation time 258497996538 ps
CPU time 906.39 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:42:33 PM PDT 24
Peak memory 200248 kb
Host smart-e02c92fa-2340-4ef8-8666-d6c68fdac9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436343230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1436343230
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3441547935
Short name T433
Test name
Test status
Simulation time 98812345329 ps
CPU time 922.95 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:42:49 PM PDT 24
Peak memory 225108 kb
Host smart-72e62cd7-3e54-4666-9cb0-ed8070b5d4c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441547935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3441547935
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2132150876
Short name T543
Test name
Test status
Simulation time 433900721 ps
CPU time 1.9 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:27:28 PM PDT 24
Peak memory 199416 kb
Host smart-4923af66-6671-4bbc-a360-8943f08ede33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132150876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2132150876
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2164489165
Short name T866
Test name
Test status
Simulation time 57704748544 ps
CPU time 96.69 seconds
Started Jul 27 06:27:15 PM PDT 24
Finished Jul 27 06:28:52 PM PDT 24
Peak memory 200192 kb
Host smart-e98c0bf9-13a6-4470-9673-44f6d01d6c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164489165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2164489165
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.113594846
Short name T342
Test name
Test status
Simulation time 40068815 ps
CPU time 0.56 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:27:38 PM PDT 24
Peak memory 195580 kb
Host smart-e3c67622-bb27-447b-9f41-13d4a4fe5ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113594846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.113594846
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4112103651
Short name T456
Test name
Test status
Simulation time 30440746785 ps
CPU time 46 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:28:11 PM PDT 24
Peak memory 200156 kb
Host smart-2c066ea4-bdb5-4e8c-a1cc-fbd959a96a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112103651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4112103651
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3099966733
Short name T449
Test name
Test status
Simulation time 27312266574 ps
CPU time 39.91 seconds
Started Jul 27 06:27:28 PM PDT 24
Finished Jul 27 06:28:08 PM PDT 24
Peak memory 200216 kb
Host smart-d8b76f63-ae0e-4a67-86f4-76f6401a4ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099966733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3099966733
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1903108741
Short name T1063
Test name
Test status
Simulation time 113334718387 ps
CPU time 159.48 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:30:05 PM PDT 24
Peak memory 200216 kb
Host smart-e350d17f-ecac-48f9-a390-31cf6aeb88e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903108741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1903108741
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.4073471192
Short name T669
Test name
Test status
Simulation time 41200221544 ps
CPU time 47.53 seconds
Started Jul 27 06:27:27 PM PDT 24
Finished Jul 27 06:28:15 PM PDT 24
Peak memory 200220 kb
Host smart-6c5dd051-ed86-4be1-92d2-2c3cf62744f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073471192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.4073471192
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.524426146
Short name T829
Test name
Test status
Simulation time 100021861135 ps
CPU time 304.14 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:32:41 PM PDT 24
Peak memory 200176 kb
Host smart-da6c6b6b-e20d-47d5-9542-95ed173d1620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524426146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.524426146
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.726349804
Short name T965
Test name
Test status
Simulation time 8398767266 ps
CPU time 12.81 seconds
Started Jul 27 06:27:38 PM PDT 24
Finished Jul 27 06:27:51 PM PDT 24
Peak memory 199984 kb
Host smart-885f5553-dfde-4c83-b54b-0eae65192fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726349804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.726349804
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1012980825
Short name T855
Test name
Test status
Simulation time 82835151739 ps
CPU time 53.15 seconds
Started Jul 27 06:27:36 PM PDT 24
Finished Jul 27 06:28:29 PM PDT 24
Peak memory 200340 kb
Host smart-2f873452-c361-409c-856b-7bee35045ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012980825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1012980825
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3417485401
Short name T921
Test name
Test status
Simulation time 12414391876 ps
CPU time 174.36 seconds
Started Jul 27 06:27:38 PM PDT 24
Finished Jul 27 06:30:32 PM PDT 24
Peak memory 200232 kb
Host smart-f72de390-ecdb-40b0-9e42-a7f69c88d845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417485401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3417485401
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.517648799
Short name T990
Test name
Test status
Simulation time 1784366989 ps
CPU time 3.07 seconds
Started Jul 27 06:27:26 PM PDT 24
Finished Jul 27 06:27:29 PM PDT 24
Peak memory 198848 kb
Host smart-187b6bfd-b677-43f2-9693-ac2d467c8eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517648799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.517648799
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2905791330
Short name T124
Test name
Test status
Simulation time 84599571790 ps
CPU time 60.81 seconds
Started Jul 27 06:27:36 PM PDT 24
Finished Jul 27 06:28:37 PM PDT 24
Peak memory 200132 kb
Host smart-e7b85bd5-a48e-43c4-a556-686f3d71f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905791330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2905791330
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.162125821
Short name T945
Test name
Test status
Simulation time 2176913231 ps
CPU time 4.1 seconds
Started Jul 27 06:27:38 PM PDT 24
Finished Jul 27 06:27:42 PM PDT 24
Peak memory 195960 kb
Host smart-5f9d2488-368f-4761-b44c-c9b2fe1a007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162125821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.162125821
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3013606787
Short name T762
Test name
Test status
Simulation time 303953783 ps
CPU time 1.32 seconds
Started Jul 27 06:27:27 PM PDT 24
Finished Jul 27 06:27:28 PM PDT 24
Peak memory 199152 kb
Host smart-8a374996-748e-44ee-bb08-d0722231f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013606787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3013606787
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2681041655
Short name T573
Test name
Test status
Simulation time 273414544528 ps
CPU time 1805.39 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:57:42 PM PDT 24
Peak memory 208528 kb
Host smart-d5306f55-753c-4339-a69c-d9aaf4c76089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681041655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2681041655
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3433958358
Short name T88
Test name
Test status
Simulation time 68114274555 ps
CPU time 629.65 seconds
Started Jul 27 06:27:38 PM PDT 24
Finished Jul 27 06:38:08 PM PDT 24
Peak memory 225064 kb
Host smart-fd553043-7db6-4314-b421-96c1418322bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433958358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3433958358
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2020138908
Short name T774
Test name
Test status
Simulation time 1134878644 ps
CPU time 2.08 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:27:39 PM PDT 24
Peak memory 198524 kb
Host smart-fb66ce85-f2ba-4a93-b902-55ae5183c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020138908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2020138908
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3373978685
Short name T682
Test name
Test status
Simulation time 32636372237 ps
CPU time 26.41 seconds
Started Jul 27 06:27:25 PM PDT 24
Finished Jul 27 06:27:52 PM PDT 24
Peak memory 200260 kb
Host smart-d8ccbedf-112c-4218-ab4d-4b331ecdd672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373978685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3373978685
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3699859347
Short name T602
Test name
Test status
Simulation time 16460775 ps
CPU time 0.57 seconds
Started Jul 27 06:27:52 PM PDT 24
Finished Jul 27 06:27:53 PM PDT 24
Peak memory 195888 kb
Host smart-00217f0f-cc7f-467a-ab79-b9439cbf867d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699859347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3699859347
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3575543448
Short name T504
Test name
Test status
Simulation time 53417940467 ps
CPU time 26.08 seconds
Started Jul 27 06:27:39 PM PDT 24
Finished Jul 27 06:28:05 PM PDT 24
Peak memory 200212 kb
Host smart-bed226f8-116f-4c7a-8b01-3f2b4d0253cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575543448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3575543448
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3824790977
Short name T757
Test name
Test status
Simulation time 28908732560 ps
CPU time 22.69 seconds
Started Jul 27 06:27:36 PM PDT 24
Finished Jul 27 06:27:59 PM PDT 24
Peak memory 200108 kb
Host smart-2bd8bba0-ff57-4d85-8c03-7affb5438e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824790977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3824790977
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1089430844
Short name T715
Test name
Test status
Simulation time 146533856980 ps
CPU time 110.53 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:29:27 PM PDT 24
Peak memory 200140 kb
Host smart-c08cb3e9-ed52-4ac4-a0fb-4b4bbcbd53a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089430844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1089430844
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.400517428
Short name T642
Test name
Test status
Simulation time 71200362996 ps
CPU time 58.73 seconds
Started Jul 27 06:27:50 PM PDT 24
Finished Jul 27 06:28:49 PM PDT 24
Peak memory 200152 kb
Host smart-bf5d23af-ff10-43c9-8f25-55adb3c64565
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400517428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.400517428
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2656602835
Short name T988
Test name
Test status
Simulation time 104015310102 ps
CPU time 235.93 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:31:45 PM PDT 24
Peak memory 200184 kb
Host smart-ec578467-e117-4fcb-a5ba-090353c5b67a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656602835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2656602835
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.166233783
Short name T574
Test name
Test status
Simulation time 11120389764 ps
CPU time 5.13 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:27:54 PM PDT 24
Peak memory 198756 kb
Host smart-704d285a-6cc7-4bc9-b854-56966e0a8685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166233783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.166233783
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2739765709
Short name T1031
Test name
Test status
Simulation time 63272638751 ps
CPU time 107.38 seconds
Started Jul 27 06:27:50 PM PDT 24
Finished Jul 27 06:29:37 PM PDT 24
Peak memory 200560 kb
Host smart-ae51f6f1-17df-4c0b-9d60-19c5d6f88fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739765709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2739765709
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3242649970
Short name T86
Test name
Test status
Simulation time 15466176518 ps
CPU time 480.98 seconds
Started Jul 27 06:27:48 PM PDT 24
Finished Jul 27 06:35:49 PM PDT 24
Peak memory 200176 kb
Host smart-648ed18e-1e5d-4867-b904-addae56bd09e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242649970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3242649970
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3099876304
Short name T635
Test name
Test status
Simulation time 2617486641 ps
CPU time 12.01 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:27:49 PM PDT 24
Peak memory 198452 kb
Host smart-3cf5ebcd-be95-4b62-85b8-e37d41aaf29d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099876304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3099876304
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1549083896
Short name T684
Test name
Test status
Simulation time 196320231147 ps
CPU time 87.69 seconds
Started Jul 27 06:27:48 PM PDT 24
Finished Jul 27 06:29:16 PM PDT 24
Peak memory 200156 kb
Host smart-5864b669-b0ee-449d-96d3-4f1a09c65ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549083896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1549083896
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3143574145
Short name T966
Test name
Test status
Simulation time 6048772848 ps
CPU time 4.62 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:27:54 PM PDT 24
Peak memory 196524 kb
Host smart-d1acf454-17b7-4dee-8694-ed07ba3b58d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143574145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3143574145
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4181521663
Short name T411
Test name
Test status
Simulation time 11621155292 ps
CPU time 44.95 seconds
Started Jul 27 06:27:35 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 199848 kb
Host smart-72199777-60d2-4934-8e35-c0ba248846d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181521663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4181521663
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2389291349
Short name T790
Test name
Test status
Simulation time 127834256698 ps
CPU time 218.9 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:31:28 PM PDT 24
Peak memory 200368 kb
Host smart-fc7852e1-58a3-41c9-bb57-7914857e59ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389291349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2389291349
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3080933656
Short name T1036
Test name
Test status
Simulation time 154303211875 ps
CPU time 1227.69 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:48:17 PM PDT 24
Peak memory 217076 kb
Host smart-8765b5c7-649e-4aa7-9a08-f8c455b9e185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080933656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3080933656
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2932930009
Short name T402
Test name
Test status
Simulation time 1414241628 ps
CPU time 1.62 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:27:50 PM PDT 24
Peak memory 198872 kb
Host smart-8492b3ce-ce98-4fe6-9505-458d527e7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932930009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2932930009
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.483521669
Short name T756
Test name
Test status
Simulation time 49455267198 ps
CPU time 6.65 seconds
Started Jul 27 06:27:37 PM PDT 24
Finished Jul 27 06:27:44 PM PDT 24
Peak memory 199992 kb
Host smart-bd66533d-4b07-411d-86c3-39c94ecf823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483521669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.483521669
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.16280663
Short name T362
Test name
Test status
Simulation time 75083181 ps
CPU time 0.56 seconds
Started Jul 27 06:27:58 PM PDT 24
Finished Jul 27 06:27:58 PM PDT 24
Peak memory 195852 kb
Host smart-e431f700-3715-47b0-a90f-2fe8599ad282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.16280663
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2011516024
Short name T135
Test name
Test status
Simulation time 139067109671 ps
CPU time 66.63 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:28:56 PM PDT 24
Peak memory 200256 kb
Host smart-e94e163e-b03e-485a-abab-c0a70173765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011516024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2011516024
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1467085328
Short name T1090
Test name
Test status
Simulation time 77515209249 ps
CPU time 58.75 seconds
Started Jul 27 06:27:51 PM PDT 24
Finished Jul 27 06:28:50 PM PDT 24
Peak memory 200204 kb
Host smart-887d1388-9b95-4ac6-a5a7-756c75d5401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467085328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1467085328
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2653420726
Short name T234
Test name
Test status
Simulation time 18045263805 ps
CPU time 31.72 seconds
Started Jul 27 06:27:48 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 200252 kb
Host smart-da5f9b1f-f8bc-4044-81ec-7d0d7423a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653420726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2653420726
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3304493619
Short name T16
Test name
Test status
Simulation time 273360936279 ps
CPU time 199.91 seconds
Started Jul 27 06:27:58 PM PDT 24
Finished Jul 27 06:31:18 PM PDT 24
Peak memory 198816 kb
Host smart-c9b5419b-35e2-421b-af2b-20091d41bd3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304493619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3304493619
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1290267511
Short name T350
Test name
Test status
Simulation time 260730878898 ps
CPU time 328.59 seconds
Started Jul 27 06:28:03 PM PDT 24
Finished Jul 27 06:33:32 PM PDT 24
Peak memory 200252 kb
Host smart-ed1a30ed-a0d6-4348-8741-665dd3dfc0fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290267511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1290267511
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1206943741
Short name T909
Test name
Test status
Simulation time 4808897570 ps
CPU time 3.8 seconds
Started Jul 27 06:28:01 PM PDT 24
Finished Jul 27 06:28:05 PM PDT 24
Peak memory 199488 kb
Host smart-78db0677-12d8-432c-af60-1f47bf1d940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206943741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1206943741
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2656417731
Short name T276
Test name
Test status
Simulation time 102644899423 ps
CPU time 193.85 seconds
Started Jul 27 06:28:02 PM PDT 24
Finished Jul 27 06:31:16 PM PDT 24
Peak memory 208508 kb
Host smart-cda60f89-94ca-4214-9133-6f6e81da7af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656417731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2656417731
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2061832647
Short name T639
Test name
Test status
Simulation time 10704604318 ps
CPU time 50.17 seconds
Started Jul 27 06:27:59 PM PDT 24
Finished Jul 27 06:28:49 PM PDT 24
Peak memory 200136 kb
Host smart-6dae4b99-0f8e-4cf4-b2c4-9c08ab99f792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061832647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2061832647
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3794133851
Short name T1152
Test name
Test status
Simulation time 6669535997 ps
CPU time 31.25 seconds
Started Jul 27 06:27:49 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 198388 kb
Host smart-60705824-0731-4ea4-8997-89aadda75cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794133851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3794133851
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3130095581
Short name T897
Test name
Test status
Simulation time 106423740180 ps
CPU time 78.29 seconds
Started Jul 27 06:27:57 PM PDT 24
Finished Jul 27 06:29:16 PM PDT 24
Peak memory 200172 kb
Host smart-d60d218c-1d85-4703-b000-c2b2dc0e91c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130095581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3130095581
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.78141255
Short name T633
Test name
Test status
Simulation time 3056624274 ps
CPU time 2.06 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:28:02 PM PDT 24
Peak memory 196144 kb
Host smart-fbfd79d0-51f7-480a-b6ce-78c3d891c622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78141255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.78141255
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1686660175
Short name T295
Test name
Test status
Simulation time 498875611 ps
CPU time 3.09 seconds
Started Jul 27 06:27:52 PM PDT 24
Finished Jul 27 06:27:55 PM PDT 24
Peak memory 198640 kb
Host smart-57ff6506-f4f2-46b6-8d93-9ab73660284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686660175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1686660175
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.303234931
Short name T339
Test name
Test status
Simulation time 405130969172 ps
CPU time 520.62 seconds
Started Jul 27 06:27:59 PM PDT 24
Finished Jul 27 06:36:40 PM PDT 24
Peak memory 200216 kb
Host smart-dbd4cea8-374b-47a4-81aa-3a5eacd5a54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303234931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.303234931
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2886635261
Short name T643
Test name
Test status
Simulation time 44513640736 ps
CPU time 711.78 seconds
Started Jul 27 06:27:58 PM PDT 24
Finished Jul 27 06:39:49 PM PDT 24
Peak memory 216696 kb
Host smart-f1b82f2c-fa7a-40cd-99d3-0066b7c33f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886635261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2886635261
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.907608021
Short name T459
Test name
Test status
Simulation time 354600848 ps
CPU time 1.33 seconds
Started Jul 27 06:28:01 PM PDT 24
Finished Jul 27 06:28:02 PM PDT 24
Peak memory 197276 kb
Host smart-34f9b819-3094-4f66-863b-f8d0d1e7f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907608021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.907608021
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.648856548
Short name T1174
Test name
Test status
Simulation time 95064749678 ps
CPU time 49.6 seconds
Started Jul 27 06:27:51 PM PDT 24
Finished Jul 27 06:28:41 PM PDT 24
Peak memory 200204 kb
Host smart-99b7834e-a9e6-42be-b887-99be9149dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648856548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.648856548
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3552419414
Short name T17
Test name
Test status
Simulation time 23251058 ps
CPU time 0.57 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:28:10 PM PDT 24
Peak memory 195880 kb
Host smart-43e44b15-9a92-4e57-b5b8-c811aa31ddc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552419414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3552419414
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3035141213
Short name T969
Test name
Test status
Simulation time 124872523816 ps
CPU time 154.07 seconds
Started Jul 27 06:28:02 PM PDT 24
Finished Jul 27 06:30:36 PM PDT 24
Peak memory 200252 kb
Host smart-6f703ec0-3d49-412c-92dd-b2c7d993d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035141213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3035141213
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3341947189
Short name T903
Test name
Test status
Simulation time 121859721168 ps
CPU time 44.65 seconds
Started Jul 27 06:27:59 PM PDT 24
Finished Jul 27 06:28:44 PM PDT 24
Peak memory 200240 kb
Host smart-1e5e1955-9a77-4f62-8f28-b51303778713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341947189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3341947189
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1748400805
Short name T220
Test name
Test status
Simulation time 100316390894 ps
CPU time 51.19 seconds
Started Jul 27 06:27:58 PM PDT 24
Finished Jul 27 06:28:49 PM PDT 24
Peak memory 200228 kb
Host smart-1ca0c570-78bd-40d7-846c-62bd61088daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748400805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1748400805
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2257920528
Short name T1074
Test name
Test status
Simulation time 9398369716 ps
CPU time 10.11 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:28:10 PM PDT 24
Peak memory 200244 kb
Host smart-ef961d95-ec1d-4a0e-965c-f3ba2c64b355
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257920528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2257920528
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2498459598
Short name T521
Test name
Test status
Simulation time 92074336426 ps
CPU time 423.8 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:35:13 PM PDT 24
Peak memory 200176 kb
Host smart-c1d56aec-54ab-44a1-878a-a7fcc7963c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498459598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2498459598
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2521984767
Short name T904
Test name
Test status
Simulation time 8338887976 ps
CPU time 10.31 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:28:11 PM PDT 24
Peak memory 199224 kb
Host smart-d0785bd2-25e4-4a21-a042-c8a97d72bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521984767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2521984767
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.466264211
Short name T750
Test name
Test status
Simulation time 72830071306 ps
CPU time 117.39 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:29:58 PM PDT 24
Peak memory 200260 kb
Host smart-84f36131-d9b2-41a9-80d8-222ea2cdbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466264211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.466264211
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2695634045
Short name T450
Test name
Test status
Simulation time 16531894002 ps
CPU time 121.52 seconds
Started Jul 27 06:28:03 PM PDT 24
Finished Jul 27 06:30:04 PM PDT 24
Peak memory 200256 kb
Host smart-ffe7f8d2-1e70-471d-b00a-ac0f4551fe5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695634045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2695634045
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3411053134
Short name T1178
Test name
Test status
Simulation time 4042641711 ps
CPU time 5.52 seconds
Started Jul 27 06:28:02 PM PDT 24
Finished Jul 27 06:28:08 PM PDT 24
Peak memory 198784 kb
Host smart-c82a86c1-3539-457c-ba3e-9b7f4f4d475d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411053134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3411053134
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2100731894
Short name T1154
Test name
Test status
Simulation time 92789506018 ps
CPU time 171.67 seconds
Started Jul 27 06:27:57 PM PDT 24
Finished Jul 27 06:30:49 PM PDT 24
Peak memory 200200 kb
Host smart-b450b65c-aff5-49f0-af89-359b143e49c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100731894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2100731894
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1578363668
Short name T314
Test name
Test status
Simulation time 6287847013 ps
CPU time 1.13 seconds
Started Jul 27 06:27:59 PM PDT 24
Finished Jul 27 06:28:00 PM PDT 24
Peak memory 196728 kb
Host smart-c7c4f87a-05cd-4452-90b7-39af43502e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578363668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1578363668
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4242648829
Short name T374
Test name
Test status
Simulation time 689428582 ps
CPU time 3.84 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:28:04 PM PDT 24
Peak memory 198592 kb
Host smart-b886abfd-1f78-44bd-bcf3-2d7f5fe75aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242648829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4242648829
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2006570401
Short name T101
Test name
Test status
Simulation time 154391054800 ps
CPU time 56.52 seconds
Started Jul 27 06:28:08 PM PDT 24
Finished Jul 27 06:29:04 PM PDT 24
Peak memory 200208 kb
Host smart-4d0824ae-d044-4c22-8e49-956219d468d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006570401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2006570401
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3832844033
Short name T1002
Test name
Test status
Simulation time 34570493674 ps
CPU time 271.33 seconds
Started Jul 27 06:28:08 PM PDT 24
Finished Jul 27 06:32:39 PM PDT 24
Peak memory 212680 kb
Host smart-5b286e21-6426-4448-9238-bf2342b411a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832844033 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3832844033
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.935277870
Short name T894
Test name
Test status
Simulation time 481374701 ps
CPU time 0.93 seconds
Started Jul 27 06:27:57 PM PDT 24
Finished Jul 27 06:27:58 PM PDT 24
Peak memory 197484 kb
Host smart-eab2d612-a226-41c7-a8b9-5edbdeb48310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935277870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.935277870
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2919532920
Short name T448
Test name
Test status
Simulation time 14941309104 ps
CPU time 21.48 seconds
Started Jul 27 06:28:00 PM PDT 24
Finished Jul 27 06:28:22 PM PDT 24
Peak memory 200052 kb
Host smart-2f697d23-54c0-4c71-aae9-cfaf59d9134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919532920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2919532920
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2858995567
Short name T997
Test name
Test status
Simulation time 38262120 ps
CPU time 0.54 seconds
Started Jul 27 06:28:17 PM PDT 24
Finished Jul 27 06:28:18 PM PDT 24
Peak memory 195816 kb
Host smart-e5408cea-5ae8-4e76-8f3c-32490b66daaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858995567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2858995567
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.215226430
Short name T950
Test name
Test status
Simulation time 203947646877 ps
CPU time 116.92 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:30:06 PM PDT 24
Peak memory 200180 kb
Host smart-b2432e47-5c76-4ad4-97e9-6bd2541cda54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215226430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.215226430
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.731403808
Short name T694
Test name
Test status
Simulation time 34141460614 ps
CPU time 14.55 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:28:24 PM PDT 24
Peak memory 200140 kb
Host smart-a7080a6c-3717-45bb-9188-19049076376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731403808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.731403808
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2203489332
Short name T893
Test name
Test status
Simulation time 11649837917 ps
CPU time 17.3 seconds
Started Jul 27 06:28:08 PM PDT 24
Finished Jul 27 06:28:26 PM PDT 24
Peak memory 200164 kb
Host smart-1e355d8b-48ff-4331-b184-00ab50afa374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203489332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2203489332
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.987810922
Short name T1089
Test name
Test status
Simulation time 31507602181 ps
CPU time 12.91 seconds
Started Jul 27 06:28:11 PM PDT 24
Finished Jul 27 06:28:24 PM PDT 24
Peak memory 200124 kb
Host smart-8c5ff2d1-9039-4888-a574-509f645819de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987810922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.987810922
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.665697373
Short name T477
Test name
Test status
Simulation time 213563497533 ps
CPU time 385.78 seconds
Started Jul 27 06:28:17 PM PDT 24
Finished Jul 27 06:34:43 PM PDT 24
Peak memory 200164 kb
Host smart-2769ff64-246d-4c50-bf71-903a248b8670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665697373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.665697373
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4258463807
Short name T514
Test name
Test status
Simulation time 9085584545 ps
CPU time 16.05 seconds
Started Jul 27 06:28:17 PM PDT 24
Finished Jul 27 06:28:33 PM PDT 24
Peak memory 199536 kb
Host smart-79445cb3-5e9b-46fc-8535-5ea04125d445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258463807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4258463807
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1170813698
Short name T1065
Test name
Test status
Simulation time 59202178861 ps
CPU time 95.38 seconds
Started Jul 27 06:28:12 PM PDT 24
Finished Jul 27 06:29:48 PM PDT 24
Peak memory 199216 kb
Host smart-93dd12b1-3d25-419d-b232-19308904ea06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170813698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1170813698
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.386306068
Short name T857
Test name
Test status
Simulation time 11428921370 ps
CPU time 552.44 seconds
Started Jul 27 06:28:17 PM PDT 24
Finished Jul 27 06:37:29 PM PDT 24
Peak memory 200244 kb
Host smart-20e9ee3d-7c91-419b-b81c-5043271f095d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386306068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.386306068
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1291272815
Short name T611
Test name
Test status
Simulation time 5517897645 ps
CPU time 47.12 seconds
Started Jul 27 06:28:08 PM PDT 24
Finished Jul 27 06:28:55 PM PDT 24
Peak memory 198468 kb
Host smart-e4e2d345-0f62-4bba-9d61-22ec1b9a3d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291272815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1291272815
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3562560564
Short name T803
Test name
Test status
Simulation time 32849170925 ps
CPU time 15.63 seconds
Started Jul 27 06:28:16 PM PDT 24
Finished Jul 27 06:28:32 PM PDT 24
Peak memory 200184 kb
Host smart-523e0ce4-4a44-4fee-b029-ee5e2d9b0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562560564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3562560564
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3225991851
Short name T951
Test name
Test status
Simulation time 5627738242 ps
CPU time 2.58 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:28:12 PM PDT 24
Peak memory 196712 kb
Host smart-ed1e258e-29a4-45d1-9e63-6ebc9e4f4c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225991851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3225991851
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3988985521
Short name T1030
Test name
Test status
Simulation time 927363202 ps
CPU time 3.48 seconds
Started Jul 27 06:28:09 PM PDT 24
Finished Jul 27 06:28:13 PM PDT 24
Peak memory 199080 kb
Host smart-65380973-c339-4776-b633-36ecefb26138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988985521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3988985521
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1240010352
Short name T861
Test name
Test status
Simulation time 71504934903 ps
CPU time 125.44 seconds
Started Jul 27 06:28:16 PM PDT 24
Finished Jul 27 06:30:21 PM PDT 24
Peak memory 208488 kb
Host smart-c9fe9c36-da33-4766-bbb9-75d8148289ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240010352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1240010352
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1055720888
Short name T1050
Test name
Test status
Simulation time 207807370765 ps
CPU time 552.71 seconds
Started Jul 27 06:28:18 PM PDT 24
Finished Jul 27 06:37:31 PM PDT 24
Peak memory 228484 kb
Host smart-7a0477ff-791e-4cd6-b49f-1248305cf255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055720888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1055720888
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1111682007
Short name T692
Test name
Test status
Simulation time 2788986344 ps
CPU time 2.06 seconds
Started Jul 27 06:28:17 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 198680 kb
Host smart-76374e15-a8d1-4af5-9124-44fa3eec7ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111682007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1111682007
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.354923344
Short name T824
Test name
Test status
Simulation time 30082741984 ps
CPU time 62.04 seconds
Started Jul 27 06:28:11 PM PDT 24
Finished Jul 27 06:29:13 PM PDT 24
Peak memory 200196 kb
Host smart-61f4839d-2833-4493-8b95-dc49bd3412e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354923344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.354923344
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2294075642
Short name T672
Test name
Test status
Simulation time 18703427 ps
CPU time 0.56 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:28:39 PM PDT 24
Peak memory 195620 kb
Host smart-c8ca4317-2857-40b5-920d-1902328691b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294075642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2294075642
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1916227671
Short name T1076
Test name
Test status
Simulation time 40862814276 ps
CPU time 14.9 seconds
Started Jul 27 06:28:28 PM PDT 24
Finished Jul 27 06:28:43 PM PDT 24
Peak memory 200192 kb
Host smart-3837bf6d-f913-41f4-a787-ccc85e1f6f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916227671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1916227671
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.4037197367
Short name T138
Test name
Test status
Simulation time 47346174280 ps
CPU time 14.56 seconds
Started Jul 27 06:28:27 PM PDT 24
Finished Jul 27 06:28:41 PM PDT 24
Peak memory 200212 kb
Host smart-9da3bb9a-5798-4778-83c3-136820538c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037197367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4037197367
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2004990049
Short name T224
Test name
Test status
Simulation time 47416743056 ps
CPU time 72.08 seconds
Started Jul 27 06:28:29 PM PDT 24
Finished Jul 27 06:29:41 PM PDT 24
Peak memory 200168 kb
Host smart-7ff481f6-8fba-4d13-9c74-3288079e1e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004990049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2004990049
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3454745469
Short name T1055
Test name
Test status
Simulation time 343990939330 ps
CPU time 122.57 seconds
Started Jul 27 06:28:28 PM PDT 24
Finished Jul 27 06:30:31 PM PDT 24
Peak memory 198344 kb
Host smart-b3916f0d-ea2f-4bc6-8178-f9e9ce6c31bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454745469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3454745469
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1574632292
Short name T735
Test name
Test status
Simulation time 202517752272 ps
CPU time 182.6 seconds
Started Jul 27 06:28:28 PM PDT 24
Finished Jul 27 06:31:31 PM PDT 24
Peak memory 200236 kb
Host smart-872c4d87-25c8-4040-aa50-e60fa27077ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574632292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1574632292
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2867833482
Short name T366
Test name
Test status
Simulation time 2677670154 ps
CPU time 3.98 seconds
Started Jul 27 06:28:33 PM PDT 24
Finished Jul 27 06:28:37 PM PDT 24
Peak memory 198736 kb
Host smart-e553c462-3a4f-494f-9d10-f401be25e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867833482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2867833482
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.376713114
Short name T978
Test name
Test status
Simulation time 37509311300 ps
CPU time 59.65 seconds
Started Jul 27 06:28:27 PM PDT 24
Finished Jul 27 06:29:27 PM PDT 24
Peak memory 200344 kb
Host smart-bf78e80d-10b1-4533-91fc-529889f134b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376713114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.376713114
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.887336617
Short name T281
Test name
Test status
Simulation time 24887188394 ps
CPU time 123.47 seconds
Started Jul 27 06:28:27 PM PDT 24
Finished Jul 27 06:30:31 PM PDT 24
Peak memory 200200 kb
Host smart-4e6585ed-9ceb-4a6d-827f-2c8992d1f205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887336617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.887336617
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3236937347
Short name T825
Test name
Test status
Simulation time 2234007892 ps
CPU time 5.53 seconds
Started Jul 27 06:28:28 PM PDT 24
Finished Jul 27 06:28:34 PM PDT 24
Peak memory 198908 kb
Host smart-859ace43-1d3f-429d-8eb7-5aa5afc7c2c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236937347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3236937347
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2854617868
Short name T589
Test name
Test status
Simulation time 77642256362 ps
CPU time 48.52 seconds
Started Jul 27 06:28:28 PM PDT 24
Finished Jul 27 06:29:17 PM PDT 24
Peak memory 200232 kb
Host smart-5c590d8b-8ca0-4e25-9e46-f9f460a8543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854617868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2854617868
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2998985556
Short name T1096
Test name
Test status
Simulation time 29016286024 ps
CPU time 18.79 seconds
Started Jul 27 06:28:27 PM PDT 24
Finished Jul 27 06:28:46 PM PDT 24
Peak memory 195980 kb
Host smart-eb7ad3bc-c60c-4873-bf90-8e18ec810c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998985556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2998985556
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4095041896
Short name T1177
Test name
Test status
Simulation time 320088411 ps
CPU time 0.95 seconds
Started Jul 27 06:28:18 PM PDT 24
Finished Jul 27 06:28:19 PM PDT 24
Peak memory 200124 kb
Host smart-6fce9f05-ac27-4955-b302-00f83afa7ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095041896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4095041896
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3954970572
Short name T377
Test name
Test status
Simulation time 100112317521 ps
CPU time 267.99 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:33:06 PM PDT 24
Peak memory 200172 kb
Host smart-43b3aa8d-50fc-441d-abc5-e46e2ddeabec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954970572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3954970572
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.760048728
Short name T368
Test name
Test status
Simulation time 2476602598 ps
CPU time 1.77 seconds
Started Jul 27 06:28:27 PM PDT 24
Finished Jul 27 06:28:29 PM PDT 24
Peak memory 199096 kb
Host smart-e53f1e4a-4a34-4735-97d4-57f1fd98641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760048728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.760048728
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2340233491
Short name T553
Test name
Test status
Simulation time 129313764457 ps
CPU time 31.24 seconds
Started Jul 27 06:28:16 PM PDT 24
Finished Jul 27 06:28:48 PM PDT 24
Peak memory 200184 kb
Host smart-0b536519-b435-4e78-9825-a392c8553b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340233491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2340233491
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1449952849
Short name T588
Test name
Test status
Simulation time 43260050 ps
CPU time 0.55 seconds
Started Jul 27 06:28:36 PM PDT 24
Finished Jul 27 06:28:37 PM PDT 24
Peak memory 195532 kb
Host smart-7738295a-f2e2-4560-9533-25aaeea40b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449952849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1449952849
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.531644590
Short name T632
Test name
Test status
Simulation time 63145039539 ps
CPU time 97.73 seconds
Started Jul 27 06:28:40 PM PDT 24
Finished Jul 27 06:30:18 PM PDT 24
Peak memory 200168 kb
Host smart-13492e4e-5b2a-4a5a-a652-54c8d9ed3d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531644590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.531644590
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.364061242
Short name T1167
Test name
Test status
Simulation time 60005121384 ps
CPU time 14.76 seconds
Started Jul 27 06:28:37 PM PDT 24
Finished Jul 27 06:28:52 PM PDT 24
Peak memory 200112 kb
Host smart-582bbb8d-0d4d-4176-b8de-781cefd6e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364061242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.364061242
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2567323987
Short name T970
Test name
Test status
Simulation time 111519837269 ps
CPU time 47.09 seconds
Started Jul 27 06:28:36 PM PDT 24
Finished Jul 27 06:29:24 PM PDT 24
Peak memory 200056 kb
Host smart-13d2a695-6c90-461d-ba05-1dedc04869cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567323987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2567323987
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2820052780
Short name T591
Test name
Test status
Simulation time 69857902256 ps
CPU time 19.05 seconds
Started Jul 27 06:28:36 PM PDT 24
Finished Jul 27 06:28:55 PM PDT 24
Peak memory 196868 kb
Host smart-b559fc40-2047-44c5-ac6f-3eb78729df25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820052780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2820052780
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.150999203
Short name T802
Test name
Test status
Simulation time 188295719352 ps
CPU time 498.14 seconds
Started Jul 27 06:28:41 PM PDT 24
Finished Jul 27 06:36:59 PM PDT 24
Peak memory 200156 kb
Host smart-2f191f21-9c5a-4fbc-88cc-0bb11cebc611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150999203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.150999203
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3275185539
Short name T484
Test name
Test status
Simulation time 13770705046 ps
CPU time 29.04 seconds
Started Jul 27 06:28:37 PM PDT 24
Finished Jul 27 06:29:06 PM PDT 24
Peak memory 199504 kb
Host smart-5e14f4e6-8428-41fd-a260-bc2ba1db1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275185539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3275185539
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.718808679
Short name T1054
Test name
Test status
Simulation time 103439992481 ps
CPU time 28.19 seconds
Started Jul 27 06:28:34 PM PDT 24
Finished Jul 27 06:29:03 PM PDT 24
Peak memory 200396 kb
Host smart-3b798970-788b-4bcb-9b05-99a3ab6d2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718808679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.718808679
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1384894568
Short name T410
Test name
Test status
Simulation time 13202490149 ps
CPU time 528.91 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:37:27 PM PDT 24
Peak memory 200020 kb
Host smart-f7102741-bbe2-48c7-8c2c-6a54ac214420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384894568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1384894568
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2302240828
Short name T1053
Test name
Test status
Simulation time 6400793737 ps
CPU time 12.46 seconds
Started Jul 27 06:28:40 PM PDT 24
Finished Jul 27 06:28:52 PM PDT 24
Peak memory 198376 kb
Host smart-0c709634-21b4-4754-bcea-438aaf542a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302240828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2302240828
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1035168871
Short name T168
Test name
Test status
Simulation time 52358423758 ps
CPU time 25.46 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:29:03 PM PDT 24
Peak memory 200016 kb
Host smart-da494e47-9f43-4d6e-bcbc-c3802be19f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035168871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1035168871
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3385611964
Short name T293
Test name
Test status
Simulation time 23851478470 ps
CPU time 8.7 seconds
Started Jul 27 06:28:37 PM PDT 24
Finished Jul 27 06:28:46 PM PDT 24
Peak memory 196340 kb
Host smart-451fd4bf-c7b3-43a2-a22b-41897e2ac09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385611964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3385611964
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3476302654
Short name T792
Test name
Test status
Simulation time 536755910 ps
CPU time 1.53 seconds
Started Jul 27 06:28:40 PM PDT 24
Finished Jul 27 06:28:42 PM PDT 24
Peak memory 200336 kb
Host smart-9679a299-5d7f-4ff1-b837-4aef111b1cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476302654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3476302654
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2871514256
Short name T840
Test name
Test status
Simulation time 198195780293 ps
CPU time 357.96 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:34:37 PM PDT 24
Peak memory 200184 kb
Host smart-6671604c-18d9-4424-bb72-c786d3f394ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871514256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2871514256
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3073193668
Short name T355
Test name
Test status
Simulation time 1897302408 ps
CPU time 1.84 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:28:40 PM PDT 24
Peak memory 198768 kb
Host smart-cdb7c0c6-b16d-41de-939a-431399f39ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073193668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3073193668
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4041954349
Short name T240
Test name
Test status
Simulation time 57275853233 ps
CPU time 58.17 seconds
Started Jul 27 06:28:38 PM PDT 24
Finished Jul 27 06:29:36 PM PDT 24
Peak memory 200160 kb
Host smart-964794c4-354b-44bf-b951-7a2a6ebf2a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041954349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4041954349
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1421642661
Short name T420
Test name
Test status
Simulation time 13358488 ps
CPU time 0.59 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:23:23 PM PDT 24
Peak memory 195044 kb
Host smart-ebec1ad9-1a43-4ec9-a53b-58f0e237317c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421642661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1421642661
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1775344221
Short name T835
Test name
Test status
Simulation time 110927549280 ps
CPU time 178.15 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:26:19 PM PDT 24
Peak memory 200132 kb
Host smart-ddca39ce-1393-4cd2-90c3-6f3d1e67d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775344221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1775344221
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4279072496
Short name T1173
Test name
Test status
Simulation time 71041402054 ps
CPU time 78.9 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:24:40 PM PDT 24
Peak memory 200248 kb
Host smart-6c6b6012-4f0c-494f-a1a3-8784cd089683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279072496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4279072496
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_intr.1748835952
Short name T415
Test name
Test status
Simulation time 339719565138 ps
CPU time 558.62 seconds
Started Jul 27 06:23:23 PM PDT 24
Finished Jul 27 06:32:42 PM PDT 24
Peak memory 198780 kb
Host smart-21283d97-b28e-420e-9b0f-f9a4756a2c44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748835952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1748835952
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1841878762
Short name T800
Test name
Test status
Simulation time 88341272687 ps
CPU time 255.65 seconds
Started Jul 27 06:23:24 PM PDT 24
Finished Jul 27 06:27:40 PM PDT 24
Peak memory 200232 kb
Host smart-1c9dcdf9-e9ad-4bb5-8364-c99e42571a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841878762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1841878762
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2886208500
Short name T954
Test name
Test status
Simulation time 3717354462 ps
CPU time 11.4 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:23:33 PM PDT 24
Peak memory 199944 kb
Host smart-2a39e96e-8798-4e26-b184-0add618a4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886208500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2886208500
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2623412259
Short name T1004
Test name
Test status
Simulation time 56137865324 ps
CPU time 92.46 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:24:54 PM PDT 24
Peak memory 208148 kb
Host smart-d5c35989-6887-4eed-8fbe-c9e02d41d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623412259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2623412259
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2295598118
Short name T261
Test name
Test status
Simulation time 15987627280 ps
CPU time 408.66 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:30:10 PM PDT 24
Peak memory 200244 kb
Host smart-98634902-8e76-4190-886c-d04fbd5a9411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295598118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2295598118
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1910230925
Short name T418
Test name
Test status
Simulation time 4261292194 ps
CPU time 21.75 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:23:44 PM PDT 24
Peak memory 199524 kb
Host smart-214ff917-eea8-4e59-bfbc-eb57a63bc2ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910230925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1910230925
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2080204776
Short name T9
Test name
Test status
Simulation time 99202020756 ps
CPU time 19.12 seconds
Started Jul 27 06:23:23 PM PDT 24
Finished Jul 27 06:23:42 PM PDT 24
Peak memory 200224 kb
Host smart-37d52c82-96d8-49da-bd80-03d702d2f5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080204776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2080204776
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1942507353
Short name T264
Test name
Test status
Simulation time 2137210381 ps
CPU time 1.52 seconds
Started Jul 27 06:23:20 PM PDT 24
Finished Jul 27 06:23:22 PM PDT 24
Peak memory 195720 kb
Host smart-09f5f514-d034-46eb-90ae-8a7d718d9763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942507353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1942507353
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1000036569
Short name T81
Test name
Test status
Simulation time 287975283 ps
CPU time 0.86 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:23:22 PM PDT 24
Peak memory 218564 kb
Host smart-d5b1a681-a999-42f3-87b8-843fb9ac8140
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000036569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1000036569
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1147272917
Short name T900
Test name
Test status
Simulation time 599604218 ps
CPU time 0.99 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:23:22 PM PDT 24
Peak memory 198608 kb
Host smart-5083e715-2c45-4e77-973e-09e683a94e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147272917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1147272917
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2770544401
Short name T335
Test name
Test status
Simulation time 50391106975 ps
CPU time 113 seconds
Started Jul 27 06:23:25 PM PDT 24
Finished Jul 27 06:25:18 PM PDT 24
Peak memory 215824 kb
Host smart-191ca595-ec93-4ae4-b7d4-47262f93a563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770544401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2770544401
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.740786862
Short name T1026
Test name
Test status
Simulation time 104727442476 ps
CPU time 457.38 seconds
Started Jul 27 06:23:25 PM PDT 24
Finished Jul 27 06:31:02 PM PDT 24
Peak memory 227884 kb
Host smart-a153ba68-7f55-45dc-971f-246e2cd612c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740786862 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.740786862
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2483490817
Short name T524
Test name
Test status
Simulation time 1080410909 ps
CPU time 2.95 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:23:25 PM PDT 24
Peak memory 199836 kb
Host smart-379a6630-918e-49bf-b0f2-8f94b6e0cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483490817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2483490817
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1852736855
Short name T253
Test name
Test status
Simulation time 142139236985 ps
CPU time 127.94 seconds
Started Jul 27 06:23:25 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 200196 kb
Host smart-05c9402b-3b64-4abc-ab24-cb35dca09ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852736855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1852736855
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2443428640
Short name T1145
Test name
Test status
Simulation time 13496135 ps
CPU time 0.57 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:28:47 PM PDT 24
Peak memory 195616 kb
Host smart-efa94a40-eedc-4ffa-a87f-8db07e6d924f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443428640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2443428640
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3056936282
Short name T816
Test name
Test status
Simulation time 31180023278 ps
CPU time 45.08 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:29:32 PM PDT 24
Peak memory 200244 kb
Host smart-29a4c03c-71a1-4cd1-95b4-59726c3d9d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056936282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3056936282
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2457572190
Short name T157
Test name
Test status
Simulation time 95103462560 ps
CPU time 45.28 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:29:32 PM PDT 24
Peak memory 200000 kb
Host smart-591f6352-c2bf-4688-87ac-4621bcc06126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457572190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2457572190
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2852867829
Short name T151
Test name
Test status
Simulation time 234872150306 ps
CPU time 55.83 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:42 PM PDT 24
Peak memory 200208 kb
Host smart-be900d4a-36fc-477c-bb87-1d3217f8c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852867829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2852867829
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3291653262
Short name T741
Test name
Test status
Simulation time 28199967284 ps
CPU time 63.03 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:49 PM PDT 24
Peak memory 200032 kb
Host smart-ecab4c44-49b6-4fdd-936e-2586eb39cde2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291653262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3291653262
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3201469781
Short name T369
Test name
Test status
Simulation time 83754756213 ps
CPU time 268.61 seconds
Started Jul 27 06:28:51 PM PDT 24
Finished Jul 27 06:33:20 PM PDT 24
Peak memory 200240 kb
Host smart-ae955708-9a98-46eb-83d2-28f6150f2a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201469781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3201469781
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.71600000
Short name T359
Test name
Test status
Simulation time 10925552874 ps
CPU time 19.38 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:06 PM PDT 24
Peak memory 200080 kb
Host smart-0096edc9-80df-4ce4-ac2b-987a0e1a6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71600000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.71600000
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2020533427
Short name T41
Test name
Test status
Simulation time 106017618749 ps
CPU time 28.65 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:29:16 PM PDT 24
Peak memory 200280 kb
Host smart-766cbf5a-c760-48dc-a7c4-ebf4206560c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020533427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2020533427
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.828587928
Short name T615
Test name
Test status
Simulation time 22855346651 ps
CPU time 1090.78 seconds
Started Jul 27 06:28:45 PM PDT 24
Finished Jul 27 06:46:56 PM PDT 24
Peak memory 200252 kb
Host smart-445059aa-93ee-4640-a0c3-7eb08a1630d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828587928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.828587928
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2618074004
Short name T841
Test name
Test status
Simulation time 3989483920 ps
CPU time 28.35 seconds
Started Jul 27 06:28:45 PM PDT 24
Finished Jul 27 06:29:14 PM PDT 24
Peak memory 198208 kb
Host smart-b86ed0d4-3829-44d6-9b70-0131d1155630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618074004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2618074004
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1289510514
Short name T609
Test name
Test status
Simulation time 2000655519 ps
CPU time 1.49 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:28:48 PM PDT 24
Peak memory 195896 kb
Host smart-b5d0b805-defa-4e93-956a-5dd6704e4670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289510514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1289510514
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3315379298
Short name T622
Test name
Test status
Simulation time 249555122 ps
CPU time 1.4 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:28:48 PM PDT 24
Peak memory 198460 kb
Host smart-70302f12-2533-4175-b9a6-148ae0b9d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315379298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3315379298
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3671167289
Short name T155
Test name
Test status
Simulation time 362320923322 ps
CPU time 45.67 seconds
Started Jul 27 06:28:48 PM PDT 24
Finished Jul 27 06:29:34 PM PDT 24
Peak memory 200236 kb
Host smart-4c17e7d2-3866-439a-bf4f-86217a79c1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671167289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3671167289
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1821340671
Short name T699
Test name
Test status
Simulation time 8855297790 ps
CPU time 104.75 seconds
Started Jul 27 06:28:48 PM PDT 24
Finished Jul 27 06:30:33 PM PDT 24
Peak memory 216760 kb
Host smart-26f42560-0902-4651-af84-6ad3ecf1f405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821340671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1821340671
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.546233295
Short name T11
Test name
Test status
Simulation time 803687515 ps
CPU time 2.07 seconds
Started Jul 27 06:28:47 PM PDT 24
Finished Jul 27 06:28:49 PM PDT 24
Peak memory 200104 kb
Host smart-367e8fad-7138-495d-b82f-12d466defebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546233295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.546233295
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_alert_test.416967924
Short name T927
Test name
Test status
Simulation time 44345945 ps
CPU time 0.53 seconds
Started Jul 27 06:28:57 PM PDT 24
Finished Jul 27 06:28:58 PM PDT 24
Peak memory 195596 kb
Host smart-f0e93046-1691-40e7-89a9-99b9de3b7f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416967924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.416967924
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1474010839
Short name T291
Test name
Test status
Simulation time 21734414102 ps
CPU time 12.07 seconds
Started Jul 27 06:28:49 PM PDT 24
Finished Jul 27 06:29:01 PM PDT 24
Peak memory 200440 kb
Host smart-c6faf47d-e892-414f-b012-c24ce0f83d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474010839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1474010839
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3148658737
Short name T471
Test name
Test status
Simulation time 48368689378 ps
CPU time 21.24 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:08 PM PDT 24
Peak memory 200244 kb
Host smart-4970daab-ab8f-4501-beaa-b67fc7274f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148658737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3148658737
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4167888304
Short name T367
Test name
Test status
Simulation time 26960984749 ps
CPU time 20.97 seconds
Started Jul 27 06:28:49 PM PDT 24
Finished Jul 27 06:29:10 PM PDT 24
Peak memory 200176 kb
Host smart-5b23931e-7db9-43ad-a152-679921515625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167888304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4167888304
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1886715587
Short name T723
Test name
Test status
Simulation time 6961875866 ps
CPU time 11.58 seconds
Started Jul 27 06:28:48 PM PDT 24
Finished Jul 27 06:29:00 PM PDT 24
Peak memory 196716 kb
Host smart-5589418f-20bd-4669-a567-da3a284e4dd8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886715587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1886715587
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1132002635
Short name T424
Test name
Test status
Simulation time 121711324624 ps
CPU time 410.91 seconds
Started Jul 27 06:28:56 PM PDT 24
Finished Jul 27 06:35:47 PM PDT 24
Peak memory 200176 kb
Host smart-d5b70780-8031-4c8f-938f-7be440c8f687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132002635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1132002635
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1933057914
Short name T722
Test name
Test status
Simulation time 1565108253 ps
CPU time 3.3 seconds
Started Jul 27 06:28:56 PM PDT 24
Finished Jul 27 06:28:59 PM PDT 24
Peak memory 198632 kb
Host smart-5d0fe99c-61b4-48dd-8992-b4a2bdcdced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933057914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1933057914
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3909116555
Short name T739
Test name
Test status
Simulation time 92391459310 ps
CPU time 73.19 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:59 PM PDT 24
Peak memory 200324 kb
Host smart-59ce9f0f-3b89-4827-a9cd-7d1646825633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909116555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3909116555
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.263367302
Short name T972
Test name
Test status
Simulation time 11142349687 ps
CPU time 630.64 seconds
Started Jul 27 06:29:00 PM PDT 24
Finished Jul 27 06:39:30 PM PDT 24
Peak memory 200216 kb
Host smart-8d81374f-2a44-4e2a-ba17-8d41a26c5fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263367302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.263367302
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1045568783
Short name T90
Test name
Test status
Simulation time 7465133478 ps
CPU time 34.64 seconds
Started Jul 27 06:28:46 PM PDT 24
Finished Jul 27 06:29:21 PM PDT 24
Peak memory 199496 kb
Host smart-b8929b14-20cf-44e0-8bc6-83d54b327602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045568783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1045568783
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2230927109
Short name T1126
Test name
Test status
Simulation time 204839243907 ps
CPU time 214.61 seconds
Started Jul 27 06:28:58 PM PDT 24
Finished Jul 27 06:32:32 PM PDT 24
Peak memory 200364 kb
Host smart-be8d0bf1-9ecc-47d8-a290-93c9967b3374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230927109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2230927109
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2635745652
Short name T523
Test name
Test status
Simulation time 6982825890 ps
CPU time 11.26 seconds
Started Jul 27 06:28:58 PM PDT 24
Finished Jul 27 06:29:09 PM PDT 24
Peak memory 196352 kb
Host smart-51171d68-b766-4b9b-a8f1-512c24b6bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635745652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2635745652
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.227477701
Short name T545
Test name
Test status
Simulation time 5516751566 ps
CPU time 9.37 seconds
Started Jul 27 06:28:51 PM PDT 24
Finished Jul 27 06:29:01 PM PDT 24
Peak memory 200236 kb
Host smart-7262370d-d6ea-4eea-8e83-171974153272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227477701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.227477701
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2421077189
Short name T842
Test name
Test status
Simulation time 23344959888 ps
CPU time 437.46 seconds
Started Jul 27 06:28:57 PM PDT 24
Finished Jul 27 06:36:14 PM PDT 24
Peak memory 200236 kb
Host smart-63d3923a-5d7e-42b5-b459-cfb828943c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421077189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2421077189
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1996333933
Short name T378
Test name
Test status
Simulation time 1601296238 ps
CPU time 1.79 seconds
Started Jul 27 06:28:55 PM PDT 24
Finished Jul 27 06:28:57 PM PDT 24
Peak memory 199864 kb
Host smart-8aeee074-aab8-4487-8899-830b929dd5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996333933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1996333933
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.83735078
Short name T396
Test name
Test status
Simulation time 28320095130 ps
CPU time 36.44 seconds
Started Jul 27 06:28:48 PM PDT 24
Finished Jul 27 06:29:25 PM PDT 24
Peak memory 200440 kb
Host smart-cf4d1276-5b32-40af-84b1-f848197d0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83735078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.83735078
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2373212171
Short name T919
Test name
Test status
Simulation time 12684131 ps
CPU time 0.56 seconds
Started Jul 27 06:29:09 PM PDT 24
Finished Jul 27 06:29:09 PM PDT 24
Peak memory 195552 kb
Host smart-a88fe56c-ba71-4b38-b12b-e0a1b0ff0b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373212171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2373212171
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4053292212
Short name T690
Test name
Test status
Simulation time 336936238792 ps
CPU time 613.6 seconds
Started Jul 27 06:28:57 PM PDT 24
Finished Jul 27 06:39:11 PM PDT 24
Peak memory 200164 kb
Host smart-a5e0ad0d-da3e-409e-b746-e3f4f97bdb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053292212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4053292212
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.670278254
Short name T942
Test name
Test status
Simulation time 125341708830 ps
CPU time 100.56 seconds
Started Jul 27 06:28:56 PM PDT 24
Finished Jul 27 06:30:37 PM PDT 24
Peak memory 200252 kb
Host smart-7e9bbdd1-0b08-4dbc-92bb-8604bec64a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670278254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.670278254
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3057942918
Short name T329
Test name
Test status
Simulation time 42911094518 ps
CPU time 26.33 seconds
Started Jul 27 06:28:55 PM PDT 24
Finished Jul 27 06:29:21 PM PDT 24
Peak memory 200172 kb
Host smart-010ea520-8c8d-474a-b58d-b564617e6650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057942918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3057942918
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2917764552
Short name T700
Test name
Test status
Simulation time 40590566050 ps
CPU time 22.89 seconds
Started Jul 27 06:28:58 PM PDT 24
Finished Jul 27 06:29:21 PM PDT 24
Peak memory 199840 kb
Host smart-9f483f1e-69a6-4043-8372-b274f7a186be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917764552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2917764552
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3040125917
Short name T768
Test name
Test status
Simulation time 158654083795 ps
CPU time 1032.93 seconds
Started Jul 27 06:29:06 PM PDT 24
Finished Jul 27 06:46:20 PM PDT 24
Peak memory 200208 kb
Host smart-beed5086-2737-4a2d-bd7b-b6166818b5d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040125917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3040125917
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.497643291
Short name T526
Test name
Test status
Simulation time 8180620800 ps
CPU time 7.9 seconds
Started Jul 27 06:29:06 PM PDT 24
Finished Jul 27 06:29:14 PM PDT 24
Peak memory 200180 kb
Host smart-c67f037e-0034-4ba1-889e-8e7a7e152912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497643291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.497643291
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.241372948
Short name T1180
Test name
Test status
Simulation time 152570874013 ps
CPU time 98.5 seconds
Started Jul 27 06:28:55 PM PDT 24
Finished Jul 27 06:30:34 PM PDT 24
Peak memory 208688 kb
Host smart-0accb4cf-7adf-459e-9256-f03bef0fb84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241372948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.241372948
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3919876204
Short name T430
Test name
Test status
Simulation time 18372450760 ps
CPU time 254 seconds
Started Jul 27 06:29:07 PM PDT 24
Finished Jul 27 06:33:21 PM PDT 24
Peak memory 200172 kb
Host smart-c8dd6119-504b-4483-a007-d6afc2fff8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919876204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3919876204
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.604562814
Short name T775
Test name
Test status
Simulation time 2837955204 ps
CPU time 9.53 seconds
Started Jul 27 06:28:57 PM PDT 24
Finished Jul 27 06:29:06 PM PDT 24
Peak memory 198360 kb
Host smart-97eee80e-4dee-401a-a576-671ebb50bc86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604562814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.604562814
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3634880590
Short name T662
Test name
Test status
Simulation time 27957886909 ps
CPU time 13.71 seconds
Started Jul 27 06:29:05 PM PDT 24
Finished Jul 27 06:29:19 PM PDT 24
Peak memory 200192 kb
Host smart-fe7e55fe-9b35-44ed-9dc8-81d065c1386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634880590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3634880590
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1467209709
Short name T706
Test name
Test status
Simulation time 1646016786 ps
CPU time 2.98 seconds
Started Jul 27 06:28:58 PM PDT 24
Finished Jul 27 06:29:01 PM PDT 24
Peak memory 195680 kb
Host smart-4f9712ce-5c97-4f11-a66e-07128016f51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467209709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1467209709
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2301510435
Short name T467
Test name
Test status
Simulation time 5704810583 ps
CPU time 5.83 seconds
Started Jul 27 06:28:56 PM PDT 24
Finished Jul 27 06:29:02 PM PDT 24
Peak memory 200092 kb
Host smart-e75341ae-0f09-458b-ae20-752df49569c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301510435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2301510435
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.194176745
Short name T971
Test name
Test status
Simulation time 424452042551 ps
CPU time 624.01 seconds
Started Jul 27 06:29:08 PM PDT 24
Finished Jul 27 06:39:32 PM PDT 24
Peak memory 200168 kb
Host smart-c21547aa-f4bf-4689-aa6d-76911a5a1831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194176745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.194176745
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1208955045
Short name T998
Test name
Test status
Simulation time 18176605348 ps
CPU time 284.22 seconds
Started Jul 27 06:29:08 PM PDT 24
Finished Jul 27 06:33:52 PM PDT 24
Peak memory 208548 kb
Host smart-49ec386c-3f71-4c56-af89-4bb9c93581c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208955045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1208955045
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1582158283
Short name T83
Test name
Test status
Simulation time 3114024269 ps
CPU time 2.34 seconds
Started Jul 27 06:29:05 PM PDT 24
Finished Jul 27 06:29:08 PM PDT 24
Peak memory 199064 kb
Host smart-14887c98-5aac-41d5-b57a-b1a46aed2809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582158283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1582158283
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.386726078
Short name T981
Test name
Test status
Simulation time 18991673229 ps
CPU time 16.02 seconds
Started Jul 27 06:29:00 PM PDT 24
Finished Jul 27 06:29:16 PM PDT 24
Peak memory 199972 kb
Host smart-7dbb2f5d-1864-41e0-ba72-043e36c0ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386726078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.386726078
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3388842626
Short name T395
Test name
Test status
Simulation time 12672885 ps
CPU time 0.55 seconds
Started Jul 27 06:29:26 PM PDT 24
Finished Jul 27 06:29:27 PM PDT 24
Peak memory 195884 kb
Host smart-f0418a9e-f044-42e7-b374-bf39d57f47e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388842626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3388842626
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.699745005
Short name T726
Test name
Test status
Simulation time 285859910666 ps
CPU time 89.31 seconds
Started Jul 27 06:29:16 PM PDT 24
Finished Jul 27 06:30:45 PM PDT 24
Peak memory 200204 kb
Host smart-3d953e5c-7b31-4c62-bfff-c16f8d6494a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699745005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.699745005
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3413513127
Short name T112
Test name
Test status
Simulation time 138367608001 ps
CPU time 50.29 seconds
Started Jul 27 06:29:16 PM PDT 24
Finished Jul 27 06:30:06 PM PDT 24
Peak memory 200144 kb
Host smart-2f0c0cbf-2466-4f03-89ae-80d73ab79ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413513127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3413513127
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.530145474
Short name T1155
Test name
Test status
Simulation time 11599222209 ps
CPU time 17.62 seconds
Started Jul 27 06:29:14 PM PDT 24
Finished Jul 27 06:29:32 PM PDT 24
Peak memory 200072 kb
Host smart-f2ee8f97-bd7f-41ff-b099-f3f541fcdaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530145474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.530145474
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1117916448
Short name T460
Test name
Test status
Simulation time 5751861510 ps
CPU time 13.47 seconds
Started Jul 27 06:29:15 PM PDT 24
Finished Jul 27 06:29:28 PM PDT 24
Peak memory 200056 kb
Host smart-1a201818-74b2-4afc-903e-8d250623ff48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117916448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1117916448
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1721924367
Short name T710
Test name
Test status
Simulation time 66600840303 ps
CPU time 353.89 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:35:18 PM PDT 24
Peak memory 200112 kb
Host smart-82c14ffd-70cd-4a2d-86d8-c0a9b114c030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721924367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1721924367
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2962036690
Short name T458
Test name
Test status
Simulation time 4342479132 ps
CPU time 2.2 seconds
Started Jul 27 06:29:14 PM PDT 24
Finished Jul 27 06:29:17 PM PDT 24
Peak memory 199152 kb
Host smart-e5a01b5a-1699-431d-888e-22cfac8ec860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962036690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2962036690
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.996008920
Short name T683
Test name
Test status
Simulation time 39197414826 ps
CPU time 104.63 seconds
Started Jul 27 06:29:18 PM PDT 24
Finished Jul 27 06:31:02 PM PDT 24
Peak memory 200368 kb
Host smart-e7e06340-a5ca-488e-8b77-02e1921fd08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996008920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.996008920
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1263528513
Short name T849
Test name
Test status
Simulation time 14901396800 ps
CPU time 800.68 seconds
Started Jul 27 06:29:15 PM PDT 24
Finished Jul 27 06:42:36 PM PDT 24
Peak memory 200252 kb
Host smart-808e8bda-86b6-4eb8-8dbb-260b124b57bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263528513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1263528513
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2087599908
Short name T351
Test name
Test status
Simulation time 6752754331 ps
CPU time 16.95 seconds
Started Jul 27 06:29:17 PM PDT 24
Finished Jul 27 06:29:34 PM PDT 24
Peak memory 198604 kb
Host smart-5fa0bd13-6443-4e51-91b4-59e1e2e28e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087599908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2087599908
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.481724591
Short name T1107
Test name
Test status
Simulation time 64804351669 ps
CPU time 26.82 seconds
Started Jul 27 06:29:16 PM PDT 24
Finished Jul 27 06:29:43 PM PDT 24
Peak memory 199532 kb
Host smart-4c86316d-ae2a-4c58-b0eb-1ff62371671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481724591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.481724591
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3401133722
Short name T558
Test name
Test status
Simulation time 44468386604 ps
CPU time 17.85 seconds
Started Jul 27 06:29:15 PM PDT 24
Finished Jul 27 06:29:33 PM PDT 24
Peak memory 196552 kb
Host smart-daed8bf2-09cb-4b3d-8b81-07ca033709d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401133722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3401133722
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3765638821
Short name T618
Test name
Test status
Simulation time 6375985446 ps
CPU time 6.08 seconds
Started Jul 27 06:29:18 PM PDT 24
Finished Jul 27 06:29:24 PM PDT 24
Peak memory 199528 kb
Host smart-0c627ef7-94d8-4d9e-bce1-e5f206377f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765638821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3765638821
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3036875935
Short name T600
Test name
Test status
Simulation time 406034643319 ps
CPU time 1933.09 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 07:01:38 PM PDT 24
Peak memory 200152 kb
Host smart-a1e9e27a-1223-4bdf-b254-a3d35a82e9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036875935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3036875935
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3579494015
Short name T251
Test name
Test status
Simulation time 38279148617 ps
CPU time 346.45 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:35:10 PM PDT 24
Peak memory 214560 kb
Host smart-82573dd5-9287-4e09-905f-e074e0647390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579494015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3579494015
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3700182594
Short name T262
Test name
Test status
Simulation time 8338052024 ps
CPU time 15.89 seconds
Started Jul 27 06:29:16 PM PDT 24
Finished Jul 27 06:29:32 PM PDT 24
Peak memory 200152 kb
Host smart-a5176e1e-0a22-4b83-92fe-5b976108fbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700182594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3700182594
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2477886698
Short name T1018
Test name
Test status
Simulation time 52345249348 ps
CPU time 23.38 seconds
Started Jul 27 06:29:16 PM PDT 24
Finished Jul 27 06:29:40 PM PDT 24
Peak memory 200260 kb
Host smart-942b26bd-3b62-4c9e-92cc-6c275a93a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477886698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2477886698
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3749349525
Short name T943
Test name
Test status
Simulation time 22220378 ps
CPU time 0.55 seconds
Started Jul 27 06:29:32 PM PDT 24
Finished Jul 27 06:29:33 PM PDT 24
Peak memory 195540 kb
Host smart-f7d23461-1e8a-40cf-abf9-9b3de71e3ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749349525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3749349525
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1137490360
Short name T1005
Test name
Test status
Simulation time 111638276073 ps
CPU time 151.31 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:31:56 PM PDT 24
Peak memory 200148 kb
Host smart-116954eb-635a-45b3-89b5-a986d21655e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137490360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1137490360
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2265037749
Short name T838
Test name
Test status
Simulation time 78849320836 ps
CPU time 37.24 seconds
Started Jul 27 06:29:23 PM PDT 24
Finished Jul 27 06:30:00 PM PDT 24
Peak memory 200424 kb
Host smart-ef16ab57-3dc4-464b-b4e5-6915b3f80fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265037749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2265037749
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2429680994
Short name T269
Test name
Test status
Simulation time 34006038494 ps
CPU time 23.03 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:29:47 PM PDT 24
Peak memory 200216 kb
Host smart-4fa51df3-7148-48fc-a6ed-6ab02b20ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429680994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2429680994
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1339251507
Short name T770
Test name
Test status
Simulation time 77717606626 ps
CPU time 24.66 seconds
Started Jul 27 06:29:23 PM PDT 24
Finished Jul 27 06:29:47 PM PDT 24
Peak memory 199388 kb
Host smart-a6b996da-3dcd-4b63-8cd7-34f3a17d3627
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339251507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1339251507
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.871418936
Short name T1023
Test name
Test status
Simulation time 166456544419 ps
CPU time 330.23 seconds
Started Jul 27 06:29:25 PM PDT 24
Finished Jul 27 06:34:55 PM PDT 24
Peak memory 200196 kb
Host smart-5115d2de-3726-4509-a562-ed8f89e1b4de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871418936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.871418936
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2463815775
Short name T786
Test name
Test status
Simulation time 3308636985 ps
CPU time 5.42 seconds
Started Jul 27 06:29:25 PM PDT 24
Finished Jul 27 06:29:31 PM PDT 24
Peak memory 199436 kb
Host smart-bc17b950-59be-46cc-b5a1-572c4fdc9354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463815775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2463815775
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1686727262
Short name T519
Test name
Test status
Simulation time 153597124639 ps
CPU time 47.59 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:30:12 PM PDT 24
Peak memory 200308 kb
Host smart-51aa8bd8-4923-49c5-9df2-388e68b8372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686727262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1686727262
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2583411352
Short name T263
Test name
Test status
Simulation time 9671583854 ps
CPU time 253.32 seconds
Started Jul 27 06:29:25 PM PDT 24
Finished Jul 27 06:33:38 PM PDT 24
Peak memory 200164 kb
Host smart-5597586c-223a-4c7d-b324-f42cad145cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583411352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2583411352
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.965667949
Short name T814
Test name
Test status
Simulation time 2137363893 ps
CPU time 3.88 seconds
Started Jul 27 06:29:25 PM PDT 24
Finished Jul 27 06:29:29 PM PDT 24
Peak memory 198376 kb
Host smart-5f0b343f-76dd-42fe-8939-a6ad2bf42786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965667949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.965667949
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.962673816
Short name T428
Test name
Test status
Simulation time 103175961910 ps
CPU time 324.2 seconds
Started Jul 27 06:29:23 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 200248 kb
Host smart-0dcfd219-a1fb-4efb-bf2b-794d9b997e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962673816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.962673816
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2573525320
Short name T406
Test name
Test status
Simulation time 7211496890 ps
CPU time 12.42 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:29:36 PM PDT 24
Peak memory 196508 kb
Host smart-f56191d3-2e16-4f1d-9ffd-3dd16411bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573525320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2573525320
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1861999045
Short name T740
Test name
Test status
Simulation time 5360140810 ps
CPU time 10.98 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:29:35 PM PDT 24
Peak memory 200192 kb
Host smart-f6c2c282-9444-407e-a534-011469c05082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861999045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1861999045
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2461334516
Short name T1139
Test name
Test status
Simulation time 166517601216 ps
CPU time 998.7 seconds
Started Jul 27 06:29:27 PM PDT 24
Finished Jul 27 06:46:06 PM PDT 24
Peak memory 200164 kb
Host smart-28a25e85-f0b2-4e36-9d08-d10faf5c7b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461334516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2461334516
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3382769961
Short name T487
Test name
Test status
Simulation time 34892105054 ps
CPU time 315.97 seconds
Started Jul 27 06:29:25 PM PDT 24
Finished Jul 27 06:34:41 PM PDT 24
Peak memory 213916 kb
Host smart-b765e5c4-4c17-4392-9349-ef9121a285b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382769961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3382769961
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1330847385
Short name T1019
Test name
Test status
Simulation time 548927826 ps
CPU time 2.45 seconds
Started Jul 27 06:29:24 PM PDT 24
Finished Jul 27 06:29:27 PM PDT 24
Peak memory 198836 kb
Host smart-877b9ee2-56d8-43ce-bcdc-4fbced2ff347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330847385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1330847385
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3427570521
Short name T705
Test name
Test status
Simulation time 6245953707 ps
CPU time 13.01 seconds
Started Jul 27 06:29:27 PM PDT 24
Finished Jul 27 06:29:40 PM PDT 24
Peak memory 200132 kb
Host smart-64edbe1a-8ecb-4d7e-90f4-fd1656ebe643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427570521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3427570521
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3656952378
Short name T864
Test name
Test status
Simulation time 36467626 ps
CPU time 0.56 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:29:34 PM PDT 24
Peak memory 195900 kb
Host smart-bab2e75d-8ff8-4888-a903-c4937ed9cb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656952378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3656952378
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3943132657
Short name T352
Test name
Test status
Simulation time 85159821822 ps
CPU time 129.26 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:31:42 PM PDT 24
Peak memory 200232 kb
Host smart-0fafc81f-63b3-4d29-82a6-a503d8b5a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943132657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3943132657
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3917707517
Short name T820
Test name
Test status
Simulation time 37439833751 ps
CPU time 53.6 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:30:27 PM PDT 24
Peak memory 200124 kb
Host smart-e8cd03e0-6f96-4207-ae57-e3dc27310a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917707517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3917707517
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.789118983
Short name T205
Test name
Test status
Simulation time 150484523309 ps
CPU time 57.02 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:30:30 PM PDT 24
Peak memory 200172 kb
Host smart-18875e72-a725-443d-8719-336f40d5c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789118983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.789118983
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.19852265
Short name T993
Test name
Test status
Simulation time 51234307819 ps
CPU time 23.92 seconds
Started Jul 27 06:29:32 PM PDT 24
Finished Jul 27 06:29:56 PM PDT 24
Peak memory 200204 kb
Host smart-bb938c02-0572-4158-8d16-87d99026a9da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19852265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.19852265
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1214407216
Short name T765
Test name
Test status
Simulation time 80843786867 ps
CPU time 258.76 seconds
Started Jul 27 06:29:32 PM PDT 24
Finished Jul 27 06:33:51 PM PDT 24
Peak memory 200088 kb
Host smart-b09557cb-a1a9-4186-b323-37d459e1af84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214407216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1214407216
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2777186313
Short name T874
Test name
Test status
Simulation time 7626710663 ps
CPU time 14.62 seconds
Started Jul 27 06:29:34 PM PDT 24
Finished Jul 27 06:29:49 PM PDT 24
Peak memory 200112 kb
Host smart-72a0234e-22ee-430e-a741-d2b8dd7be946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777186313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2777186313
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1069405677
Short name T319
Test name
Test status
Simulation time 147853892895 ps
CPU time 119.56 seconds
Started Jul 27 06:29:34 PM PDT 24
Finished Jul 27 06:31:33 PM PDT 24
Peak memory 208536 kb
Host smart-9adc1fe2-780c-463d-8c3e-d6c8b6daa934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069405677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1069405677
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.16041561
Short name T39
Test name
Test status
Simulation time 10846153657 ps
CPU time 164.11 seconds
Started Jul 27 06:29:38 PM PDT 24
Finished Jul 27 06:32:22 PM PDT 24
Peak memory 200276 kb
Host smart-d5e38b9d-f773-440c-8a98-7e0801cccda5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16041561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.16041561
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3471751846
Short name T626
Test name
Test status
Simulation time 2542483042 ps
CPU time 18.93 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:29:52 PM PDT 24
Peak memory 198604 kb
Host smart-caaf5517-7052-4581-9ee4-0e29bd8d70d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471751846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3471751846
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.284772908
Short name T766
Test name
Test status
Simulation time 108288731990 ps
CPU time 90.14 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:31:03 PM PDT 24
Peak memory 200180 kb
Host smart-773efabc-f0a1-4945-b0a8-95c4990cb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284772908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.284772908
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3913007827
Short name T586
Test name
Test status
Simulation time 4237869691 ps
CPU time 7 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:29:40 PM PDT 24
Peak memory 196524 kb
Host smart-5fe7d3c5-9355-4f78-a1a9-57f5cbac1364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913007827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3913007827
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2969693
Short name T1009
Test name
Test status
Simulation time 321315141 ps
CPU time 1.13 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:29:34 PM PDT 24
Peak memory 199640 kb
Host smart-2e8f3977-b487-4d91-bf5c-d7c100dca10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2969693
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.21412622
Short name T165
Test name
Test status
Simulation time 218386591499 ps
CPU time 260.82 seconds
Started Jul 27 06:29:33 PM PDT 24
Finished Jul 27 06:33:53 PM PDT 24
Peak memory 200248 kb
Host smart-9c71fca7-bc11-46c5-81b1-caa38e6a82d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21412622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.21412622
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.935740182
Short name T108
Test name
Test status
Simulation time 77606578516 ps
CPU time 725.11 seconds
Started Jul 27 06:29:34 PM PDT 24
Finished Jul 27 06:41:40 PM PDT 24
Peak memory 216852 kb
Host smart-b0b2f315-2051-425d-8acd-80061c54c2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935740182 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.935740182
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3114905100
Short name T727
Test name
Test status
Simulation time 686675170 ps
CPU time 2.88 seconds
Started Jul 27 06:29:32 PM PDT 24
Finished Jul 27 06:29:35 PM PDT 24
Peak memory 198696 kb
Host smart-2a721fe5-ea9e-4dd3-ace2-984432bd9c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114905100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3114905100
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1046627916
Short name T955
Test name
Test status
Simulation time 29951180491 ps
CPU time 17.94 seconds
Started Jul 27 06:29:34 PM PDT 24
Finished Jul 27 06:29:52 PM PDT 24
Peak memory 200264 kb
Host smart-5c99db83-f639-4bc9-a8b3-4644c5941977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046627916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1046627916
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1978152034
Short name T349
Test name
Test status
Simulation time 31614616 ps
CPU time 0.53 seconds
Started Jul 27 06:29:41 PM PDT 24
Finished Jul 27 06:29:41 PM PDT 24
Peak memory 195068 kb
Host smart-23306a66-11a8-488c-b2cb-001aa2504e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978152034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1978152034
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2548473801
Short name T1172
Test name
Test status
Simulation time 89518396424 ps
CPU time 29.97 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:30:12 PM PDT 24
Peak memory 200196 kb
Host smart-c5103823-3766-4e43-ae55-f05bdd1f32cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548473801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2548473801
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3843772908
Short name T434
Test name
Test status
Simulation time 81186085010 ps
CPU time 15.45 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:29:57 PM PDT 24
Peak memory 200088 kb
Host smart-0227c7db-dd5c-4183-9afe-394030263126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843772908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3843772908
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4287589471
Short name T1085
Test name
Test status
Simulation time 46236926738 ps
CPU time 69.63 seconds
Started Jul 27 06:29:43 PM PDT 24
Finished Jul 27 06:30:52 PM PDT 24
Peak memory 200204 kb
Host smart-4310fce9-a46b-4c2c-a72e-052f7e08e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287589471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4287589471
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1006652113
Short name T1150
Test name
Test status
Simulation time 629332560536 ps
CPU time 1202.57 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:49:45 PM PDT 24
Peak memory 200164 kb
Host smart-ed99655c-bbe2-4bde-82e4-debd3df93069
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006652113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1006652113
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3385177874
Short name T84
Test name
Test status
Simulation time 57109133479 ps
CPU time 145.37 seconds
Started Jul 27 06:29:41 PM PDT 24
Finished Jul 27 06:32:07 PM PDT 24
Peak memory 200236 kb
Host smart-33baeddc-fb3e-4eae-b752-ac68ce4c7ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385177874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3385177874
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3261034333
Short name T345
Test name
Test status
Simulation time 8781505915 ps
CPU time 20.17 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:30:02 PM PDT 24
Peak memory 200260 kb
Host smart-60caf5b9-227d-491d-8d0c-fe6a2907a308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261034333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3261034333
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.672013878
Short name T720
Test name
Test status
Simulation time 136631108477 ps
CPU time 155.79 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:32:18 PM PDT 24
Peak memory 199780 kb
Host smart-acdcd509-19da-4988-a2aa-9a3e42e6c108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672013878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.672013878
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3326545089
Short name T271
Test name
Test status
Simulation time 7531217906 ps
CPU time 107.74 seconds
Started Jul 27 06:29:44 PM PDT 24
Finished Jul 27 06:31:32 PM PDT 24
Peak memory 200188 kb
Host smart-9f2e7834-0463-4b7b-be9c-cd48c58dcc4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326545089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3326545089
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1821414830
Short name T1080
Test name
Test status
Simulation time 3911387601 ps
CPU time 34.47 seconds
Started Jul 27 06:29:41 PM PDT 24
Finished Jul 27 06:30:16 PM PDT 24
Peak memory 198756 kb
Host smart-69ebe2d7-c0f2-4152-9d20-c5e0beb584c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821414830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1821414830
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.333794136
Short name T941
Test name
Test status
Simulation time 5040180661 ps
CPU time 6.68 seconds
Started Jul 27 06:29:43 PM PDT 24
Finished Jul 27 06:29:50 PM PDT 24
Peak memory 196720 kb
Host smart-5617627e-eacd-4c26-b5ad-bd235cda6ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333794136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.333794136
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3098180881
Short name T405
Test name
Test status
Simulation time 449438044 ps
CPU time 1.95 seconds
Started Jul 27 06:29:43 PM PDT 24
Finished Jul 27 06:29:45 PM PDT 24
Peak memory 198624 kb
Host smart-58a13194-16ab-45dc-823e-7ac90a56fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098180881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3098180881
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.549591340
Short name T106
Test name
Test status
Simulation time 160786228582 ps
CPU time 703.11 seconds
Started Jul 27 06:29:41 PM PDT 24
Finished Jul 27 06:41:24 PM PDT 24
Peak memory 200232 kb
Host smart-b074a7c4-7737-4104-8473-3b79212d057d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549591340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.549591340
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3270584500
Short name T961
Test name
Test status
Simulation time 89035554909 ps
CPU time 363.83 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:35:47 PM PDT 24
Peak memory 216724 kb
Host smart-24cfa340-203f-44ff-9033-2a03ffa20c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270584500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3270584500
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3303128277
Short name T725
Test name
Test status
Simulation time 1185014005 ps
CPU time 2.38 seconds
Started Jul 27 06:29:43 PM PDT 24
Finished Jul 27 06:29:46 PM PDT 24
Peak memory 199644 kb
Host smart-9900556f-3d9e-4685-b870-5777b0447d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303128277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3303128277
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1049785395
Short name T1106
Test name
Test status
Simulation time 169952617226 ps
CPU time 68.78 seconds
Started Jul 27 06:29:42 PM PDT 24
Finished Jul 27 06:30:51 PM PDT 24
Peak memory 200168 kb
Host smart-22724ae8-49cd-4c9f-bc2c-430c20044621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049785395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1049785395
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4067438305
Short name T884
Test name
Test status
Simulation time 24923074 ps
CPU time 0.55 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:29:54 PM PDT 24
Peak memory 195520 kb
Host smart-d62a48c5-905d-469f-ad78-217856f51892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067438305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4067438305
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3436597527
Short name T125
Test name
Test status
Simulation time 37105677417 ps
CPU time 12.17 seconds
Started Jul 27 06:29:54 PM PDT 24
Finished Jul 27 06:30:06 PM PDT 24
Peak memory 200112 kb
Host smart-33c154bd-9d70-4203-993a-5fb15ee3c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436597527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3436597527
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2344395696
Short name T561
Test name
Test status
Simulation time 17056637481 ps
CPU time 27.34 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:30:20 PM PDT 24
Peak memory 200164 kb
Host smart-f191146a-cec6-4c82-a4f4-df326a4d1efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344395696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2344395696
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3187562959
Short name T500
Test name
Test status
Simulation time 12323470237 ps
CPU time 26.46 seconds
Started Jul 27 06:29:57 PM PDT 24
Finished Jul 27 06:30:23 PM PDT 24
Peak memory 200172 kb
Host smart-27642b76-c8a0-4e77-875e-062b6b59a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187562959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3187562959
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2669585346
Short name T535
Test name
Test status
Simulation time 489190018102 ps
CPU time 532.06 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:38:46 PM PDT 24
Peak memory 198616 kb
Host smart-9c7b70f6-ab2e-473c-bdd4-e58320fad211
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669585346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2669585346
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3537531397
Short name T305
Test name
Test status
Simulation time 83832572830 ps
CPU time 246.93 seconds
Started Jul 27 06:29:56 PM PDT 24
Finished Jul 27 06:34:03 PM PDT 24
Peak memory 200172 kb
Host smart-05da9ff6-ad64-4c1d-a069-6de6fc474b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537531397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3537531397
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.870127544
Short name T348
Test name
Test status
Simulation time 2813303770 ps
CPU time 2.74 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:29:56 PM PDT 24
Peak memory 200180 kb
Host smart-52baf10c-72df-48ff-b43b-226220fa397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870127544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.870127544
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2383329187
Short name T1176
Test name
Test status
Simulation time 44463629268 ps
CPU time 73.56 seconds
Started Jul 27 06:29:55 PM PDT 24
Finished Jul 27 06:31:08 PM PDT 24
Peak memory 200380 kb
Host smart-e2b460e5-c098-435a-824b-299b2424bbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383329187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2383329187
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.24496510
Short name T1132
Test name
Test status
Simulation time 22574661024 ps
CPU time 305.33 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:34:58 PM PDT 24
Peak memory 200152 kb
Host smart-efbb5290-697f-4264-962c-a0ac2b254f6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24496510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.24496510
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1921666680
Short name T592
Test name
Test status
Simulation time 4770617211 ps
CPU time 40.15 seconds
Started Jul 27 06:29:56 PM PDT 24
Finished Jul 27 06:30:36 PM PDT 24
Peak memory 198644 kb
Host smart-86f53c6d-9a29-46fe-bf17-9b170f95233c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921666680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1921666680
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.119975381
Short name T871
Test name
Test status
Simulation time 81615736477 ps
CPU time 33.14 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:30:27 PM PDT 24
Peak memory 200204 kb
Host smart-797bfec2-f7ac-445a-96e4-57de8cd12e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119975381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.119975381
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.218014638
Short name T572
Test name
Test status
Simulation time 45059291909 ps
CPU time 18.04 seconds
Started Jul 27 06:30:01 PM PDT 24
Finished Jul 27 06:30:19 PM PDT 24
Peak memory 196088 kb
Host smart-f0f70747-1a99-4d93-9ff4-61bdaa79bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218014638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.218014638
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3659173472
Short name T400
Test name
Test status
Simulation time 5488925524 ps
CPU time 13.93 seconds
Started Jul 27 06:29:43 PM PDT 24
Finished Jul 27 06:29:57 PM PDT 24
Peak memory 199924 kb
Host smart-e6d6c076-bf85-4fee-aa62-f04e69da026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659173472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3659173472
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3584103502
Short name T865
Test name
Test status
Simulation time 318421284744 ps
CPU time 875.94 seconds
Started Jul 27 06:29:52 PM PDT 24
Finished Jul 27 06:44:28 PM PDT 24
Peak memory 208480 kb
Host smart-1c577a72-3e0b-496f-8bb2-fb01fb0c6e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584103502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3584103502
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.128594355
Short name T776
Test name
Test status
Simulation time 35969419750 ps
CPU time 647.3 seconds
Started Jul 27 06:29:55 PM PDT 24
Finished Jul 27 06:40:43 PM PDT 24
Peak memory 210524 kb
Host smart-7e7922d5-0f0f-4275-a0e4-9929e1f2abf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128594355 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.128594355
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1718658123
Short name T310
Test name
Test status
Simulation time 824562405 ps
CPU time 1.51 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:29:55 PM PDT 24
Peak memory 198896 kb
Host smart-539c37fe-bb6c-47b0-9096-3daaf209a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718658123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1718658123
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4131221942
Short name T674
Test name
Test status
Simulation time 89105392344 ps
CPU time 91.15 seconds
Started Jul 27 06:29:54 PM PDT 24
Finished Jul 27 06:31:26 PM PDT 24
Peak memory 200192 kb
Host smart-09c69f83-ced0-406b-a484-60347ffbaf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131221942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4131221942
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1196301499
Short name T1039
Test name
Test status
Simulation time 30722226 ps
CPU time 0.58 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:04 PM PDT 24
Peak memory 195900 kb
Host smart-70c893ee-abd9-498e-8bfa-076ce28e6996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196301499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1196301499
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1091241525
Short name T470
Test name
Test status
Simulation time 68193142041 ps
CPU time 27.63 seconds
Started Jul 27 06:29:53 PM PDT 24
Finished Jul 27 06:30:21 PM PDT 24
Peak memory 200176 kb
Host smart-6166fd2f-5110-476b-aef4-0429b958b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091241525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1091241525
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.311558290
Short name T1156
Test name
Test status
Simulation time 91861078422 ps
CPU time 107.73 seconds
Started Jul 27 06:30:08 PM PDT 24
Finished Jul 27 06:31:56 PM PDT 24
Peak memory 200272 kb
Host smart-e8c413ad-063e-482b-897b-36138835ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311558290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.311558290
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1479630275
Short name T327
Test name
Test status
Simulation time 42555391444 ps
CPU time 12.43 seconds
Started Jul 27 06:30:02 PM PDT 24
Finished Jul 27 06:30:14 PM PDT 24
Peak memory 200192 kb
Host smart-90456c1e-f22a-40da-9f17-0ad685a47835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479630275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1479630275
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2362042849
Short name T575
Test name
Test status
Simulation time 86764708940 ps
CPU time 611.19 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:40:16 PM PDT 24
Peak memory 200212 kb
Host smart-0bfd797e-2385-46ff-9ab7-004c463c3e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362042849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2362042849
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1180469095
Short name T371
Test name
Test status
Simulation time 6586292317 ps
CPU time 6.4 seconds
Started Jul 27 06:30:05 PM PDT 24
Finished Jul 27 06:30:11 PM PDT 24
Peak memory 199384 kb
Host smart-66fcd203-d8cd-46d7-a422-79b885882885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180469095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1180469095
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1231517771
Short name T463
Test name
Test status
Simulation time 18264018614 ps
CPU time 25.63 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:30:30 PM PDT 24
Peak memory 198304 kb
Host smart-f780461e-d0bb-4182-a227-70ceddb1cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231517771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1231517771
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.823172480
Short name T758
Test name
Test status
Simulation time 8396111252 ps
CPU time 358.99 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:36:03 PM PDT 24
Peak memory 200164 kb
Host smart-05a1174d-09c8-4226-a1eb-634ae83393bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823172480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.823172480
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.4274264215
Short name T363
Test name
Test status
Simulation time 1506094632 ps
CPU time 1.85 seconds
Started Jul 27 06:30:05 PM PDT 24
Finished Jul 27 06:30:07 PM PDT 24
Peak memory 198192 kb
Host smart-2ed7b1cc-d393-4d77-8304-7eb59a700c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274264215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4274264215
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.350270684
Short name T248
Test name
Test status
Simulation time 16735731320 ps
CPU time 30.38 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:33 PM PDT 24
Peak memory 200204 kb
Host smart-84a3360e-0a86-43ce-b7d7-0023abd5351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350270684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.350270684
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1849028896
Short name T468
Test name
Test status
Simulation time 4457369414 ps
CPU time 3.61 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:07 PM PDT 24
Peak memory 196524 kb
Host smart-ad2ec13f-8e91-4264-9bad-bf131c6d33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849028896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1849028896
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2615639376
Short name T1015
Test name
Test status
Simulation time 690044467 ps
CPU time 1.48 seconds
Started Jul 27 06:29:55 PM PDT 24
Finished Jul 27 06:29:56 PM PDT 24
Peak memory 200116 kb
Host smart-f1fa41f2-1642-43ee-8238-49a3e65ade43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615639376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2615639376
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1359321864
Short name T191
Test name
Test status
Simulation time 114725812384 ps
CPU time 199.51 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:33:24 PM PDT 24
Peak memory 200196 kb
Host smart-4c8a2a9a-ffed-4d2d-8d6c-5abbbd5d724f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359321864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1359321864
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3396810496
Short name T810
Test name
Test status
Simulation time 28545284508 ps
CPU time 416.83 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:37:01 PM PDT 24
Peak memory 214940 kb
Host smart-6518863b-655b-48e8-8159-e73af0651a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396810496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3396810496
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1035269239
Short name T744
Test name
Test status
Simulation time 1246710993 ps
CPU time 4.12 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:07 PM PDT 24
Peak memory 198520 kb
Host smart-bb89f668-d7fe-4aea-9ebc-4daea1ae2973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035269239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1035269239
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3069624368
Short name T382
Test name
Test status
Simulation time 16373389921 ps
CPU time 27.19 seconds
Started Jul 27 06:29:52 PM PDT 24
Finished Jul 27 06:30:20 PM PDT 24
Peak memory 200212 kb
Host smart-0275a778-7b99-444a-9d3a-7ee5c201fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069624368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3069624368
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.602472901
Short name T462
Test name
Test status
Simulation time 14604417 ps
CPU time 0.57 seconds
Started Jul 27 06:30:15 PM PDT 24
Finished Jul 27 06:30:16 PM PDT 24
Peak memory 195856 kb
Host smart-4a8087da-d65c-4c53-91da-b6e09ee10966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602472901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.602472901
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1130223608
Short name T931
Test name
Test status
Simulation time 151665061991 ps
CPU time 342.03 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:35:45 PM PDT 24
Peak memory 200172 kb
Host smart-283e8807-703b-463e-b82e-2f3367867224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130223608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1130223608
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3886275000
Short name T100
Test name
Test status
Simulation time 182655159153 ps
CPU time 50.23 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:54 PM PDT 24
Peak memory 200152 kb
Host smart-c371819e-8522-4066-a989-99114b9734b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886275000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3886275000
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3715954111
Short name T952
Test name
Test status
Simulation time 17930008963 ps
CPU time 31.74 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:30:36 PM PDT 24
Peak memory 200232 kb
Host smart-c1ca9862-33c6-4c7f-a143-1a28e772a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715954111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3715954111
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.165492430
Short name T704
Test name
Test status
Simulation time 26384829962 ps
CPU time 18.08 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:21 PM PDT 24
Peak memory 198980 kb
Host smart-cb0a7d40-3db1-4154-8a9d-6425a3b4fe1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165492430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.165492430
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1394078318
Short name T1020
Test name
Test status
Simulation time 113341089788 ps
CPU time 318.66 seconds
Started Jul 27 06:30:12 PM PDT 24
Finished Jul 27 06:35:31 PM PDT 24
Peak memory 200240 kb
Host smart-c438da0f-1120-47de-9354-6a705e076527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394078318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1394078318
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.98079624
Short name T344
Test name
Test status
Simulation time 7781752261 ps
CPU time 9.9 seconds
Started Jul 27 06:30:16 PM PDT 24
Finished Jul 27 06:30:26 PM PDT 24
Peak memory 199636 kb
Host smart-e2868495-eb1f-4734-9ea7-71a54e81f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98079624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.98079624
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2075047417
Short name T466
Test name
Test status
Simulation time 65686296478 ps
CPU time 58.08 seconds
Started Jul 27 06:30:15 PM PDT 24
Finished Jul 27 06:31:13 PM PDT 24
Peak memory 208160 kb
Host smart-391b41ac-d171-4ee5-8903-a756d1dc8fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075047417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2075047417
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3790303294
Short name T737
Test name
Test status
Simulation time 10725993301 ps
CPU time 290.53 seconds
Started Jul 27 06:30:12 PM PDT 24
Finished Jul 27 06:35:03 PM PDT 24
Peak memory 200196 kb
Host smart-a5b16b5e-834a-49b5-80f2-970ca2d65b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790303294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3790303294
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3379971684
Short name T714
Test name
Test status
Simulation time 5918829602 ps
CPU time 53.61 seconds
Started Jul 27 06:30:03 PM PDT 24
Finished Jul 27 06:30:57 PM PDT 24
Peak memory 198452 kb
Host smart-be406fdc-3d59-4854-84b6-e7180ca51351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379971684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3379971684
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3095133734
Short name T920
Test name
Test status
Simulation time 35982091993 ps
CPU time 93.55 seconds
Started Jul 27 06:30:13 PM PDT 24
Finished Jul 27 06:31:47 PM PDT 24
Peak memory 200224 kb
Host smart-7d7adc82-37d2-4233-a2c4-3f81c8e7200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095133734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3095133734
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3147872925
Short name T590
Test name
Test status
Simulation time 1861015698 ps
CPU time 3.74 seconds
Started Jul 27 06:30:16 PM PDT 24
Finished Jul 27 06:30:20 PM PDT 24
Peak memory 195692 kb
Host smart-8a2be945-3b6a-4cda-9734-0c6531e6a24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147872925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3147872925
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1954859534
Short name T962
Test name
Test status
Simulation time 808551819 ps
CPU time 1.23 seconds
Started Jul 27 06:30:04 PM PDT 24
Finished Jul 27 06:30:05 PM PDT 24
Peak memory 200100 kb
Host smart-f399902e-2c43-465f-8c7a-ebe44e1efa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954859534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1954859534
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1020673177
Short name T279
Test name
Test status
Simulation time 188701693567 ps
CPU time 1136.65 seconds
Started Jul 27 06:30:13 PM PDT 24
Finished Jul 27 06:49:09 PM PDT 24
Peak memory 208564 kb
Host smart-73e15969-820d-4295-9bd3-3344030bc1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020673177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1020673177
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1481937997
Short name T877
Test name
Test status
Simulation time 216016496553 ps
CPU time 588.61 seconds
Started Jul 27 06:30:13 PM PDT 24
Finished Jul 27 06:40:02 PM PDT 24
Peak memory 216912 kb
Host smart-3caa2b6f-e35a-4ae9-80ed-7292c58e9119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481937997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1481937997
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.297439006
Short name T300
Test name
Test status
Simulation time 1282187186 ps
CPU time 3.92 seconds
Started Jul 27 06:30:14 PM PDT 24
Finished Jul 27 06:30:18 PM PDT 24
Peak memory 199160 kb
Host smart-cd307b3b-81c0-4365-af9b-ec8febe18ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297439006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.297439006
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.82418315
Short name T846
Test name
Test status
Simulation time 5085749548 ps
CPU time 7.65 seconds
Started Jul 27 06:30:08 PM PDT 24
Finished Jul 27 06:30:16 PM PDT 24
Peak memory 198148 kb
Host smart-3530f437-f6e7-4a17-9a4f-ad5792fe89d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82418315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.82418315
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1959477620
Short name T358
Test name
Test status
Simulation time 28618248 ps
CPU time 0.56 seconds
Started Jul 27 06:23:34 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 195624 kb
Host smart-27b3f2ec-1a1a-4e13-8bbe-41fde3267fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959477620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1959477620
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2032908437
Short name T830
Test name
Test status
Simulation time 54812385277 ps
CPU time 89.33 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:24:51 PM PDT 24
Peak memory 200224 kb
Host smart-4fa7b71d-6325-446f-a98b-8cd87eb88f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032908437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2032908437
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1180810062
Short name T769
Test name
Test status
Simulation time 16010878225 ps
CPU time 24.86 seconds
Started Jul 27 06:23:22 PM PDT 24
Finished Jul 27 06:23:47 PM PDT 24
Peak memory 200200 kb
Host smart-6bcb4e9f-023a-4f9a-9962-70d4ce322ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180810062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1180810062
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3364876729
Short name T606
Test name
Test status
Simulation time 76703007867 ps
CPU time 118 seconds
Started Jul 27 06:23:24 PM PDT 24
Finished Jul 27 06:25:22 PM PDT 24
Peak memory 200212 kb
Host smart-c68e8f6b-64aa-4e97-85f9-bbac6fb3b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364876729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3364876729
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.564434762
Short name T107
Test name
Test status
Simulation time 57479813120 ps
CPU time 32.39 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:24:02 PM PDT 24
Peak memory 200220 kb
Host smart-fd1c048d-3806-47d1-afed-1c7425eff020
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564434762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.564434762
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3195157580
Short name T1064
Test name
Test status
Simulation time 98298908469 ps
CPU time 340.4 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:29:10 PM PDT 24
Peak memory 200228 kb
Host smart-e75b9668-155e-40e2-84d1-c58081078c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195157580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3195157580
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.914997463
Short name T324
Test name
Test status
Simulation time 3369443510 ps
CPU time 2.4 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 199060 kb
Host smart-f56f1717-4c97-4e2a-9848-13065d61cd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914997463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.914997463
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3716356884
Short name T1043
Test name
Test status
Simulation time 75854441836 ps
CPU time 213.24 seconds
Started Jul 27 06:23:29 PM PDT 24
Finished Jul 27 06:27:02 PM PDT 24
Peak memory 199804 kb
Host smart-5626a9ad-3ba6-4d37-9d83-82bdf226bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716356884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3716356884
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3321794707
Short name T42
Test name
Test status
Simulation time 17723439517 ps
CPU time 649.71 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:34:22 PM PDT 24
Peak memory 200160 kb
Host smart-da1a51e5-26f7-48d9-af96-26e01d2ea061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321794707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3321794707
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3509759437
Short name T827
Test name
Test status
Simulation time 1619406246 ps
CPU time 2.48 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 199132 kb
Host smart-88d1dc3b-84fd-4b5b-9782-a0f8c989e1e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509759437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3509759437
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3913803185
Short name T1136
Test name
Test status
Simulation time 26656166747 ps
CPU time 11.17 seconds
Started Jul 27 06:23:38 PM PDT 24
Finished Jul 27 06:23:49 PM PDT 24
Peak memory 199932 kb
Host smart-25eb1afc-cdaf-47b8-9d8c-44f3ff24b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913803185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3913803185
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2919372361
Short name T346
Test name
Test status
Simulation time 1683896785 ps
CPU time 1.29 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 195712 kb
Host smart-ba7c5e2a-bc15-4650-822b-f4730ea8508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919372361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2919372361
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3762156263
Short name T934
Test name
Test status
Simulation time 471522663 ps
CPU time 1.34 seconds
Started Jul 27 06:23:20 PM PDT 24
Finished Jul 27 06:23:21 PM PDT 24
Peak memory 198516 kb
Host smart-77dbc15b-454d-4681-84e7-0bf0f681e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762156263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3762156263
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2981812972
Short name T780
Test name
Test status
Simulation time 108214577258 ps
CPU time 188.16 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:26:41 PM PDT 24
Peak memory 200160 kb
Host smart-5d092630-5a2f-41db-a08b-a1cd841ce155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981812972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2981812972
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3542853114
Short name T92
Test name
Test status
Simulation time 95327382637 ps
CPU time 232.39 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:27:23 PM PDT 24
Peak memory 216660 kb
Host smart-574d0b0b-97ea-4e37-ae19-b9033ab04e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542853114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3542853114
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.375983755
Short name T414
Test name
Test status
Simulation time 2277018400 ps
CPU time 1.7 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:34 PM PDT 24
Peak memory 198924 kb
Host smart-758b7acd-bfe3-43d4-b8b2-908298d39510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375983755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.375983755
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.336828094
Short name T454
Test name
Test status
Simulation time 24880191852 ps
CPU time 39.03 seconds
Started Jul 27 06:23:21 PM PDT 24
Finished Jul 27 06:24:00 PM PDT 24
Peak memory 200172 kb
Host smart-4d4d2171-08c4-4589-bc53-744093b24508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336828094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.336828094
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1907640411
Short name T732
Test name
Test status
Simulation time 38322006873 ps
CPU time 29.09 seconds
Started Jul 27 06:30:15 PM PDT 24
Finished Jul 27 06:30:44 PM PDT 24
Peak memory 200080 kb
Host smart-df670bd6-6835-47b7-b7bc-381b6a0b1def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907640411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1907640411
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2447077174
Short name T631
Test name
Test status
Simulation time 48365586325 ps
CPU time 71.62 seconds
Started Jul 27 06:30:14 PM PDT 24
Finished Jul 27 06:31:25 PM PDT 24
Peak memory 200168 kb
Host smart-00eb5a34-2d73-419b-ae80-a521339a3269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447077174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2447077174
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.811541067
Short name T187
Test name
Test status
Simulation time 30719607966 ps
CPU time 50.14 seconds
Started Jul 27 06:30:15 PM PDT 24
Finished Jul 27 06:31:05 PM PDT 24
Peak memory 200128 kb
Host smart-214a82d7-a859-4bd3-bfde-484b04af246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811541067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.811541067
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.219093716
Short name T512
Test name
Test status
Simulation time 43755376287 ps
CPU time 389.43 seconds
Started Jul 27 06:30:14 PM PDT 24
Finished Jul 27 06:36:44 PM PDT 24
Peak memory 216884 kb
Host smart-3d668658-a208-4d32-b69e-61ac90bee2d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219093716 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.219093716
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.808072595
Short name T823
Test name
Test status
Simulation time 19653043780 ps
CPU time 26.48 seconds
Started Jul 27 06:30:13 PM PDT 24
Finished Jul 27 06:30:39 PM PDT 24
Peak memory 200144 kb
Host smart-e03f7a34-6015-4e29-9c36-4af77ad8a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808072595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.808072595
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2091967060
Short name T119
Test name
Test status
Simulation time 124653019321 ps
CPU time 207.02 seconds
Started Jul 27 06:30:16 PM PDT 24
Finished Jul 27 06:33:43 PM PDT 24
Peak memory 199620 kb
Host smart-115264c1-0e1c-48a2-8fdf-4cb90fcf9ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091967060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2091967060
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2458960446
Short name T513
Test name
Test status
Simulation time 55939097471 ps
CPU time 357.45 seconds
Started Jul 27 06:30:15 PM PDT 24
Finished Jul 27 06:36:13 PM PDT 24
Peak memory 216752 kb
Host smart-fd43614f-9404-44cc-883c-1a651eb4e2c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458960446 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2458960446
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1317852257
Short name T306
Test name
Test status
Simulation time 254278587370 ps
CPU time 96.69 seconds
Started Jul 27 06:30:14 PM PDT 24
Finished Jul 27 06:31:51 PM PDT 24
Peak memory 200160 kb
Host smart-1b748e4c-0cb5-4e74-bc60-34ed3e4cbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317852257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1317852257
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2775094309
Short name T390
Test name
Test status
Simulation time 220732237942 ps
CPU time 1205.98 seconds
Started Jul 27 06:30:12 PM PDT 24
Finished Jul 27 06:50:19 PM PDT 24
Peak memory 225032 kb
Host smart-bb374862-921a-47b9-a7a7-63b65ae2559e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775094309 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2775094309
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1760999614
Short name T1141
Test name
Test status
Simulation time 36241944969 ps
CPU time 30.55 seconds
Started Jul 27 06:30:22 PM PDT 24
Finished Jul 27 06:30:52 PM PDT 24
Peak memory 200164 kb
Host smart-a7037ef0-d774-4cda-b97f-226178f974c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760999614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1760999614
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.326353958
Short name T926
Test name
Test status
Simulation time 163496424553 ps
CPU time 411.3 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:37:13 PM PDT 24
Peak memory 200220 kb
Host smart-ae38f5a4-9bdb-47ca-9995-bef38cf8e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326353958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.326353958
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.671656800
Short name T645
Test name
Test status
Simulation time 221203041418 ps
CPU time 617.39 seconds
Started Jul 27 06:30:20 PM PDT 24
Finished Jul 27 06:40:38 PM PDT 24
Peak memory 216748 kb
Host smart-706f3664-54aa-4a59-b9ee-92ada1f45e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671656800 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.671656800
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1337983187
Short name T137
Test name
Test status
Simulation time 163280578146 ps
CPU time 36.27 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:30:58 PM PDT 24
Peak memory 200108 kb
Host smart-881211b6-d31c-4a46-9a9d-759d29909b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337983187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1337983187
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1128592060
Short name T564
Test name
Test status
Simulation time 238592402121 ps
CPU time 624.05 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:40:45 PM PDT 24
Peak memory 230304 kb
Host smart-d5c1a0e2-438f-488d-9ebb-888eb28e11cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128592060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1128592060
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1785537465
Short name T113
Test name
Test status
Simulation time 199022718758 ps
CPU time 36.47 seconds
Started Jul 27 06:30:22 PM PDT 24
Finished Jul 27 06:30:59 PM PDT 24
Peak memory 200144 kb
Host smart-cdd2ac88-3dc2-4c38-a885-aff8e4c409b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785537465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1785537465
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1602408026
Short name T636
Test name
Test status
Simulation time 34848929 ps
CPU time 0.56 seconds
Started Jul 27 06:23:34 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 195872 kb
Host smart-dde99807-25cc-4765-9895-df3fb3db60ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602408026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1602408026
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.241873897
Short name T671
Test name
Test status
Simulation time 73803481274 ps
CPU time 50.7 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:24:22 PM PDT 24
Peak memory 200184 kb
Host smart-2665e22c-6659-4311-a11d-8beb908d00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241873897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.241873897
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2973662359
Short name T6
Test name
Test status
Simulation time 76743260768 ps
CPU time 115.71 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:25:25 PM PDT 24
Peak memory 200132 kb
Host smart-4cc823a9-a8c6-4792-bb6b-928b0287212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973662359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2973662359
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1400845927
Short name T1149
Test name
Test status
Simulation time 139483866569 ps
CPU time 12.02 seconds
Started Jul 27 06:23:35 PM PDT 24
Finished Jul 27 06:23:47 PM PDT 24
Peak memory 200032 kb
Host smart-27514502-a042-47b8-9beb-16c5c179f300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400845927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1400845927
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3860716272
Short name T317
Test name
Test status
Simulation time 221678490399 ps
CPU time 307.12 seconds
Started Jul 27 06:23:31 PM PDT 24
Finished Jul 27 06:28:38 PM PDT 24
Peak memory 200216 kb
Host smart-23455f8d-d06e-41b3-b621-a3e280bb6e55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860716272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3860716272
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.231422541
Short name T860
Test name
Test status
Simulation time 80032925369 ps
CPU time 413.26 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:30:26 PM PDT 24
Peak memory 200236 kb
Host smart-7d11440f-42fa-46f0-9a29-ec146c219c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231422541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.231422541
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3210836932
Short name T525
Test name
Test status
Simulation time 8845012976 ps
CPU time 5.02 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:23:35 PM PDT 24
Peak memory 199836 kb
Host smart-7f44700a-a9b8-4e5b-9b51-f1bf2b58703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210836932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3210836932
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4042624829
Short name T560
Test name
Test status
Simulation time 122193074889 ps
CPU time 115.91 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:25:30 PM PDT 24
Peak memory 200388 kb
Host smart-7847d85a-b482-425d-b989-17eb390ac455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042624829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4042624829
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.52920693
Short name T995
Test name
Test status
Simulation time 14522253931 ps
CPU time 185.09 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:26:38 PM PDT 24
Peak memory 200244 kb
Host smart-a6476298-9dae-4826-a1fd-34f661cf1506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52920693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.52920693
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.184519784
Short name T914
Test name
Test status
Simulation time 5482667823 ps
CPU time 46.14 seconds
Started Jul 27 06:23:31 PM PDT 24
Finished Jul 27 06:24:17 PM PDT 24
Peak memory 199488 kb
Host smart-873551af-6a51-4ccc-b97e-eff698b1125f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184519784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.184519784
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3198890832
Short name T905
Test name
Test status
Simulation time 33425343804 ps
CPU time 13.88 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:23:47 PM PDT 24
Peak memory 199492 kb
Host smart-b21d3cc1-2173-46a4-b2b9-3b44eaaf6ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198890832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3198890832
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3963592782
Short name T929
Test name
Test status
Simulation time 36872947780 ps
CPU time 50.57 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:24:21 PM PDT 24
Peak memory 196344 kb
Host smart-c153fcd1-f917-4b2a-b6e4-c53c126e8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963592782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3963592782
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.707247971
Short name T354
Test name
Test status
Simulation time 103319660 ps
CPU time 1.13 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:23:31 PM PDT 24
Peak memory 198784 kb
Host smart-93088f0f-a14a-445d-ace0-967ea4135507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707247971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.707247971
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2744898393
Short name T888
Test name
Test status
Simulation time 578884251116 ps
CPU time 492.01 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:31:44 PM PDT 24
Peak memory 200152 kb
Host smart-fdb1073b-916b-4322-bd11-4fa5535e87d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744898393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2744898393
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1653771070
Short name T982
Test name
Test status
Simulation time 32432790163 ps
CPU time 280.67 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:28:14 PM PDT 24
Peak memory 208564 kb
Host smart-a2714017-38f3-4e59-8117-256e16cfb9ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653771070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1653771070
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3403748855
Short name T404
Test name
Test status
Simulation time 1517627740 ps
CPU time 3.63 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:36 PM PDT 24
Peak memory 200008 kb
Host smart-299b7456-0560-4f22-a3af-5c2a4db6aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403748855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3403748855
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1199579954
Short name T1029
Test name
Test status
Simulation time 61162576231 ps
CPU time 26.28 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:58 PM PDT 24
Peak memory 199988 kb
Host smart-01fae28e-7efd-4eb0-98cc-879b13857bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199579954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1199579954
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.726645286
Short name T872
Test name
Test status
Simulation time 74681217126 ps
CPU time 677.71 seconds
Started Jul 27 06:30:24 PM PDT 24
Finished Jul 27 06:41:42 PM PDT 24
Peak memory 213636 kb
Host smart-01ba0605-a63c-4242-b8c9-31a2ef2467fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726645286 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.726645286
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1796462161
Short name T1079
Test name
Test status
Simulation time 6741228582 ps
CPU time 10.72 seconds
Started Jul 27 06:30:22 PM PDT 24
Finished Jul 27 06:30:32 PM PDT 24
Peak memory 200024 kb
Host smart-4f4ab87a-8187-4c96-8bc2-baa0a86bc005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796462161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1796462161
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1933970607
Short name T321
Test name
Test status
Simulation time 127939782813 ps
CPU time 650.65 seconds
Started Jul 27 06:30:23 PM PDT 24
Finished Jul 27 06:41:14 PM PDT 24
Peak memory 224948 kb
Host smart-7261db4b-25ea-4930-8d8f-f5be16af8931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933970607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1933970607
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4184447876
Short name T1101
Test name
Test status
Simulation time 7659371319 ps
CPU time 7.2 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:30:28 PM PDT 24
Peak memory 200168 kb
Host smart-e5d80b08-820c-4514-8a6e-6129bc10aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184447876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4184447876
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1856547117
Short name T1124
Test name
Test status
Simulation time 22557113269 ps
CPU time 20.49 seconds
Started Jul 27 06:30:21 PM PDT 24
Finished Jul 27 06:30:42 PM PDT 24
Peak memory 200196 kb
Host smart-9d8a493b-46e9-4222-b3a7-768160cf5396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856547117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1856547117
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3051166228
Short name T48
Test name
Test status
Simulation time 71733977895 ps
CPU time 628.18 seconds
Started Jul 27 06:30:31 PM PDT 24
Finished Jul 27 06:40:59 PM PDT 24
Peak memory 216744 kb
Host smart-3dfb94ca-ff2e-458d-81d9-ac0d28380c88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051166228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3051166228
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.627823662
Short name T1032
Test name
Test status
Simulation time 41572880950 ps
CPU time 71.38 seconds
Started Jul 27 06:30:30 PM PDT 24
Finished Jul 27 06:31:42 PM PDT 24
Peak memory 200104 kb
Host smart-34fb4513-8d44-4cbe-82d0-0b665729e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627823662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.627823662
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.108546291
Short name T14
Test name
Test status
Simulation time 45017520460 ps
CPU time 154.68 seconds
Started Jul 27 06:30:31 PM PDT 24
Finished Jul 27 06:33:06 PM PDT 24
Peak memory 216704 kb
Host smart-a78b3775-a963-40df-9ab9-457d1434195b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108546291 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.108546291
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.281276898
Short name T963
Test name
Test status
Simulation time 9197559925 ps
CPU time 15.48 seconds
Started Jul 27 06:30:33 PM PDT 24
Finished Jul 27 06:30:49 PM PDT 24
Peak memory 200212 kb
Host smart-cb824722-9755-40bb-8d94-c5ed5f1ad24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281276898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.281276898
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.771780269
Short name T52
Test name
Test status
Simulation time 135008990308 ps
CPU time 351.18 seconds
Started Jul 27 06:30:32 PM PDT 24
Finished Jul 27 06:36:23 PM PDT 24
Peak memory 216768 kb
Host smart-3021fccf-52f2-4f80-b73c-fe93a3ddfef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771780269 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.771780269
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3372781913
Short name T808
Test name
Test status
Simulation time 88568678220 ps
CPU time 140.26 seconds
Started Jul 27 06:30:33 PM PDT 24
Finished Jul 27 06:32:53 PM PDT 24
Peak memory 200092 kb
Host smart-cbb7a58b-566a-4e9f-9c31-0c48c683ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372781913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3372781913
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3718495107
Short name T911
Test name
Test status
Simulation time 101574861252 ps
CPU time 746.71 seconds
Started Jul 27 06:30:32 PM PDT 24
Finished Jul 27 06:42:59 PM PDT 24
Peak memory 214416 kb
Host smart-2e988c9d-39dc-4656-bd24-7e292ebe7213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718495107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3718495107
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1990663073
Short name T630
Test name
Test status
Simulation time 128243309658 ps
CPU time 761.86 seconds
Started Jul 27 06:30:32 PM PDT 24
Finished Jul 27 06:43:14 PM PDT 24
Peak memory 216688 kb
Host smart-05da163a-d0f7-48c0-b6ce-9f9227f59feb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990663073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1990663073
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1629416416
Short name T850
Test name
Test status
Simulation time 8765495924 ps
CPU time 12.8 seconds
Started Jul 27 06:30:31 PM PDT 24
Finished Jul 27 06:30:44 PM PDT 24
Peak memory 200124 kb
Host smart-8f55d7a3-8ee7-4a4a-b35b-ee1a1d00ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629416416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1629416416
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1960481763
Short name T1077
Test name
Test status
Simulation time 71665546063 ps
CPU time 388.04 seconds
Started Jul 27 06:30:31 PM PDT 24
Finished Jul 27 06:36:59 PM PDT 24
Peak memory 216744 kb
Host smart-f7284142-d766-4238-8a8e-b62410fb84b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960481763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1960481763
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1792232102
Short name T476
Test name
Test status
Simulation time 32100944868 ps
CPU time 29.56 seconds
Started Jul 27 06:30:35 PM PDT 24
Finished Jul 27 06:31:05 PM PDT 24
Peak memory 199724 kb
Host smart-0dd53128-daec-4f17-97b4-90450fb35160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792232102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1792232102
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2142072909
Short name T443
Test name
Test status
Simulation time 15114135730 ps
CPU time 188 seconds
Started Jul 27 06:30:35 PM PDT 24
Finished Jul 27 06:33:44 PM PDT 24
Peak memory 209976 kb
Host smart-a79efbc7-b3e4-4fdc-aa83-0d3dba57f256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142072909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2142072909
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2668450576
Short name T658
Test name
Test status
Simulation time 60955483 ps
CPU time 0.57 seconds
Started Jul 27 06:23:40 PM PDT 24
Finished Jul 27 06:23:41 PM PDT 24
Peak memory 195624 kb
Host smart-e9d47b24-f594-48e7-ae17-dfd3244887ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668450576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2668450576
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1856059837
Short name T506
Test name
Test status
Simulation time 48302223762 ps
CPU time 39.61 seconds
Started Jul 27 06:23:29 PM PDT 24
Finished Jul 27 06:24:09 PM PDT 24
Peak memory 200196 kb
Host smart-9cfa1ed6-66f8-42e4-a1a2-aa3b5ad9ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856059837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1856059837
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2680170445
Short name T654
Test name
Test status
Simulation time 191991781633 ps
CPU time 66.18 seconds
Started Jul 27 06:23:34 PM PDT 24
Finished Jul 27 06:24:41 PM PDT 24
Peak memory 200216 kb
Host smart-60916de2-3b47-4302-992a-e665dc95d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680170445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2680170445
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2939341192
Short name T1072
Test name
Test status
Simulation time 92185101926 ps
CPU time 19.57 seconds
Started Jul 27 06:23:35 PM PDT 24
Finished Jul 27 06:23:54 PM PDT 24
Peak memory 200220 kb
Host smart-2100fd66-dd45-496e-9b0a-d1d3462b85dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939341192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2939341192
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1841570311
Short name T531
Test name
Test status
Simulation time 4144540481 ps
CPU time 7.48 seconds
Started Jul 27 06:23:26 PM PDT 24
Finished Jul 27 06:23:33 PM PDT 24
Peak memory 200140 kb
Host smart-738dea25-6a36-4c1b-814f-432e578f46ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841570311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1841570311
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.684316896
Short name T1159
Test name
Test status
Simulation time 79799365691 ps
CPU time 465.99 seconds
Started Jul 27 06:23:40 PM PDT 24
Finished Jul 27 06:31:26 PM PDT 24
Peak memory 200152 kb
Host smart-b73d10a5-4a7c-428c-b805-e185749951c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684316896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.684316896
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2831110734
Short name T1084
Test name
Test status
Simulation time 7375568994 ps
CPU time 8.32 seconds
Started Jul 27 06:23:29 PM PDT 24
Finished Jul 27 06:23:38 PM PDT 24
Peak memory 199884 kb
Host smart-d45bb21e-787e-494d-a19c-6a27057ea7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831110734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2831110734
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1651122839
Short name T258
Test name
Test status
Simulation time 349107686587 ps
CPU time 32.05 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:24:05 PM PDT 24
Peak memory 199840 kb
Host smart-a5996591-6bdb-4a8b-9ddd-9da12a066f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651122839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1651122839
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2130927149
Short name T604
Test name
Test status
Simulation time 9223658083 ps
CPU time 472.62 seconds
Started Jul 27 06:23:31 PM PDT 24
Finished Jul 27 06:31:24 PM PDT 24
Peak memory 200280 kb
Host smart-e0899113-0c82-466f-928b-29962af29d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130927149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2130927149
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3393549766
Short name T1083
Test name
Test status
Simulation time 7113460941 ps
CPU time 63.4 seconds
Started Jul 27 06:23:30 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 198372 kb
Host smart-285892a5-3ea9-49a1-9ea4-4b99d2dd1122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393549766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3393549766
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2483116548
Short name T666
Test name
Test status
Simulation time 163161638734 ps
CPU time 100.49 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:25:13 PM PDT 24
Peak memory 200136 kb
Host smart-c0e0face-9ace-4756-8e26-eee881b24a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483116548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2483116548
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2780630302
Short name T915
Test name
Test status
Simulation time 5077334441 ps
CPU time 1.03 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:23:34 PM PDT 24
Peak memory 197080 kb
Host smart-d52f41c6-4898-4f34-bcb0-b7a996c7ffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780630302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2780630302
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4182449606
Short name T975
Test name
Test status
Simulation time 502493159 ps
CPU time 1.56 seconds
Started Jul 27 06:23:38 PM PDT 24
Finished Jul 27 06:23:39 PM PDT 24
Peak memory 199984 kb
Host smart-38e93588-bd9e-4519-85bb-30b72deb4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182449606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4182449606
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1839720568
Short name T619
Test name
Test status
Simulation time 265018679443 ps
CPU time 118.63 seconds
Started Jul 27 06:23:44 PM PDT 24
Finished Jul 27 06:25:42 PM PDT 24
Peak memory 208476 kb
Host smart-7cc9bb72-5a1a-487e-a857-7fe7027f9344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839720568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1839720568
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.378291737
Short name T867
Test name
Test status
Simulation time 34516896800 ps
CPU time 108.15 seconds
Started Jul 27 06:23:50 PM PDT 24
Finished Jul 27 06:25:38 PM PDT 24
Peak memory 212492 kb
Host smart-ee36d4b9-9672-49ad-8db0-b21e9cf46707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378291737 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.378291737
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2906248567
Short name T304
Test name
Test status
Simulation time 425143494 ps
CPU time 1.33 seconds
Started Jul 27 06:23:32 PM PDT 24
Finished Jul 27 06:23:34 PM PDT 24
Peak memory 197476 kb
Host smart-cf7a1d1a-984f-4c48-b272-e6817a20963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906248567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2906248567
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.408669443
Short name T33
Test name
Test status
Simulation time 121041616786 ps
CPU time 41.33 seconds
Started Jul 27 06:23:33 PM PDT 24
Finished Jul 27 06:24:15 PM PDT 24
Peak memory 200200 kb
Host smart-ef89a1f6-61d3-4d5a-afcf-0261a232e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408669443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.408669443
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2886396838
Short name T229
Test name
Test status
Simulation time 35135270134 ps
CPU time 60.15 seconds
Started Jul 27 06:30:31 PM PDT 24
Finished Jul 27 06:31:31 PM PDT 24
Peak memory 200204 kb
Host smart-a06a5a47-a604-42e3-8806-8b1b0939c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886396838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2886396838
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4057028337
Short name T96
Test name
Test status
Simulation time 187171628633 ps
CPU time 829.5 seconds
Started Jul 27 06:30:33 PM PDT 24
Finished Jul 27 06:44:23 PM PDT 24
Peak memory 216328 kb
Host smart-c9651f3f-9a90-497f-ab68-604487111dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057028337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4057028337
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3050900371
Short name T225
Test name
Test status
Simulation time 33092811605 ps
CPU time 16.64 seconds
Started Jul 27 06:30:35 PM PDT 24
Finished Jul 27 06:30:51 PM PDT 24
Peak memory 200224 kb
Host smart-9a2d4fc1-fb7a-4bc1-aae0-d57ae3629a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050900371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3050900371
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.464989437
Short name T47
Test name
Test status
Simulation time 318680219862 ps
CPU time 1781.55 seconds
Started Jul 27 06:30:29 PM PDT 24
Finished Jul 27 07:00:11 PM PDT 24
Peak memory 242372 kb
Host smart-7201a333-3622-4453-a7ae-0d379bbc5cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464989437 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.464989437
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2022887467
Short name T1038
Test name
Test status
Simulation time 27945185227 ps
CPU time 19.39 seconds
Started Jul 27 06:30:30 PM PDT 24
Finished Jul 27 06:30:50 PM PDT 24
Peak memory 200100 kb
Host smart-285f913b-b8b9-499b-9d17-ccaf7a7ac4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022887467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2022887467
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.195004277
Short name T549
Test name
Test status
Simulation time 21189115268 ps
CPU time 226.01 seconds
Started Jul 27 06:30:40 PM PDT 24
Finished Jul 27 06:34:26 PM PDT 24
Peak memory 210536 kb
Host smart-090a1f83-688a-4471-8100-5a65e7b678d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195004277 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.195004277
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.279569148
Short name T280
Test name
Test status
Simulation time 263691642783 ps
CPU time 115.23 seconds
Started Jul 27 06:30:42 PM PDT 24
Finished Jul 27 06:32:37 PM PDT 24
Peak memory 200232 kb
Host smart-a4ef60a0-42b5-479a-8350-c55b229a703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279569148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.279569148
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.910878178
Short name T277
Test name
Test status
Simulation time 51001016171 ps
CPU time 271.34 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:35:13 PM PDT 24
Peak memory 216220 kb
Host smart-da29f6de-f04b-4fcf-b1c0-8edc244eb5e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910878178 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.910878178
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1451381642
Short name T1071
Test name
Test status
Simulation time 44046155828 ps
CPU time 137.74 seconds
Started Jul 27 06:30:42 PM PDT 24
Finished Jul 27 06:33:00 PM PDT 24
Peak memory 200264 kb
Host smart-be981cf7-81ff-420b-a152-656a9be5efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451381642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1451381642
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1234430451
Short name T169
Test name
Test status
Simulation time 198423007865 ps
CPU time 411.46 seconds
Started Jul 27 06:30:40 PM PDT 24
Finished Jul 27 06:37:32 PM PDT 24
Peak memory 216740 kb
Host smart-06fd54df-1322-4831-8a25-ecc8a0121bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234430451 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1234430451
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.779294987
Short name T1060
Test name
Test status
Simulation time 35283218292 ps
CPU time 129.56 seconds
Started Jul 27 06:30:38 PM PDT 24
Finished Jul 27 06:32:48 PM PDT 24
Peak memory 200188 kb
Host smart-6976ee04-1e5e-4741-9fc2-c3e24f19ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779294987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.779294987
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3736356662
Short name T95
Test name
Test status
Simulation time 81454261863 ps
CPU time 263.97 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:35:05 PM PDT 24
Peak memory 208668 kb
Host smart-d0d2de02-d827-4291-8c16-7940df750b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736356662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3736356662
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.308447726
Short name T536
Test name
Test status
Simulation time 249758689525 ps
CPU time 56.94 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:31:38 PM PDT 24
Peak memory 200184 kb
Host smart-5d66381d-f841-4a45-867e-163ba43892cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308447726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.308447726
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2813827295
Short name T608
Test name
Test status
Simulation time 33246122466 ps
CPU time 199.16 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:34:00 PM PDT 24
Peak memory 216888 kb
Host smart-6cfb7d8b-57a7-41a4-8981-f3961aef89d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813827295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2813827295
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.972058463
Short name T930
Test name
Test status
Simulation time 92563109585 ps
CPU time 138.8 seconds
Started Jul 27 06:30:40 PM PDT 24
Finished Jul 27 06:32:59 PM PDT 24
Peak memory 200232 kb
Host smart-ba6c463d-87c8-469f-a650-6af0683bf67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972058463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.972058463
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1867701913
Short name T681
Test name
Test status
Simulation time 71052658021 ps
CPU time 48.09 seconds
Started Jul 27 06:30:40 PM PDT 24
Finished Jul 27 06:31:28 PM PDT 24
Peak memory 200228 kb
Host smart-f2c2e471-886e-46a5-af1c-3fc397d98ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867701913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1867701913
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2958892280
Short name T822
Test name
Test status
Simulation time 243089487989 ps
CPU time 107.47 seconds
Started Jul 27 06:30:40 PM PDT 24
Finished Jul 27 06:32:28 PM PDT 24
Peak memory 200224 kb
Host smart-41e7a6bd-f5b8-4c4e-90e4-8eff6d0b65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958892280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2958892280
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2629265667
Short name T918
Test name
Test status
Simulation time 119187963230 ps
CPU time 425.07 seconds
Started Jul 27 06:30:38 PM PDT 24
Finished Jul 27 06:37:43 PM PDT 24
Peak memory 216740 kb
Host smart-4bbf55ab-4bfc-4db9-b896-d289838b371a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629265667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2629265667
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.351513909
Short name T764
Test name
Test status
Simulation time 16935118 ps
CPU time 0.55 seconds
Started Jul 27 06:23:50 PM PDT 24
Finished Jul 27 06:23:50 PM PDT 24
Peak memory 195060 kb
Host smart-643bfabf-9414-47bf-ad6b-dd8baa53e19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351513909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.351513909
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1950128151
Short name T863
Test name
Test status
Simulation time 45941211431 ps
CPU time 28.89 seconds
Started Jul 27 06:23:44 PM PDT 24
Finished Jul 27 06:24:13 PM PDT 24
Peak memory 200212 kb
Host smart-1f582a42-e170-4eb3-9192-72d51bdf3262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950128151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1950128151
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2630937832
Short name T668
Test name
Test status
Simulation time 14070138611 ps
CPU time 11.9 seconds
Started Jul 27 06:23:41 PM PDT 24
Finished Jul 27 06:23:53 PM PDT 24
Peak memory 199880 kb
Host smart-6947fabb-e1e7-4f4d-9c07-7ec931938fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630937832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2630937832
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3974700243
Short name T170
Test name
Test status
Simulation time 93156824334 ps
CPU time 16.74 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:24:06 PM PDT 24
Peak memory 200188 kb
Host smart-ed1ccd0f-59cf-4d7d-851d-ec14e516acb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974700243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3974700243
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3415538269
Short name T1008
Test name
Test status
Simulation time 372946640819 ps
CPU time 260.79 seconds
Started Jul 27 06:23:50 PM PDT 24
Finished Jul 27 06:28:11 PM PDT 24
Peak memory 200020 kb
Host smart-aa6cd69d-add8-4512-8c78-08fc2f987f33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415538269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3415538269
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2740818651
Short name T501
Test name
Test status
Simulation time 145627390619 ps
CPU time 258.62 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:28:08 PM PDT 24
Peak memory 200232 kb
Host smart-ab0d389b-600c-4430-8068-25da776e09e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740818651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2740818651
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4120129363
Short name T365
Test name
Test status
Simulation time 7710599832 ps
CPU time 5.77 seconds
Started Jul 27 06:23:42 PM PDT 24
Finished Jul 27 06:23:48 PM PDT 24
Peak memory 200104 kb
Host smart-08992ac7-b354-4daf-95e2-cafe624346da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120129363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4120129363
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3663408719
Short name T479
Test name
Test status
Simulation time 58223306428 ps
CPU time 22.38 seconds
Started Jul 27 06:23:42 PM PDT 24
Finished Jul 27 06:24:04 PM PDT 24
Peak memory 200344 kb
Host smart-d24b288b-4dbd-44aa-bf25-bcae802694f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663408719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3663408719
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.331435615
Short name T385
Test name
Test status
Simulation time 14576099878 ps
CPU time 425.98 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:30:56 PM PDT 24
Peak memory 200248 kb
Host smart-d3a0ea8f-3d86-43af-aeeb-c94b96cbfef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331435615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.331435615
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2201605855
Short name T924
Test name
Test status
Simulation time 6993910948 ps
CPU time 16.13 seconds
Started Jul 27 06:23:41 PM PDT 24
Finished Jul 27 06:23:57 PM PDT 24
Peak memory 198364 kb
Host smart-268cb35a-bd3e-4a98-96e3-b7e87a29aa5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201605855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2201605855
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3596932359
Short name T303
Test name
Test status
Simulation time 323330918573 ps
CPU time 36.99 seconds
Started Jul 27 06:23:38 PM PDT 24
Finished Jul 27 06:24:15 PM PDT 24
Peak memory 200012 kb
Host smart-7ede9c24-6ffe-4def-9d67-875821e17f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596932359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3596932359
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2900978349
Short name T1138
Test name
Test status
Simulation time 2147638742 ps
CPU time 1.46 seconds
Started Jul 27 06:23:40 PM PDT 24
Finished Jul 27 06:23:41 PM PDT 24
Peak memory 195800 kb
Host smart-7428c0f5-8e41-470c-8a82-7f8125e2c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900978349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2900978349
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2891902864
Short name T419
Test name
Test status
Simulation time 822465471 ps
CPU time 2.19 seconds
Started Jul 27 06:23:43 PM PDT 24
Finished Jul 27 06:23:46 PM PDT 24
Peak memory 199656 kb
Host smart-86f3c908-9833-42a3-ad66-b159fcebcaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891902864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2891902864
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.151436015
Short name T89
Test name
Test status
Simulation time 125881359413 ps
CPU time 415.79 seconds
Started Jul 27 06:23:48 PM PDT 24
Finished Jul 27 06:30:44 PM PDT 24
Peak memory 200096 kb
Host smart-ec3f462f-636b-4b06-a6fd-845a0f25ddfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151436015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.151436015
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1890427736
Short name T1051
Test name
Test status
Simulation time 753670673 ps
CPU time 2.09 seconds
Started Jul 27 06:23:41 PM PDT 24
Finished Jul 27 06:23:43 PM PDT 24
Peak memory 198548 kb
Host smart-99d638cd-3029-493b-98c0-0fc77748cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890427736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1890427736
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.906365782
Short name T940
Test name
Test status
Simulation time 112827594670 ps
CPU time 135.68 seconds
Started Jul 27 06:23:40 PM PDT 24
Finished Jul 27 06:25:56 PM PDT 24
Peak memory 200192 kb
Host smart-02890a69-c5bd-47d4-b304-a016e55f4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906365782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.906365782
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.581637336
Short name T437
Test name
Test status
Simulation time 23313297822 ps
CPU time 15.83 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:30:57 PM PDT 24
Peak memory 200164 kb
Host smart-b75273d8-6c9d-4f85-944b-18a485810cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581637336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.581637336
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.846418870
Short name T93
Test name
Test status
Simulation time 28712483156 ps
CPU time 297.81 seconds
Started Jul 27 06:30:36 PM PDT 24
Finished Jul 27 06:35:34 PM PDT 24
Peak memory 216796 kb
Host smart-45e9e216-3f6d-478f-b7ad-af208aefc341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846418870 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.846418870
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.777577114
Short name T204
Test name
Test status
Simulation time 112065094956 ps
CPU time 44.96 seconds
Started Jul 27 06:30:41 PM PDT 24
Finished Jul 27 06:31:26 PM PDT 24
Peak memory 200124 kb
Host smart-7ca38699-1ce6-434e-afdc-51a191b97b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777577114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.777577114
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2952166298
Short name T533
Test name
Test status
Simulation time 165125917338 ps
CPU time 663.21 seconds
Started Jul 27 06:30:51 PM PDT 24
Finished Jul 27 06:41:54 PM PDT 24
Peak memory 216720 kb
Host smart-ae67c654-4f54-4ad1-a9a6-5c874223e6ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952166298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2952166298
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2031308926
Short name T621
Test name
Test status
Simulation time 88227779652 ps
CPU time 128.13 seconds
Started Jul 27 06:30:49 PM PDT 24
Finished Jul 27 06:32:57 PM PDT 24
Peak memory 200224 kb
Host smart-6d84246a-b7b4-4fa1-a0f6-5c5d20013ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031308926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2031308926
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.375682683
Short name T603
Test name
Test status
Simulation time 90463708865 ps
CPU time 310.17 seconds
Started Jul 27 06:30:51 PM PDT 24
Finished Jul 27 06:36:01 PM PDT 24
Peak memory 216852 kb
Host smart-2d8d910d-cfe0-4890-8eca-db1e3447372a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375682683 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.375682683
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3638853235
Short name T485
Test name
Test status
Simulation time 15764852843 ps
CPU time 31.07 seconds
Started Jul 27 06:30:51 PM PDT 24
Finished Jul 27 06:31:23 PM PDT 24
Peak memory 200132 kb
Host smart-4b485b30-459e-4d56-adff-901ac707d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638853235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3638853235
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1713052280
Short name T50
Test name
Test status
Simulation time 79914138114 ps
CPU time 201.94 seconds
Started Jul 27 06:30:49 PM PDT 24
Finished Jul 27 06:34:11 PM PDT 24
Peak memory 212808 kb
Host smart-f41c4002-3705-4246-9369-554facc053a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713052280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1713052280
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2931662821
Short name T489
Test name
Test status
Simulation time 97117394705 ps
CPU time 133.1 seconds
Started Jul 27 06:30:49 PM PDT 24
Finished Jul 27 06:33:02 PM PDT 24
Peak memory 200172 kb
Host smart-19110504-9115-4ec3-b534-09b78fd88912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931662821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2931662821
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4086591969
Short name T45
Test name
Test status
Simulation time 102318901140 ps
CPU time 601.51 seconds
Started Jul 27 06:30:52 PM PDT 24
Finished Jul 27 06:40:54 PM PDT 24
Peak memory 216928 kb
Host smart-968a3aa0-24a5-422e-beed-5681f4a20b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086591969 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4086591969
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2475763821
Short name T1171
Test name
Test status
Simulation time 20108648995 ps
CPU time 11.59 seconds
Started Jul 27 06:30:53 PM PDT 24
Finished Jul 27 06:31:05 PM PDT 24
Peak memory 200156 kb
Host smart-e4a5a9d3-9d15-4340-ab8a-2d23ded972ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475763821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2475763821
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1164989164
Short name T44
Test name
Test status
Simulation time 20602373451 ps
CPU time 200.5 seconds
Started Jul 27 06:30:52 PM PDT 24
Finished Jul 27 06:34:13 PM PDT 24
Peak memory 216856 kb
Host smart-edf33ea6-6e4e-4c56-83e4-4a307aa47751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164989164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1164989164
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.340927542
Short name T331
Test name
Test status
Simulation time 128709863068 ps
CPU time 68.06 seconds
Started Jul 27 06:30:49 PM PDT 24
Finished Jul 27 06:31:57 PM PDT 24
Peak memory 200228 kb
Host smart-058af470-d166-4d91-a4e3-7ec2070d839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340927542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.340927542
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3125339202
Short name T1103
Test name
Test status
Simulation time 333729420615 ps
CPU time 266.11 seconds
Started Jul 27 06:30:50 PM PDT 24
Finished Jul 27 06:35:17 PM PDT 24
Peak memory 216648 kb
Host smart-e67f014e-4530-416d-90fd-1ef033168aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125339202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3125339202
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2435105372
Short name T146
Test name
Test status
Simulation time 35979701195 ps
CPU time 12.19 seconds
Started Jul 27 06:30:53 PM PDT 24
Finished Jul 27 06:31:05 PM PDT 24
Peak memory 200160 kb
Host smart-d9e54ba3-743c-4cc3-beae-9c6ef99f998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435105372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2435105372
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1044884699
Short name T421
Test name
Test status
Simulation time 51073627872 ps
CPU time 314.68 seconds
Started Jul 27 06:30:52 PM PDT 24
Finished Jul 27 06:36:07 PM PDT 24
Peak memory 216808 kb
Host smart-6efdfad1-af44-4208-8e96-a9e98d7839c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044884699 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1044884699
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3066300197
Short name T451
Test name
Test status
Simulation time 66010229642 ps
CPU time 111.97 seconds
Started Jul 27 06:30:49 PM PDT 24
Finished Jul 27 06:32:42 PM PDT 24
Peak memory 200164 kb
Host smart-fbd7ed8b-695a-445f-b36c-88a69137835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066300197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3066300197
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.138716141
Short name T166
Test name
Test status
Simulation time 65511881042 ps
CPU time 600.36 seconds
Started Jul 27 06:31:01 PM PDT 24
Finished Jul 27 06:41:02 PM PDT 24
Peak memory 227832 kb
Host smart-7b06c332-12d2-4d95-9b67-7bcb4c0ef3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138716141 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.138716141
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2611745811
Short name T541
Test name
Test status
Simulation time 34209521 ps
CPU time 0.56 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:23:59 PM PDT 24
Peak memory 195888 kb
Host smart-348d7d68-f845-44a9-9f43-fb6cb150b5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611745811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2611745811
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2367880961
Short name T544
Test name
Test status
Simulation time 281882147166 ps
CPU time 83.21 seconds
Started Jul 27 06:23:50 PM PDT 24
Finished Jul 27 06:25:14 PM PDT 24
Peak memory 200248 kb
Host smart-261d278c-e6ae-4a5d-a08f-6867c055a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367880961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2367880961
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2524051046
Short name T431
Test name
Test status
Simulation time 63040156331 ps
CPU time 26.53 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:24:16 PM PDT 24
Peak memory 200172 kb
Host smart-47023386-052f-4e15-b220-83036ec7b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524051046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2524051046
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.456748753
Short name T1012
Test name
Test status
Simulation time 24781079193 ps
CPU time 17.26 seconds
Started Jul 27 06:23:49 PM PDT 24
Finished Jul 27 06:24:06 PM PDT 24
Peak memory 200156 kb
Host smart-2167af24-68ae-4d8a-bfa9-5cfa83839eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456748753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.456748753
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.412982314
Short name T82
Test name
Test status
Simulation time 45163394766 ps
CPU time 22.68 seconds
Started Jul 27 06:23:51 PM PDT 24
Finished Jul 27 06:24:14 PM PDT 24
Peak memory 200236 kb
Host smart-de319e00-77d8-4bf6-aa88-07672e7722ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412982314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.412982314
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2461682294
Short name T644
Test name
Test status
Simulation time 93706757491 ps
CPU time 649.14 seconds
Started Jul 27 06:24:01 PM PDT 24
Finished Jul 27 06:34:50 PM PDT 24
Peak memory 200176 kb
Host smart-f0289af5-d31b-40d0-bfb7-864508e7aef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461682294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2461682294
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3214148474
Short name T637
Test name
Test status
Simulation time 10465198901 ps
CPU time 7.37 seconds
Started Jul 27 06:24:00 PM PDT 24
Finished Jul 27 06:24:07 PM PDT 24
Peak memory 200152 kb
Host smart-60aa4a07-c876-4f01-b479-b05ff97bd5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214148474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3214148474
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2309428726
Short name T587
Test name
Test status
Simulation time 111751559514 ps
CPU time 127.75 seconds
Started Jul 27 06:23:50 PM PDT 24
Finished Jul 27 06:25:57 PM PDT 24
Peak memory 208356 kb
Host smart-e4d820ce-968d-47c4-a237-200bfa135c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309428726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2309428726
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3323238304
Short name T680
Test name
Test status
Simulation time 16909625952 ps
CPU time 145.66 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:26:24 PM PDT 24
Peak memory 200196 kb
Host smart-becf424f-05a6-4310-b3df-03fbd565dcc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323238304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3323238304
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.133591184
Short name T832
Test name
Test status
Simulation time 4992151651 ps
CPU time 45.6 seconds
Started Jul 27 06:23:48 PM PDT 24
Finished Jul 27 06:24:33 PM PDT 24
Peak memory 199176 kb
Host smart-42edc401-c118-4db3-89af-6d20a3d96424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133591184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.133591184
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4258663616
Short name T546
Test name
Test status
Simulation time 36544609556 ps
CPU time 63.63 seconds
Started Jul 27 06:23:48 PM PDT 24
Finished Jul 27 06:24:51 PM PDT 24
Peak memory 200344 kb
Host smart-d10a403a-75ff-42ff-b42f-5adeefee76c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258663616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4258663616
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1871086315
Short name T1110
Test name
Test status
Simulation time 2332199870 ps
CPU time 4.02 seconds
Started Jul 27 06:23:52 PM PDT 24
Finished Jul 27 06:23:56 PM PDT 24
Peak memory 195992 kb
Host smart-404ec1c7-f78c-4455-8fb7-d31d0f5c10af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871086315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1871086315
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2995394465
Short name T1091
Test name
Test status
Simulation time 627505552 ps
CPU time 1.75 seconds
Started Jul 27 06:23:51 PM PDT 24
Finished Jul 27 06:23:53 PM PDT 24
Peak memory 199076 kb
Host smart-6bd4216d-a6b1-4e2d-8adb-7e1305ccf125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995394465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2995394465
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2345024539
Short name T167
Test name
Test status
Simulation time 331164319815 ps
CPU time 530.12 seconds
Started Jul 27 06:23:58 PM PDT 24
Finished Jul 27 06:32:48 PM PDT 24
Peak memory 200176 kb
Host smart-61537190-6da7-4987-b34a-1fdf9f98f6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345024539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2345024539
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.814081630
Short name T826
Test name
Test status
Simulation time 29756693440 ps
CPU time 93.91 seconds
Started Jul 27 06:23:59 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 216268 kb
Host smart-8e5ceef7-a9c1-4dd5-96e5-d441fe138fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814081630 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.814081630
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2126518482
Short name T925
Test name
Test status
Simulation time 6935492299 ps
CPU time 31.43 seconds
Started Jul 27 06:23:48 PM PDT 24
Finished Jul 27 06:24:20 PM PDT 24
Peak memory 200240 kb
Host smart-e6a7e7a6-163d-4e7f-ab31-86f63f87a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126518482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2126518482
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3988267217
Short name T1137
Test name
Test status
Simulation time 150891031660 ps
CPU time 339.83 seconds
Started Jul 27 06:23:51 PM PDT 24
Finished Jul 27 06:29:31 PM PDT 24
Peak memory 200184 kb
Host smart-b1e2de3e-0f9d-48e6-92f8-74a82691715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988267217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3988267217
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.34766930
Short name T435
Test name
Test status
Simulation time 22277719227 ps
CPU time 34.01 seconds
Started Jul 27 06:31:02 PM PDT 24
Finished Jul 27 06:31:36 PM PDT 24
Peak memory 200240 kb
Host smart-e25d3e84-70f1-49f3-bea7-57dc48125500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34766930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.34766930
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.534067770
Short name T798
Test name
Test status
Simulation time 405020087658 ps
CPU time 917.86 seconds
Started Jul 27 06:30:59 PM PDT 24
Finished Jul 27 06:46:17 PM PDT 24
Peak memory 224872 kb
Host smart-a874210a-097d-42eb-a6d0-6a2ea44564c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534067770 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.534067770
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2072410852
Short name T734
Test name
Test status
Simulation time 113875042000 ps
CPU time 39.74 seconds
Started Jul 27 06:30:59 PM PDT 24
Finished Jul 27 06:31:39 PM PDT 24
Peak memory 200148 kb
Host smart-f643f82e-cd58-465a-8374-47c26f983d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072410852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2072410852
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3308846358
Short name T323
Test name
Test status
Simulation time 105600348162 ps
CPU time 268.92 seconds
Started Jul 27 06:30:59 PM PDT 24
Finished Jul 27 06:35:28 PM PDT 24
Peak memory 216812 kb
Host smart-af1cb6f4-89f4-49c0-a92f-09f64a84cb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308846358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3308846358
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3254678497
Short name T164
Test name
Test status
Simulation time 330698296217 ps
CPU time 1149.72 seconds
Started Jul 27 06:30:59 PM PDT 24
Finished Jul 27 06:50:09 PM PDT 24
Peak memory 226484 kb
Host smart-d00732ea-267e-44a1-8d63-66879d76bb54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254678497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3254678497
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3360302521
Short name T140
Test name
Test status
Simulation time 116203532415 ps
CPU time 71.7 seconds
Started Jul 27 06:31:00 PM PDT 24
Finished Jul 27 06:32:12 PM PDT 24
Peak memory 200232 kb
Host smart-3a87ea85-7e13-4253-90d6-abd5aa1548a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360302521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3360302521
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.568812593
Short name T51
Test name
Test status
Simulation time 242307979236 ps
CPU time 3446.76 seconds
Started Jul 27 06:30:59 PM PDT 24
Finished Jul 27 07:28:26 PM PDT 24
Peak memory 233232 kb
Host smart-0848ad14-d8bd-4f56-b3e1-0b4a2d3e40e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568812593 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.568812593
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3001627854
Short name T194
Test name
Test status
Simulation time 57286644652 ps
CPU time 24.89 seconds
Started Jul 27 06:31:02 PM PDT 24
Finished Jul 27 06:31:27 PM PDT 24
Peak memory 200128 kb
Host smart-4eeb86cd-f865-4908-92d5-32aafac246be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001627854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3001627854
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1620659572
Short name T27
Test name
Test status
Simulation time 44645138670 ps
CPU time 518.13 seconds
Started Jul 27 06:30:57 PM PDT 24
Finished Jul 27 06:39:35 PM PDT 24
Peak memory 216740 kb
Host smart-89ce102f-5ce0-437f-904a-864b3a9b9ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620659572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1620659572
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2799624940
Short name T379
Test name
Test status
Simulation time 218225004544 ps
CPU time 36.86 seconds
Started Jul 27 06:30:57 PM PDT 24
Finished Jul 27 06:31:34 PM PDT 24
Peak memory 200084 kb
Host smart-ee7b3648-5acf-4759-89b4-e6e0adb370b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799624940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2799624940
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.52849688
Short name T935
Test name
Test status
Simulation time 37193637519 ps
CPU time 724.11 seconds
Started Jul 27 06:30:58 PM PDT 24
Finished Jul 27 06:43:02 PM PDT 24
Peak memory 216824 kb
Host smart-1b993305-2229-4b65-a066-4ee17ab29acb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52849688 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.52849688
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2021123805
Short name T1163
Test name
Test status
Simulation time 115592000154 ps
CPU time 30.87 seconds
Started Jul 27 06:30:58 PM PDT 24
Finished Jul 27 06:31:29 PM PDT 24
Peak memory 200084 kb
Host smart-096236f9-bdf0-48e1-bcff-b48b2fba3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021123805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2021123805
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4249126717
Short name T1121
Test name
Test status
Simulation time 91506878865 ps
CPU time 611.42 seconds
Started Jul 27 06:31:01 PM PDT 24
Finished Jul 27 06:41:12 PM PDT 24
Peak memory 228324 kb
Host smart-7ebec677-0978-4b0b-8021-a2ff1b5fa521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249126717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4249126717
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1726001369
Short name T793
Test name
Test status
Simulation time 185057690243 ps
CPU time 38.88 seconds
Started Jul 27 06:31:01 PM PDT 24
Finished Jul 27 06:31:40 PM PDT 24
Peak memory 200192 kb
Host smart-c0ebdead-c0d9-4297-91d8-b8678d4307d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726001369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1726001369
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3281102874
Short name T307
Test name
Test status
Simulation time 100519102504 ps
CPU time 415.92 seconds
Started Jul 27 06:30:58 PM PDT 24
Finished Jul 27 06:37:54 PM PDT 24
Peak memory 216592 kb
Host smart-95ad241f-1a7a-4dd6-896f-b9f9341ffa29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281102874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3281102874
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.217306328
Short name T721
Test name
Test status
Simulation time 48169066393 ps
CPU time 21.24 seconds
Started Jul 27 06:31:10 PM PDT 24
Finished Jul 27 06:31:31 PM PDT 24
Peak memory 200240 kb
Host smart-c8c105f0-ae29-41dc-b35c-bc2231c14e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217306328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.217306328
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.114102507
Short name T789
Test name
Test status
Simulation time 402093574480 ps
CPU time 1085.78 seconds
Started Jul 27 06:31:08 PM PDT 24
Finished Jul 27 06:49:14 PM PDT 24
Peak memory 216816 kb
Host smart-264fdaf3-f21c-40c4-abdd-9d6593284397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114102507 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.114102507
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.572149590
Short name T483
Test name
Test status
Simulation time 19797294378 ps
CPU time 36.28 seconds
Started Jul 27 06:31:08 PM PDT 24
Finished Jul 27 06:31:45 PM PDT 24
Peak memory 200212 kb
Host smart-db009540-f115-47c0-8e67-c7867b8e7c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572149590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.572149590
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2966141857
Short name T508
Test name
Test status
Simulation time 142009909058 ps
CPU time 784.42 seconds
Started Jul 27 06:31:07 PM PDT 24
Finished Jul 27 06:44:12 PM PDT 24
Peak memory 216744 kb
Host smart-e3e58a09-06ec-4a34-8f1d-a9058ee76daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966141857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2966141857
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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