Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99156	1			T1	35		T2	42		T3	17
all_values[1]	99156	1			T1	35		T2	42		T3	17
all_values[2]	99156	1			T1	35		T2	42		T3	17
all_values[3]	99156	1			T1	35		T2	42		T3	17
all_values[4]	99156	1			T1	35		T2	42		T3	17
all_values[5]	99156	1			T1	35		T2	42		T3	17
all_values[6]	99156	1			T1	35		T2	42		T3	17
all_values[7]	99156	1			T1	35		T2	42		T3	17
all_values[8]	99156	1			T1	35		T2	42		T3	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443020

1

T1

199

T2

178

T3

93

auto[1]

449384

1

T1

116

T2

200

T3

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

811075

1

T1

264

T2

313

T3

116

auto[1]

81329

1

T1

51

T2

65

T3

37

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27702	1			T1	11		T2	8		T3	5
all_values[0]	auto[0]	auto[1]	19686	1			T1	19		T3	2		T4	3
all_values[0]	auto[1]	auto[0]	30993	1			T2	4		T6	6		T8	8
all_values[0]	auto[1]	auto[1]	20775	1			T1	5		T2	30		T3	10
all_values[1]	auto[0]	auto[0]	48151	1			T1	3		T2	7		T4	17
all_values[1]	auto[0]	auto[1]	1425	1			T2	1		T3	10		T25	1
all_values[1]	auto[1]	auto[0]	47891	1			T1	32		T2	34		T3	7
all_values[1]	auto[1]	auto[1]	1689	1			T6	6		T10	10		T24	1
all_values[2]	auto[0]	auto[0]	45825	1			T1	27		T2	27		T3	13
all_values[2]	auto[0]	auto[1]	2693	1			T1	3		T2	3		T3	2
all_values[2]	auto[1]	auto[0]	48119	1			T1	3		T2	10		T3	1
all_values[2]	auto[1]	auto[1]	2519	1			T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[0]	48810	1			T1	33		T2	40		T3	10
all_values[3]	auto[0]	auto[1]	326	1			T11	1		T14	3		T15	1
all_values[3]	auto[1]	auto[0]	49660	1			T1	1		T2	2		T3	7
all_values[3]	auto[1]	auto[1]	360	1			T1	1		T11	2		T12	1
all_values[4]	auto[0]	auto[0]	49220	1			T1	5		T2	6		T3	12
all_values[4]	auto[0]	auto[1]	500	1			T14	3		T15	4		T34	1
all_values[4]	auto[1]	auto[0]	48959	1			T1	30		T2	36		T3	5
all_values[4]	auto[1]	auto[1]	477	1			T11	2		T12	9		T14	5
all_values[5]	auto[0]	auto[0]	48250	1			T1	2		T2	5		T3	17
all_values[5]	auto[0]	auto[1]	192	1			T11	3		T14	3		T34	3
all_values[5]	auto[1]	auto[0]	50518	1			T1	33		T2	37		T5	12
all_values[5]	auto[1]	auto[1]	196	1			T14	2		T34	2		T35	1
all_values[6]	auto[0]	auto[0]	49940	1			T1	30		T2	8		T3	5
all_values[6]	auto[0]	auto[1]	195	1			T14	4		T34	4		T38	1
all_values[6]	auto[1]	auto[0]	48840	1			T1	5		T2	34		T3	12
all_values[6]	auto[1]	auto[1]	181	1			T14	1		T34	1		T35	1
all_values[7]	auto[0]	auto[0]	48228	1			T1	33		T2	36		T3	10
all_values[7]	auto[0]	auto[1]	363	1			T16	7		T11	1		T12	2
all_values[7]	auto[1]	auto[0]	50216	1			T1	2		T2	6		T3	7
all_values[7]	auto[1]	auto[1]	349	1			T16	1		T11	2		T12	3
all_values[8]	auto[0]	auto[0]	34620	1			T1	14		T2	8		T4	3
all_values[8]	auto[0]	auto[1]	16894	1			T1	19		T2	29		T3	7
all_values[8]	auto[1]	auto[0]	35133	1			T2	5		T3	5		T4	13
all_values[8]	auto[1]	auto[1]	12509	1			T1	2		T3	5		T5	2