Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2294	1			T1	1		T2	3		T3	4
auto[BaudRate115200]	2211	1			T2	2		T3	1		T4	2
auto[BaudRate230400]	2057	1			T1	2		T2	2		T3	1
auto[BaudRate128Kbps]	2178	1			T1	1		T4	1		T6	2
auto[BaudRate256Kbps]	2342	1			T1	1		T2	1		T4	1
auto[BaudRate1Mbps]	1854	1			T1	1		T4	1		T5	1
auto[BaudRate1p5Mbps]	1362	1			T4	1		T5	1		T6	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1356	1			T45	5		T19	28		T282	2
freqs[25]	1150	1			T9	2		T26	2		T24	9
freqs[48]	389	1			T10	9		T248	6		T148	52
freqs[50]	433	1			T256	2		T266	10		T281	13
freqs[100]	1269	1			T5	5		T46	8		T18	52

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	233	1			T138	2		T38	13		T313	2
auto[BaudRate9600]	freqs[25]	181	1			T24	2		T137	2		T12	4
auto[BaudRate9600]	freqs[48]	79	1			T10	3		T248	1		T148	5
auto[BaudRate9600]	freqs[50]	45	1			T266	1		T281	1		T314	1
auto[BaudRate9600]	freqs[100]	200	1			T5	1		T18	1		T44	2
auto[BaudRate115200]	freqs[24]	221	1			T19	4		T138	5		T267	2
auto[BaudRate115200]	freqs[25]	189	1			T9	1		T24	1		T137	4
auto[BaudRate115200]	freqs[48]	44	1			T10	1		T148	9		T315	1
auto[BaudRate115200]	freqs[50]	57	1			T256	1		T281	1		T174	1
auto[BaudRate115200]	freqs[100]	183	1			T5	1		T46	3		T18	15
auto[BaudRate230400]	freqs[24]	189	1			T45	1		T19	6		T138	3
auto[BaudRate230400]	freqs[25]	162	1			T26	1		T137	3		T12	4
auto[BaudRate230400]	freqs[48]	48	1			T10	2		T148	11		T53	1
auto[BaudRate230400]	freqs[50]	66	1			T266	2		T281	3		T316	1
auto[BaudRate230400]	freqs[100]	151	1			T46	1		T18	9		T260	1
auto[BaudRate128Kbps]	freqs[24]	179	1			T45	3		T19	5		T282	1
auto[BaudRate128Kbps]	freqs[25]	185	1			T24	1		T137	3		T12	5
auto[BaudRate128Kbps]	freqs[48]	65	1			T10	1		T248	3		T148	5
auto[BaudRate128Kbps]	freqs[50]	63	1			T256	1		T266	2		T281	3
auto[BaudRate128Kbps]	freqs[100]	183	1			T46	1		T18	11		T44	2
auto[BaudRate256Kbps]	freqs[24]	186	1			T19	4		T282	1		T138	2
auto[BaudRate256Kbps]	freqs[25]	180	1			T26	1		T24	2		T137	1
auto[BaudRate256Kbps]	freqs[48]	53	1			T10	1		T248	2		T148	6
auto[BaudRate256Kbps]	freqs[50]	64	1			T266	2		T281	2		T174	2
auto[BaudRate256Kbps]	freqs[100]	194	1			T5	1		T46	2		T18	9
auto[BaudRate1Mbps]	freqs[24]	227	1			T45	1		T19	6		T138	3
auto[BaudRate1Mbps]	freqs[25]	161	1			T9	1		T24	2		T137	4
auto[BaudRate1Mbps]	freqs[48]	40	1			T10	1		T148	7		T150	2
auto[BaudRate1Mbps]	freqs[50]	66	1			T266	1		T281	2		T174	2
auto[BaudRate1Mbps]	freqs[100]	197	1			T5	1		T46	1		T18	4
auto[BaudRate1p5Mbps]	freqs[25]	92	1			T24	1		T137	2		T12	2
auto[BaudRate1p5Mbps]	freqs[48]	60	1			T148	9		T150	2		T317	1
auto[BaudRate1p5Mbps]	freqs[50]	72	1			T266	2		T281	1		T174	3
auto[BaudRate1p5Mbps]	freqs[100]	161	1			T5	1		T18	3		T44	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded